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netxen: code cleanup
[deliverable/linux.git] / drivers / net / netxen / netxen_nic_hw.c
CommitLineData
3d396eb1 1/*
5d242f1c 2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3d396eb1 3 * All rights reserved.
80922fbc 4 *
3d396eb1
AK		 5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
cb8011ad 9 *
3d396eb1
AK		 10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
cb8011ad 14 *
3d396eb1
AK		 15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
80922fbc 19 *
3d396eb1
AK		 20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
80922fbc 22 *
3d396eb1
AK		 23 * Contact Information:
24 * info@netxen.com
5d242f1c
DP		 25 * NetXen Inc,
26 * 18922 Forge Drive
27 * Cupertino, CA 95014-0701
3d396eb1
AK		 28 *
29 */
30
31#include "netxen_nic.h"
32#include "netxen_nic_hw.h"
33#include "netxen_nic_phan_reg.h"
34
ba599d4f 35#include <linux/firmware.h>
c9bdd4b5
ACM		 36#include <net/ip.h>
37
3ce06a32
DP		 38#define MASK(n) ((1ULL<<(n))-1)
39#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
40#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
41#define MS_WIN(addr) (addr & 0x0ffc0000)
42
43#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
44
45#define CRB_BLK(off) ((off >> 20) & 0x3f)
46#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
47#define CRB_WINDOW_2M (0x130060)
48#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
49#define CRB_INDIRECT_2M (0x1e0000UL)
50
e98e3350
DP		 51#ifndef readq
52static inline u64 readq(void __iomem *addr)
53{
54 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
55}
56#endif
57
58#ifndef writeq
59static inline void writeq(u64 val, void __iomem *addr)
60{
61 writel(((u32) (val)), (addr));
62 writel(((u32) (val >> 32)), (addr + 4));
63}
64#endif
65
3ce06a32
DP		 66#define CRB_WIN_LOCK_TIMEOUT 100000000
67static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {
68 {{{0, 0, 0, 0} } }, /* 0: PCI */
69 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
70 {1, 0x0110000, 0x0120000, 0x130000},
71 {1, 0x0120000, 0x0122000, 0x124000},
72 {1, 0x0130000, 0x0132000, 0x126000},
73 {1, 0x0140000, 0x0142000, 0x128000},
74 {1, 0x0150000, 0x0152000, 0x12a000},
75 {1, 0x0160000, 0x0170000, 0x110000},
76 {1, 0x0170000, 0x0172000, 0x12e000},
77 {0, 0x0000000, 0x0000000, 0x000000},
78 {0, 0x0000000, 0x0000000, 0x000000},
79 {0, 0x0000000, 0x0000000, 0x000000},
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {1, 0x01e0000, 0x01e0800, 0x122000},
84 {0, 0x0000000, 0x0000000, 0x000000} } },
85 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
86 {{{0, 0, 0, 0} } }, /* 3: */
87 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
88 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
89 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
90 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
91 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {1, 0x08f0000, 0x08f2000, 0x172000} } },
107 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {1, 0x09f0000, 0x09f2000, 0x176000} } },
123 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
139 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
155 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
156 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
157 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
158 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
159 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
160 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
161 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
162 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
163 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
164 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
165 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
166 {{{0, 0, 0, 0} } }, /* 23: */
167 {{{0, 0, 0, 0} } }, /* 24: */
168 {{{0, 0, 0, 0} } }, /* 25: */
169 {{{0, 0, 0, 0} } }, /* 26: */
170 {{{0, 0, 0, 0} } }, /* 27: */
171 {{{0, 0, 0, 0} } }, /* 28: */
172 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
173 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
174 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
175 {{{0} } }, /* 32: PCI */
176 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
177 {1, 0x2110000, 0x2120000, 0x130000},
178 {1, 0x2120000, 0x2122000, 0x124000},
179 {1, 0x2130000, 0x2132000, 0x126000},
180 {1, 0x2140000, 0x2142000, 0x128000},
181 {1, 0x2150000, 0x2152000, 0x12a000},
182 {1, 0x2160000, 0x2170000, 0x110000},
183 {1, 0x2170000, 0x2172000, 0x12e000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000} } },
192 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
193 {{{0} } }, /* 35: */
194 {{{0} } }, /* 36: */
195 {{{0} } }, /* 37: */
196 {{{0} } }, /* 38: */
197 {{{0} } }, /* 39: */
198 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
199 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
200 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
201 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
202 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
203 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
204 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
205 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
206 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
207 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
208 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
209 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
210 {{{0} } }, /* 52: */
211 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
212 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
213 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
214 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
215 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
216 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
217 {{{0} } }, /* 59: I2C0 */
218 {{{0} } }, /* 60: I2C1 */
219 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
220 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
221 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
222};
223
224/*
225 * top 12 bits of crb internal address (hub, agent)
226 */
227static unsigned crb_hub_agt[64] =
228{
229 0,
230 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
231 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
232 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
233 0,
234 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
235 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
236 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
237 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
238 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
239 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
240 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
241 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
242 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
243 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
244 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
245 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
246 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
247 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
248 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
249 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
250 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
251 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
252 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
253 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
254 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
255 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
256 0,
257 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
258 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
259 0,
260 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
261 0,
262 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
263 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
264 0,
265 0,
266 0,
267 0,
268 0,
269 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
270 0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
272 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
273 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
274 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
275 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
276 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
277 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
278 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
279 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
280 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
281 0,
282 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
283 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
284 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
285 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
286 0,
287 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
288 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
289 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
290 0,
291 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
292 0,
293};
294
3d396eb1
AK		 295/* PCI Windowing for DDR regions. */
296
297#define ADDR_IN_RANGE(addr, low, high) \
298 (((addr) <= (high)) && ((addr) >= (low)))
299
3ce06a32 300#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
3d396eb1 301
cb8011ad
AK		 302#define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
303#define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
304#define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
305#define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
306
307#define NETXEN_NIC_WINDOW_MARGIN 0x100000
308
3d396eb1
AK		 309int netxen_nic_set_mac(struct net_device *netdev, void *p)
310{
3176ff3e 311 struct netxen_adapter *adapter = netdev_priv(netdev);
3d396eb1
AK		 312 struct sockaddr *addr = p;
313
314 if (netif_running(netdev))
315 return -EBUSY;
316
317 if (!is_valid_ether_addr(addr->sa_data))
318 return -EADDRNOTAVAIL;
319
3d396eb1
AK		 320 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
321
c9fc891f
DP		 322 /* For P3, MAC addr is not set in NIU */
323 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
324 if (adapter->macaddr_set)
325 adapter->macaddr_set(adapter, addr->sa_data);
3d396eb1
AK		 326
327 return 0;
328}
329
623621b0
DP		 330#define NETXEN_UNICAST_ADDR(port, index) \
331 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
332#define NETXEN_MCAST_ADDR(port, index) \
333 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
334#define MAC_HI(addr) \
335 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
336#define MAC_LO(addr) \
337 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
338
339static int
340netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
341{
342 u32 val = 0;
343 u16 port = adapter->physical_port;
344 u8 *addr = adapter->netdev->dev_addr;
345
346 if (adapter->mc_enabled)
347 return 0;
348
3ce06a32 349 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
623621b0 350 val |= (1UL << (28+port));
3ce06a32 351 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
623621b0
DP		 352
353 /* add broadcast addr to filter */
354 val = 0xffffff;
355 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
356 netxen_crb_writelit_adapter(adapter,
357 NETXEN_UNICAST_ADDR(port, 0)+4, val);
358
359 /* add station addr to filter */
360 val = MAC_HI(addr);
361 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
362 val = MAC_LO(addr);
363 netxen_crb_writelit_adapter(adapter,
364 NETXEN_UNICAST_ADDR(port, 1)+4, val);
365
366 adapter->mc_enabled = 1;
367 return 0;
368}
369
370static int
371netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
372{
373 u32 val = 0;
374 u16 port = adapter->physical_port;
375 u8 *addr = adapter->netdev->dev_addr;
376
377 if (!adapter->mc_enabled)
378 return 0;
379
3ce06a32 380 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
623621b0 381 val &= ~(1UL << (28+port));
3ce06a32 382 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
623621b0
DP		 383
384 val = MAC_HI(addr);
385 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
386 val = MAC_LO(addr);
387 netxen_crb_writelit_adapter(adapter,
388 NETXEN_UNICAST_ADDR(port, 0)+4, val);
389
390 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
391 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
392
393 adapter->mc_enabled = 0;
394 return 0;
395}
396
397static int
398netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
399 int index, u8 *addr)
400{
401 u32 hi = 0, lo = 0;
402 u16 port = adapter->physical_port;
403
404 lo = MAC_LO(addr);
405 hi = MAC_HI(addr);
406
407 netxen_crb_writelit_adapter(adapter,
408 NETXEN_MCAST_ADDR(port, index), hi);
409 netxen_crb_writelit_adapter(adapter,
410 NETXEN_MCAST_ADDR(port, index)+4, lo);
411
412 return 0;
413}
414
c9fc891f 415void netxen_p2_nic_set_multi(struct net_device *netdev)
3d396eb1 416{
3176ff3e 417 struct netxen_adapter *adapter = netdev_priv(netdev);
3d396eb1 418 struct dev_mc_list *mc_ptr;
623621b0
DP		 419 u8 null_addr[6];
420 int index = 0;
421
422 memset(null_addr, 0, 6);
3d396eb1 423
3d396eb1 424 if (netdev->flags & IFF_PROMISC) {
623621b0
DP		 425
426 adapter->set_promisc(adapter,
427 NETXEN_NIU_PROMISC_MODE);
428
429 /* Full promiscuous mode */
430 netxen_nic_disable_mcast_filter(adapter);
431
432 return;
433 }
434
435 if (netdev->mc_count == 0) {
436 adapter->set_promisc(adapter,
437 NETXEN_NIU_NON_PROMISC_MODE);
438 netxen_nic_disable_mcast_filter(adapter);
439 return;
440 }
441
442 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
443 if (netdev->flags & IFF_ALLMULTI ||
444 netdev->mc_count > adapter->max_mc_count) {
445 netxen_nic_disable_mcast_filter(adapter);
446 return;
3d396eb1 447 }
623621b0
DP		 448
449 netxen_nic_enable_mcast_filter(adapter);
450
451 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
452 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
453
454 if (index != netdev->mc_count)
455 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
456 netxen_nic_driver_name, netdev->name);
457
458 /* Clear out remaining addresses */
459 for (; index < adapter->max_mc_count; index++)
460 netxen_nic_set_mcast_addr(adapter, index, null_addr);
3d396eb1
AK		 461}
462
c9fc891f
DP		 463static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
464 u8 *addr, nx_mac_list_t **add_list, nx_mac_list_t **del_list)
465{
466 nx_mac_list_t *cur, *prev;
467
468 /* if in del_list, move it to adapter->mac_list */
469 for (cur = *del_list, prev = NULL; cur;) {
470 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
471 if (prev == NULL)
472 *del_list = cur->next;
473 else
474 prev->next = cur->next;
475 cur->next = adapter->mac_list;
476 adapter->mac_list = cur;
477 return 0;
478 }
479 prev = cur;
480 cur = cur->next;
481 }
482
483 /* make sure to add each mac address only once */
484 for (cur = adapter->mac_list; cur; cur = cur->next) {
485 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
486 return 0;
487 }
488 /* not in del_list, create new entry and add to add_list */
489 cur = kmalloc(sizeof(*cur), in_atomic()? GFP_ATOMIC : GFP_KERNEL);
490 if (cur == NULL) {
491 printk(KERN_ERR "%s: cannot allocate memory. MAC filtering may"
492 "not work properly from now.\n", __func__);
493 return -1;
494 }
495
496 memcpy(cur->mac_addr, addr, ETH_ALEN);
497 cur->next = *add_list;
498 *add_list = cur;
499 return 0;
500}
501
502static int
503netxen_send_cmd_descs(struct netxen_adapter *adapter,
504 struct cmd_desc_type0 *cmd_desc_arr, int nr_elements)
505{
506 uint32_t i, producer;
507 struct netxen_cmd_buffer *pbuf;
508 struct cmd_desc_type0 *cmd_desc;
509
510 if (nr_elements > MAX_PENDING_DESC_BLOCK_SIZE || nr_elements == 0) {
511 printk(KERN_WARNING "%s: Too many command descriptors in a "
512 "request\n", __func__);
513 return -EINVAL;
514 }
515
516 i = 0;
517
03e678ee
DP		 518 netif_tx_lock_bh(adapter->netdev);
519
c9fc891f
DP		 520 producer = adapter->cmd_producer;
521 do {
522 cmd_desc = &cmd_desc_arr[i];
523
524 pbuf = &adapter->cmd_buf_arr[producer];
c9fc891f 525 pbuf->skb = NULL;
c9fc891f 526 pbuf->frag_count = 0;
c9fc891f
DP		 527
528 /* adapter->ahw.cmd_desc_head[producer] = *cmd_desc; */
529 memcpy(&adapter->ahw.cmd_desc_head[producer],
530 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
531
532 producer = get_next_index(producer,
438627c7 533 adapter->num_txd);
c9fc891f
DP		 534 i++;
535
536 } while (i != nr_elements);
537
538 adapter->cmd_producer = producer;
539
540 /* write producer index to start the xmit */
541
542 netxen_nic_update_cmd_producer(adapter, adapter->cmd_producer);
543
03e678ee
DP		 544 netif_tx_unlock_bh(adapter->netdev);
545
c9fc891f
DP		 546 return 0;
547}
548
c9fc891f
DP		 549static int nx_p3_sre_macaddr_change(struct net_device *dev,
550 u8 *addr, unsigned op)
551{
4cf1653a 552 struct netxen_adapter *adapter = netdev_priv(dev);
c9fc891f 553 nx_nic_req_t req;
2edbb454
DP		 554 nx_mac_req_t *mac_req;
555 u64 word;
c9fc891f
DP		 556 int rv;
557
558 memset(&req, 0, sizeof(nx_nic_req_t));
2edbb454
DP		 559 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
560
561 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
562 req.req_hdr = cpu_to_le64(word);
563
564 mac_req = (nx_mac_req_t *)&req.words[0];
565 mac_req->op = op;
566 memcpy(mac_req->mac_addr, addr, 6);
c9fc891f
DP		 567
568 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
569 if (rv != 0) {
570 printk(KERN_ERR "ERROR. Could not send mac update\n");
571 return rv;
572 }
573
574 return 0;
575}
576
577void netxen_p3_nic_set_multi(struct net_device *netdev)
578{
579 struct netxen_adapter *adapter = netdev_priv(netdev);
580 nx_mac_list_t *cur, *next, *del_list, *add_list = NULL;
581 struct dev_mc_list *mc_ptr;
582 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
9ad27643 583 u32 mode = VPORT_MISS_MODE_DROP;
c9fc891f
DP		 584
585 del_list = adapter->mac_list;
586 adapter->mac_list = NULL;
587
588 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &add_list, &del_list);
9ad27643
DP		 589 nx_p3_nic_add_mac(adapter, bcast_addr, &add_list, &del_list);
590
591 if (netdev->flags & IFF_PROMISC) {
592 mode = VPORT_MISS_MODE_ACCEPT_ALL;
593 goto send_fw_cmd;
594 }
595
596 if ((netdev->flags & IFF_ALLMULTI) ||
597 (netdev->mc_count > adapter->max_mc_count)) {
598 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
599 goto send_fw_cmd;
600 }
601
c9fc891f 602 if (netdev->mc_count > 0) {
c9fc891f
DP		 603 for (mc_ptr = netdev->mc_list; mc_ptr;
604 mc_ptr = mc_ptr->next) {
605 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr,
606 &add_list, &del_list);
607 }
608 }
9ad27643
DP		 609
610send_fw_cmd:
611 adapter->set_promisc(adapter, mode);
c9fc891f
DP		 612 for (cur = del_list; cur;) {
613 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_DEL);
614 next = cur->next;
615 kfree(cur);
616 cur = next;
617 }
618 for (cur = add_list; cur;) {
619 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_ADD);
620 next = cur->next;
621 cur->next = adapter->mac_list;
622 adapter->mac_list = cur;
623 cur = next;
624 }
625}
626
9ad27643
DP		 627int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
628{
629 nx_nic_req_t req;
2edbb454 630 u64 word;
9ad27643
DP		 631
632 memset(&req, 0, sizeof(nx_nic_req_t));
633
2edbb454
DP		 634 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
635
636 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
637 ((u64)adapter->portnum << 16);
638 req.req_hdr = cpu_to_le64(word);
639
9ad27643
DP		 640 req.words[0] = cpu_to_le64(mode);
641
642 return netxen_send_cmd_descs(adapter,
643 (struct cmd_desc_type0 *)&req, 1);
644}
645
06e9d9f9
DP		 646void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
647{
648 nx_mac_list_t *cur, *next;
649
650 cur = adapter->mac_list;
651
652 while (cur) {
653 next = cur->next;
654 kfree(cur);
655 cur = next;
656 }
657}
658
cd1f8160
DP		 659#define NETXEN_CONFIG_INTR_COALESCE 3
660
661/*
662 * Send the interrupt coalescing parameter set by ethtool to the card.
663 */
664int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
665{
666 nx_nic_req_t req;
2edbb454 667 u64 word;
cd1f8160
DP		 668 int rv;
669
670 memset(&req, 0, sizeof(nx_nic_req_t));
671
2edbb454
DP		 672 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
673
674 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
675 req.req_hdr = cpu_to_le64(word);
cd1f8160
DP		 676
677 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
678
679 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
680 if (rv != 0) {
681 printk(KERN_ERR "ERROR. Could not send "
682 "interrupt coalescing parameters\n");
683 }
684
685 return rv;
686}
687
d8b100c5
DP		 688#define RSS_HASHTYPE_IP_TCP 0x3
689
690int netxen_config_rss(struct netxen_adapter *adapter, int enable)
691{
692 nx_nic_req_t req;
693 u64 word;
694 int i, rv;
695
696 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
697 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
698 0x255b0ec26d5a56daULL };
699
700
701 memset(&req, 0, sizeof(nx_nic_req_t));
702 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
703
704 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
705 req.req_hdr = cpu_to_le64(word);
706
707 /*
708 * RSS request:
709 * bits 3-0: hash_method
710 * 5-4: hash_type_ipv4
711 * 7-6: hash_type_ipv6
712 * 8: enable
713 * 9: use indirection table
714 * 47-10: reserved
715 * 63-48: indirection table mask
716 */
717 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
718 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
719 ((u64)(enable & 0x1) << 8) |
720 ((0x7ULL) << 48);
721 req.words[0] = cpu_to_le64(word);
722 for (i = 0; i < 5; i++)
723 req.words[i+1] = cpu_to_le64(key[i]);
724
725
726 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
727 if (rv != 0) {
728 printk(KERN_ERR "%s: could not configure RSS\n",
729 adapter->netdev->name);
730 }
731
732 return rv;
733}
734
3d396eb1
AK		 735/*
736 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
737 * @returns 0 on success, negative on failure
738 */
c9fc891f
DP		 739
740#define MTU_FUDGE_FACTOR 100
741
3d396eb1
AK		 742int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
743{
3176ff3e 744 struct netxen_adapter *adapter = netdev_priv(netdev);
c9fc891f 745 int max_mtu;
9ad27643 746 int rc = 0;
3d396eb1 747
c9fc891f
DP		 748 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
749 max_mtu = P3_MAX_MTU;
750 else
751 max_mtu = P2_MAX_MTU;
752
753 if (mtu > max_mtu) {
754 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
755 netdev->name, max_mtu);
3d396eb1
AK		 756 return -EINVAL;
757 }
758
80922fbc 759 if (adapter->set_mtu)
9ad27643 760 rc = adapter->set_mtu(adapter, mtu);
3d396eb1 761
9ad27643
DP		 762 if (!rc)
763 netdev->mtu = mtu;
c9fc891f 764
9ad27643 765 return rc;
3d396eb1
AK		 766}
767
3d396eb1 768static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
f305f789 769 int size, __le32 * buf)
3d396eb1 770{
1e2d0059 771 int i, v, addr;
f305f789 772 __le32 *ptr32;
3d396eb1
AK		 773
774 addr = base;
775 ptr32 = buf;
776 for (i = 0; i < size / sizeof(u32); i++) {
f305f789 777 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 778 return -1;
f305f789 779 *ptr32 = cpu_to_le32(v);
3d396eb1
AK		 780 ptr32++;
781 addr += sizeof(u32);
782 }
783 if ((char *)buf + size > (char *)ptr32) {
f305f789
AV		 784 __le32 local;
785 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 786 return -1;
f305f789 787 local = cpu_to_le32(v);
3d396eb1
AK		 788 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
789 }
790
791 return 0;
792}
793
9dc28efe 794int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
3d396eb1 795{
9dc28efe
DP		 796 __le32 *pmac = (__le32 *) mac;
797 u32 offset;
3d396eb1 798
9dc28efe
DP		 799 offset = NETXEN_USER_START +
800 offsetof(struct netxen_new_user_info, mac_addr) +
801 adapter->portnum * sizeof(u64);
802
803 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
3d396eb1 804 return -1;
9dc28efe 805
f305f789 806 if (*mac == cpu_to_le64(~0ULL)) {
9dc28efe
DP		 807
808 offset = NETXEN_USER_START_OLD +
809 offsetof(struct netxen_user_old_info, mac_addr) +
810 adapter->portnum * sizeof(u64);
811
3d396eb1 812 if (netxen_get_flash_block(adapter,
9dc28efe 813 offset, sizeof(u64), pmac) == -1)
3d396eb1 814 return -1;
9dc28efe 815
f305f789 816 if (*mac == cpu_to_le64(~0ULL))
3d396eb1
AK		 817 return -1;
818 }
819 return 0;
820}
821
9dc28efe
DP		 822int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
823{
824 uint32_t crbaddr, mac_hi, mac_lo;
825 int pci_func = adapter->ahw.pci_func;
826
827 crbaddr = CRB_MAC_BLOCK_START +
828 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
829
830 adapter->hw_read_wx(adapter, crbaddr, &mac_lo, 4);
831 adapter->hw_read_wx(adapter, crbaddr+4, &mac_hi, 4);
832
9dc28efe 833 if (pci_func & 1)
2edbb454 834 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
9dc28efe 835 else
2edbb454 836 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
9dc28efe
DP		 837
838 return 0;
839}
840
3ce06a32
DP		 841#define CRB_WIN_LOCK_TIMEOUT 100000000
842
843static int crb_win_lock(struct netxen_adapter *adapter)
844{
845 int done = 0, timeout = 0;
846
847 while (!done) {
848 /* acquire semaphore3 from PCI HW block */
849 adapter->hw_read_wx(adapter,
850 NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4);
851 if (done == 1)
852 break;
853 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
854 return -1;
855 timeout++;
856 udelay(1);
857 }
858 netxen_crb_writelit_adapter(adapter,
859 NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
860 return 0;
861}
862
863static void crb_win_unlock(struct netxen_adapter *adapter)
864{
865 int val;
866
867 adapter->hw_read_wx(adapter,
868 NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4);
869}
870
3d396eb1
AK		 871/*
872 * Changes the CRB window to the specified window.
873 */
3ce06a32
DP		 874void
875netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
3d396eb1
AK		 876{
877 void __iomem *offset;
878 u32 tmp;
879 int count = 0;
e4c93c81 880 uint8_t func = adapter->ahw.pci_func;
3d396eb1
AK		 881
882 if (adapter->curr_window == wndw)
883 return;
3d396eb1
AK		 884 /*
885 * Move the CRB window.
886 * We need to write to the "direct access" region of PCI
887 * to avoid a race condition where the window register has
888 * not been successfully written across CRB before the target
889 * register address is received by PCI. The direct region bypasses
890 * the CRB bus.
891 */
e4c93c81
DP		 892 offset = PCI_OFFSET_SECOND_RANGE(adapter,
893 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
3d396eb1
AK		 894
895 if (wndw & 0x1)
896 wndw = NETXEN_WINDOW_ONE;
897
898 writel(wndw, offset);
899
900 /* MUST make sure window is set before we forge on... */
901 while ((tmp = readl(offset)) != wndw) {
902 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
903 "registered properly: 0x%08x.\n",
3ce06a32 904 netxen_nic_driver_name, __func__, tmp);
3d396eb1
AK		 905 mdelay(1);
906 if (count >= 10)
907 break;
908 count++;
909 }
910
6c80b18d
MT		 911 if (wndw == NETXEN_WINDOW_ONE)
912 adapter->curr_window = 1;
913 else
914 adapter->curr_window = 0;
3d396eb1
AK		 915}
916
3ce06a32
DP		 917/*
918 * Return -1 if off is not valid,
919 * 1 if window access is needed. 'off' is set to offset from
920 * CRB space in 128M pci map
921 * 0 if no window access is needed. 'off' is set to 2M addr
922 * In: 'off' is offset from base in 128M pci map
923 */
924static int
925netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
926 ulong *off, int len)
927{
928 unsigned long end = *off + len;
929 crb_128M_2M_sub_block_map_t *m;
930
931
932 if (*off >= NETXEN_CRB_MAX)
933 return -1;
934
935 if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) {
936 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
937 (ulong)adapter->ahw.pci_base0;
938 return 0;
939 }
940
941 if (*off < NETXEN_PCI_CRBSPACE)
942 return -1;
943
944 *off -= NETXEN_PCI_CRBSPACE;
945 end = *off + len;
946
947 /*
948 * Try direct map
949 */
950 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
951
952 if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) {
953 *off = *off + m->start_2M - m->start_128M +
954 (ulong)adapter->ahw.pci_base0;
955 return 0;
956 }
957
958 /*
959 * Not in direct map, use crb window
960 */
961 return 1;
962}
963
964/*
965 * In: 'off' is offset from CRB space in 128M pci map
966 * Out: 'off' is 2M pci map addr
967 * side effect: lock crb window
968 */
969static void
970netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
971{
972 u32 win_read;
973
974 adapter->crb_win = CRB_HI(*off);
d8313ce0 975 writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M));
3ce06a32
DP		 976 /*
977 * Read back value to make sure write has gone through before trying
978 * to use it.
979 */
d8313ce0 980 win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M);
3ce06a32
DP		 981 if (win_read != adapter->crb_win) {
982 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
983 "Read crbwin (0x%x), off=0x%lx\n",
984 __func__, adapter->crb_win, win_read, *off);
985 }
986 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
987 (ulong)adapter->ahw.pci_base0;
988}
989
ba599d4f
DP		 990static int
991netxen_do_load_firmware(struct netxen_adapter *adapter, const char *fwname,
992 const struct firmware *fw)
3d396eb1 993{
ba599d4f
DP		 994 u64 *ptr64;
995 u32 i, flashaddr, size;
996 struct pci_dev *pdev = adapter->pdev;
2956640d 997
ba599d4f
DP		 998 if (fw)
999 dev_info(&pdev->dev, "loading firmware from file %s\n", fwname);
1000 else
1001 dev_info(&pdev->dev, "loading firmware from flash\n");
3d396eb1 1002
2956640d
DP		 1003 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1004 adapter->pci_write_normalize(adapter,
3ce06a32 1005 NETXEN_ROMUSB_GLB_CAS_RST, 1);
3d396eb1 1006
ba599d4f
DP		 1007 if (fw) {
1008 __le64 data;
1009
1010 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
1011
1012 ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
1013 flashaddr = NETXEN_BOOTLD_START;
1014
1015 for (i = 0; i < size; i++) {
1016 data = cpu_to_le64(ptr64[i]);
1017 adapter->pci_mem_write(adapter, flashaddr, &data, 8);
1018 flashaddr += 8;
1019 }
1020
1021 size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
1022 size = (__force u32)cpu_to_le32(size) / 8;
1023
1024 ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
1025 flashaddr = NETXEN_IMAGE_START;
1026
1027 for (i = 0; i < size; i++) {
1028 data = cpu_to_le64(ptr64[i]);
1029
1030 if (adapter->pci_mem_write(adapter,
1031 flashaddr, &data, 8))
1032 return -EIO;
1033
1034 flashaddr += 8;
1035 }
1036 } else {
1037 u32 data;
1038
1039 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 4;
1040 flashaddr = NETXEN_BOOTLD_START;
1041
1042 for (i = 0; i < size; i++) {
1043 if (netxen_rom_fast_read(adapter,
1044 flashaddr, (int *)&data) != 0)
1045 return -EIO;
96acb6eb 1046
ba599d4f
DP		 1047 if (adapter->pci_mem_write(adapter,
1048 flashaddr, &data, 4))
1049 return -EIO;
1050
1051 flashaddr += 4;
1052 }
3d396eb1 1053 }
2956640d
DP		 1054 msleep(1);
1055
1056 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1057 adapter->pci_write_normalize(adapter,
1058 NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
1059 else {
1060 adapter->pci_write_normalize(adapter,
3ce06a32 1061 NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
2956640d 1062 adapter->pci_write_normalize(adapter,
3ce06a32 1063 NETXEN_ROMUSB_GLB_CAS_RST, 0);
2956640d 1064 }
3d396eb1 1065
96acb6eb 1066 return 0;
3d396eb1
AK		 1067}
1068
ba599d4f
DP		 1069static int
1070netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname,
1071 const struct firmware *fw)
1072{
1073 __le32 val;
1074 u32 major, minor, build, ver, min_ver, bios;
1075 struct pci_dev *pdev = adapter->pdev;
1076
1077 if (fw->size < NX_FW_MIN_SIZE)
1078 return -EINVAL;
1079
1080 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
1081 if ((__force u32)val != NETXEN_BDINFO_MAGIC)
1082 return -EINVAL;
1083
1084 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
1085 major = (__force u32)val & 0xff;
1086 minor = ((__force u32)val >> 8) & 0xff;
1087 build = (__force u32)val >> 16;
1088
1089 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1090 min_ver = NETXEN_VERSION_CODE(4, 0, 216);
1091 else
1092 min_ver = NETXEN_VERSION_CODE(3, 4, 216);
1093
1094 ver = NETXEN_VERSION_CODE(major, minor, build);
1095
1096 if ((major > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
1097 dev_err(&pdev->dev,
1098 "%s: firmware version %d.%d.%d unsupported\n",
1099 fwname, major, minor, build);
1100 return -EINVAL;
1101 }
1102
1103 val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
1104 netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
1105 if ((__force u32)val != bios) {
1106 dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
1107 fwname);
1108 return -EINVAL;
1109 }
1110
567c6c4e
DP		 1111 /* check if flashed firmware is newer */
1112 if (netxen_rom_fast_read(adapter,
1113 NX_FW_VERSION_OFFSET, (int *)&val))
1114 return -EIO;
1115 major = (__force u32)val & 0xff;
1116 minor = ((__force u32)val >> 8) & 0xff;
1117 build = (__force u32)val >> 16;
1118 if (NETXEN_VERSION_CODE(major, minor, build) > ver)
1119 return -EINVAL;
1120
ba599d4f
DP		 1121 netxen_nic_reg_write(adapter, NETXEN_CAM_RAM(0x1fc),
1122 NETXEN_BDINFO_MAGIC);
1123 return 0;
1124}
1125
bd257ed9
DP		 1126static char *fw_name[] = { "nxromimg.bin", "nx3fwct.bin", "nx3fwmn.bin" };
1127
ba599d4f
DP		 1128int netxen_load_firmware(struct netxen_adapter *adapter)
1129{
1130 u32 capability, flashed_ver;
1131 const struct firmware *fw;
bd257ed9 1132 int fw_type;
ba599d4f
DP		 1133 struct pci_dev *pdev = adapter->pdev;
1134 int rc = 0;
1135
1136 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
bd257ed9 1137 fw_type = NX_P2_MN_ROMIMAGE;
ba599d4f 1138 goto request_fw;
bd257ed9
DP		 1139 } else {
1140 fw_type = NX_P3_CT_ROMIMAGE;
567c6c4e
DP		 1141 goto request_fw;
1142 }
1143
1144request_mn:
ba599d4f
DP		 1145 capability = 0;
1146
1147 netxen_rom_fast_read(adapter,
1148 NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
1149 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
1150 adapter->hw_read_wx(adapter,
1151 NX_PEG_TUNE_CAPABILITY, &capability, 4);
1152 if (capability & NX_PEG_TUNE_MN_PRESENT) {
bd257ed9 1153 fw_type = NX_P3_MN_ROMIMAGE;
ba599d4f
DP		 1154 goto request_fw;
1155 }
1156 }
1157
ba599d4f 1158request_fw:
bd257ed9 1159 rc = request_firmware(&fw, fw_name[fw_type], &pdev->dev);
ba599d4f 1160 if (rc != 0) {
bd257ed9 1161 if (fw_type == NX_P3_CT_ROMIMAGE) {
ba599d4f 1162 msleep(1);
567c6c4e 1163 goto request_mn;
ba599d4f
DP		 1164 }
1165
1166 fw = NULL;
1167 goto load_fw;
1168 }
1169
bd257ed9 1170 rc = netxen_validate_firmware(adapter, fw_name[fw_type], fw);
ba599d4f
DP		 1171 if (rc != 0) {
1172 release_firmware(fw);
1173
bd257ed9 1174 if (fw_type == NX_P3_CT_ROMIMAGE) {
ba599d4f 1175 msleep(1);
567c6c4e 1176 goto request_mn;
ba599d4f
DP		 1177 }
1178
1179 fw = NULL;
1180 }
1181
1182load_fw:
bd257ed9 1183 rc = netxen_do_load_firmware(adapter, fw_name[fw_type], fw);
ba599d4f
DP		 1184
1185 if (fw)
1186 release_firmware(fw);
1187 return rc;
1188}
1189
3d396eb1 1190int
3ce06a32
DP		 1191netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1192 ulong off, void *data, int len)
3d396eb1
AK		 1193{
1194 void __iomem *addr;
1195
d8313ce0
DP		 1196 BUG_ON(len != 4);
1197
3d396eb1
AK		 1198 if (ADDR_IN_WINDOW1(off)) {
1199 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1200 } else { /* Window 0 */
cb8011ad 1201 addr = pci_base_offset(adapter, off);
3ce06a32 1202 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
3d396eb1
AK		 1203 }
1204
cb8011ad 1205 if (!addr) {
3ce06a32 1206 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
cb8011ad
AK		 1207 return 1;
1208 }
1209
d8313ce0 1210 writel(*(u32 *) data, addr);
3d396eb1 1211
3d396eb1 1212 if (!ADDR_IN_WINDOW1(off))
3ce06a32 1213 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
3d396eb1
AK		 1214
1215 return 0;
1216}
1217
1218int
3ce06a32
DP		 1219netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1220 ulong off, void *data, int len)
3d396eb1
AK		 1221{
1222 void __iomem *addr;
1223
d8313ce0
DP		 1224 BUG_ON(len != 4);
1225
3d396eb1
AK		 1226 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1227 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1228 } else { /* Window 0 */
cb8011ad 1229 addr = pci_base_offset(adapter, off);
3ce06a32 1230 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
3d396eb1
AK		 1231 }
1232
cb8011ad 1233 if (!addr) {
3ce06a32 1234 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
cb8011ad
AK		 1235 return 1;
1236 }
d8313ce0
DP		 1237
1238 *(u32 *)data = readl(addr);
3d396eb1
AK		 1239
1240 if (!ADDR_IN_WINDOW1(off))
3ce06a32 1241 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
3d396eb1
AK		 1242
1243 return 0;
1244}
1245
3ce06a32
DP		 1246int
1247netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1248 ulong off, void *data, int len)
1249{
1250 unsigned long flags = 0;
1251 int rv;
3d396eb1 1252
d8313ce0
DP		 1253 BUG_ON(len != 4);
1254
3ce06a32 1255 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
3d396eb1 1256
3ce06a32
DP		 1257 if (rv == -1) {
1258 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1259 __func__, off);
1260 dump_stack();
1261 return -1;
1262 }
1263
1264 if (rv == 1) {
1265 write_lock_irqsave(&adapter->adapter_lock, flags);
1266 crb_win_lock(adapter);
1267 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
d8313ce0 1268 writel(*(uint32_t *)data, (void __iomem *)off);
3ce06a32
DP		 1269 crb_win_unlock(adapter);
1270 write_unlock_irqrestore(&adapter->adapter_lock, flags);
d8313ce0
DP		 1271 } else
1272 writel(*(uint32_t *)data, (void __iomem *)off);
1273
3ce06a32
DP		 1274
1275 return 0;
3d396eb1
AK		 1276}
1277
3ce06a32
DP		 1278int
1279netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1280 ulong off, void *data, int len)
1281{
1282 unsigned long flags = 0;
1283 int rv;
3d396eb1 1284
d8313ce0
DP		 1285 BUG_ON(len != 4);
1286
3ce06a32
DP		 1287 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1288
1289 if (rv == -1) {
1290 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1291 __func__, off);
1292 dump_stack();
1293 return -1;
1294 }
1295
1296 if (rv == 1) {
1297 write_lock_irqsave(&adapter->adapter_lock, flags);
1298 crb_win_lock(adapter);
1299 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
d8313ce0 1300 *(uint32_t *)data = readl((void __iomem *)off);
3ce06a32
DP		 1301 crb_win_unlock(adapter);
1302 write_unlock_irqrestore(&adapter->adapter_lock, flags);
d8313ce0
DP		 1303 } else
1304 *(uint32_t *)data = readl((void __iomem *)off);
3ce06a32
DP		 1305
1306 return 0;
1307}
1308
1309void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
1310{
1311 adapter->hw_write_wx(adapter, off, &val, 4);
1312}
1313
1314int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
1315{
1316 int val;
1317 adapter->hw_read_wx(adapter, off, &val, 4);
3d396eb1
AK		 1318 return val;
1319}
1320
1321/* Change the window to 0, write and change back to window 1. */
1322void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
1323{
3ce06a32 1324 adapter->hw_write_wx(adapter, index, &value, 4);
3d396eb1
AK		 1325}
1326
1327/* Change the window to 0, read and change back to window 1. */
3ce06a32 1328void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value)
3d396eb1 1329{
3ce06a32
DP		 1330 adapter->hw_read_wx(adapter, index, value, 4);
1331}
3d396eb1 1332
3ce06a32
DP		 1333void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value)
1334{
1335 adapter->hw_write_wx(adapter, index, &value, 4);
1336}
1337
1338void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value)
1339{
1340 adapter->hw_read_wx(adapter, index, value, 4);
1341}
1342
1343/*
1344 * check memory access boundary.
1345 * used by test agent. support ddr access only for now
1346 */
1347static unsigned long
1348netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1349 unsigned long long addr, int size)
1350{
1351 if (!ADDR_IN_RANGE(addr,
1352 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1353 !ADDR_IN_RANGE(addr+size-1,
1354 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1355 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1356 return 0;
1357 }
3d396eb1 1358
3ce06a32 1359 return 1;
3d396eb1
AK		 1360}
1361
4790654c 1362static int netxen_pci_set_window_warning_count;
3d396eb1 1363
3ce06a32
DP		 1364unsigned long
1365netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1366 unsigned long long addr)
3d396eb1 1367{
e4c93c81 1368 void __iomem *offset;
3d396eb1 1369 int window;
3ce06a32 1370 unsigned long long qdr_max;
e4c93c81 1371 uint8_t func = adapter->ahw.pci_func;
3d396eb1 1372
3ce06a32
DP		 1373 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1374 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1375 } else {
1376 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1377 }
1378
3d396eb1
AK		 1379 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1380 /* DDR network side */
1381 addr -= NETXEN_ADDR_DDR_NET;
1382 window = (addr >> 25) & 0x3ff;
3ce06a32
DP		 1383 if (adapter->ahw.ddr_mn_window != window) {
1384 adapter->ahw.ddr_mn_window = window;
e4c93c81
DP		 1385 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1386 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1387 writel(window, offset);
3d396eb1 1388 /* MUST make sure window is set before we forge on... */
e4c93c81 1389 readl(offset);
3d396eb1 1390 }
cb8011ad 1391 addr -= (window * NETXEN_WINDOW_ONE);
3d396eb1
AK		 1392 addr += NETXEN_PCI_DDR_NET;
1393 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1394 addr -= NETXEN_ADDR_OCM0;
1395 addr += NETXEN_PCI_OCM0;
1396 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1397 addr -= NETXEN_ADDR_OCM1;
1398 addr += NETXEN_PCI_OCM1;
3ce06a32 1399 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
3d396eb1
AK		 1400 /* QDR network side */
1401 addr -= NETXEN_ADDR_QDR_NET;
1402 window = (addr >> 22) & 0x3f;
3ce06a32
DP		 1403 if (adapter->ahw.qdr_sn_window != window) {
1404 adapter->ahw.qdr_sn_window = window;
e4c93c81
DP		 1405 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1406 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1407 writel((window << 22), offset);
3d396eb1 1408 /* MUST make sure window is set before we forge on... */
e4c93c81 1409 readl(offset);
3d396eb1
AK		 1410 }
1411 addr -= (window * 0x400000);
1412 addr += NETXEN_PCI_QDR_NET;
1413 } else {
1414 /*
1415 * peg gdb frequently accesses memory that doesn't exist,
1416 * this limits the chit chat so debugging isn't slowed down.
1417 */
1418 if ((netxen_pci_set_window_warning_count++ < 8)
1419 || (netxen_pci_set_window_warning_count % 64 == 0))
1420 printk("%s: Warning:netxen_nic_pci_set_window()"
1421 " Unknown address range!\n",
1422 netxen_nic_driver_name);
3ce06a32
DP		 1423 addr = -1UL;
1424 }
1425 return addr;
1426}
1427
1428/*
1429 * Note : only 32-bit writes!
1430 */
1431int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1432 u64 off, u32 data)
1433{
1434 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1435 return 0;
1436}
1437
1438u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1439{
1440 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1441}
1442
1443void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1444 u64 off, u32 data)
1445{
1446 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1447}
1448
1449u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off)
1450{
1451 return readl(NETXEN_CRB_NORMALIZE(adapter, off));
1452}
1453
1454unsigned long
1455netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1456 unsigned long long addr)
1457{
1458 int window;
1459 u32 win_read;
3d396eb1 1460
3ce06a32
DP		 1461 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1462 /* DDR network side */
1463 window = MN_WIN(addr);
1464 adapter->ahw.ddr_mn_window = window;
1465 adapter->hw_write_wx(adapter,
1466 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1467 &window, 4);
1468 adapter->hw_read_wx(adapter,
1469 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1470 &win_read, 4);
1471 if ((win_read << 17) != window) {
1472 printk(KERN_INFO "Written MNwin (0x%x) != "
1473 "Read MNwin (0x%x)\n", window, win_read);
1474 }
1475 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1476 } else if (ADDR_IN_RANGE(addr,
1477 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1478 if ((addr & 0x00ff800) == 0xff800) {
1479 printk("%s: QM access not handled.\n", __func__);
1480 addr = -1UL;
1481 }
1482
1483 window = OCM_WIN(addr);
1484 adapter->ahw.ddr_mn_window = window;
1485 adapter->hw_write_wx(adapter,
1486 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1487 &window, 4);
1488 adapter->hw_read_wx(adapter,
1489 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1490 &win_read, 4);
1491 if ((win_read >> 7) != window) {
1492 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1493 "Read OCMwin (0x%x)\n",
1494 __func__, window, win_read);
1495 }
1496 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1497
1498 } else if (ADDR_IN_RANGE(addr,
1499 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1500 /* QDR network side */
1501 window = MS_WIN(addr);
1502 adapter->ahw.qdr_sn_window = window;
1503 adapter->hw_write_wx(adapter,
1504 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1505 &window, 4);
1506 adapter->hw_read_wx(adapter,
1507 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1508 &win_read, 4);
1509 if (win_read != window) {
1510 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1511 "Read MSwin (0x%x)\n",
1512 __func__, window, win_read);
1513 }
1514 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1515
1516 } else {
1517 /*
1518 * peg gdb frequently accesses memory that doesn't exist,
1519 * this limits the chit chat so debugging isn't slowed down.
1520 */
1521 if ((netxen_pci_set_window_warning_count++ < 8)
1522 || (netxen_pci_set_window_warning_count%64 == 0)) {
1523 printk("%s: Warning:%s Unknown address range!\n",
1524 __func__, netxen_nic_driver_name);
1525}
1526 addr = -1UL;
3d396eb1
AK		 1527 }
1528 return addr;
1529}
1530
3ce06a32
DP		 1531static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1532 unsigned long long addr)
1533{
1534 int window;
1535 unsigned long long qdr_max;
1536
1537 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1538 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1539 else
1540 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1541
1542 if (ADDR_IN_RANGE(addr,
1543 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1544 /* DDR network side */
1545 BUG(); /* MN access can not come here */
1546 } else if (ADDR_IN_RANGE(addr,
1547 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1548 return 1;
1549 } else if (ADDR_IN_RANGE(addr,
1550 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1551 return 1;
1552 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1553 /* QDR network side */
1554 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1555 if (adapter->ahw.qdr_sn_window == window)
1556 return 1;
1557 }
1558
1559 return 0;
1560}
1561
1562static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1563 u64 off, void *data, int size)
1564{
1565 unsigned long flags;
d8313ce0 1566 void __iomem *addr, *mem_ptr = NULL;
3ce06a32
DP		 1567 int ret = 0;
1568 u64 start;
3ce06a32
DP		 1569 unsigned long mem_base;
1570 unsigned long mem_page;
1571
1572 write_lock_irqsave(&adapter->adapter_lock, flags);
1573
1574 /*
1575 * If attempting to access unknown address or straddle hw windows,
1576 * do not access.
1577 */
1578 start = adapter->pci_set_window(adapter, off);
1579 if ((start == -1UL) ||
1580 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1581 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1582 printk(KERN_ERR "%s out of bound pci memory access. "
11a859e5
AM		 1583 "offset is 0x%llx\n", netxen_nic_driver_name,
1584 (unsigned long long)off);
3ce06a32
DP		 1585 return -1;
1586 }
1587
d8313ce0 1588 addr = pci_base_offset(adapter, start);
3ce06a32
DP		 1589 if (!addr) {
1590 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1591 mem_base = pci_resource_start(adapter->pdev, 0);
1592 mem_page = start & PAGE_MASK;
1593 /* Map two pages whenever user tries to access addresses in two
1594 consecutive pages.
1595 */
1596 if (mem_page != ((start + size - 1) & PAGE_MASK))
1597 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1598 else
1599 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
f8057b7f 1600 if (mem_ptr == NULL) {
3ce06a32
DP		 1601 *(uint8_t *)data = 0;
1602 return -1;
1603 }
1604 addr = mem_ptr;
1605 addr += start & (PAGE_SIZE - 1);
1606 write_lock_irqsave(&adapter->adapter_lock, flags);
1607 }
1608
1609 switch (size) {
1610 case 1:
1611 *(uint8_t *)data = readb(addr);
1612 break;
1613 case 2:
1614 *(uint16_t *)data = readw(addr);
1615 break;
1616 case 4:
1617 *(uint32_t *)data = readl(addr);
1618 break;
1619 case 8:
1620 *(uint64_t *)data = readq(addr);
1621 break;
1622 default:
1623 ret = -1;
1624 break;
1625 }
1626 write_unlock_irqrestore(&adapter->adapter_lock, flags);
3ce06a32
DP		 1627
1628 if (mem_ptr)
1629 iounmap(mem_ptr);
1630 return ret;
1631}
1632
1633static int
1634netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1635 void *data, int size)
1636{
1637 unsigned long flags;
d8313ce0 1638 void __iomem *addr, *mem_ptr = NULL;
3ce06a32
DP		 1639 int ret = 0;
1640 u64 start;
3ce06a32
DP		 1641 unsigned long mem_base;
1642 unsigned long mem_page;
1643
1644 write_lock_irqsave(&adapter->adapter_lock, flags);
1645
1646 /*
1647 * If attempting to access unknown address or straddle hw windows,
1648 * do not access.
1649 */
1650 start = adapter->pci_set_window(adapter, off);
1651 if ((start == -1UL) ||
1652 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1653 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1654 printk(KERN_ERR "%s out of bound pci memory access. "
11a859e5
AM		 1655 "offset is 0x%llx\n", netxen_nic_driver_name,
1656 (unsigned long long)off);
3ce06a32
DP		 1657 return -1;
1658 }
1659
d8313ce0 1660 addr = pci_base_offset(adapter, start);
3ce06a32
DP		 1661 if (!addr) {
1662 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1663 mem_base = pci_resource_start(adapter->pdev, 0);
1664 mem_page = start & PAGE_MASK;
1665 /* Map two pages whenever user tries to access addresses in two
1666 * consecutive pages.
1667 */
1668 if (mem_page != ((start + size - 1) & PAGE_MASK))
1669 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1670 else
1671 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
f8057b7f 1672 if (mem_ptr == NULL)
3ce06a32
DP		 1673 return -1;
1674 addr = mem_ptr;
1675 addr += start & (PAGE_SIZE - 1);
1676 write_lock_irqsave(&adapter->adapter_lock, flags);
1677 }
1678
1679 switch (size) {
1680 case 1:
1681 writeb(*(uint8_t *)data, addr);
1682 break;
1683 case 2:
1684 writew(*(uint16_t *)data, addr);
1685 break;
1686 case 4:
1687 writel(*(uint32_t *)data, addr);
1688 break;
1689 case 8:
1690 writeq(*(uint64_t *)data, addr);
1691 break;
1692 default:
1693 ret = -1;
1694 break;
1695 }
1696 write_unlock_irqrestore(&adapter->adapter_lock, flags);
3ce06a32
DP		 1697 if (mem_ptr)
1698 iounmap(mem_ptr);
1699 return ret;
1700}
1701
1702#define MAX_CTL_CHECK 1000
1703
1704int
1705netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1706 u64 off, void *data, int size)
1707{
d8313ce0 1708 unsigned long flags;
3ce06a32
DP		 1709 int i, j, ret = 0, loop, sz[2], off0;
1710 uint32_t temp;
1711 uint64_t off8, tmpw, word[2] = {0, 0};
d8313ce0 1712 void __iomem *mem_crb;
3ce06a32
DP		 1713
1714 /*
1715 * If not MN, go check for MS or invalid.
1716 */
1717 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1718 return netxen_nic_pci_mem_write_direct(adapter,
1719 off, data, size);
1720
1721 off8 = off & 0xfffffff8;
1722 off0 = off & 0x7;
1723 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1724 sz[1] = size - sz[0];
1725 loop = ((off0 + size - 1) >> 3) + 1;
d8313ce0 1726 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
3ce06a32
DP		 1727
1728 if ((size != 8) || (off0 != 0)) {
1729 for (i = 0; i < loop; i++) {
1730 if (adapter->pci_mem_read(adapter,
1731 off8 + (i << 3), &word[i], 8))
1732 return -1;
1733 }
1734 }
1735
1736 switch (size) {
1737 case 1:
1738 tmpw = *((uint8_t *)data);
1739 break;
1740 case 2:
1741 tmpw = *((uint16_t *)data);
1742 break;
1743 case 4:
1744 tmpw = *((uint32_t *)data);
1745 break;
1746 case 8:
1747 default:
1748 tmpw = *((uint64_t *)data);
1749 break;
1750 }
1751 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1752 word[0] |= tmpw << (off0 * 8);
1753
1754 if (loop == 2) {
1755 word[1] &= ~(~0ULL << (sz[1] * 8));
1756 word[1] |= tmpw >> (sz[0] * 8);
1757 }
1758
1759 write_lock_irqsave(&adapter->adapter_lock, flags);
1760 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1761
1762 for (i = 0; i < loop; i++) {
1763 writel((uint32_t)(off8 + (i << 3)),
d8313ce0 1764 (mem_crb+MIU_TEST_AGT_ADDR_LO));
3ce06a32 1765 writel(0,
d8313ce0 1766 (mem_crb+MIU_TEST_AGT_ADDR_HI));
3ce06a32 1767 writel(word[i] & 0xffffffff,
d8313ce0 1768 (mem_crb+MIU_TEST_AGT_WRDATA_LO));
3ce06a32 1769 writel((word[i] >> 32) & 0xffffffff,
d8313ce0 1770 (mem_crb+MIU_TEST_AGT_WRDATA_HI));
3ce06a32 1771 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
d8313ce0 1772 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32 1773 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
d8313ce0 1774 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1775
1776 for (j = 0; j < MAX_CTL_CHECK; j++) {
1777 temp = readl(
d8313ce0 1778 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1779 if ((temp & MIU_TA_CTL_BUSY) == 0)
1780 break;
1781 }
1782
1783 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 1784 if (printk_ratelimit())
1785 dev_err(&adapter->pdev->dev,
1786 "failed to write through agent\n");
3ce06a32
DP		 1787 ret = -1;
1788 break;
1789 }
1790 }
1791
1792 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1793 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1794 return ret;
1795}
1796
1797int
1798netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1799 u64 off, void *data, int size)
1800{
d8313ce0 1801 unsigned long flags;
3ce06a32
DP		 1802 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1803 uint32_t temp;
1804 uint64_t off8, val, word[2] = {0, 0};
d8313ce0 1805 void __iomem *mem_crb;
3ce06a32
DP		 1806
1807
1808 /*
1809 * If not MN, go check for MS or invalid.
1810 */
1811 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1812 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1813
1814 off8 = off & 0xfffffff8;
1815 off0[0] = off & 0x7;
1816 off0[1] = 0;
1817 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1818 sz[1] = size - sz[0];
1819 loop = ((off0[0] + size - 1) >> 3) + 1;
d8313ce0 1820 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
3ce06a32
DP		 1821
1822 write_lock_irqsave(&adapter->adapter_lock, flags);
1823 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1824
1825 for (i = 0; i < loop; i++) {
1826 writel((uint32_t)(off8 + (i << 3)),
d8313ce0 1827 (mem_crb+MIU_TEST_AGT_ADDR_LO));
3ce06a32 1828 writel(0,
d8313ce0 1829 (mem_crb+MIU_TEST_AGT_ADDR_HI));
3ce06a32 1830 writel(MIU_TA_CTL_ENABLE,
d8313ce0 1831 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32 1832 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
d8313ce0 1833 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1834
1835 for (j = 0; j < MAX_CTL_CHECK; j++) {
1836 temp = readl(
d8313ce0 1837 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1838 if ((temp & MIU_TA_CTL_BUSY) == 0)
1839 break;
1840 }
1841
1842 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 1843 if (printk_ratelimit())
1844 dev_err(&adapter->pdev->dev,
1845 "failed to read through agent\n");
3ce06a32
DP		 1846 break;
1847 }
1848
1849 start = off0[i] >> 2;
1850 end = (off0[i] + sz[i] - 1) >> 2;
1851 for (k = start; k <= end; k++) {
1852 word[i] |= ((uint64_t) readl(
d8313ce0 1853 (mem_crb +
3ce06a32
DP		 1854 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1855 }
1856 }
1857
1858 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1859 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1860
1861 if (j >= MAX_CTL_CHECK)
1862 return -1;
1863
1864 if (sz[0] == 8) {
1865 val = word[0];
1866 } else {
1867 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1868 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1869 }
1870
1871 switch (size) {
1872 case 1:
1873 *(uint8_t *)data = val;
1874 break;
1875 case 2:
1876 *(uint16_t *)data = val;
1877 break;
1878 case 4:
1879 *(uint32_t *)data = val;
1880 break;
1881 case 8:
1882 *(uint64_t *)data = val;
1883 break;
1884 }
3ce06a32
DP		 1885 return 0;
1886}
1887
1888int
1889netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1890 u64 off, void *data, int size)
1891{
1892 int i, j, ret = 0, loop, sz[2], off0;
1893 uint32_t temp;
1894 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1895
1896 /*
1897 * If not MN, go check for MS or invalid.
1898 */
1899 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1900 mem_crb = NETXEN_CRB_QDR_NET;
1901 else {
1902 mem_crb = NETXEN_CRB_DDR_NET;
1903 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1904 return netxen_nic_pci_mem_write_direct(adapter,
1905 off, data, size);
1906 }
1907
1908 off8 = off & 0xfffffff8;
1909 off0 = off & 0x7;
1910 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1911 sz[1] = size - sz[0];
1912 loop = ((off0 + size - 1) >> 3) + 1;
1913
1914 if ((size != 8) || (off0 != 0)) {
1915 for (i = 0; i < loop; i++) {
1916 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1917 &word[i], 8))
1918 return -1;
1919 }
1920 }
1921
1922 switch (size) {
1923 case 1:
1924 tmpw = *((uint8_t *)data);
1925 break;
1926 case 2:
1927 tmpw = *((uint16_t *)data);
1928 break;
1929 case 4:
1930 tmpw = *((uint32_t *)data);
1931 break;
1932 case 8:
1933 default:
1934 tmpw = *((uint64_t *)data);
1935 break;
1936 }
1937
1938 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1939 word[0] |= tmpw << (off0 * 8);
1940
1941 if (loop == 2) {
1942 word[1] &= ~(~0ULL << (sz[1] * 8));
1943 word[1] |= tmpw >> (sz[0] * 8);
1944 }
1945
1946 /*
1947 * don't lock here - write_wx gets the lock if each time
1948 * write_lock_irqsave(&adapter->adapter_lock, flags);
1949 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1950 */
1951
1952 for (i = 0; i < loop; i++) {
1953 temp = off8 + (i << 3);
1954 adapter->hw_write_wx(adapter,
1955 mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4);
1956 temp = 0;
1957 adapter->hw_write_wx(adapter,
1958 mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4);
1959 temp = word[i] & 0xffffffff;
1960 adapter->hw_write_wx(adapter,
1961 mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4);
1962 temp = (word[i] >> 32) & 0xffffffff;
1963 adapter->hw_write_wx(adapter,
1964 mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4);
1965 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1966 adapter->hw_write_wx(adapter,
1967 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1968 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1969 adapter->hw_write_wx(adapter,
1970 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1971
1972 for (j = 0; j < MAX_CTL_CHECK; j++) {
1973 adapter->hw_read_wx(adapter,
1974 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1975 if ((temp & MIU_TA_CTL_BUSY) == 0)
1976 break;
1977 }
1978
1979 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 1980 if (printk_ratelimit())
1981 dev_err(&adapter->pdev->dev,
1982 "failed to write through agent\n");
3ce06a32
DP		 1983 ret = -1;
1984 break;
1985 }
1986 }
1987
1988 /*
1989 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1990 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1991 */
1992 return ret;
1993}
1994
1995int
1996netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1997 u64 off, void *data, int size)
1998{
1999 int i, j = 0, k, start, end, loop, sz[2], off0[2];
2000 uint32_t temp;
2001 uint64_t off8, val, mem_crb, word[2] = {0, 0};
2002
2003 /*
2004 * If not MN, go check for MS or invalid.
2005 */
2006
2007 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
2008 mem_crb = NETXEN_CRB_QDR_NET;
2009 else {
2010 mem_crb = NETXEN_CRB_DDR_NET;
2011 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
2012 return netxen_nic_pci_mem_read_direct(adapter,
2013 off, data, size);
2014 }
2015
2016 off8 = off & 0xfffffff8;
2017 off0[0] = off & 0x7;
2018 off0[1] = 0;
2019 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
2020 sz[1] = size - sz[0];
2021 loop = ((off0[0] + size - 1) >> 3) + 1;
2022
2023 /*
2024 * don't lock here - write_wx gets the lock if each time
2025 * write_lock_irqsave(&adapter->adapter_lock, flags);
2026 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
2027 */
2028
2029 for (i = 0; i < loop; i++) {
2030 temp = off8 + (i << 3);
2031 adapter->hw_write_wx(adapter,
2032 mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4);
2033 temp = 0;
2034 adapter->hw_write_wx(adapter,
2035 mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4);
2036 temp = MIU_TA_CTL_ENABLE;
2037 adapter->hw_write_wx(adapter,
2038 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
2039 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
2040 adapter->hw_write_wx(adapter,
2041 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
2042
2043 for (j = 0; j < MAX_CTL_CHECK; j++) {
2044 adapter->hw_read_wx(adapter,
2045 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
2046 if ((temp & MIU_TA_CTL_BUSY) == 0)
2047 break;
2048 }
2049
2050 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 2051 if (printk_ratelimit())
2052 dev_err(&adapter->pdev->dev,
2053 "failed to read through agent\n");
3ce06a32
DP		 2054 break;
2055 }
2056
2057 start = off0[i] >> 2;
2058 end = (off0[i] + sz[i] - 1) >> 2;
2059 for (k = start; k <= end; k++) {
2060 adapter->hw_read_wx(adapter,
2061 mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4);
2062 word[i] |= ((uint64_t)temp << (32 * k));
2063 }
2064 }
2065
2066 /*
2067 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
2068 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
2069 */
2070
2071 if (j >= MAX_CTL_CHECK)
2072 return -1;
2073
2074 if (sz[0] == 8) {
2075 val = word[0];
2076 } else {
2077 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
2078 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
2079 }
2080
2081 switch (size) {
2082 case 1:
2083 *(uint8_t *)data = val;
2084 break;
2085 case 2:
2086 *(uint16_t *)data = val;
2087 break;
2088 case 4:
2089 *(uint32_t *)data = val;
2090 break;
2091 case 8:
2092 *(uint64_t *)data = val;
2093 break;
2094 }
3ce06a32
DP		 2095 return 0;
2096}
2097
2098/*
2099 * Note : only 32-bit writes!
2100 */
2101int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
2102 u64 off, u32 data)
2103{
2104 adapter->hw_write_wx(adapter, off, &data, 4);
2105
2106 return 0;
2107}
2108
2109u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
2110{
2111 u32 temp;
2112 adapter->hw_read_wx(adapter, off, &temp, 4);
2113 return temp;
2114}
2115
2116void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
2117 u64 off, u32 data)
2118{
2119 adapter->hw_write_wx(adapter, off, &data, 4);
2120}
2121
2122u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off)
2123{
2124 u32 temp;
2125 adapter->hw_read_wx(adapter, off, &temp, 4);
2126 return temp;
2127}
2128
3d396eb1
AK		 2129int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2130{
1e2d0059
DP		 2131 int offset, board_type, magic, header_version;
2132 struct pci_dev *pdev = adapter->pdev;
3d396eb1 2133
1e2d0059
DP		 2134 offset = NETXEN_BRDCFG_START +
2135 offsetof(struct netxen_board_info, magic);
2136 if (netxen_rom_fast_read(adapter, offset, &magic))
2137 return -EIO;
3d396eb1 2138
1e2d0059
DP		 2139 offset = NETXEN_BRDCFG_START +
2140 offsetof(struct netxen_board_info, header_version);
2141 if (netxen_rom_fast_read(adapter, offset, &header_version))
2142 return -EIO;
2143
2144 if (magic != NETXEN_BDINFO_MAGIC ||
2145 header_version != NETXEN_BDINFO_VERSION) {
2146 dev_err(&pdev->dev,
2147 "invalid board config, magic=%08x, version=%08x\n",
2148 magic, header_version);
2149 return -EIO;
3d396eb1
AK		 2150 }
2151
1e2d0059
DP		 2152 offset = NETXEN_BRDCFG_START +
2153 offsetof(struct netxen_board_info, board_type);
2154 if (netxen_rom_fast_read(adapter, offset, &board_type))
2155 return -EIO;
2156
2157 adapter->ahw.board_type = board_type;
2158
2159 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
c7860a2a
DP		 2160 u32 gpio = netxen_nic_reg_read(adapter,
2161 NETXEN_ROMUSB_GLB_PAD_GPIO_I);
2162 if ((gpio & 0x8000) == 0)
1e2d0059 2163 board_type = NETXEN_BRDTYPE_P3_10G_TP;
c7860a2a
DP		 2164 }
2165
e98e3350 2166 switch (board_type) {
3d396eb1 2167 case NETXEN_BRDTYPE_P2_SB35_4G:
1e2d0059 2168 adapter->ahw.port_type = NETXEN_NIC_GBE;
3d396eb1
AK		 2169 break;
2170 case NETXEN_BRDTYPE_P2_SB31_10G:
2171 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
2172 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
2173 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
e4c93c81
DP		 2174 case NETXEN_BRDTYPE_P3_HMEZ:
2175 case NETXEN_BRDTYPE_P3_XG_LOM:
2176 case NETXEN_BRDTYPE_P3_10G_CX4:
2177 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
2178 case NETXEN_BRDTYPE_P3_IMEZ:
2179 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
a70f9393
DP		 2180 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
2181 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
e4c93c81
DP		 2182 case NETXEN_BRDTYPE_P3_10G_XFP:
2183 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1e2d0059 2184 adapter->ahw.port_type = NETXEN_NIC_XGBE;
3d396eb1
AK		 2185 break;
2186 case NETXEN_BRDTYPE_P1_BD:
2187 case NETXEN_BRDTYPE_P1_SB:
2188 case NETXEN_BRDTYPE_P1_SMAX:
2189 case NETXEN_BRDTYPE_P1_SOCK:
e4c93c81
DP		 2190 case NETXEN_BRDTYPE_P3_REF_QG:
2191 case NETXEN_BRDTYPE_P3_4_GB:
2192 case NETXEN_BRDTYPE_P3_4_GB_MM:
1e2d0059 2193 adapter->ahw.port_type = NETXEN_NIC_GBE;
3d396eb1 2194 break;
c7860a2a 2195 case NETXEN_BRDTYPE_P3_10G_TP:
1e2d0059 2196 adapter->ahw.port_type = (adapter->portnum < 2) ?
c7860a2a
DP		 2197 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
2198 break;
3d396eb1 2199 default:
1e2d0059
DP		 2200 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
2201 adapter->ahw.port_type = NETXEN_NIC_XGBE;
3d396eb1
AK		 2202 break;
2203 }
2204
1e2d0059 2205 return 0;
3d396eb1
AK		 2206}
2207
2208/* NIU access sections */
2209
3176ff3e 2210int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 2211{
9ad27643 2212 new_mtu += MTU_FUDGE_FACTOR;
3d396eb1 2213 netxen_nic_write_w0(adapter,
3276fbad
DP		 2214 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2215 new_mtu);
3d396eb1
AK		 2216 return 0;
2217}
2218
3176ff3e 2219int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 2220{
9ad27643 2221 new_mtu += MTU_FUDGE_FACTOR;
3276fbad 2222 if (adapter->physical_port == 0)
4790654c 2223 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
595e3fb8 2224 new_mtu);
4790654c 2225 else
595e3fb8
MT		 2226 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
2227 new_mtu);
3d396eb1
AK		 2228 return 0;
2229}
2230
3d396eb1 2231void
3ce06a32
DP		 2232netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
2233 unsigned long off, int data)
3d396eb1 2234{
3ce06a32 2235 adapter->hw_write_wx(adapter, off, &data, 4);
3d396eb1
AK		 2236}
2237
3176ff3e 2238void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
3d396eb1 2239{
a608ab9c
AV		 2240 __u32 status;
2241 __u32 autoneg;
24a7a455 2242 __u32 port_mode;
3d396eb1 2243
c7860a2a
DP		 2244 if (!netif_carrier_ok(adapter->netdev)) {
2245 adapter->link_speed = 0;
2246 adapter->link_duplex = -1;
2247 adapter->link_autoneg = AUTONEG_ENABLE;
2248 return;
2249 }
24a7a455 2250
1e2d0059 2251 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
24a7a455
DP		 2252 adapter->hw_read_wx(adapter,
2253 NETXEN_PORT_MODE_ADDR, &port_mode, 4);
2254 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2255 adapter->link_speed = SPEED_1000;
2256 adapter->link_duplex = DUPLEX_FULL;
2257 adapter->link_autoneg = AUTONEG_DISABLE;
2258 return;
2259 }
2260
80922fbc 2261 if (adapter->phy_read
24a7a455 2262 && adapter->phy_read(adapter,
3d396eb1
AK		 2263 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2264 &status) == 0) {
2265 if (netxen_get_phy_link(status)) {
2266 switch (netxen_get_phy_speed(status)) {
2267 case 0:
3176ff3e 2268 adapter->link_speed = SPEED_10;
3d396eb1
AK		 2269 break;
2270 case 1:
3176ff3e 2271 adapter->link_speed = SPEED_100;
3d396eb1
AK		 2272 break;
2273 case 2:
3176ff3e 2274 adapter->link_speed = SPEED_1000;
3d396eb1
AK		 2275 break;
2276 default:
c7860a2a 2277 adapter->link_speed = 0;
3d396eb1
AK		 2278 break;
2279 }
2280 switch (netxen_get_phy_duplex(status)) {
2281 case 0:
3176ff3e 2282 adapter->link_duplex = DUPLEX_HALF;
3d396eb1
AK		 2283 break;
2284 case 1:
3176ff3e 2285 adapter->link_duplex = DUPLEX_FULL;
3d396eb1
AK		 2286 break;
2287 default:
3176ff3e 2288 adapter->link_duplex = -1;
3d396eb1
AK		 2289 break;
2290 }
80922fbc 2291 if (adapter->phy_read
24a7a455 2292 && adapter->phy_read(adapter,
3d396eb1 2293 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
ed25ffa1 2294 &autoneg) != 0)
3176ff3e 2295 adapter->link_autoneg = autoneg;
3d396eb1
AK		 2296 } else
2297 goto link_down;
2298 } else {
2299 link_down:
c7860a2a 2300 adapter->link_speed = 0;
3176ff3e 2301 adapter->link_duplex = -1;
3d396eb1
AK		 2302 }
2303 }
2304}
2305
1e2d0059 2306void netxen_nic_get_firmware_info(struct netxen_adapter *adapter)
3d396eb1 2307{
1e2d0059 2308 u32 fw_major, fw_minor, fw_build;
cb8011ad 2309 char brd_name[NETXEN_MAX_SHORT_NAME];
8d74849b 2310 char serial_num[32];
fbb52f22 2311 int i, addr, val;
d8313ce0 2312 int *ptr32;
1e2d0059 2313 struct pci_dev *pdev = adapter->pdev;
dcd56fdb
DP		 2314
2315 adapter->driver_mismatch = 0;
2316
d8313ce0 2317 ptr32 = (int *)&serial_num;
dcd56fdb
DP		 2318 addr = NETXEN_USER_START +
2319 offsetof(struct netxen_new_user_info, serial_num);
2320 for (i = 0; i < 8; i++) {
fbb52f22
DP		 2321 if (netxen_rom_fast_read(adapter, addr, &val) == -1) {
2322 dev_err(&pdev->dev, "error reading board info\n");
dcd56fdb
DP		 2323 adapter->driver_mismatch = 1;
2324 return;
cb8011ad 2325 }
fbb52f22 2326 ptr32[i] = cpu_to_le32(val);
dcd56fdb
DP		 2327 addr += sizeof(u32);
2328 }
2329
3ce06a32
DP		 2330 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4);
2331 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4);
2332 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4);
8d74849b 2333
2956640d 2334 adapter->fw_major = fw_major;
1e2d0059 2335 adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build);
2956640d 2336
dcd56fdb 2337 if (adapter->portnum == 0) {
1e2d0059 2338 get_brd_name_by_type(adapter->ahw.board_type, brd_name);
cb8011ad 2339
11d89d63
DP		 2340 printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n",
2341 brd_name, serial_num, adapter->ahw.revision_id);
3d396eb1 2342 }
dcd56fdb 2343
1e2d0059 2344 if (adapter->fw_version < NETXEN_VERSION_CODE(3, 4, 216)) {
3d396eb1 2345 adapter->driver_mismatch = 1;
1e2d0059 2346 dev_warn(&pdev->dev, "firmware version %d.%d.%d unsupported\n",
58735567 2347 fw_major, fw_minor, fw_build);
dcd56fdb
DP		 2348 return;
2349 }
1e2d0059
DP		 2350
2351 dev_info(&pdev->dev, "firmware version %d.%d.%d\n",
2352 fw_major, fw_minor, fw_build);
2353
2354 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
2355 adapter->hw_read_wx(adapter,
2356 NETXEN_MIU_MN_CONTROL, &i, 4);
2357 adapter->ahw.cut_through = (i & 0x4) ? 1 : 0;
2358 dev_info(&pdev->dev, "firmware running in %s mode\n",
2359 adapter->ahw.cut_through ? "cut-through" : "legacy");
2360 }
3d396eb1
AK		 2361}
2362
0b72e659
DP		 2363int
2364netxen_nic_wol_supported(struct netxen_adapter *adapter)
2365{
2366 u32 wol_cfg;
2367
2368 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2369 return 0;
2370
2371 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG_NV);
2372 if (wol_cfg & (1UL << adapter->portnum)) {
2373 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG);
2374 if (wol_cfg & (1 << adapter->portnum))
2375 return 1;
2376 }
2377
2378 return 0;
2379}
Linux kernel - Deliverables
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