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3d396eb1 AK |
1 | /* |
2 | * Copyright (C) 2003 - 2006 NetXen, Inc. | |
3 | * All rights reserved. | |
80922fbc | 4 | * |
3d396eb1 AK |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
80922fbc | 19 | * |
3d396eb1 AK |
20 | * The full GNU General Public License is included in this distribution |
21 | * in the file called LICENSE. | |
80922fbc | 22 | * |
3d396eb1 AK |
23 | * Contact Information: |
24 | * info@netxen.com | |
25 | * NetXen, | |
26 | * 3965 Freedom Circle, Fourth floor, | |
27 | * Santa Clara, CA 95054 | |
28 | * | |
29 | * | |
30 | * Structures, enums, and macros for the MAC | |
31 | * | |
32 | */ | |
33 | ||
34 | #ifndef __NETXEN_NIC_HW_H_ | |
35 | #define __NETXEN_NIC_HW_H_ | |
36 | ||
37 | #include "netxen_nic_hdr.h" | |
38 | ||
39 | /* Hardware memory size of 128 meg */ | |
40 | #define NETXEN_MEMADDR_MAX (128 * 1024 * 1024) | |
41 | ||
42 | #ifndef readq | |
43 | static inline u64 readq(void __iomem * addr) | |
44 | { | |
45 | return readl(addr) | (((u64) readl(addr + 4)) << 32LL); | |
46 | } | |
47 | #endif | |
48 | ||
49 | #ifndef writeq | |
50 | static inline void writeq(u64 val, void __iomem * addr) | |
51 | { | |
52 | writel(((u32) (val)), (addr)); | |
53 | writel(((u32) (val >> 32)), (addr + 4)); | |
54 | } | |
55 | #endif | |
56 | ||
57 | static inline void netxen_nic_hw_block_write64(u64 __iomem * data_ptr, | |
58 | u64 __iomem * addr, | |
59 | int num_words) | |
60 | { | |
61 | int num; | |
62 | for (num = 0; num < num_words; num++) { | |
63 | writeq(readq((void __iomem *)data_ptr), addr); | |
64 | addr++; | |
65 | data_ptr++; | |
66 | } | |
67 | } | |
68 | ||
69 | static inline void netxen_nic_hw_block_read64(u64 __iomem * data_ptr, | |
70 | u64 __iomem * addr, int num_words) | |
71 | { | |
72 | int num; | |
73 | for (num = 0; num < num_words; num++) { | |
74 | writeq(readq((void __iomem *)addr), data_ptr); | |
75 | addr++; | |
76 | data_ptr++; | |
77 | } | |
78 | ||
79 | } | |
80 | ||
81 | struct netxen_adapter; | |
82 | ||
83 | #define NETXEN_PCI_MAPSIZE_BYTES (NETXEN_PCI_MAPSIZE << 20) | |
84 | ||
cb8011ad | 85 | #define NETXEN_NIC_LOCKED_READ_REG(X, Y) \ |
80922fbc AK |
86 | addr = pci_base_offset(adapter, X); \ |
87 | *(u32 *)Y = readl((void __iomem*) addr); | |
3d396eb1 AK |
88 | |
89 | struct netxen_port; | |
90 | void netxen_nic_set_link_parameters(struct netxen_port *port); | |
91 | void netxen_nic_flash_print(struct netxen_adapter *adapter); | |
92 | int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, | |
93 | void *data, int len); | |
94 | void netxen_crb_writelit_adapter(struct netxen_adapter *adapter, | |
95 | unsigned long off, int data); | |
96 | int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, | |
97 | void *data, int len); | |
98 | ||
99 | typedef u8 netxen_ethernet_macaddr_t[6]; | |
100 | ||
101 | /* Nibble or Byte mode for phy interface (GbE mode only) */ | |
102 | typedef enum { | |
103 | NETXEN_NIU_10_100_MB = 0, | |
104 | NETXEN_NIU_1000_MB | |
105 | } netxen_niu_gbe_ifmode_t; | |
106 | ||
107 | #define _netxen_crb_get_bit(var, bit) ((var >> bit) & 0x1) | |
108 | ||
109 | /* | |
110 | * NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3) | |
111 | * | |
112 | * Bit 0 : enable_tx => 1:enable frame xmit, 0:disable | |
113 | * Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream | |
114 | * Bit 2 : enable_rx => 1:enable frame recv, 0:disable | |
115 | * Bit 3 : rx_synced => R/O: recv enable synched to recv stream | |
116 | * Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable | |
117 | * Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore | |
118 | * Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal | |
119 | * Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op | |
120 | * Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op | |
121 | * Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op | |
122 | * Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op | |
123 | * Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op | |
124 | */ | |
125 | ||
126 | #define netxen_gb_enable_tx(config_word) \ | |
a608ab9c | 127 | ((config_word) |= 1 << 0) |
3d396eb1 | 128 | #define netxen_gb_enable_rx(config_word) \ |
a608ab9c | 129 | ((config_word) |= 1 << 2) |
3d396eb1 | 130 | #define netxen_gb_tx_flowctl(config_word) \ |
a608ab9c | 131 | ((config_word) |= 1 << 4) |
3d396eb1 | 132 | #define netxen_gb_rx_flowctl(config_word) \ |
a608ab9c | 133 | ((config_word) |= 1 << 5) |
3d396eb1 | 134 | #define netxen_gb_tx_reset_pb(config_word) \ |
a608ab9c | 135 | ((config_word) |= 1 << 16) |
3d396eb1 | 136 | #define netxen_gb_rx_reset_pb(config_word) \ |
a608ab9c | 137 | ((config_word) |= 1 << 17) |
3d396eb1 | 138 | #define netxen_gb_tx_reset_mac(config_word) \ |
a608ab9c | 139 | ((config_word) |= 1 << 18) |
3d396eb1 | 140 | #define netxen_gb_rx_reset_mac(config_word) \ |
a608ab9c | 141 | ((config_word) |= 1 << 19) |
3d396eb1 | 142 | #define netxen_gb_soft_reset(config_word) \ |
a608ab9c | 143 | ((config_word) |= 1 << 31) |
3d396eb1 AK |
144 | |
145 | #define netxen_gb_unset_tx_flowctl(config_word) \ | |
a608ab9c | 146 | ((config_word) &= ~(1 << 4)) |
3d396eb1 | 147 | #define netxen_gb_unset_rx_flowctl(config_word) \ |
a608ab9c | 148 | ((config_word) &= ~(1 << 5)) |
3d396eb1 AK |
149 | |
150 | #define netxen_gb_get_tx_synced(config_word) \ | |
151 | _netxen_crb_get_bit((config_word), 1) | |
152 | #define netxen_gb_get_rx_synced(config_word) \ | |
153 | _netxen_crb_get_bit((config_word), 3) | |
154 | #define netxen_gb_get_tx_flowctl(config_word) \ | |
155 | _netxen_crb_get_bit((config_word), 4) | |
156 | #define netxen_gb_get_rx_flowctl(config_word) \ | |
157 | _netxen_crb_get_bit((config_word), 5) | |
158 | #define netxen_gb_get_soft_reset(config_word) \ | |
159 | _netxen_crb_get_bit((config_word), 31) | |
160 | ||
161 | /* | |
162 | * NIU GB MAC Config Register 1 (applies to GB0, GB1, GB2, GB3) | |
163 | * | |
164 | * Bit 0 : duplex => 1:full duplex mode, 0:half duplex | |
165 | * Bit 1 : crc_enable => 1:append CRC to xmit frames, 0:dont append | |
166 | * Bit 2 : padshort => 1:pad short frames and add CRC, 0:dont pad | |
167 | * Bit 4 : checklength => 1:check framelen with actual,0:dont check | |
168 | * Bit 5 : hugeframes => 1:allow oversize xmit frames, 0:dont allow | |
169 | * Bits 8-9 : intfmode => 01:nibble (10/100), 10:byte (1000) | |
170 | * Bits 12-15 : preamblelen => preamble field length in bytes, default 7 | |
171 | */ | |
172 | ||
173 | #define netxen_gb_set_duplex(config_word) \ | |
a608ab9c | 174 | ((config_word) |= 1 << 0) |
3d396eb1 | 175 | #define netxen_gb_set_crc_enable(config_word) \ |
a608ab9c | 176 | ((config_word) |= 1 << 1) |
3d396eb1 | 177 | #define netxen_gb_set_padshort(config_word) \ |
a608ab9c | 178 | ((config_word) |= 1 << 2) |
3d396eb1 | 179 | #define netxen_gb_set_checklength(config_word) \ |
a608ab9c | 180 | ((config_word) |= 1 << 4) |
3d396eb1 | 181 | #define netxen_gb_set_hugeframes(config_word) \ |
a608ab9c | 182 | ((config_word) |= 1 << 5) |
3d396eb1 AK |
183 | #define netxen_gb_set_preamblelen(config_word, val) \ |
184 | ((config_word) |= ((val) << 12) & 0xF000) | |
185 | #define netxen_gb_set_intfmode(config_word, val) \ | |
186 | ((config_word) |= ((val) << 8) & 0x300) | |
187 | ||
188 | #define netxen_gb_get_stationaddress_low(config_word) ((config_word) >> 16) | |
189 | ||
190 | #define netxen_gb_set_mii_mgmt_clockselect(config_word, val) \ | |
191 | ((config_word) |= ((val) & 0x07)) | |
192 | #define netxen_gb_mii_mgmt_reset(config_word) \ | |
a608ab9c | 193 | ((config_word) |= 1 << 31) |
3d396eb1 | 194 | #define netxen_gb_mii_mgmt_unset(config_word) \ |
a608ab9c | 195 | ((config_word) &= ~(1 << 31)) |
3d396eb1 AK |
196 | |
197 | /* | |
198 | * NIU GB MII Mgmt Command Register (applies to GB0, GB1, GB2, GB3) | |
199 | * Bit 0 : read_cycle => 1:perform single read cycle, 0:no-op | |
200 | * Bit 1 : scan_cycle => 1:perform continuous read cycles, 0:no-op | |
201 | */ | |
202 | ||
203 | #define netxen_gb_mii_mgmt_set_read_cycle(config_word) \ | |
a608ab9c | 204 | ((config_word) |= 1 << 0) |
3d396eb1 AK |
205 | #define netxen_gb_mii_mgmt_reg_addr(config_word, val) \ |
206 | ((config_word) |= ((val) & 0x1F)) | |
207 | #define netxen_gb_mii_mgmt_phy_addr(config_word, val) \ | |
208 | ((config_word) |= (((val) & 0x1F) << 8)) | |
209 | ||
210 | /* | |
211 | * NIU GB MII Mgmt Indicators Register (applies to GB0, GB1, GB2, GB3) | |
212 | * Read-only register. | |
213 | * Bit 0 : busy => 1:performing an MII mgmt cycle, 0:idle | |
214 | * Bit 1 : scanning => 1:scan operation in progress, 0:idle | |
215 | * Bit 2 : notvalid => :mgmt result data not yet valid, 0:idle | |
216 | */ | |
217 | #define netxen_get_gb_mii_mgmt_busy(config_word) \ | |
218 | _netxen_crb_get_bit(config_word, 0) | |
219 | #define netxen_get_gb_mii_mgmt_scanning(config_word) \ | |
220 | _netxen_crb_get_bit(config_word, 1) | |
221 | #define netxen_get_gb_mii_mgmt_notvalid(config_word) \ | |
222 | _netxen_crb_get_bit(config_word, 2) | |
223 | ||
224 | /* | |
225 | * PHY-Specific MII control/status registers. | |
226 | */ | |
227 | typedef enum { | |
228 | NETXEN_NIU_GB_MII_MGMT_ADDR_CONTROL = 0, | |
229 | NETXEN_NIU_GB_MII_MGMT_ADDR_STATUS = 1, | |
230 | NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_0 = 2, | |
231 | NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_1 = 3, | |
232 | NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG = 4, | |
233 | NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART = 5, | |
234 | NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG_MORE = 6, | |
235 | NETXEN_NIU_GB_MII_MGMT_ADDR_NEXTPAGE_XMIT = 7, | |
236 | NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART_NEXTPAGE = 8, | |
237 | NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_CONTROL = 9, | |
238 | NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_STATUS = 10, | |
239 | NETXEN_NIU_GB_MII_MGMT_ADDR_EXTENDED_STATUS = 15, | |
240 | NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL = 16, | |
241 | NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS = 17, | |
242 | NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE = 18, | |
243 | NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS = 19, | |
244 | NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE = 20, | |
245 | NETXEN_NIU_GB_MII_MGMT_ADDR_RECV_ERROR_COUNT = 21, | |
246 | NETXEN_NIU_GB_MII_MGMT_ADDR_LED_CONTROL = 24, | |
247 | NETXEN_NIU_GB_MII_MGMT_ADDR_LED_OVERRIDE = 25, | |
248 | NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE_YET = 26, | |
249 | NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS_MORE = 27 | |
250 | } netxen_niu_phy_register_t; | |
251 | ||
252 | /* | |
253 | * PHY-Specific Status Register (reg 17). | |
254 | * | |
255 | * Bit 0 : jabber => 1:jabber detected, 0:not | |
256 | * Bit 1 : polarity => 1:polarity reversed, 0:normal | |
257 | * Bit 2 : recvpause => 1:receive pause enabled, 0:disabled | |
258 | * Bit 3 : xmitpause => 1:transmit pause enabled, 0:disabled | |
259 | * Bit 4 : energydetect => 1:sleep, 0:active | |
260 | * Bit 5 : downshift => 1:downshift, 0:no downshift | |
261 | * Bit 6 : crossover => 1:MDIX (crossover), 0:MDI (no crossover) | |
262 | * Bits 7-9 : cablelen => not valid in 10Mb/s mode | |
263 | * 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m | |
264 | * Bit 10 : link => 1:link up, 0:link down | |
265 | * Bit 11 : resolved => 1:speed and duplex resolved, 0:not yet | |
266 | * Bit 12 : pagercvd => 1:page received, 0:page not received | |
267 | * Bit 13 : duplex => 1:full duplex, 0:half duplex | |
268 | * Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd | |
269 | */ | |
270 | ||
271 | #define netxen_get_phy_cablelen(config_word) (((config_word) >> 7) & 0x07) | |
272 | #define netxen_get_phy_speed(config_word) (((config_word) >> 14) & 0x03) | |
273 | ||
274 | #define netxen_set_phy_speed(config_word, val) \ | |
275 | ((config_word) |= ((val & 0x03) << 14)) | |
276 | #define netxen_set_phy_duplex(config_word) \ | |
a608ab9c | 277 | ((config_word) |= 1 << 13) |
3d396eb1 | 278 | #define netxen_clear_phy_duplex(config_word) \ |
a608ab9c | 279 | ((config_word) &= ~(1 << 13)) |
3d396eb1 AK |
280 | |
281 | #define netxen_get_phy_jabber(config_word) \ | |
282 | _netxen_crb_get_bit(config_word, 0) | |
283 | #define netxen_get_phy_polarity(config_word) \ | |
284 | _netxen_crb_get_bit(config_word, 1) | |
285 | #define netxen_get_phy_recvpause(config_word) \ | |
286 | _netxen_crb_get_bit(config_word, 2) | |
287 | #define netxen_get_phy_xmitpause(config_word) \ | |
288 | _netxen_crb_get_bit(config_word, 3) | |
289 | #define netxen_get_phy_energydetect(config_word) \ | |
290 | _netxen_crb_get_bit(config_word, 4) | |
291 | #define netxen_get_phy_downshift(config_word) \ | |
292 | _netxen_crb_get_bit(config_word, 5) | |
293 | #define netxen_get_phy_crossover(config_word) \ | |
294 | _netxen_crb_get_bit(config_word, 6) | |
295 | #define netxen_get_phy_link(config_word) \ | |
296 | _netxen_crb_get_bit(config_word, 10) | |
297 | #define netxen_get_phy_resolved(config_word) \ | |
298 | _netxen_crb_get_bit(config_word, 11) | |
299 | #define netxen_get_phy_pagercvd(config_word) \ | |
300 | _netxen_crb_get_bit(config_word, 12) | |
301 | #define netxen_get_phy_duplex(config_word) \ | |
302 | _netxen_crb_get_bit(config_word, 13) | |
303 | ||
304 | /* | |
305 | * Interrupt Register definition | |
306 | * This definition applies to registers 18 and 19 (int enable and int status). | |
307 | * Bit 0 : jabber | |
308 | * Bit 1 : polarity_changed | |
309 | * Bit 4 : energy_detect | |
310 | * Bit 5 : downshift | |
311 | * Bit 6 : mdi_xover_changed | |
312 | * Bit 7 : fifo_over_underflow | |
313 | * Bit 8 : false_carrier | |
314 | * Bit 9 : symbol_error | |
315 | * Bit 10: link_status_changed | |
316 | * Bit 11: autoneg_completed | |
317 | * Bit 12: page_received | |
318 | * Bit 13: duplex_changed | |
319 | * Bit 14: speed_changed | |
320 | * Bit 15: autoneg_error | |
321 | */ | |
322 | ||
323 | #define netxen_get_phy_int_jabber(config_word) \ | |
324 | _netxen_crb_get_bit(config_word, 0) | |
325 | #define netxen_get_phy_int_polarity_changed(config_word) \ | |
326 | _netxen_crb_get_bit(config_word, 1) | |
327 | #define netxen_get_phy_int_energy_detect(config_word) \ | |
328 | _netxen_crb_get_bit(config_word, 4) | |
329 | #define netxen_get_phy_int_downshift(config_word) \ | |
330 | _netxen_crb_get_bit(config_word, 5) | |
331 | #define netxen_get_phy_int_mdi_xover_changed(config_word) \ | |
332 | _netxen_crb_get_bit(config_word, 6) | |
333 | #define netxen_get_phy_int_fifo_over_underflow(config_word) \ | |
334 | _netxen_crb_get_bit(config_word, 7) | |
335 | #define netxen_get_phy_int_false_carrier(config_word) \ | |
336 | _netxen_crb_get_bit(config_word, 8) | |
337 | #define netxen_get_phy_int_symbol_error(config_word) \ | |
338 | _netxen_crb_get_bit(config_word, 9) | |
339 | #define netxen_get_phy_int_link_status_changed(config_word) \ | |
340 | _netxen_crb_get_bit(config_word, 10) | |
341 | #define netxen_get_phy_int_autoneg_completed(config_word) \ | |
342 | _netxen_crb_get_bit(config_word, 11) | |
343 | #define netxen_get_phy_int_page_received(config_word) \ | |
344 | _netxen_crb_get_bit(config_word, 12) | |
345 | #define netxen_get_phy_int_duplex_changed(config_word) \ | |
346 | _netxen_crb_get_bit(config_word, 13) | |
347 | #define netxen_get_phy_int_speed_changed(config_word) \ | |
348 | _netxen_crb_get_bit(config_word, 14) | |
349 | #define netxen_get_phy_int_autoneg_error(config_word) \ | |
350 | _netxen_crb_get_bit(config_word, 15) | |
351 | ||
352 | #define netxen_set_phy_int_link_status_changed(config_word) \ | |
a608ab9c | 353 | ((config_word) |= 1 << 10) |
3d396eb1 | 354 | #define netxen_set_phy_int_autoneg_completed(config_word) \ |
a608ab9c | 355 | ((config_word) |= 1 << 11) |
3d396eb1 | 356 | #define netxen_set_phy_int_speed_changed(config_word) \ |
a608ab9c | 357 | ((config_word) |= 1 << 14) |
3d396eb1 AK |
358 | |
359 | /* | |
360 | * NIU Mode Register. | |
361 | * Bit 0 : enable FibreChannel | |
362 | * Bit 1 : enable 10/100/1000 Ethernet | |
363 | * Bit 2 : enable 10Gb Ethernet | |
364 | */ | |
365 | ||
366 | #define netxen_get_niu_enable_ge(config_word) \ | |
367 | _netxen_crb_get_bit(config_word, 1) | |
368 | ||
369 | /* Promiscous mode options (GbE mode only) */ | |
370 | typedef enum { | |
371 | NETXEN_NIU_PROMISC_MODE = 0, | |
372 | NETXEN_NIU_NON_PROMISC_MODE | |
373 | } netxen_niu_prom_mode_t; | |
374 | ||
375 | /* | |
376 | * NIU GB Drop CRC Register | |
377 | * | |
378 | * Bit 0 : drop_gb0 => 1:drop pkts with bad CRCs, 0:pass them on | |
379 | * Bit 1 : drop_gb1 => 1:drop pkts with bad CRCs, 0:pass them on | |
380 | * Bit 2 : drop_gb2 => 1:drop pkts with bad CRCs, 0:pass them on | |
381 | * Bit 3 : drop_gb3 => 1:drop pkts with bad CRCs, 0:pass them on | |
382 | */ | |
383 | ||
384 | #define netxen_set_gb_drop_gb0(config_word) \ | |
a608ab9c | 385 | ((config_word) |= 1 << 0) |
3d396eb1 | 386 | #define netxen_set_gb_drop_gb1(config_word) \ |
a608ab9c | 387 | ((config_word) |= 1 << 1) |
3d396eb1 | 388 | #define netxen_set_gb_drop_gb2(config_word) \ |
a608ab9c | 389 | ((config_word) |= 1 << 2) |
3d396eb1 | 390 | #define netxen_set_gb_drop_gb3(config_word) \ |
a608ab9c | 391 | ((config_word) |= 1 << 3) |
3d396eb1 AK |
392 | |
393 | #define netxen_clear_gb_drop_gb0(config_word) \ | |
a608ab9c | 394 | ((config_word) &= ~(1 << 0)) |
3d396eb1 | 395 | #define netxen_clear_gb_drop_gb1(config_word) \ |
a608ab9c | 396 | ((config_word) &= ~(1 << 1)) |
3d396eb1 | 397 | #define netxen_clear_gb_drop_gb2(config_word) \ |
a608ab9c | 398 | ((config_word) &= ~(1 << 2)) |
3d396eb1 | 399 | #define netxen_clear_gb_drop_gb3(config_word) \ |
a608ab9c | 400 | ((config_word) &= ~(1 << 3)) |
3d396eb1 AK |
401 | |
402 | /* | |
403 | * NIU XG MAC Config Register | |
404 | * | |
405 | * Bit 0 : tx_enable => 1:enable frame xmit, 0:disable | |
406 | * Bit 2 : rx_enable => 1:enable frame recv, 0:disable | |
407 | * Bit 4 : soft_reset => 1:reset the MAC , 0:no-op | |
408 | * Bit 27: xaui_framer_reset | |
409 | * Bit 28: xaui_rx_reset | |
410 | * Bit 29: xaui_tx_reset | |
411 | * Bit 30: xg_ingress_afifo_reset | |
412 | * Bit 31: xg_egress_afifo_reset | |
413 | */ | |
414 | ||
415 | #define netxen_xg_soft_reset(config_word) \ | |
a608ab9c | 416 | ((config_word) |= 1 << 4) |
3d396eb1 AK |
417 | |
418 | /* | |
419 | * MAC Control Register | |
420 | * | |
421 | * Bit 0-1 : id_pool0 | |
422 | * Bit 2 : enable_xtnd0 | |
423 | * Bit 4-5 : id_pool1 | |
424 | * Bit 6 : enable_xtnd1 | |
425 | * Bit 8-9 : id_pool2 | |
426 | * Bit 10 : enable_xtnd2 | |
427 | * Bit 12-13 : id_pool3 | |
428 | * Bit 14 : enable_xtnd3 | |
429 | * Bit 24-25 : mode_select | |
430 | * Bit 28-31 : enable_pool | |
431 | */ | |
432 | ||
433 | #define netxen_nic_mcr_set_id_pool0(config, val) \ | |
434 | ((config) |= ((val) &0x03)) | |
435 | #define netxen_nic_mcr_set_enable_xtnd0(config) \ | |
a608ab9c | 436 | ((config) |= 1 << 3) |
3d396eb1 AK |
437 | #define netxen_nic_mcr_set_id_pool1(config, val) \ |
438 | ((config) |= (((val) & 0x03) << 4)) | |
439 | #define netxen_nic_mcr_set_enable_xtnd1(config) \ | |
a608ab9c | 440 | ((config) |= 1 << 6) |
3d396eb1 AK |
441 | #define netxen_nic_mcr_set_id_pool2(config, val) \ |
442 | ((config) |= (((val) & 0x03) << 8)) | |
443 | #define netxen_nic_mcr_set_enable_xtnd2(config) \ | |
a608ab9c | 444 | ((config) |= 1 << 10) |
3d396eb1 AK |
445 | #define netxen_nic_mcr_set_id_pool3(config, val) \ |
446 | ((config) |= (((val) & 0x03) << 12)) | |
447 | #define netxen_nic_mcr_set_enable_xtnd3(config) \ | |
a608ab9c | 448 | ((config) |= 1 << 14) |
3d396eb1 AK |
449 | #define netxen_nic_mcr_set_mode_select(config, val) \ |
450 | ((config) |= (((val) & 0x03) << 24)) | |
451 | #define netxen_nic_mcr_set_enable_pool(config, val) \ | |
452 | ((config) |= (((val) & 0x0f) << 28)) | |
453 | ||
454 | /* Set promiscuous mode for a GbE interface */ | |
455 | int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter, int port, | |
456 | netxen_niu_prom_mode_t mode); | |
457 | int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter, | |
458 | int port, netxen_niu_prom_mode_t mode); | |
459 | ||
460 | /* get/set the MAC address for a given MAC */ | |
461 | int netxen_niu_macaddr_get(struct netxen_adapter *adapter, int port, | |
462 | netxen_ethernet_macaddr_t * addr); | |
463 | int netxen_niu_macaddr_set(struct netxen_port *port, | |
464 | netxen_ethernet_macaddr_t addr); | |
465 | ||
466 | /* XG versons */ | |
467 | int netxen_niu_xg_macaddr_get(struct netxen_adapter *adapter, int port, | |
468 | netxen_ethernet_macaddr_t * addr); | |
469 | int netxen_niu_xg_macaddr_set(struct netxen_port *port, | |
470 | netxen_ethernet_macaddr_t addr); | |
471 | ||
472 | /* Generic enable for GbE ports. Will detect the speed of the link. */ | |
473 | int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port); | |
474 | ||
cb8011ad AK |
475 | int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port); |
476 | ||
3d396eb1 AK |
477 | /* Disable a GbE interface */ |
478 | int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter, int port); | |
479 | ||
480 | int netxen_niu_disable_xg_port(struct netxen_adapter *adapter, int port); | |
481 | ||
482 | #endif /* __NETXEN_NIC_HW_H_ */ |