Commit | Line | Data |
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3d396eb1 AK |
1 | /* |
2 | * Copyright (C) 2003 - 2006 NetXen, Inc. | |
3 | * All rights reserved. | |
80922fbc | 4 | * |
3d396eb1 AK |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
80922fbc | 9 | * |
3d396eb1 AK |
10 | * This program is distributed in the hope that it will be useful, but |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
80922fbc | 14 | * |
3d396eb1 AK |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
80922fbc | 19 | * |
3d396eb1 AK |
20 | * The full GNU General Public License is included in this distribution |
21 | * in the file called LICENSE. | |
80922fbc | 22 | * |
3d396eb1 AK |
23 | * Contact Information: |
24 | * info@netxen.com | |
25 | * NetXen, | |
26 | * 3965 Freedom Circle, Fourth floor, | |
27 | * Santa Clara, CA 95054 | |
28 | * | |
29 | * | |
30 | * Source file for NIC routines to initialize the Phantom Hardware | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <linux/netdevice.h> | |
35 | #include <linux/delay.h> | |
36 | #include "netxen_nic.h" | |
37 | #include "netxen_nic_hw.h" | |
3d396eb1 AK |
38 | #include "netxen_nic_phan_reg.h" |
39 | ||
40 | struct crb_addr_pair { | |
e0e20a1a LCMT |
41 | u32 addr; |
42 | u32 data; | |
3d396eb1 AK |
43 | }; |
44 | ||
b58ecad8 LCMT |
45 | unsigned long last_schedule_time; |
46 | ||
3d396eb1 AK |
47 | #define NETXEN_MAX_CRB_XFORM 60 |
48 | static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM]; | |
e0e20a1a | 49 | #define NETXEN_ADDR_ERROR (0xffffffff) |
3d396eb1 AK |
50 | |
51 | #define crb_addr_transform(name) \ | |
52 | crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \ | |
53 | NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20 | |
54 | ||
cb8011ad AK |
55 | #define NETXEN_NIC_XDMA_RESET 0x8000ff |
56 | ||
993fb90c AB |
57 | static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, |
58 | uint32_t ctx, uint32_t ringid); | |
59 | ||
60 | #if 0 | |
61 | static void netxen_nic_locked_write_reg(struct netxen_adapter *adapter, | |
62 | unsigned long off, int *data) | |
3d396eb1 | 63 | { |
cb8011ad | 64 | void __iomem *addr = pci_base_offset(adapter, off); |
3d396eb1 AK |
65 | writel(*data, addr); |
66 | } | |
993fb90c | 67 | #endif /* 0 */ |
3d396eb1 AK |
68 | |
69 | static void crb_addr_transform_setup(void) | |
70 | { | |
71 | crb_addr_transform(XDMA); | |
72 | crb_addr_transform(TIMR); | |
73 | crb_addr_transform(SRE); | |
74 | crb_addr_transform(SQN3); | |
75 | crb_addr_transform(SQN2); | |
76 | crb_addr_transform(SQN1); | |
77 | crb_addr_transform(SQN0); | |
78 | crb_addr_transform(SQS3); | |
79 | crb_addr_transform(SQS2); | |
80 | crb_addr_transform(SQS1); | |
81 | crb_addr_transform(SQS0); | |
82 | crb_addr_transform(RPMX7); | |
83 | crb_addr_transform(RPMX6); | |
84 | crb_addr_transform(RPMX5); | |
85 | crb_addr_transform(RPMX4); | |
86 | crb_addr_transform(RPMX3); | |
87 | crb_addr_transform(RPMX2); | |
88 | crb_addr_transform(RPMX1); | |
89 | crb_addr_transform(RPMX0); | |
90 | crb_addr_transform(ROMUSB); | |
91 | crb_addr_transform(SN); | |
92 | crb_addr_transform(QMN); | |
93 | crb_addr_transform(QMS); | |
94 | crb_addr_transform(PGNI); | |
95 | crb_addr_transform(PGND); | |
96 | crb_addr_transform(PGN3); | |
97 | crb_addr_transform(PGN2); | |
98 | crb_addr_transform(PGN1); | |
99 | crb_addr_transform(PGN0); | |
100 | crb_addr_transform(PGSI); | |
101 | crb_addr_transform(PGSD); | |
102 | crb_addr_transform(PGS3); | |
103 | crb_addr_transform(PGS2); | |
104 | crb_addr_transform(PGS1); | |
105 | crb_addr_transform(PGS0); | |
106 | crb_addr_transform(PS); | |
107 | crb_addr_transform(PH); | |
108 | crb_addr_transform(NIU); | |
109 | crb_addr_transform(I2Q); | |
110 | crb_addr_transform(EG); | |
111 | crb_addr_transform(MN); | |
112 | crb_addr_transform(MS); | |
113 | crb_addr_transform(CAS2); | |
114 | crb_addr_transform(CAS1); | |
115 | crb_addr_transform(CAS0); | |
116 | crb_addr_transform(CAM); | |
117 | crb_addr_transform(C2C1); | |
118 | crb_addr_transform(C2C0); | |
1fcca1a5 | 119 | crb_addr_transform(SMB); |
3d396eb1 AK |
120 | } |
121 | ||
122 | int netxen_init_firmware(struct netxen_adapter *adapter) | |
123 | { | |
124 | u32 state = 0, loops = 0, err = 0; | |
125 | ||
126 | /* Window 1 call */ | |
127 | state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE)); | |
128 | ||
129 | if (state == PHAN_INITIALIZE_ACK) | |
130 | return 0; | |
131 | ||
132 | while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) { | |
133 | udelay(100); | |
134 | /* Window 1 call */ | |
135 | state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE)); | |
136 | ||
137 | loops++; | |
138 | } | |
139 | if (loops >= 2000) { | |
140 | printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n", | |
141 | state); | |
142 | err = -EIO; | |
143 | return err; | |
144 | } | |
145 | /* Window 1 call */ | |
2d1a3bbd | 146 | writel(INTR_SCHEME_PERPORT, |
147 | NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_CAPABILITIES_HOST)); | |
443be796 DP |
148 | writel(MSI_MODE_MULTIFUNC, |
149 | NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_MSI_MODE_HOST)); | |
3176ff3e | 150 | writel(MPORT_MULTI_FUNCTION_MODE, |
ed25ffa1 | 151 | NETXEN_CRB_NORMALIZE(adapter, CRB_MPORT_MODE)); |
3d396eb1 AK |
152 | writel(PHAN_INITIALIZE_ACK, |
153 | NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE)); | |
154 | ||
155 | return err; | |
156 | } | |
157 | ||
cb8011ad AK |
158 | #define NETXEN_ADDR_LIMIT 0xffffffffULL |
159 | ||
160 | void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr, | |
161 | struct pci_dev **used_dev) | |
162 | { | |
163 | void *addr; | |
164 | ||
165 | addr = pci_alloc_consistent(pdev, sz, ptr); | |
166 | if ((unsigned long long)(*ptr) < NETXEN_ADDR_LIMIT) { | |
167 | *used_dev = pdev; | |
168 | return addr; | |
169 | } | |
170 | pci_free_consistent(pdev, sz, addr, *ptr); | |
171 | addr = pci_alloc_consistent(NULL, sz, ptr); | |
172 | *used_dev = NULL; | |
173 | return addr; | |
174 | } | |
175 | ||
3d396eb1 AK |
176 | void netxen_initialize_adapter_sw(struct netxen_adapter *adapter) |
177 | { | |
178 | int ctxid, ring; | |
179 | u32 i; | |
180 | u32 num_rx_bufs = 0; | |
181 | struct netxen_rcv_desc_ctx *rcv_desc; | |
182 | ||
183 | DPRINTK(INFO, "initializing some queues: %p\n", adapter); | |
184 | for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) { | |
185 | for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) { | |
186 | struct netxen_rx_buffer *rx_buf; | |
187 | rcv_desc = &adapter->recv_ctx[ctxid].rcv_desc[ring]; | |
3d396eb1 AK |
188 | rcv_desc->begin_alloc = 0; |
189 | rx_buf = rcv_desc->rx_buf_arr; | |
190 | num_rx_bufs = rcv_desc->max_rx_desc_count; | |
191 | /* | |
192 | * Now go through all of them, set reference handles | |
193 | * and put them in the queues. | |
194 | */ | |
195 | for (i = 0; i < num_rx_bufs; i++) { | |
196 | rx_buf->ref_handle = i; | |
197 | rx_buf->state = NETXEN_BUFFER_FREE; | |
3d396eb1 AK |
198 | DPRINTK(INFO, "Rx buf:ctx%d i(%d) rx_buf:" |
199 | "%p\n", ctxid, i, rx_buf); | |
200 | rx_buf++; | |
201 | } | |
202 | } | |
203 | } | |
3d396eb1 AK |
204 | } |
205 | ||
206 | void netxen_initialize_adapter_hw(struct netxen_adapter *adapter) | |
207 | { | |
cb8011ad AK |
208 | int ports = 0; |
209 | struct netxen_board_info *board_info = &(adapter->ahw.boardcfg); | |
210 | ||
3d396eb1 AK |
211 | if (netxen_nic_get_board_info(adapter) != 0) |
212 | printk("%s: Error getting board config info.\n", | |
213 | netxen_nic_driver_name); | |
cb8011ad AK |
214 | get_brd_port_by_type(board_info->board_type, &ports); |
215 | if (ports == 0) | |
3d396eb1 AK |
216 | printk(KERN_ERR "%s: Unknown board type\n", |
217 | netxen_nic_driver_name); | |
cb8011ad | 218 | adapter->ahw.max_ports = ports; |
3d396eb1 AK |
219 | } |
220 | ||
221 | void netxen_initialize_adapter_ops(struct netxen_adapter *adapter) | |
222 | { | |
3d396eb1 AK |
223 | switch (adapter->ahw.board_type) { |
224 | case NETXEN_NIC_GBE: | |
80922fbc | 225 | adapter->enable_phy_interrupts = |
3d396eb1 | 226 | netxen_niu_gbe_enable_phy_interrupts; |
80922fbc | 227 | adapter->disable_phy_interrupts = |
3d396eb1 | 228 | netxen_niu_gbe_disable_phy_interrupts; |
80922fbc AK |
229 | adapter->handle_phy_intr = netxen_nic_gbe_handle_phy_intr; |
230 | adapter->macaddr_set = netxen_niu_macaddr_set; | |
231 | adapter->set_mtu = netxen_nic_set_mtu_gb; | |
232 | adapter->set_promisc = netxen_niu_set_promiscuous_mode; | |
233 | adapter->unset_promisc = netxen_niu_set_promiscuous_mode; | |
234 | adapter->phy_read = netxen_niu_gbe_phy_read; | |
235 | adapter->phy_write = netxen_niu_gbe_phy_write; | |
80922fbc AK |
236 | adapter->init_niu = netxen_nic_init_niu_gb; |
237 | adapter->stop_port = netxen_niu_disable_gbe_port; | |
3d396eb1 AK |
238 | break; |
239 | ||
240 | case NETXEN_NIC_XGBE: | |
80922fbc | 241 | adapter->enable_phy_interrupts = |
3d396eb1 | 242 | netxen_niu_xgbe_enable_phy_interrupts; |
80922fbc | 243 | adapter->disable_phy_interrupts = |
3d396eb1 | 244 | netxen_niu_xgbe_disable_phy_interrupts; |
80922fbc AK |
245 | adapter->handle_phy_intr = netxen_nic_xgbe_handle_phy_intr; |
246 | adapter->macaddr_set = netxen_niu_xg_macaddr_set; | |
247 | adapter->set_mtu = netxen_nic_set_mtu_xgb; | |
248 | adapter->init_port = netxen_niu_xg_init_port; | |
249 | adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode; | |
250 | adapter->unset_promisc = netxen_niu_xg_set_promiscuous_mode; | |
251 | adapter->stop_port = netxen_niu_disable_xg_port; | |
3d396eb1 AK |
252 | break; |
253 | ||
254 | default: | |
255 | break; | |
256 | } | |
257 | } | |
258 | ||
259 | /* | |
260 | * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB | |
261 | * address to external PCI CRB address. | |
262 | */ | |
993fb90c | 263 | static u32 netxen_decode_crb_addr(u32 addr) |
3d396eb1 AK |
264 | { |
265 | int i; | |
e0e20a1a | 266 | u32 base_addr, offset, pci_base; |
3d396eb1 AK |
267 | |
268 | crb_addr_transform_setup(); | |
269 | ||
270 | pci_base = NETXEN_ADDR_ERROR; | |
271 | base_addr = addr & 0xfff00000; | |
272 | offset = addr & 0x000fffff; | |
273 | ||
274 | for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) { | |
275 | if (crb_addr_xform[i] == base_addr) { | |
276 | pci_base = i << 20; | |
277 | break; | |
278 | } | |
279 | } | |
280 | if (pci_base == NETXEN_ADDR_ERROR) | |
281 | return pci_base; | |
282 | else | |
283 | return (pci_base + offset); | |
284 | } | |
285 | ||
13ba9c77 MT |
286 | static long rom_max_timeout = 100; |
287 | static long rom_lock_timeout = 10000; | |
27d2ab54 | 288 | static long rom_write_timeout = 700; |
3d396eb1 | 289 | |
993fb90c | 290 | static int rom_lock(struct netxen_adapter *adapter) |
3d396eb1 AK |
291 | { |
292 | int iter; | |
293 | u32 done = 0; | |
294 | int timeout = 0; | |
295 | ||
296 | while (!done) { | |
297 | /* acquire semaphore2 from PCI HW block */ | |
298 | netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK), | |
299 | &done); | |
300 | if (done == 1) | |
301 | break; | |
302 | if (timeout >= rom_lock_timeout) | |
303 | return -EIO; | |
304 | ||
305 | timeout++; | |
306 | /* | |
307 | * Yield CPU | |
308 | */ | |
309 | if (!in_atomic()) | |
310 | schedule(); | |
311 | else { | |
312 | for (iter = 0; iter < 20; iter++) | |
313 | cpu_relax(); /*This a nop instr on i386 */ | |
314 | } | |
315 | } | |
316 | netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER); | |
317 | return 0; | |
318 | } | |
319 | ||
993fb90c | 320 | static int netxen_wait_rom_done(struct netxen_adapter *adapter) |
3d396eb1 AK |
321 | { |
322 | long timeout = 0; | |
323 | long done = 0; | |
324 | ||
325 | while (done == 0) { | |
326 | done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS); | |
327 | done &= 2; | |
328 | timeout++; | |
329 | if (timeout >= rom_max_timeout) { | |
330 | printk("Timeout reached waiting for rom done"); | |
331 | return -EIO; | |
332 | } | |
333 | } | |
334 | return 0; | |
335 | } | |
336 | ||
993fb90c | 337 | static int netxen_rom_wren(struct netxen_adapter *adapter) |
cb8011ad AK |
338 | { |
339 | /* Set write enable latch in ROM status register */ | |
340 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); | |
341 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, | |
342 | M25P_INSTR_WREN); | |
343 | if (netxen_wait_rom_done(adapter)) { | |
344 | return -1; | |
345 | } | |
346 | return 0; | |
347 | } | |
348 | ||
993fb90c AB |
349 | static unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter, |
350 | unsigned int addr) | |
cb8011ad AK |
351 | { |
352 | unsigned int data = 0xdeaddead; | |
353 | data = netxen_nic_reg_read(adapter, addr); | |
354 | return data; | |
355 | } | |
356 | ||
993fb90c | 357 | static int netxen_do_rom_rdsr(struct netxen_adapter *adapter) |
cb8011ad AK |
358 | { |
359 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, | |
360 | M25P_INSTR_RDSR); | |
361 | if (netxen_wait_rom_done(adapter)) { | |
362 | return -1; | |
363 | } | |
364 | return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA); | |
365 | } | |
366 | ||
993fb90c | 367 | static void netxen_rom_unlock(struct netxen_adapter *adapter) |
cb8011ad AK |
368 | { |
369 | u32 val; | |
370 | ||
371 | /* release semaphore2 */ | |
372 | netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val); | |
373 | ||
374 | } | |
375 | ||
993fb90c | 376 | static int netxen_rom_wip_poll(struct netxen_adapter *adapter) |
cb8011ad AK |
377 | { |
378 | long timeout = 0; | |
379 | long wip = 1; | |
380 | int val; | |
381 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); | |
382 | while (wip != 0) { | |
383 | val = netxen_do_rom_rdsr(adapter); | |
384 | wip = val & 1; | |
385 | timeout++; | |
386 | if (timeout > rom_max_timeout) { | |
387 | return -1; | |
388 | } | |
389 | } | |
390 | return 0; | |
391 | } | |
392 | ||
993fb90c AB |
393 | static int do_rom_fast_write(struct netxen_adapter *adapter, int addr, |
394 | int data) | |
cb8011ad AK |
395 | { |
396 | if (netxen_rom_wren(adapter)) { | |
397 | return -1; | |
398 | } | |
399 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data); | |
400 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr); | |
401 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3); | |
402 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, | |
403 | M25P_INSTR_PP); | |
404 | if (netxen_wait_rom_done(adapter)) { | |
405 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); | |
406 | return -1; | |
407 | } | |
408 | ||
409 | return netxen_rom_wip_poll(adapter); | |
410 | } | |
411 | ||
993fb90c AB |
412 | static int do_rom_fast_read(struct netxen_adapter *adapter, |
413 | int addr, int *valp) | |
3d396eb1 | 414 | { |
96acb6eb | 415 | cond_resched(); |
b58ecad8 | 416 | |
3d396eb1 AK |
417 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr); |
418 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3); | |
b58ecad8 | 419 | udelay(100); /* prevent bursting on CRB */ |
3d396eb1 AK |
420 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); |
421 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb); | |
422 | if (netxen_wait_rom_done(adapter)) { | |
423 | printk("Error waiting for rom done\n"); | |
424 | return -EIO; | |
425 | } | |
426 | /* reset abyte_cnt and dummy_byte_cnt */ | |
427 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); | |
b58ecad8 | 428 | udelay(100); /* prevent bursting on CRB */ |
3d396eb1 AK |
429 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); |
430 | ||
431 | *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA); | |
432 | return 0; | |
433 | } | |
434 | ||
993fb90c AB |
435 | static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
436 | u8 *bytes, size_t size) | |
27d2ab54 AK |
437 | { |
438 | int addridx; | |
439 | int ret = 0; | |
440 | ||
441 | for (addridx = addr; addridx < (addr + size); addridx += 4) { | |
f305f789 AV |
442 | int v; |
443 | ret = do_rom_fast_read(adapter, addridx, &v); | |
27d2ab54 AK |
444 | if (ret != 0) |
445 | break; | |
f305f789 | 446 | *(__le32 *)bytes = cpu_to_le32(v); |
27d2ab54 AK |
447 | bytes += 4; |
448 | } | |
449 | ||
450 | return ret; | |
451 | } | |
452 | ||
453 | int | |
4790654c | 454 | netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
27d2ab54 AK |
455 | u8 *bytes, size_t size) |
456 | { | |
457 | int ret; | |
458 | ||
459 | ret = rom_lock(adapter); | |
460 | if (ret < 0) | |
461 | return ret; | |
462 | ||
463 | ret = do_rom_fast_read_words(adapter, addr, bytes, size); | |
464 | ||
465 | netxen_rom_unlock(adapter); | |
466 | return ret; | |
467 | } | |
468 | ||
3d396eb1 AK |
469 | int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp) |
470 | { | |
471 | int ret; | |
472 | ||
473 | if (rom_lock(adapter) != 0) | |
474 | return -EIO; | |
475 | ||
476 | ret = do_rom_fast_read(adapter, addr, valp); | |
cb8011ad AK |
477 | netxen_rom_unlock(adapter); |
478 | return ret; | |
479 | } | |
480 | ||
993fb90c | 481 | #if 0 |
cb8011ad AK |
482 | int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data) |
483 | { | |
484 | int ret = 0; | |
485 | ||
486 | if (rom_lock(adapter) != 0) { | |
487 | return -1; | |
488 | } | |
489 | ret = do_rom_fast_write(adapter, addr, data); | |
490 | netxen_rom_unlock(adapter); | |
491 | return ret; | |
492 | } | |
993fb90c | 493 | #endif /* 0 */ |
27d2ab54 | 494 | |
4790654c | 495 | static int do_rom_fast_write_words(struct netxen_adapter *adapter, |
993fb90c | 496 | int addr, u8 *bytes, size_t size) |
27d2ab54 AK |
497 | { |
498 | int addridx = addr; | |
499 | int ret = 0; | |
500 | ||
501 | while (addridx < (addr + size)) { | |
502 | int last_attempt = 0; | |
503 | int timeout = 0; | |
504 | int data; | |
505 | ||
f305f789 | 506 | data = le32_to_cpu((*(__le32*)bytes)); |
27d2ab54 AK |
507 | ret = do_rom_fast_write(adapter, addridx, data); |
508 | if (ret < 0) | |
509 | return ret; | |
4790654c | 510 | |
27d2ab54 AK |
511 | while(1) { |
512 | int data1; | |
513 | ||
f8dfdd5c SH |
514 | ret = do_rom_fast_read(adapter, addridx, &data1); |
515 | if (ret < 0) | |
516 | return ret; | |
517 | ||
27d2ab54 AK |
518 | if (data1 == data) |
519 | break; | |
520 | ||
521 | if (timeout++ >= rom_write_timeout) { | |
522 | if (last_attempt++ < 4) { | |
4790654c | 523 | ret = do_rom_fast_write(adapter, |
27d2ab54 AK |
524 | addridx, data); |
525 | if (ret < 0) | |
526 | return ret; | |
527 | } | |
528 | else { | |
529 | printk(KERN_INFO "Data write did not " | |
530 | "succeed at address 0x%x\n", addridx); | |
531 | break; | |
532 | } | |
533 | } | |
534 | } | |
535 | ||
536 | bytes += 4; | |
537 | addridx += 4; | |
538 | } | |
539 | ||
540 | return ret; | |
541 | } | |
542 | ||
4790654c | 543 | int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr, |
27d2ab54 AK |
544 | u8 *bytes, size_t size) |
545 | { | |
546 | int ret = 0; | |
547 | ||
548 | ret = rom_lock(adapter); | |
549 | if (ret < 0) | |
550 | return ret; | |
551 | ||
552 | ret = do_rom_fast_write_words(adapter, addr, bytes, size); | |
553 | netxen_rom_unlock(adapter); | |
554 | ||
555 | return ret; | |
556 | } | |
557 | ||
993fb90c | 558 | static int netxen_rom_wrsr(struct netxen_adapter *adapter, int data) |
27d2ab54 AK |
559 | { |
560 | int ret; | |
561 | ||
562 | ret = netxen_rom_wren(adapter); | |
563 | if (ret < 0) | |
564 | return ret; | |
565 | ||
566 | netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data); | |
4790654c | 567 | netxen_crb_writelit_adapter(adapter, |
27d2ab54 AK |
568 | NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1); |
569 | ||
570 | ret = netxen_wait_rom_done(adapter); | |
571 | if (ret < 0) | |
572 | return ret; | |
573 | ||
574 | return netxen_rom_wip_poll(adapter); | |
575 | } | |
576 | ||
993fb90c | 577 | static int netxen_rom_rdsr(struct netxen_adapter *adapter) |
27d2ab54 AK |
578 | { |
579 | int ret; | |
580 | ||
581 | ret = rom_lock(adapter); | |
582 | if (ret < 0) | |
583 | return ret; | |
584 | ||
585 | ret = netxen_do_rom_rdsr(adapter); | |
586 | netxen_rom_unlock(adapter); | |
587 | return ret; | |
588 | } | |
589 | ||
590 | int netxen_backup_crbinit(struct netxen_adapter *adapter) | |
591 | { | |
592 | int ret = FLASH_SUCCESS; | |
593 | int val; | |
0d04761d | 594 | char *buffer = kmalloc(NETXEN_FLASH_SECTOR_SIZE, GFP_KERNEL); |
27d2ab54 AK |
595 | |
596 | if (!buffer) | |
4790654c | 597 | return -ENOMEM; |
27d2ab54 AK |
598 | /* unlock sector 63 */ |
599 | val = netxen_rom_rdsr(adapter); | |
600 | val = val & 0xe3; | |
601 | ret = netxen_rom_wrsr(adapter, val); | |
602 | if (ret != FLASH_SUCCESS) | |
603 | goto out_kfree; | |
604 | ||
605 | ret = netxen_rom_wip_poll(adapter); | |
606 | if (ret != FLASH_SUCCESS) | |
607 | goto out_kfree; | |
608 | ||
609 | /* copy sector 0 to sector 63 */ | |
4790654c | 610 | ret = netxen_rom_fast_read_words(adapter, NETXEN_CRBINIT_START, |
0d04761d | 611 | buffer, NETXEN_FLASH_SECTOR_SIZE); |
27d2ab54 AK |
612 | if (ret != FLASH_SUCCESS) |
613 | goto out_kfree; | |
614 | ||
4790654c | 615 | ret = netxen_rom_fast_write_words(adapter, NETXEN_FIXED_START, |
0d04761d | 616 | buffer, NETXEN_FLASH_SECTOR_SIZE); |
27d2ab54 AK |
617 | if (ret != FLASH_SUCCESS) |
618 | goto out_kfree; | |
619 | ||
620 | /* lock sector 63 */ | |
621 | val = netxen_rom_rdsr(adapter); | |
622 | if (!(val & 0x8)) { | |
623 | val |= (0x1 << 2); | |
624 | /* lock sector 63 */ | |
625 | if (netxen_rom_wrsr(adapter, val) == 0) { | |
626 | ret = netxen_rom_wip_poll(adapter); | |
627 | if (ret != FLASH_SUCCESS) | |
628 | goto out_kfree; | |
629 | ||
630 | /* lock SR writes */ | |
631 | ret = netxen_rom_wip_poll(adapter); | |
632 | if (ret != FLASH_SUCCESS) | |
633 | goto out_kfree; | |
634 | } | |
635 | } | |
636 | ||
637 | out_kfree: | |
638 | kfree(buffer); | |
639 | return ret; | |
640 | } | |
641 | ||
993fb90c | 642 | static int netxen_do_rom_se(struct netxen_adapter *adapter, int addr) |
cb8011ad AK |
643 | { |
644 | netxen_rom_wren(adapter); | |
645 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr); | |
646 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3); | |
647 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, | |
648 | M25P_INSTR_SE); | |
649 | if (netxen_wait_rom_done(adapter)) { | |
650 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); | |
651 | return -1; | |
652 | } | |
653 | return netxen_rom_wip_poll(adapter); | |
654 | } | |
655 | ||
993fb90c | 656 | static void check_erased_flash(struct netxen_adapter *adapter, int addr) |
27d2ab54 AK |
657 | { |
658 | int i; | |
659 | int val; | |
660 | int count = 0, erased_errors = 0; | |
661 | int range; | |
662 | ||
4790654c | 663 | range = (addr == NETXEN_USER_START) ? |
0d04761d | 664 | NETXEN_FIXED_START : addr + NETXEN_FLASH_SECTOR_SIZE; |
4790654c | 665 | |
27d2ab54 AK |
666 | for (i = addr; i < range; i += 4) { |
667 | netxen_rom_fast_read(adapter, i, &val); | |
668 | if (val != 0xffffffff) | |
669 | erased_errors++; | |
670 | count++; | |
671 | } | |
672 | ||
673 | if (erased_errors) | |
674 | printk(KERN_INFO "0x%x out of 0x%x words fail to be erased " | |
675 | "for sector address: %x\n", erased_errors, count, addr); | |
676 | } | |
677 | ||
cb8011ad AK |
678 | int netxen_rom_se(struct netxen_adapter *adapter, int addr) |
679 | { | |
680 | int ret = 0; | |
681 | if (rom_lock(adapter) != 0) { | |
682 | return -1; | |
683 | } | |
684 | ret = netxen_do_rom_se(adapter, addr); | |
685 | netxen_rom_unlock(adapter); | |
27d2ab54 AK |
686 | msleep(30); |
687 | check_erased_flash(adapter, addr); | |
688 | ||
689 | return ret; | |
690 | } | |
691 | ||
993fb90c AB |
692 | static int netxen_flash_erase_sections(struct netxen_adapter *adapter, |
693 | int start, int end) | |
27d2ab54 AK |
694 | { |
695 | int ret = FLASH_SUCCESS; | |
696 | int i; | |
697 | ||
698 | for (i = start; i < end; i++) { | |
0d04761d | 699 | ret = netxen_rom_se(adapter, i * NETXEN_FLASH_SECTOR_SIZE); |
27d2ab54 AK |
700 | if (ret) |
701 | break; | |
702 | ret = netxen_rom_wip_poll(adapter); | |
703 | if (ret < 0) | |
704 | return ret; | |
705 | } | |
706 | ||
707 | return ret; | |
708 | } | |
709 | ||
710 | int | |
711 | netxen_flash_erase_secondary(struct netxen_adapter *adapter) | |
712 | { | |
713 | int ret = FLASH_SUCCESS; | |
714 | int start, end; | |
715 | ||
0d04761d MT |
716 | start = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE; |
717 | end = NETXEN_USER_START / NETXEN_FLASH_SECTOR_SIZE; | |
27d2ab54 AK |
718 | ret = netxen_flash_erase_sections(adapter, start, end); |
719 | ||
720 | return ret; | |
721 | } | |
722 | ||
723 | int | |
724 | netxen_flash_erase_primary(struct netxen_adapter *adapter) | |
725 | { | |
726 | int ret = FLASH_SUCCESS; | |
727 | int start, end; | |
728 | ||
0d04761d MT |
729 | start = NETXEN_PRIMARY_START / NETXEN_FLASH_SECTOR_SIZE; |
730 | end = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE; | |
27d2ab54 AK |
731 | ret = netxen_flash_erase_sections(adapter, start, end); |
732 | ||
733 | return ret; | |
734 | } | |
735 | ||
e45d9ab4 AK |
736 | void netxen_halt_pegs(struct netxen_adapter *adapter) |
737 | { | |
738 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x3c, 1); | |
739 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x3c, 1); | |
740 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x3c, 1); | |
741 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x3c, 1); | |
742 | } | |
743 | ||
27d2ab54 AK |
744 | int netxen_flash_unlock(struct netxen_adapter *adapter) |
745 | { | |
746 | int ret = 0; | |
747 | ||
748 | ret = netxen_rom_wrsr(adapter, 0); | |
749 | if (ret < 0) | |
750 | return ret; | |
751 | ||
752 | ret = netxen_rom_wren(adapter); | |
753 | if (ret < 0) | |
754 | return ret; | |
755 | ||
3d396eb1 AK |
756 | return ret; |
757 | } | |
758 | ||
759 | #define NETXEN_BOARDTYPE 0x4008 | |
760 | #define NETXEN_BOARDNUM 0x400c | |
761 | #define NETXEN_CHIPNUM 0x4010 | |
762 | #define NETXEN_ROMBUS_RESET 0xFFFFFFFF | |
763 | #define NETXEN_ROM_FIRST_BARRIER 0x800000000ULL | |
764 | #define NETXEN_ROM_FOUND_INIT 0x400 | |
765 | ||
766 | int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose) | |
767 | { | |
768 | int addr, val, status; | |
769 | int n, i; | |
770 | int init_delay = 0; | |
771 | struct crb_addr_pair *buf; | |
e0e20a1a | 772 | u32 off; |
3d396eb1 AK |
773 | |
774 | /* resetall */ | |
775 | status = netxen_nic_get_board_info(adapter); | |
776 | if (status) | |
cb8011ad | 777 | printk("%s: netxen_pinit_from_rom: Error getting board info\n", |
3d396eb1 AK |
778 | netxen_nic_driver_name); |
779 | ||
780 | netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET, | |
781 | NETXEN_ROMBUS_RESET); | |
782 | ||
783 | if (verbose) { | |
784 | int val; | |
785 | if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0) | |
786 | printk("P2 ROM board type: 0x%08x\n", val); | |
787 | else | |
788 | printk("Could not read board type\n"); | |
789 | if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0) | |
790 | printk("P2 ROM board num: 0x%08x\n", val); | |
791 | else | |
792 | printk("Could not read board number\n"); | |
793 | if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0) | |
794 | printk("P2 ROM chip num: 0x%08x\n", val); | |
795 | else | |
796 | printk("Could not read chip number\n"); | |
797 | } | |
798 | ||
799 | if (netxen_rom_fast_read(adapter, 0, &n) == 0 | |
800 | && (n & NETXEN_ROM_FIRST_BARRIER)) { | |
801 | n &= ~NETXEN_ROM_ROUNDUP; | |
802 | if (n < NETXEN_ROM_FOUND_INIT) { | |
803 | if (verbose) | |
804 | printk("%s: %d CRB init values found" | |
805 | " in ROM.\n", netxen_nic_driver_name, n); | |
806 | } else { | |
807 | printk("%s:n=0x%x Error! NetXen card flash not" | |
808 | " initialized.\n", __FUNCTION__, n); | |
809 | return -EIO; | |
810 | } | |
811 | buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL); | |
812 | if (buf == NULL) { | |
cb8011ad AK |
813 | printk("%s: netxen_pinit_from_rom: Unable to calloc " |
814 | "memory.\n", netxen_nic_driver_name); | |
3d396eb1 AK |
815 | return -ENOMEM; |
816 | } | |
817 | for (i = 0; i < n; i++) { | |
818 | if (netxen_rom_fast_read(adapter, 8 * i + 4, &val) != 0 | |
819 | || netxen_rom_fast_read(adapter, 8 * i + 8, | |
820 | &addr) != 0) | |
821 | return -EIO; | |
822 | ||
823 | buf[i].addr = addr; | |
824 | buf[i].data = val; | |
825 | ||
826 | if (verbose) | |
827 | printk("%s: PCI: 0x%08x == 0x%08x\n", | |
828 | netxen_nic_driver_name, (unsigned int) | |
e0e20a1a | 829 | netxen_decode_crb_addr(addr), val); |
3d396eb1 AK |
830 | } |
831 | for (i = 0; i < n; i++) { | |
832 | ||
e0e20a1a | 833 | off = netxen_decode_crb_addr(buf[i].addr); |
1fcca1a5 | 834 | if (off == NETXEN_ADDR_ERROR) { |
e0e20a1a | 835 | printk(KERN_ERR"CRB init value out of range %x\n", |
1fcca1a5 AK |
836 | buf[i].addr); |
837 | continue; | |
838 | } | |
839 | off += NETXEN_PCI_CRBSPACE; | |
3d396eb1 AK |
840 | /* skipping cold reboot MAGIC */ |
841 | if (off == NETXEN_CAM_RAM(0x1fc)) | |
842 | continue; | |
843 | ||
844 | /* After writing this register, HW needs time for CRB */ | |
845 | /* to quiet down (else crb_window returns 0xffffffff) */ | |
846 | if (off == NETXEN_ROMUSB_GLB_SW_RESET) { | |
847 | init_delay = 1; | |
848 | /* hold xdma in reset also */ | |
cb8011ad | 849 | buf[i].data = NETXEN_NIC_XDMA_RESET; |
3d396eb1 AK |
850 | } |
851 | ||
852 | if (ADDR_IN_WINDOW1(off)) { | |
853 | writel(buf[i].data, | |
854 | NETXEN_CRB_NORMALIZE(adapter, off)); | |
855 | } else { | |
856 | netxen_nic_pci_change_crbwindow(adapter, 0); | |
857 | writel(buf[i].data, | |
cb8011ad | 858 | pci_base_offset(adapter, off)); |
3d396eb1 AK |
859 | |
860 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
861 | } | |
862 | if (init_delay == 1) { | |
96acb6eb | 863 | msleep(2000); |
3d396eb1 AK |
864 | init_delay = 0; |
865 | } | |
96acb6eb | 866 | msleep(20); |
3d396eb1 AK |
867 | } |
868 | kfree(buf); | |
869 | ||
870 | /* disable_peg_cache_all */ | |
871 | ||
872 | /* unreset_net_cache */ | |
873 | netxen_nic_hw_read_wx(adapter, NETXEN_ROMUSB_GLB_SW_RESET, &val, | |
874 | 4); | |
875 | netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET, | |
876 | (val & 0xffffff0f)); | |
877 | /* p2dn replyCount */ | |
878 | netxen_crb_writelit_adapter(adapter, | |
879 | NETXEN_CRB_PEG_NET_D + 0xec, 0x1e); | |
880 | /* disable_peg_cache 0 */ | |
881 | netxen_crb_writelit_adapter(adapter, | |
882 | NETXEN_CRB_PEG_NET_D + 0x4c, 8); | |
883 | /* disable_peg_cache 1 */ | |
884 | netxen_crb_writelit_adapter(adapter, | |
885 | NETXEN_CRB_PEG_NET_I + 0x4c, 8); | |
886 | ||
887 | /* peg_clr_all */ | |
888 | ||
889 | /* peg_clr 0 */ | |
890 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, | |
891 | 0); | |
892 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, | |
893 | 0); | |
894 | /* peg_clr 1 */ | |
895 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, | |
896 | 0); | |
897 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, | |
898 | 0); | |
899 | /* peg_clr 2 */ | |
900 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, | |
901 | 0); | |
902 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, | |
903 | 0); | |
904 | /* peg_clr 3 */ | |
905 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, | |
906 | 0); | |
907 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, | |
908 | 0); | |
909 | } | |
910 | return 0; | |
911 | } | |
912 | ||
ed25ffa1 AK |
913 | int netxen_initialize_adapter_offload(struct netxen_adapter *adapter) |
914 | { | |
915 | uint64_t addr; | |
916 | uint32_t hi; | |
917 | uint32_t lo; | |
918 | ||
919 | adapter->dummy_dma.addr = | |
920 | pci_alloc_consistent(adapter->ahw.pdev, | |
921 | NETXEN_HOST_DUMMY_DMA_SIZE, | |
922 | &adapter->dummy_dma.phys_addr); | |
923 | if (adapter->dummy_dma.addr == NULL) { | |
924 | printk("%s: ERROR: Could not allocate dummy DMA memory\n", | |
925 | __FUNCTION__); | |
926 | return -ENOMEM; | |
927 | } | |
928 | ||
929 | addr = (uint64_t) adapter->dummy_dma.phys_addr; | |
930 | hi = (addr >> 32) & 0xffffffff; | |
931 | lo = addr & 0xffffffff; | |
932 | ||
933 | writel(hi, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI)); | |
934 | writel(lo, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO)); | |
935 | ||
936 | return 0; | |
937 | } | |
938 | ||
939 | void netxen_free_adapter_offload(struct netxen_adapter *adapter) | |
940 | { | |
941 | if (adapter->dummy_dma.addr) { | |
942 | pci_free_consistent(adapter->ahw.pdev, | |
943 | NETXEN_HOST_DUMMY_DMA_SIZE, | |
944 | adapter->dummy_dma.addr, | |
945 | adapter->dummy_dma.phys_addr); | |
946 | adapter->dummy_dma.addr = NULL; | |
947 | } | |
948 | } | |
949 | ||
96acb6eb | 950 | int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val) |
3d396eb1 AK |
951 | { |
952 | u32 val = 0; | |
96acb6eb | 953 | int retries = 30; |
3d396eb1 | 954 | |
cb8011ad | 955 | if (!pegtune_val) { |
96acb6eb DP |
956 | do { |
957 | val = readl(NETXEN_CRB_NORMALIZE | |
3d396eb1 | 958 | (adapter, CRB_CMDPEG_STATE)); |
96acb6eb DP |
959 | pegtune_val = readl(NETXEN_CRB_NORMALIZE |
960 | (adapter, NETXEN_ROMUSB_GLB_PEGTUNE_DONE)); | |
961 | ||
962 | if (val == PHAN_INITIALIZE_COMPLETE || | |
963 | val == PHAN_INITIALIZE_ACK) | |
964 | return 0; | |
965 | ||
966 | msleep(1000); | |
967 | } while (--retries); | |
968 | if (!retries) { | |
969 | printk(KERN_WARNING "netxen_phantom_init: init failed, " | |
970 | "pegtune_val=%x\n", pegtune_val); | |
971 | return -1; | |
3d396eb1 | 972 | } |
3d396eb1 | 973 | } |
96acb6eb DP |
974 | |
975 | return 0; | |
3d396eb1 AK |
976 | } |
977 | ||
993fb90c | 978 | static int netxen_nic_check_temp(struct netxen_adapter *adapter) |
cb8011ad | 979 | { |
3176ff3e | 980 | struct net_device *netdev = adapter->netdev; |
cb8011ad AK |
981 | uint32_t temp, temp_state, temp_val; |
982 | int rv = 0; | |
983 | ||
984 | temp = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_TEMP_STATE)); | |
985 | ||
986 | temp_state = nx_get_temp_state(temp); | |
987 | temp_val = nx_get_temp_val(temp); | |
988 | ||
989 | if (temp_state == NX_TEMP_PANIC) { | |
990 | printk(KERN_ALERT | |
991 | "%s: Device temperature %d degrees C exceeds" | |
992 | " maximum allowed. Hardware has been shut down.\n", | |
993 | netxen_nic_driver_name, temp_val); | |
cb8011ad | 994 | |
3176ff3e MT |
995 | netif_carrier_off(netdev); |
996 | netif_stop_queue(netdev); | |
cb8011ad AK |
997 | rv = 1; |
998 | } else if (temp_state == NX_TEMP_WARN) { | |
999 | if (adapter->temp == NX_TEMP_NORMAL) { | |
1000 | printk(KERN_ALERT | |
1001 | "%s: Device temperature %d degrees C " | |
1002 | "exceeds operating range." | |
1003 | " Immediate action needed.\n", | |
1004 | netxen_nic_driver_name, temp_val); | |
1005 | } | |
1006 | } else { | |
1007 | if (adapter->temp == NX_TEMP_WARN) { | |
1008 | printk(KERN_INFO | |
1009 | "%s: Device temperature is now %d degrees C" | |
1010 | " in normal range.\n", netxen_nic_driver_name, | |
1011 | temp_val); | |
1012 | } | |
1013 | } | |
1014 | adapter->temp = temp_state; | |
1015 | return rv; | |
1016 | } | |
1017 | ||
6d5aefb8 | 1018 | void netxen_watchdog_task(struct work_struct *work) |
3d396eb1 | 1019 | { |
6d5aefb8 DH |
1020 | struct netxen_adapter *adapter = |
1021 | container_of(work, struct netxen_adapter, watchdog_task); | |
3d396eb1 | 1022 | |
6c80b18d | 1023 | if ((adapter->portnum == 0) && netxen_nic_check_temp(adapter)) |
cb8011ad AK |
1024 | return; |
1025 | ||
c27e6721 MT |
1026 | if (adapter->handle_phy_intr) |
1027 | adapter->handle_phy_intr(adapter); | |
1028 | ||
3d396eb1 AK |
1029 | mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ); |
1030 | } | |
1031 | ||
1032 | /* | |
1033 | * netxen_process_rcv() send the received packet to the protocol stack. | |
1034 | * and if the number of receives exceeds RX_BUFFERS_REFILL, then we | |
1035 | * invoke the routine to send more rx buffers to the Phantom... | |
1036 | */ | |
993fb90c AB |
1037 | static void netxen_process_rcv(struct netxen_adapter *adapter, int ctxid, |
1038 | struct status_desc *desc) | |
3d396eb1 | 1039 | { |
3176ff3e MT |
1040 | struct pci_dev *pdev = adapter->pdev; |
1041 | struct net_device *netdev = adapter->netdev; | |
5dc16268 DP |
1042 | u64 sts_data = le64_to_cpu(desc->status_desc_data); |
1043 | int index = netxen_get_sts_refhandle(sts_data); | |
3d396eb1 AK |
1044 | struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]); |
1045 | struct netxen_rx_buffer *buffer; | |
1046 | struct sk_buff *skb; | |
5dc16268 | 1047 | u32 length = netxen_get_sts_totallength(sts_data); |
3d396eb1 AK |
1048 | u32 desc_ctx; |
1049 | struct netxen_rcv_desc_ctx *rcv_desc; | |
1050 | int ret; | |
1051 | ||
5dc16268 | 1052 | desc_ctx = netxen_get_sts_type(sts_data); |
3d396eb1 AK |
1053 | if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) { |
1054 | printk("%s: %s Bad Rcv descriptor ring\n", | |
1055 | netxen_nic_driver_name, netdev->name); | |
1056 | return; | |
1057 | } | |
1058 | ||
1059 | rcv_desc = &recv_ctx->rcv_desc[desc_ctx]; | |
ed25ffa1 AK |
1060 | if (unlikely(index > rcv_desc->max_rx_desc_count)) { |
1061 | DPRINTK(ERR, "Got a buffer index:%x Max is %x\n", | |
1062 | index, rcv_desc->max_rx_desc_count); | |
1063 | return; | |
1064 | } | |
3d396eb1 | 1065 | buffer = &rcv_desc->rx_buf_arr[index]; |
ed25ffa1 AK |
1066 | if (desc_ctx == RCV_DESC_LRO_CTXID) { |
1067 | buffer->lro_current_frags++; | |
1068 | if (netxen_get_sts_desc_lro_last_frag(desc)) { | |
1069 | buffer->lro_expected_frags = | |
1070 | netxen_get_sts_desc_lro_cnt(desc); | |
1071 | buffer->lro_length = length; | |
1072 | } | |
1073 | if (buffer->lro_current_frags != buffer->lro_expected_frags) { | |
1074 | if (buffer->lro_expected_frags != 0) { | |
5bc51424 JP |
1075 | printk("LRO: (refhandle:%x) recv frag. " |
1076 | "wait for last. flags: %x expected:%d " | |
ed25ffa1 AK |
1077 | "have:%d\n", index, |
1078 | netxen_get_sts_desc_lro_last_frag(desc), | |
1079 | buffer->lro_expected_frags, | |
1080 | buffer->lro_current_frags); | |
1081 | } | |
1082 | return; | |
1083 | } | |
1084 | } | |
3d396eb1 AK |
1085 | |
1086 | pci_unmap_single(pdev, buffer->dma, rcv_desc->dma_size, | |
1087 | PCI_DMA_FROMDEVICE); | |
1088 | ||
1089 | skb = (struct sk_buff *)buffer->skb; | |
1090 | ||
200eef20 | 1091 | if (likely(adapter->rx_csum && |
5dc16268 | 1092 | netxen_get_sts_status(sts_data) == STATUS_CKSUM_OK)) { |
3176ff3e | 1093 | adapter->stats.csummed++; |
3d396eb1 | 1094 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
200eef20 DP |
1095 | } else |
1096 | skb->ip_summed = CHECKSUM_NONE; | |
1097 | ||
96acb6eb | 1098 | skb->dev = netdev; |
ed25ffa1 AK |
1099 | if (desc_ctx == RCV_DESC_LRO_CTXID) { |
1100 | /* True length was only available on the last pkt */ | |
1101 | skb_put(skb, buffer->lro_length); | |
1102 | } else { | |
1103 | skb_put(skb, length); | |
1104 | } | |
1105 | ||
3d396eb1 AK |
1106 | skb->protocol = eth_type_trans(skb, netdev); |
1107 | ||
1108 | ret = netif_receive_skb(skb); | |
1109 | ||
1110 | /* | |
1111 | * RH: Do we need these stats on a regular basis. Can we get it from | |
1112 | * Linux stats. | |
1113 | */ | |
1114 | switch (ret) { | |
1115 | case NET_RX_SUCCESS: | |
3176ff3e | 1116 | adapter->stats.uphappy++; |
3d396eb1 AK |
1117 | break; |
1118 | ||
1119 | case NET_RX_CN_LOW: | |
3176ff3e | 1120 | adapter->stats.uplcong++; |
3d396eb1 AK |
1121 | break; |
1122 | ||
1123 | case NET_RX_CN_MOD: | |
3176ff3e | 1124 | adapter->stats.upmcong++; |
3d396eb1 AK |
1125 | break; |
1126 | ||
1127 | case NET_RX_CN_HIGH: | |
3176ff3e | 1128 | adapter->stats.uphcong++; |
3d396eb1 AK |
1129 | break; |
1130 | ||
1131 | case NET_RX_DROP: | |
3176ff3e | 1132 | adapter->stats.updropped++; |
3d396eb1 AK |
1133 | break; |
1134 | ||
1135 | default: | |
3176ff3e | 1136 | adapter->stats.updunno++; |
3d396eb1 AK |
1137 | break; |
1138 | } | |
1139 | ||
1140 | netdev->last_rx = jiffies; | |
1141 | ||
3d396eb1 AK |
1142 | rcv_desc->rcv_pending--; |
1143 | ||
1144 | /* | |
1145 | * We just consumed one buffer so post a buffer. | |
1146 | */ | |
3d396eb1 AK |
1147 | buffer->skb = NULL; |
1148 | buffer->state = NETXEN_BUFFER_FREE; | |
ed25ffa1 AK |
1149 | buffer->lro_current_frags = 0; |
1150 | buffer->lro_expected_frags = 0; | |
3d396eb1 | 1151 | |
3176ff3e MT |
1152 | adapter->stats.no_rcv++; |
1153 | adapter->stats.rxbytes += length; | |
3d396eb1 AK |
1154 | } |
1155 | ||
1156 | /* Process Receive status ring */ | |
1157 | u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max) | |
1158 | { | |
1159 | struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]); | |
1160 | struct status_desc *desc_head = recv_ctx->rcv_status_desc_head; | |
1161 | struct status_desc *desc; /* used to read status desc here */ | |
1162 | u32 consumer = recv_ctx->status_rx_consumer; | |
ed25ffa1 | 1163 | u32 producer = 0; |
3d396eb1 AK |
1164 | int count = 0, ring; |
1165 | ||
3d396eb1 AK |
1166 | while (count < max) { |
1167 | desc = &desc_head[consumer]; | |
a608ab9c | 1168 | if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) { |
ed25ffa1 AK |
1169 | DPRINTK(ERR, "desc %p ownedby %x\n", desc, |
1170 | netxen_get_sts_owner(desc)); | |
3d396eb1 AK |
1171 | break; |
1172 | } | |
1173 | netxen_process_rcv(adapter, ctxid, desc); | |
a608ab9c | 1174 | netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM); |
3d396eb1 AK |
1175 | consumer = (consumer + 1) & (adapter->max_rx_desc_count - 1); |
1176 | count++; | |
1177 | } | |
05aaa02d DP |
1178 | for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) { |
1179 | netxen_post_rx_buffers_nodb(adapter, ctxid, ring); | |
3d396eb1 AK |
1180 | } |
1181 | ||
1182 | /* update the consumer index in phantom */ | |
1183 | if (count) { | |
3d396eb1 | 1184 | recv_ctx->status_rx_consumer = consumer; |
ed25ffa1 | 1185 | recv_ctx->status_rx_producer = producer; |
3d396eb1 AK |
1186 | |
1187 | /* Window = 1 */ | |
1188 | writel(consumer, | |
1189 | NETXEN_CRB_NORMALIZE(adapter, | |
05aaa02d | 1190 | recv_crb_registers[adapter->portnum]. |
3d396eb1 AK |
1191 | crb_rcv_status_consumer)); |
1192 | } | |
1193 | ||
1194 | return count; | |
1195 | } | |
1196 | ||
1197 | /* Process Command status ring */ | |
05aaa02d | 1198 | int netxen_process_cmd_ring(struct netxen_adapter *adapter) |
3d396eb1 AK |
1199 | { |
1200 | u32 last_consumer; | |
1201 | u32 consumer; | |
ed25ffa1 AK |
1202 | int count1 = 0; |
1203 | int count2 = 0; | |
3d396eb1 | 1204 | struct netxen_cmd_buffer *buffer; |
3d396eb1 AK |
1205 | struct pci_dev *pdev; |
1206 | struct netxen_skb_frag *frag; | |
1207 | u32 i; | |
ed25ffa1 | 1208 | int done; |
3d396eb1 AK |
1209 | |
1210 | spin_lock(&adapter->tx_lock); | |
1211 | last_consumer = adapter->last_cmd_consumer; | |
1212 | DPRINTK(INFO, "procesing xmit complete\n"); | |
1213 | /* we assume in this case that there is only one port and that is | |
1214 | * port #1...changes need to be done in firmware to indicate port | |
1215 | * number as part of the descriptor. This way we will be able to get | |
1216 | * the netdev which is associated with that device. | |
1217 | */ | |
3d396eb1 | 1218 | |
9b410117 | 1219 | consumer = le32_to_cpu(*(adapter->cmd_consumer)); |
3d396eb1 AK |
1220 | if (last_consumer == consumer) { /* Ring is empty */ |
1221 | DPRINTK(INFO, "last_consumer %d == consumer %d\n", | |
1222 | last_consumer, consumer); | |
1223 | spin_unlock(&adapter->tx_lock); | |
ed25ffa1 | 1224 | return 1; |
3d396eb1 AK |
1225 | } |
1226 | ||
1227 | adapter->proc_cmd_buf_counter++; | |
3d396eb1 AK |
1228 | /* |
1229 | * Not needed - does not seem to be used anywhere. | |
1230 | * adapter->cmd_consumer = consumer; | |
1231 | */ | |
1232 | spin_unlock(&adapter->tx_lock); | |
1233 | ||
ed25ffa1 | 1234 | while ((last_consumer != consumer) && (count1 < MAX_STATUS_HANDLE)) { |
3d396eb1 | 1235 | buffer = &adapter->cmd_buf_arr[last_consumer]; |
3176ff3e | 1236 | pdev = adapter->pdev; |
53a01e00 | 1237 | if (buffer->skb) { |
1238 | frag = &buffer->frag_array[0]; | |
3d396eb1 AK |
1239 | pci_unmap_single(pdev, frag->dma, frag->length, |
1240 | PCI_DMA_TODEVICE); | |
96acb6eb | 1241 | frag->dma = 0ULL; |
3d396eb1 AK |
1242 | for (i = 1; i < buffer->frag_count; i++) { |
1243 | DPRINTK(INFO, "getting fragment no %d\n", i); | |
1244 | frag++; /* Get the next frag */ | |
1245 | pci_unmap_page(pdev, frag->dma, frag->length, | |
1246 | PCI_DMA_TODEVICE); | |
96acb6eb | 1247 | frag->dma = 0ULL; |
3d396eb1 AK |
1248 | } |
1249 | ||
3176ff3e | 1250 | adapter->stats.skbfreed++; |
53a01e00 | 1251 | dev_kfree_skb_any(buffer->skb); |
1252 | buffer->skb = NULL; | |
3d396eb1 | 1253 | } else if (adapter->proc_cmd_buf_counter == 1) { |
3176ff3e | 1254 | adapter->stats.txnullskb++; |
3d396eb1 | 1255 | } |
3176ff3e MT |
1256 | if (unlikely(netif_queue_stopped(adapter->netdev) |
1257 | && netif_carrier_ok(adapter->netdev)) | |
1258 | && ((jiffies - adapter->netdev->trans_start) > | |
1259 | adapter->netdev->watchdog_timeo)) { | |
1260 | SCHEDULE_WORK(&adapter->tx_timeout_task); | |
3d396eb1 AK |
1261 | } |
1262 | ||
1263 | last_consumer = get_next_index(last_consumer, | |
1264 | adapter->max_tx_desc_count); | |
ed25ffa1 | 1265 | count1++; |
3d396eb1 | 1266 | } |
3d396eb1 | 1267 | |
ed25ffa1 | 1268 | count2 = 0; |
3d396eb1 AK |
1269 | spin_lock(&adapter->tx_lock); |
1270 | if ((--adapter->proc_cmd_buf_counter) == 0) { | |
1271 | adapter->last_cmd_consumer = last_consumer; | |
1272 | while ((adapter->last_cmd_consumer != consumer) | |
ed25ffa1 | 1273 | && (count2 < MAX_STATUS_HANDLE)) { |
3d396eb1 AK |
1274 | buffer = |
1275 | &adapter->cmd_buf_arr[adapter->last_cmd_consumer]; | |
ed25ffa1 | 1276 | count2++; |
3d396eb1 AK |
1277 | if (buffer->skb) |
1278 | break; | |
1279 | else | |
1280 | adapter->last_cmd_consumer = | |
1281 | get_next_index(adapter->last_cmd_consumer, | |
1282 | adapter->max_tx_desc_count); | |
1283 | } | |
1284 | } | |
ed25ffa1 | 1285 | if (count1 || count2) { |
3176ff3e MT |
1286 | if (netif_queue_stopped(adapter->netdev) |
1287 | && (adapter->flags & NETXEN_NETDEV_STATUS)) { | |
1288 | netif_wake_queue(adapter->netdev); | |
1289 | adapter->flags &= ~NETXEN_NETDEV_STATUS; | |
3d396eb1 AK |
1290 | } |
1291 | } | |
ed25ffa1 AK |
1292 | /* |
1293 | * If everything is freed up to consumer then check if the ring is full | |
1294 | * If the ring is full then check if more needs to be freed and | |
1295 | * schedule the call back again. | |
1296 | * | |
1297 | * This happens when there are 2 CPUs. One could be freeing and the | |
1298 | * other filling it. If the ring is full when we get out of here and | |
1299 | * the card has already interrupted the host then the host can miss the | |
1300 | * interrupt. | |
1301 | * | |
1302 | * There is still a possible race condition and the host could miss an | |
1303 | * interrupt. The card has to take care of this. | |
1304 | */ | |
1305 | if (adapter->last_cmd_consumer == consumer && | |
1306 | (((adapter->cmd_producer + 1) % | |
1307 | adapter->max_tx_desc_count) == adapter->last_cmd_consumer)) { | |
9b410117 | 1308 | consumer = le32_to_cpu(*(adapter->cmd_consumer)); |
ed25ffa1 AK |
1309 | } |
1310 | done = (adapter->last_cmd_consumer == consumer); | |
3d396eb1 AK |
1311 | |
1312 | spin_unlock(&adapter->tx_lock); | |
1313 | DPRINTK(INFO, "last consumer is %d in %s\n", last_consumer, | |
1314 | __FUNCTION__); | |
ed25ffa1 | 1315 | return (done); |
3d396eb1 AK |
1316 | } |
1317 | ||
1318 | /* | |
1319 | * netxen_post_rx_buffers puts buffer in the Phantom memory | |
1320 | */ | |
1321 | void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid) | |
1322 | { | |
1323 | struct pci_dev *pdev = adapter->ahw.pdev; | |
1324 | struct sk_buff *skb; | |
1325 | struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]); | |
1326 | struct netxen_rcv_desc_ctx *rcv_desc = NULL; | |
ed25ffa1 | 1327 | uint producer; |
3d396eb1 AK |
1328 | struct rcv_desc *pdesc; |
1329 | struct netxen_rx_buffer *buffer; | |
1330 | int count = 0; | |
1331 | int index = 0; | |
ed25ffa1 AK |
1332 | netxen_ctx_msg msg = 0; |
1333 | dma_addr_t dma; | |
3d396eb1 | 1334 | |
3d396eb1 | 1335 | rcv_desc = &recv_ctx->rcv_desc[ringid]; |
3d396eb1 AK |
1336 | |
1337 | producer = rcv_desc->producer; | |
1338 | index = rcv_desc->begin_alloc; | |
1339 | buffer = &rcv_desc->rx_buf_arr[index]; | |
1340 | /* We can start writing rx descriptors into the phantom memory. */ | |
1341 | while (buffer->state == NETXEN_BUFFER_FREE) { | |
1342 | skb = dev_alloc_skb(rcv_desc->skb_size); | |
1343 | if (unlikely(!skb)) { | |
1344 | /* | |
ed25ffa1 | 1345 | * TODO |
3d396eb1 AK |
1346 | * We need to schedule the posting of buffers to the pegs. |
1347 | */ | |
1348 | rcv_desc->begin_alloc = index; | |
cb8011ad | 1349 | DPRINTK(ERR, "netxen_post_rx_buffers: " |
3d396eb1 AK |
1350 | " allocated only %d buffers\n", count); |
1351 | break; | |
1352 | } | |
ed25ffa1 AK |
1353 | |
1354 | count++; /* now there should be no failure */ | |
1355 | pdesc = &rcv_desc->desc_head[producer]; | |
1356 | ||
1357 | #if defined(XGB_DEBUG) | |
1358 | *(unsigned long *)(skb->head) = 0xc0debabe; | |
1359 | if (skb_is_nonlinear(skb)) { | |
1360 | printk("Allocated SKB @%p is nonlinear\n"); | |
1361 | } | |
1362 | #endif | |
1363 | skb_reserve(skb, 2); | |
1364 | /* This will be setup when we receive the | |
1365 | * buffer after it has been filled FSL TBD TBD | |
1366 | * skb->dev = netdev; | |
1367 | */ | |
1368 | dma = pci_map_single(pdev, skb->data, rcv_desc->dma_size, | |
1369 | PCI_DMA_FROMDEVICE); | |
ed33ebe4 | 1370 | pdesc->addr_buffer = cpu_to_le64(dma); |
ed25ffa1 AK |
1371 | buffer->skb = skb; |
1372 | buffer->state = NETXEN_BUFFER_BUSY; | |
1373 | buffer->dma = dma; | |
1374 | /* make a rcv descriptor */ | |
ed33ebe4 AK |
1375 | pdesc->reference_handle = cpu_to_le16(buffer->ref_handle); |
1376 | pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size); | |
ed25ffa1 AK |
1377 | DPRINTK(INFO, "done writing descripter\n"); |
1378 | producer = | |
1379 | get_next_index(producer, rcv_desc->max_rx_desc_count); | |
1380 | index = get_next_index(index, rcv_desc->max_rx_desc_count); | |
1381 | buffer = &rcv_desc->rx_buf_arr[index]; | |
1382 | } | |
1383 | /* if we did allocate buffers, then write the count to Phantom */ | |
1384 | if (count) { | |
1385 | rcv_desc->begin_alloc = index; | |
1386 | rcv_desc->rcv_pending += count; | |
ed25ffa1 | 1387 | rcv_desc->producer = producer; |
ed25ffa1 AK |
1388 | /* Window = 1 */ |
1389 | writel((producer - 1) & | |
1390 | (rcv_desc->max_rx_desc_count - 1), | |
1391 | NETXEN_CRB_NORMALIZE(adapter, | |
3176ff3e MT |
1392 | recv_crb_registers[ |
1393 | adapter->portnum]. | |
ed25ffa1 AK |
1394 | rcv_desc_crb[ringid]. |
1395 | crb_rcv_producer_offset)); | |
1396 | /* | |
1397 | * Write a doorbell msg to tell phanmon of change in | |
1398 | * receive ring producer | |
1399 | */ | |
1400 | netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID); | |
1401 | netxen_set_msg_privid(msg); | |
1402 | netxen_set_msg_count(msg, | |
1403 | ((producer - | |
1404 | 1) & (rcv_desc-> | |
1405 | max_rx_desc_count - 1))); | |
3176ff3e | 1406 | netxen_set_msg_ctxid(msg, adapter->portnum); |
ed25ffa1 AK |
1407 | netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid)); |
1408 | writel(msg, | |
1409 | DB_NORMALIZE(adapter, | |
1410 | NETXEN_RCV_PRODUCER_OFFSET)); | |
ed25ffa1 AK |
1411 | } |
1412 | } | |
1413 | ||
993fb90c AB |
1414 | static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, |
1415 | uint32_t ctx, uint32_t ringid) | |
ed25ffa1 AK |
1416 | { |
1417 | struct pci_dev *pdev = adapter->ahw.pdev; | |
1418 | struct sk_buff *skb; | |
1419 | struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]); | |
1420 | struct netxen_rcv_desc_ctx *rcv_desc = NULL; | |
1421 | u32 producer; | |
1422 | struct rcv_desc *pdesc; | |
1423 | struct netxen_rx_buffer *buffer; | |
1424 | int count = 0; | |
1425 | int index = 0; | |
1426 | ||
ed25ffa1 AK |
1427 | rcv_desc = &recv_ctx->rcv_desc[ringid]; |
1428 | ||
1429 | producer = rcv_desc->producer; | |
1430 | index = rcv_desc->begin_alloc; | |
1431 | buffer = &rcv_desc->rx_buf_arr[index]; | |
1432 | /* We can start writing rx descriptors into the phantom memory. */ | |
1433 | while (buffer->state == NETXEN_BUFFER_FREE) { | |
1434 | skb = dev_alloc_skb(rcv_desc->skb_size); | |
1435 | if (unlikely(!skb)) { | |
1436 | /* | |
1437 | * We need to schedule the posting of buffers to the pegs. | |
1438 | */ | |
1439 | rcv_desc->begin_alloc = index; | |
1440 | DPRINTK(ERR, "netxen_post_rx_buffers_nodb: " | |
1441 | " allocated only %d buffers\n", count); | |
1442 | break; | |
1443 | } | |
3d396eb1 AK |
1444 | count++; /* now there should be no failure */ |
1445 | pdesc = &rcv_desc->desc_head[producer]; | |
ed25ffa1 | 1446 | skb_reserve(skb, 2); |
4790654c | 1447 | /* |
3d396eb1 AK |
1448 | * This will be setup when we receive the |
1449 | * buffer after it has been filled | |
1450 | * skb->dev = netdev; | |
1451 | */ | |
1452 | buffer->skb = skb; | |
1453 | buffer->state = NETXEN_BUFFER_BUSY; | |
1454 | buffer->dma = pci_map_single(pdev, skb->data, | |
1455 | rcv_desc->dma_size, | |
1456 | PCI_DMA_FROMDEVICE); | |
ed25ffa1 | 1457 | |
3d396eb1 | 1458 | /* make a rcv descriptor */ |
ed33ebe4 | 1459 | pdesc->reference_handle = cpu_to_le16(buffer->ref_handle); |
a608ab9c | 1460 | pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size); |
3d396eb1 AK |
1461 | pdesc->addr_buffer = cpu_to_le64(buffer->dma); |
1462 | DPRINTK(INFO, "done writing descripter\n"); | |
1463 | producer = | |
1464 | get_next_index(producer, rcv_desc->max_rx_desc_count); | |
1465 | index = get_next_index(index, rcv_desc->max_rx_desc_count); | |
1466 | buffer = &rcv_desc->rx_buf_arr[index]; | |
1467 | } | |
1468 | ||
1469 | /* if we did allocate buffers, then write the count to Phantom */ | |
1470 | if (count) { | |
1471 | rcv_desc->begin_alloc = index; | |
1472 | rcv_desc->rcv_pending += count; | |
3d396eb1 | 1473 | rcv_desc->producer = producer; |
3d396eb1 AK |
1474 | /* Window = 1 */ |
1475 | writel((producer - 1) & | |
1476 | (rcv_desc->max_rx_desc_count - 1), | |
1477 | NETXEN_CRB_NORMALIZE(adapter, | |
3176ff3e MT |
1478 | recv_crb_registers[ |
1479 | adapter->portnum]. | |
ed25ffa1 | 1480 | rcv_desc_crb[ringid]. |
3d396eb1 AK |
1481 | crb_rcv_producer_offset)); |
1482 | wmb(); | |
3d396eb1 AK |
1483 | } |
1484 | } | |
1485 | ||
3d396eb1 AK |
1486 | void netxen_nic_clear_stats(struct netxen_adapter *adapter) |
1487 | { | |
3d396eb1 | 1488 | memset(&adapter->stats, 0, sizeof(adapter->stats)); |
3176ff3e | 1489 | return; |
3d396eb1 AK |
1490 | } |
1491 |