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netxen: annotate dma watchdog setup
[deliverable/linux.git] / drivers / net / netxen / netxen_nic_init.c
CommitLineData
3d396eb1 1/*
5d242f1c 2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3d396eb1 3 * All rights reserved.
80922fbc 4 *
3d396eb1
AK		 5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
80922fbc 9 *
3d396eb1
AK		 10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
80922fbc 14 *
3d396eb1
AK		 15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
80922fbc 19 *
3d396eb1
AK		 20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
80922fbc 22 *
3d396eb1
AK		 23 * Contact Information:
24 * info@netxen.com
5d242f1c
DP		 25 * NetXen Inc,
26 * 18922 Forge Drive
27 * Cupertino, CA 95014-0701
3d396eb1
AK		 28 *
29 */
30
31#include <linux/netdevice.h>
32#include <linux/delay.h>
33#include "netxen_nic.h"
34#include "netxen_nic_hw.h"
3d396eb1
AK		 35#include "netxen_nic_phan_reg.h"
36
37struct crb_addr_pair {
e0e20a1a
LCMT		 38 u32 addr;
39 u32 data;
3d396eb1
AK		 40};
41
42#define NETXEN_MAX_CRB_XFORM 60
43static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
e0e20a1a 44#define NETXEN_ADDR_ERROR (0xffffffff)
3d396eb1
AK		 45
46#define crb_addr_transform(name) \
47 crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
48 NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
49
cb8011ad
AK		 50#define NETXEN_NIC_XDMA_RESET 0x8000ff
51
becf46a0 52static void
d8b100c5
DP		 53netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
54 struct nx_host_rds_ring *rds_ring);
993fb90c 55
3d396eb1
AK		 56static void crb_addr_transform_setup(void)
57{
58 crb_addr_transform(XDMA);
59 crb_addr_transform(TIMR);
60 crb_addr_transform(SRE);
61 crb_addr_transform(SQN3);
62 crb_addr_transform(SQN2);
63 crb_addr_transform(SQN1);
64 crb_addr_transform(SQN0);
65 crb_addr_transform(SQS3);
66 crb_addr_transform(SQS2);
67 crb_addr_transform(SQS1);
68 crb_addr_transform(SQS0);
69 crb_addr_transform(RPMX7);
70 crb_addr_transform(RPMX6);
71 crb_addr_transform(RPMX5);
72 crb_addr_transform(RPMX4);
73 crb_addr_transform(RPMX3);
74 crb_addr_transform(RPMX2);
75 crb_addr_transform(RPMX1);
76 crb_addr_transform(RPMX0);
77 crb_addr_transform(ROMUSB);
78 crb_addr_transform(SN);
79 crb_addr_transform(QMN);
80 crb_addr_transform(QMS);
81 crb_addr_transform(PGNI);
82 crb_addr_transform(PGND);
83 crb_addr_transform(PGN3);
84 crb_addr_transform(PGN2);
85 crb_addr_transform(PGN1);
86 crb_addr_transform(PGN0);
87 crb_addr_transform(PGSI);
88 crb_addr_transform(PGSD);
89 crb_addr_transform(PGS3);
90 crb_addr_transform(PGS2);
91 crb_addr_transform(PGS1);
92 crb_addr_transform(PGS0);
93 crb_addr_transform(PS);
94 crb_addr_transform(PH);
95 crb_addr_transform(NIU);
96 crb_addr_transform(I2Q);
97 crb_addr_transform(EG);
98 crb_addr_transform(MN);
99 crb_addr_transform(MS);
100 crb_addr_transform(CAS2);
101 crb_addr_transform(CAS1);
102 crb_addr_transform(CAS0);
103 crb_addr_transform(CAM);
104 crb_addr_transform(C2C1);
105 crb_addr_transform(C2C0);
1fcca1a5 106 crb_addr_transform(SMB);
e4c93c81
DP		 107 crb_addr_transform(OCM0);
108 crb_addr_transform(I2C0);
3d396eb1
AK		 109}
110
2956640d 111void netxen_release_rx_buffers(struct netxen_adapter *adapter)
3d396eb1 112{
2956640d 113 struct netxen_recv_context *recv_ctx;
48bfd1e0 114 struct nx_host_rds_ring *rds_ring;
2956640d 115 struct netxen_rx_buffer *rx_buf;
becf46a0
DP		 116 int i, ring;
117
118 recv_ctx = &adapter->recv_ctx;
119 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
120 rds_ring = &recv_ctx->rds_rings[ring];
438627c7 121 for (i = 0; i < rds_ring->num_desc; ++i) {
becf46a0
DP		 122 rx_buf = &(rds_ring->rx_buf_arr[i]);
123 if (rx_buf->state == NETXEN_BUFFER_FREE)
124 continue;
125 pci_unmap_single(adapter->pdev,
126 rx_buf->dma,
127 rds_ring->dma_size,
128 PCI_DMA_FROMDEVICE);
129 if (rx_buf->skb != NULL)
130 dev_kfree_skb_any(rx_buf->skb);
2956640d
DP		 131 }
132 }
133}
134
135void netxen_release_tx_buffers(struct netxen_adapter *adapter)
136{
137 struct netxen_cmd_buffer *cmd_buf;
138 struct netxen_skb_frag *buffrag;
139 int i, j;
4ea528a1 140 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
2956640d 141
d877f1e3
DP		 142 cmd_buf = tx_ring->cmd_buf_arr;
143 for (i = 0; i < tx_ring->num_desc; i++) {
2956640d
DP		 144 buffrag = cmd_buf->frag_array;
145 if (buffrag->dma) {
146 pci_unmap_single(adapter->pdev, buffrag->dma,
147 buffrag->length, PCI_DMA_TODEVICE);
148 buffrag->dma = 0ULL;
149 }
150 for (j = 0; j < cmd_buf->frag_count; j++) {
151 buffrag++;
152 if (buffrag->dma) {
153 pci_unmap_page(adapter->pdev, buffrag->dma,
154 buffrag->length,
155 PCI_DMA_TODEVICE);
156 buffrag->dma = 0ULL;
157 }
158 }
2956640d
DP		 159 if (cmd_buf->skb) {
160 dev_kfree_skb_any(cmd_buf->skb);
161 cmd_buf->skb = NULL;
162 }
163 cmd_buf++;
164 }
165}
166
167void netxen_free_sw_resources(struct netxen_adapter *adapter)
168{
169 struct netxen_recv_context *recv_ctx;
48bfd1e0 170 struct nx_host_rds_ring *rds_ring;
d877f1e3 171 struct nx_host_tx_ring *tx_ring;
becf46a0
DP		 172 int ring;
173
174 recv_ctx = &adapter->recv_ctx;
4ea528a1
DP		 175
176 if (recv_ctx->rds_rings == NULL)
177 goto skip_rds;
178
becf46a0
DP		 179 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
180 rds_ring = &recv_ctx->rds_rings[ring];
f2333a01
F		 181 vfree(rds_ring->rx_buf_arr);
182 rds_ring->rx_buf_arr = NULL;
2956640d 183 }
4ea528a1
DP		 184 kfree(recv_ctx->rds_rings);
185
186skip_rds:
187 if (adapter->tx_ring == NULL)
188 return;
becf46a0 189
4ea528a1 190 tx_ring = adapter->tx_ring;
f2333a01 191 vfree(tx_ring->cmd_buf_arr);
2956640d
DP		 192}
193
194int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
195{
196 struct netxen_recv_context *recv_ctx;
48bfd1e0 197 struct nx_host_rds_ring *rds_ring;
d8b100c5 198 struct nx_host_sds_ring *sds_ring;
4ea528a1 199 struct nx_host_tx_ring *tx_ring;
2956640d 200 struct netxen_rx_buffer *rx_buf;
4ea528a1 201 int ring, i, size;
2956640d
DP		 202
203 struct netxen_cmd_buffer *cmd_buf_arr;
204 struct net_device *netdev = adapter->netdev;
d877f1e3 205 struct pci_dev *pdev = adapter->pdev;
2956640d 206
4ea528a1
DP		 207 size = sizeof(struct nx_host_tx_ring);
208 tx_ring = kzalloc(size, GFP_KERNEL);
209 if (tx_ring == NULL) {
210 dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
211 netdev->name);
212 return -ENOMEM;
213 }
214 adapter->tx_ring = tx_ring;
215
d877f1e3 216 tx_ring->num_desc = adapter->num_txd;
b2af9cb0 217 tx_ring->txq = netdev_get_tx_queue(netdev, 0);
4ea528a1
DP		 218
219 cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
2956640d 220 if (cmd_buf_arr == NULL) {
d877f1e3 221 dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
2956640d
DP		 222 netdev->name);
223 return -ENOMEM;
224 }
d877f1e3
DP		 225 memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
226 tx_ring->cmd_buf_arr = cmd_buf_arr;
2956640d 227
becf46a0 228 recv_ctx = &adapter->recv_ctx;
4ea528a1
DP		 229
230 size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
231 rds_ring = kzalloc(size, GFP_KERNEL);
232 if (rds_ring == NULL) {
233 dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
234 netdev->name);
235 return -ENOMEM;
236 }
237 recv_ctx->rds_rings = rds_ring;
238
becf46a0
DP		 239 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
240 rds_ring = &recv_ctx->rds_rings[ring];
438627c7
DP		 241 switch (ring) {
242 case RCV_RING_NORMAL:
243 rds_ring->num_desc = adapter->num_rxd;
becf46a0
DP		 244 if (adapter->ahw.cut_through) {
245 rds_ring->dma_size =
246 NX_CT_DEFAULT_RX_BUF_LEN;
48bfd1e0 247 rds_ring->skb_size =
becf46a0
DP		 248 NX_CT_DEFAULT_RX_BUF_LEN;
249 } else {
250 rds_ring->dma_size = RX_DMA_MAP_LEN;
251 rds_ring->skb_size =
252 MAX_RX_BUFFER_LENGTH;
253 }
254 break;
2956640d 255
438627c7
DP		 256 case RCV_RING_JUMBO:
257 rds_ring->num_desc = adapter->num_jumbo_rxd;
becf46a0
DP		 258 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
259 rds_ring->dma_size =
260 NX_P3_RX_JUMBO_BUF_MAX_LEN;
261 else
262 rds_ring->dma_size =
263 NX_P2_RX_JUMBO_BUF_MAX_LEN;
264 rds_ring->skb_size =
265 rds_ring->dma_size + NET_IP_ALIGN;
266 break;
2956640d 267
becf46a0 268 case RCV_RING_LRO:
438627c7 269 rds_ring->num_desc = adapter->num_lro_rxd;
becf46a0
DP		 270 rds_ring->dma_size = RX_LRO_DMA_MAP_LEN;
271 rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH;
272 break;
273
274 }
275 rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
d8b100c5 276 vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
becf46a0
DP		 277 if (rds_ring->rx_buf_arr == NULL) {
278 printk(KERN_ERR "%s: Failed to allocate "
279 "rx buffer ring %d\n",
280 netdev->name, ring);
281 /* free whatever was already allocated */
282 goto err_out;
283 }
d8b100c5 284 memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
becf46a0
DP		 285 INIT_LIST_HEAD(&rds_ring->free_list);
286 /*
287 * Now go through all of them, set reference handles
288 * and put them in the queues.
289 */
becf46a0 290 rx_buf = rds_ring->rx_buf_arr;
4ea528a1 291 for (i = 0; i < rds_ring->num_desc; i++) {
becf46a0
DP		 292 list_add_tail(&rx_buf->list,
293 &rds_ring->free_list);
294 rx_buf->ref_handle = i;
295 rx_buf->state = NETXEN_BUFFER_FREE;
296 rx_buf++;
3d396eb1 297 }
d8b100c5
DP		 298 spin_lock_init(&rds_ring->lock);
299 }
300
301 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
302 sds_ring = &recv_ctx->sds_rings[ring];
303 sds_ring->irq = adapter->msix_entries[ring].vector;
d8b100c5
DP		 304 sds_ring->adapter = adapter;
305 sds_ring->num_desc = adapter->num_rxd;
306
307 for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
308 INIT_LIST_HEAD(&sds_ring->free_list[i]);
3d396eb1 309 }
2956640d
DP		 310
311 return 0;
312
313err_out:
314 netxen_free_sw_resources(adapter);
315 return -ENOMEM;
3d396eb1
AK		 316}
317
3d396eb1
AK		 318void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
319{
3d0a3cc9
DP		 320 adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
321 adapter->set_multi = netxen_p2_nic_set_multi;
322
1e2d0059 323 switch (adapter->ahw.port_type) {
3d396eb1 324 case NETXEN_NIC_GBE:
80922fbc 325 adapter->enable_phy_interrupts =
3d396eb1 326 netxen_niu_gbe_enable_phy_interrupts;
80922fbc 327 adapter->disable_phy_interrupts =
3d396eb1 328 netxen_niu_gbe_disable_phy_interrupts;
80922fbc
AK		 329 adapter->set_mtu = netxen_nic_set_mtu_gb;
330 adapter->set_promisc = netxen_niu_set_promiscuous_mode;
80922fbc
AK		 331 adapter->phy_read = netxen_niu_gbe_phy_read;
332 adapter->phy_write = netxen_niu_gbe_phy_write;
c9fc891f 333 adapter->init_port = netxen_niu_gbe_init_port;
80922fbc 334 adapter->stop_port = netxen_niu_disable_gbe_port;
3d396eb1
AK		 335 break;
336
337 case NETXEN_NIC_XGBE:
80922fbc 338 adapter->enable_phy_interrupts =
3d396eb1 339 netxen_niu_xgbe_enable_phy_interrupts;
80922fbc 340 adapter->disable_phy_interrupts =
3d396eb1 341 netxen_niu_xgbe_disable_phy_interrupts;
80922fbc
AK		 342 adapter->set_mtu = netxen_nic_set_mtu_xgb;
343 adapter->init_port = netxen_niu_xg_init_port;
344 adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
80922fbc 345 adapter->stop_port = netxen_niu_disable_xg_port;
3d396eb1
AK		 346 break;
347
348 default:
349 break;
350 }
9ad27643
DP		 351
352 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
353 adapter->set_mtu = nx_fw_cmd_set_mtu;
354 adapter->set_promisc = netxen_p3_nic_set_promisc;
3d0a3cc9
DP		 355 adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
356 adapter->set_multi = netxen_p3_nic_set_multi;
9ad27643 357 }
3d396eb1
AK		 358}
359
360/*
361 * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
362 * address to external PCI CRB address.
363 */
993fb90c 364static u32 netxen_decode_crb_addr(u32 addr)
3d396eb1
AK		 365{
366 int i;
e0e20a1a 367 u32 base_addr, offset, pci_base;
3d396eb1
AK		 368
369 crb_addr_transform_setup();
370
371 pci_base = NETXEN_ADDR_ERROR;
372 base_addr = addr & 0xfff00000;
373 offset = addr & 0x000fffff;
374
375 for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
376 if (crb_addr_xform[i] == base_addr) {
377 pci_base = i << 20;
378 break;
379 }
380 }
381 if (pci_base == NETXEN_ADDR_ERROR)
382 return pci_base;
383 else
384 return (pci_base + offset);
385}
386
13ba9c77
MT		 387static long rom_max_timeout = 100;
388static long rom_lock_timeout = 10000;
3d396eb1 389
993fb90c 390static int rom_lock(struct netxen_adapter *adapter)
3d396eb1
AK		 391{
392 int iter;
393 u32 done = 0;
394 int timeout = 0;
395
396 while (!done) {
397 /* acquire semaphore2 from PCI HW block */
f98a9f69 398 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK));
3d396eb1
AK		 399 if (done == 1)
400 break;
401 if (timeout >= rom_lock_timeout)
402 return -EIO;
403
404 timeout++;
405 /*
406 * Yield CPU
407 */
408 if (!in_atomic())
409 schedule();
410 else {
411 for (iter = 0; iter < 20; iter++)
412 cpu_relax(); /*This a nop instr on i386 */
413 }
414 }
f98a9f69 415 NXWR32(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
3d396eb1
AK		 416 return 0;
417}
418
993fb90c 419static int netxen_wait_rom_done(struct netxen_adapter *adapter)
3d396eb1
AK		 420{
421 long timeout = 0;
422 long done = 0;
423
27c915a4
DP		 424 cond_resched();
425
3d396eb1 426 while (done == 0) {
f98a9f69 427 done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
3d396eb1
AK		 428 done &= 2;
429 timeout++;
430 if (timeout >= rom_max_timeout) {
431 printk("Timeout reached waiting for rom done");
432 return -EIO;
433 }
434 }
435 return 0;
436}
437
993fb90c 438static void netxen_rom_unlock(struct netxen_adapter *adapter)
cb8011ad 439{
cb8011ad 440 /* release semaphore2 */
f98a9f69 441 NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK));
cb8011ad
AK		 442
443}
444
993fb90c
AB		 445static int do_rom_fast_read(struct netxen_adapter *adapter,
446 int addr, int *valp)
3d396eb1 447{
f98a9f69
DP		 448 NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
449 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
450 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
451 NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
3d396eb1
AK		 452 if (netxen_wait_rom_done(adapter)) {
453 printk("Error waiting for rom done\n");
454 return -EIO;
455 }
456 /* reset abyte_cnt and dummy_byte_cnt */
f98a9f69 457 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
27c915a4 458 udelay(10);
f98a9f69 459 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
3d396eb1 460
f98a9f69 461 *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
3d396eb1
AK		 462 return 0;
463}
464
993fb90c
AB		 465static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
466 u8 *bytes, size_t size)
27d2ab54
AK		 467{
468 int addridx;
469 int ret = 0;
470
471 for (addridx = addr; addridx < (addr + size); addridx += 4) {
f305f789
AV		 472 int v;
473 ret = do_rom_fast_read(adapter, addridx, &v);
27d2ab54
AK		 474 if (ret != 0)
475 break;
f305f789 476 *(__le32 *)bytes = cpu_to_le32(v);
27d2ab54
AK		 477 bytes += 4;
478 }
479
480 return ret;
481}
482
483int
4790654c 484netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
27d2ab54
AK		 485 u8 *bytes, size_t size)
486{
487 int ret;
488
489 ret = rom_lock(adapter);
490 if (ret < 0)
491 return ret;
492
493 ret = do_rom_fast_read_words(adapter, addr, bytes, size);
494
495 netxen_rom_unlock(adapter);
496 return ret;
497}
498
3d396eb1
AK		 499int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
500{
501 int ret;
502
503 if (rom_lock(adapter) != 0)
504 return -EIO;
505
506 ret = do_rom_fast_read(adapter, addr, valp);
cb8011ad
AK		 507 netxen_rom_unlock(adapter);
508 return ret;
509}
510
3d396eb1
AK		 511#define NETXEN_BOARDTYPE 0x4008
512#define NETXEN_BOARDNUM 0x400c
513#define NETXEN_CHIPNUM 0x4010
3d396eb1
AK		 514
515int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
516{
dcd56fdb 517 int addr, val;
27c915a4 518 int i, n, init_delay = 0;
3d396eb1 519 struct crb_addr_pair *buf;
27c915a4 520 unsigned offset;
e0e20a1a 521 u32 off;
3d396eb1
AK		 522
523 /* resetall */
27c915a4 524 rom_lock(adapter);
f98a9f69 525 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
27c915a4 526 netxen_rom_unlock(adapter);
3d396eb1
AK		 527
528 if (verbose) {
3d396eb1
AK		 529 if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
530 printk("P2 ROM board type: 0x%08x\n", val);
531 else
532 printk("Could not read board type\n");
533 if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
534 printk("P2 ROM board num: 0x%08x\n", val);
535 else
536 printk("Could not read board number\n");
537 if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
538 printk("P2 ROM chip num: 0x%08x\n", val);
539 else
540 printk("Could not read chip number\n");
541 }
542
2956640d
DP		 543 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
544 if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
27c915a4 545 (n != 0xcafecafe) ||
2956640d
DP		 546 netxen_rom_fast_read(adapter, 4, &n) != 0) {
547 printk(KERN_ERR "%s: ERROR Reading crb_init area: "
548 "n: %08x\n", netxen_nic_driver_name, n);
3d396eb1
AK		 549 return -EIO;
550 }
2956640d
DP		 551 offset = n & 0xffffU;
552 n = (n >> 16) & 0xffffU;
553 } else {
554 if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
555 !(n & 0x80000000)) {
556 printk(KERN_ERR "%s: ERROR Reading crb_init area: "
557 "n: %08x\n", netxen_nic_driver_name, n);
558 return -EIO;
3d396eb1 559 }
2956640d
DP		 560 offset = 1;
561 n &= ~0x80000000;
562 }
563
564 if (n < 1024) {
565 if (verbose)
566 printk(KERN_DEBUG "%s: %d CRB init values found"
567 " in ROM.\n", netxen_nic_driver_name, n);
568 } else {
569 printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
570 " initialized.\n", __func__, n);
571 return -EIO;
572 }
3d396eb1 573
2956640d
DP		 574 buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
575 if (buf == NULL) {
576 printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
577 netxen_nic_driver_name);
578 return -ENOMEM;
579 }
580 for (i = 0; i < n; i++) {
581 if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
584dbe94
DM		 582 netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
583 kfree(buf);
2956640d 584 return -EIO;
584dbe94 585 }
2956640d
DP		 586
587 buf[i].addr = addr;
588 buf[i].data = val;
589
590 if (verbose)
591 printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
592 netxen_nic_driver_name,
593 (u32)netxen_decode_crb_addr(addr), val);
594 }
595 for (i = 0; i < n; i++) {
596
597 off = netxen_decode_crb_addr(buf[i].addr);
598 if (off == NETXEN_ADDR_ERROR) {
599 printk(KERN_ERR"CRB init value out of range %x\n",
1fcca1a5 600 buf[i].addr);
2956640d
DP		 601 continue;
602 }
603 off += NETXEN_PCI_CRBSPACE;
604 /* skipping cold reboot MAGIC */
605 if (off == NETXEN_CAM_RAM(0x1fc))
606 continue;
607
608 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
609 /* do not reset PCI */
610 if (off == (ROMUSB_GLB + 0xbc))
1fcca1a5 611 continue;
27c915a4
DP		 612 if (off == (ROMUSB_GLB + 0xa8))
613 continue;
614 if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
615 continue;
616 if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
617 continue;
618 if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
619 continue;
2956640d
DP		 620 if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
621 buf[i].data = 0x1020;
622 /* skip the function enable register */
623 if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
3d396eb1 624 continue;
2956640d
DP		 625 if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
626 continue;
627 if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
628 continue;
629 }
3d396eb1 630
2956640d
DP		 631 if (off == NETXEN_ADDR_ERROR) {
632 printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
633 netxen_nic_driver_name, buf[i].addr);
634 continue;
635 }
636
27c915a4 637 init_delay = 1;
2956640d
DP		 638 /* After writing this register, HW needs time for CRB */
639 /* to quiet down (else crb_window returns 0xffffffff) */
640 if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
27c915a4 641 init_delay = 1000;
2956640d 642 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
3d396eb1 643 /* hold xdma in reset also */
cb8011ad 644 buf[i].data = NETXEN_NIC_XDMA_RESET;
27c915a4 645 buf[i].data = 0x8000ff;
3d396eb1 646 }
2956640d 647 }
3d396eb1 648
f98a9f69 649 NXWR32(adapter, off, buf[i].data);
3d396eb1 650
27c915a4 651 msleep(init_delay);
2956640d
DP		 652 }
653 kfree(buf);
3d396eb1 654
2956640d 655 /* disable_peg_cache_all */
3d396eb1 656
2956640d
DP		 657 /* unreset_net_cache */
658 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
f98a9f69
DP		 659 val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
660 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
3d396eb1 661 }
2956640d
DP		 662
663 /* p2dn replyCount */
f98a9f69 664 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
2956640d 665 /* disable_peg_cache 0 */
f98a9f69 666 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
2956640d 667 /* disable_peg_cache 1 */
f98a9f69 668 NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
2956640d
DP		 669
670 /* peg_clr_all */
671
672 /* peg_clr 0 */
f98a9f69
DP		 673 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
674 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
2956640d 675 /* peg_clr 1 */
f98a9f69
DP		 676 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
677 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
2956640d 678 /* peg_clr 2 */
f98a9f69
DP		 679 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
680 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
2956640d 681 /* peg_clr 3 */
f98a9f69
DP		 682 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
683 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
3d396eb1
AK		 684 return 0;
685}
686
67c38fc6
DP		 687int
688netxen_need_fw_reset(struct netxen_adapter *adapter)
689{
690 u32 count, old_count;
691 u32 val, version, major, minor, build;
692 int i, timeout;
693 u8 fw_type;
694
695 /* NX2031 firmware doesn't support heartbit */
696 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
697 return 1;
698
699 /* last attempt had failed */
700 if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
701 return 1;
702
703 old_count = count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
704
705 for (i = 0; i < 10; i++) {
706
707 timeout = msleep_interruptible(200);
708 if (timeout) {
709 NXWR32(adapter, CRB_CMDPEG_STATE,
710 PHAN_INITIALIZE_FAILED);
711 return -EINTR;
712 }
713
714 count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
715 if (count != old_count)
716 break;
717 }
718
719 /* firmware is dead */
720 if (count == old_count)
721 return 1;
722
723 /* check if we have got newer or different file firmware */
724 if (adapter->fw) {
725
726 const struct firmware *fw = adapter->fw;
727
728 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
729 version = NETXEN_DECODE_VERSION(val);
730
731 major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
732 minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
733 build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
734
735 if (version > NETXEN_VERSION_CODE(major, minor, build))
736 return 1;
737
738 if (version == NETXEN_VERSION_CODE(major, minor, build)) {
739
740 val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
741 fw_type = (val & 0x4) ?
742 NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
743
744 if (adapter->fw_type != fw_type)
745 return 1;
746 }
747 }
748
749 return 0;
750}
751
752static char *fw_name[] = {
753 "nxromimg.bin", "nx3fwct.bin", "nx3fwmn.bin", "flash",
754};
755
f7185c71
DP		 756int
757netxen_load_firmware(struct netxen_adapter *adapter)
758{
759 u64 *ptr64;
760 u32 i, flashaddr, size;
761 const struct firmware *fw = adapter->fw;
67c38fc6
DP		 762 struct pci_dev *pdev = adapter->pdev;
763
764 dev_info(&pdev->dev, "loading firmware from %s\n",
765 fw_name[adapter->fw_type]);
f7185c71
DP		 766
767 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
768 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
769
770 if (fw) {
771 __le64 data;
772
773 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
774
775 ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
776 flashaddr = NETXEN_BOOTLD_START;
777
778 for (i = 0; i < size; i++) {
779 data = cpu_to_le64(ptr64[i]);
780 adapter->pci_mem_write(adapter, flashaddr, &data, 8);
781 flashaddr += 8;
782 }
783
784 size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
785 size = (__force u32)cpu_to_le32(size) / 8;
786
787 ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
788 flashaddr = NETXEN_IMAGE_START;
789
790 for (i = 0; i < size; i++) {
791 data = cpu_to_le64(ptr64[i]);
792
793 if (adapter->pci_mem_write(adapter,
794 flashaddr, &data, 8))
795 return -EIO;
796
797 flashaddr += 8;
798 }
799 } else {
800 u32 data;
801
802 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 4;
803 flashaddr = NETXEN_BOOTLD_START;
804
805 for (i = 0; i < size; i++) {
806 if (netxen_rom_fast_read(adapter,
807 flashaddr, (int *)&data) != 0)
808 return -EIO;
809
810 if (adapter->pci_mem_write(adapter,
811 flashaddr, &data, 4))
812 return -EIO;
813
814 flashaddr += 4;
815 }
816 }
817 msleep(1);
818
819 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
820 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
821 else {
822 NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
823 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
824 }
825
826 return 0;
827}
828
829static int
830netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname)
831{
832 __le32 val;
98e31bb0 833 u32 ver, min_ver, bios;
f7185c71
DP		 834 struct pci_dev *pdev = adapter->pdev;
835 const struct firmware *fw = adapter->fw;
836
837 if (fw->size < NX_FW_MIN_SIZE)
838 return -EINVAL;
839
840 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
841 if ((__force u32)val != NETXEN_BDINFO_MAGIC)
842 return -EINVAL;
843
844 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
f7185c71
DP		 845
846 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
847 min_ver = NETXEN_VERSION_CODE(4, 0, 216);
848 else
849 min_ver = NETXEN_VERSION_CODE(3, 4, 216);
850
98e31bb0 851 ver = NETXEN_DECODE_VERSION(val);
f7185c71 852
98e31bb0 853 if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
f7185c71
DP		 854 dev_err(&pdev->dev,
855 "%s: firmware version %d.%d.%d unsupported\n",
98e31bb0 856 fwname, _major(ver), _minor(ver), _build(ver));
f7185c71
DP		 857 return -EINVAL;
858 }
859
860 val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
861 netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
862 if ((__force u32)val != bios) {
863 dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
864 fwname);
865 return -EINVAL;
866 }
867
868 /* check if flashed firmware is newer */
869 if (netxen_rom_fast_read(adapter,
870 NX_FW_VERSION_OFFSET, (int *)&val))
871 return -EIO;
98e31bb0
DP		 872 val = NETXEN_DECODE_VERSION(val);
873 if (val > ver) {
874 dev_info(&pdev->dev, "%s: firmware is older than flash\n",
875 fwname);
f7185c71 876 return -EINVAL;
98e31bb0 877 }
f7185c71
DP		 878
879 NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
880 return 0;
881}
882
6598b169
DP		 883static int
884netxen_p3_has_mn(struct netxen_adapter *adapter)
f7185c71
DP		 885{
886 u32 capability, flashed_ver;
f7185c71
DP		 887 capability = 0;
888
889 netxen_rom_fast_read(adapter,
890 NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
98e31bb0
DP		 891 flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
892
f7185c71 893 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
6598b169 894
f7185c71 895 capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
6598b169
DP		 896 if (capability & NX_PEG_TUNE_MN_PRESENT)
897 return 1;
898 }
899 return 0;
900}
901
902void netxen_request_firmware(struct netxen_adapter *adapter)
903{
904 u8 fw_type;
905 struct pci_dev *pdev = adapter->pdev;
906 int rc = 0;
907
908 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
909 fw_type = NX_P2_MN_ROMIMAGE;
910 goto request_fw;
f7185c71
DP		 911 }
912
6598b169
DP		 913 fw_type = netxen_p3_has_mn(adapter) ?
914 NX_P3_MN_ROMIMAGE : NX_P3_CT_ROMIMAGE;
98e31bb0 915
f7185c71
DP		 916request_fw:
917 rc = request_firmware(&adapter->fw, fw_name[fw_type], &pdev->dev);
918 if (rc != 0) {
6598b169 919 if (fw_type == NX_P3_MN_ROMIMAGE) {
f7185c71 920 msleep(1);
6598b169
DP		 921 fw_type = NX_P3_CT_ROMIMAGE;
922 goto request_fw;
f7185c71
DP		 923 }
924
67c38fc6 925 fw_type = NX_FLASH_ROMIMAGE;
f7185c71
DP		 926 adapter->fw = NULL;
927 goto done;
928 }
929
930 rc = netxen_validate_firmware(adapter, fw_name[fw_type]);
931 if (rc != 0) {
932 release_firmware(adapter->fw);
933
6598b169 934 if (fw_type == NX_P3_MN_ROMIMAGE) {
f7185c71 935 msleep(1);
6598b169
DP		 936 fw_type = NX_P3_CT_ROMIMAGE;
937 goto request_fw;
f7185c71
DP		 938 }
939
67c38fc6 940 fw_type = NX_FLASH_ROMIMAGE;
f7185c71
DP		 941 adapter->fw = NULL;
942 goto done;
943 }
944
945done:
67c38fc6 946 adapter->fw_type = fw_type;
f7185c71
DP		 947}
948
949
950void
951netxen_release_firmware(struct netxen_adapter *adapter)
952{
953 if (adapter->fw)
954 release_firmware(adapter->fw);
955}
956
83ac51fa 957int netxen_init_dummy_dma(struct netxen_adapter *adapter)
ed25ffa1 958{
83ac51fa
DP		 959 u64 addr;
960 u32 hi, lo;
ed25ffa1 961
83ac51fa
DP		 962 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
963 return 0;
964
965 adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
ed25ffa1
AK		 966 NETXEN_HOST_DUMMY_DMA_SIZE,
967 &adapter->dummy_dma.phys_addr);
968 if (adapter->dummy_dma.addr == NULL) {
83ac51fa
DP		 969 dev_err(&adapter->pdev->dev,
970 "ERROR: Could not allocate dummy DMA memory\n");
ed25ffa1
AK		 971 return -ENOMEM;
972 }
973
974 addr = (uint64_t) adapter->dummy_dma.phys_addr;
975 hi = (addr >> 32) & 0xffffffff;
976 lo = addr & 0xffffffff;
977
f98a9f69
DP		 978 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
979 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
ed25ffa1
AK		 980
981 return 0;
982}
983
83ac51fa
DP		 984/*
985 * NetXen DMA watchdog control:
986 *
987 * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
988 * Bit 1 : disable_request => 1 req disable dma watchdog
989 * Bit 2 : enable_request => 1 req enable dma watchdog
990 * Bit 3-31 : unused
991 */
992void netxen_free_dummy_dma(struct netxen_adapter *adapter)
ed25ffa1 993{
15eef1e1 994 int i = 100;
83ac51fa
DP		 995 u32 ctrl;
996
997 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
998 return;
15eef1e1
DP		 999
1000 if (!adapter->dummy_dma.addr)
1001 return;
439b454e 1002
83ac51fa
DP		 1003 ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
1004 if ((ctrl & 0x1) != 0) {
1005 NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
1006
1007 while ((ctrl & 0x1) != 0) {
1008
439b454e 1009 msleep(50);
83ac51fa
DP		 1010
1011 ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
1012
1013 if (--i == 0)
439b454e 1014 break;
83ac51fa 1015 };
15eef1e1 1016 }
439b454e 1017
15eef1e1
DP		 1018 if (i) {
1019 pci_free_consistent(adapter->pdev,
1020 NETXEN_HOST_DUMMY_DMA_SIZE,
1021 adapter->dummy_dma.addr,
1022 adapter->dummy_dma.phys_addr);
1023 adapter->dummy_dma.addr = NULL;
83ac51fa
DP		 1024 } else
1025 dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
ed25ffa1
AK		 1026}
1027
96acb6eb 1028int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
3d396eb1
AK		 1029{
1030 u32 val = 0;
2956640d 1031 int retries = 60;
3d396eb1 1032
96f2ebd2
DP		 1033 if (pegtune_val)
1034 return 0;
1035
1036 do {
1037 val = NXRD32(adapter, CRB_CMDPEG_STATE);
96acb6eb 1038
96f2ebd2
DP		 1039 switch (val) {
1040 case PHAN_INITIALIZE_COMPLETE:
1041 case PHAN_INITIALIZE_ACK:
1042 return 0;
1043 case PHAN_INITIALIZE_FAILED:
1044 goto out_err;
1045 default:
1046 break;
1047 }
96acb6eb 1048
96f2ebd2 1049 msleep(500);
2956640d 1050
96f2ebd2 1051 } while (--retries);
2956640d 1052
96f2ebd2 1053 NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
96acb6eb 1054
96f2ebd2
DP		 1055out_err:
1056 dev_warn(&adapter->pdev->dev, "firmware init failed\n");
1057 return -EIO;
3d396eb1
AK		 1058}
1059
56a00787
DP		 1060static int
1061netxen_receive_peg_ready(struct netxen_adapter *adapter)
2956640d
DP		 1062{
1063 u32 val = 0;
1064 int retries = 2000;
1065
1066 do {
f98a9f69 1067 val = NXRD32(adapter, CRB_RCVPEG_STATE);
2956640d
DP		 1068
1069 if (val == PHAN_PEG_RCV_INITIALIZED)
1070 return 0;
1071
1072 msleep(10);
1073
1074 } while (--retries);
1075
1076 if (!retries) {
1077 printk(KERN_ERR "Receive Peg initialization not "
1078 "complete, state: 0x%x.\n", val);
1079 return -EIO;
1080 }
1081
1082 return 0;
1083}
1084
56a00787
DP		 1085int netxen_init_firmware(struct netxen_adapter *adapter)
1086{
1087 int err;
1088
1089 err = netxen_receive_peg_ready(adapter);
1090 if (err)
1091 return err;
1092
f98a9f69
DP		 1093 NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
1094 NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
1095 NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
1096 NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
56a00787
DP		 1097
1098 return err;
1099}
1100
3bf26ce3
DP		 1101static void
1102netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
1103{
1104 u32 cable_OUI;
1105 u16 cable_len;
1106 u16 link_speed;
1107 u8 link_status, module, duplex, autoneg;
1108 struct net_device *netdev = adapter->netdev;
1109
1110 adapter->has_link_events = 1;
1111
1112 cable_OUI = msg->body[1] & 0xffffffff;
1113 cable_len = (msg->body[1] >> 32) & 0xffff;
1114 link_speed = (msg->body[1] >> 48) & 0xffff;
1115
1116 link_status = msg->body[2] & 0xff;
1117 duplex = (msg->body[2] >> 16) & 0xff;
1118 autoneg = (msg->body[2] >> 24) & 0xff;
1119
1120 module = (msg->body[2] >> 8) & 0xff;
1121 if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
1122 printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
1123 netdev->name, cable_OUI, cable_len);
1124 } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
1125 printk(KERN_INFO "%s: unsupported cable length %d\n",
1126 netdev->name, cable_len);
1127 }
1128
1129 netxen_advert_link_change(adapter, link_status);
1130
1131 /* update link parameters */
1132 if (duplex == LINKEVENT_FULL_DUPLEX)
1133 adapter->link_duplex = DUPLEX_FULL;
1134 else
1135 adapter->link_duplex = DUPLEX_HALF;
1136 adapter->module_type = module;
1137 adapter->link_autoneg = autoneg;
1138 adapter->link_speed = link_speed;
1139}
1140
1141static void
1142netxen_handle_fw_message(int desc_cnt, int index,
1143 struct nx_host_sds_ring *sds_ring)
1144{
1145 nx_fw_msg_t msg;
1146 struct status_desc *desc;
1147 int i = 0, opcode;
1148
1149 while (desc_cnt > 0 && i < 8) {
1150 desc = &sds_ring->desc_head[index];
1151 msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
1152 msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
1153
1154 index = get_next_index(index, sds_ring->num_desc);
1155 desc_cnt--;
1156 }
1157
1158 opcode = netxen_get_nic_msg_opcode(msg.body[0]);
1159 switch (opcode) {
1160 case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
1161 netxen_handle_linkevent(sds_ring->adapter, &msg);
1162 break;
1163 default:
1164 break;
1165 }
1166}
1167
d8b100c5
DP		 1168static int
1169netxen_alloc_rx_skb(struct netxen_adapter *adapter,
1170 struct nx_host_rds_ring *rds_ring,
1171 struct netxen_rx_buffer *buffer)
1172{
1173 struct sk_buff *skb;
1174 dma_addr_t dma;
1175 struct pci_dev *pdev = adapter->pdev;
1176
1177 buffer->skb = dev_alloc_skb(rds_ring->skb_size);
1178 if (!buffer->skb)
1179 return 1;
1180
1181 skb = buffer->skb;
1182
1183 if (!adapter->ahw.cut_through)
1184 skb_reserve(skb, 2);
1185
1186 dma = pci_map_single(pdev, skb->data,
1187 rds_ring->dma_size, PCI_DMA_FROMDEVICE);
1188
1189 if (pci_dma_mapping_error(pdev, dma)) {
1190 dev_kfree_skb_any(skb);
1191 buffer->skb = NULL;
1192 return 1;
1193 }
1194
1195 buffer->skb = skb;
1196 buffer->dma = dma;
1197 buffer->state = NETXEN_BUFFER_BUSY;
1198
1199 return 0;
1200}
1201
d9e651bc
DP		 1202static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
1203 struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
1204{
1205 struct netxen_rx_buffer *buffer;
1206 struct sk_buff *skb;
1207
1208 buffer = &rds_ring->rx_buf_arr[index];
1209
1210 pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
1211 PCI_DMA_FROMDEVICE);
1212
1213 skb = buffer->skb;
1214 if (!skb)
1215 goto no_skb;
1216
1217 if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
1218 adapter->stats.csummed++;
1219 skb->ip_summed = CHECKSUM_UNNECESSARY;
1220 } else
1221 skb->ip_summed = CHECKSUM_NONE;
1222
1223 skb->dev = adapter->netdev;
1224
1225 buffer->skb = NULL;
d9e651bc
DP		 1226no_skb:
1227 buffer->state = NETXEN_BUFFER_FREE;
d9e651bc
DP		 1228 return skb;
1229}
1230
d8b100c5 1231static struct netxen_rx_buffer *
9b3ef55c 1232netxen_process_rcv(struct netxen_adapter *adapter,
a92e9e65
AKS		 1233 int ring, int index, int length, int cksum, int pkt_offset,
1234 struct nx_host_sds_ring *sds_ring)
3d396eb1 1235{
3176ff3e 1236 struct net_device *netdev = adapter->netdev;
becf46a0 1237 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
3d396eb1
AK		 1238 struct netxen_rx_buffer *buffer;
1239 struct sk_buff *skb;
9b3ef55c 1240 struct nx_host_rds_ring *rds_ring = &recv_ctx->rds_rings[ring];
3d396eb1 1241
438627c7 1242 if (unlikely(index > rds_ring->num_desc))
d8b100c5 1243 return NULL;
438627c7 1244
48bfd1e0 1245 buffer = &rds_ring->rx_buf_arr[index];
3d396eb1 1246
d9e651bc
DP		 1247 skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
1248 if (!skb)
d8b100c5 1249 return buffer;
200eef20 1250
9b3ef55c
DP		 1251 if (length > rds_ring->skb_size)
1252 skb_put(skb, rds_ring->skb_size);
1253 else
1254 skb_put(skb, length);
d9e651bc 1255
9b3ef55c
DP		 1256
1257 if (pkt_offset)
1258 skb_pull(skb, pkt_offset);
ed25ffa1 1259
3d396eb1
AK		 1260 skb->protocol = eth_type_trans(skb, netdev);
1261
a92e9e65 1262 napi_gro_receive(&sds_ring->napi, skb);
d9e651bc 1263
0ddc110c
DP		 1264 adapter->stats.no_rcv++;
1265 adapter->stats.rxbytes += length;
d8b100c5
DP		 1266
1267 return buffer;
3d396eb1
AK		 1268}
1269
d8b100c5
DP		 1270#define netxen_merge_rx_buffers(list, head) \
1271 do { list_splice_tail_init(list, head); } while (0);
1272
becf46a0 1273int
d8b100c5 1274netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
3d396eb1 1275{
d8b100c5
DP		 1276 struct netxen_adapter *adapter = sds_ring->adapter;
1277
1278 struct list_head *cur;
1279
0ddc110c 1280 struct status_desc *desc;
d8b100c5
DP		 1281 struct netxen_rx_buffer *rxbuf;
1282
1283 u32 consumer = sds_ring->consumer;
1284
9b3ef55c 1285 int count = 0;
d9e651bc 1286 u64 sts_data;
3bf26ce3 1287 int opcode, ring, index, length, cksum, pkt_offset, desc_cnt;
3d396eb1 1288
3d396eb1 1289 while (count < max) {
d8b100c5 1290 desc = &sds_ring->desc_head[consumer];
3bf26ce3 1291 sts_data = le64_to_cpu(desc->status_desc_data[0]);
0ddc110c
DP		 1292
1293 if (!(sts_data & STATUS_OWNER_HOST))
3d396eb1 1294 break;
d9e651bc 1295
3bf26ce3 1296 desc_cnt = netxen_get_sts_desc_cnt(sts_data);
9b3ef55c 1297 ring = netxen_get_sts_type(sts_data);
3bf26ce3 1298
9b3ef55c 1299 if (ring > RCV_RING_JUMBO)
3bf26ce3 1300 goto skip;
9b3ef55c 1301
d9e651bc 1302 opcode = netxen_get_sts_opcode(sts_data);
d9e651bc 1303
3bf26ce3
DP		 1304 switch (opcode) {
1305 case NETXEN_NIC_RXPKT_DESC:
1306 case NETXEN_OLD_RXPKT_DESC:
6598b169 1307 case NETXEN_NIC_SYN_OFFLOAD:
3bf26ce3
DP		 1308 break;
1309 case NETXEN_NIC_RESPONSE_DESC:
1310 netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
1311 default:
1312 goto skip;
1313 }
1314
1315 WARN_ON(desc_cnt > 1);
1316
9b3ef55c
DP		 1317 index = netxen_get_sts_refhandle(sts_data);
1318 length = netxen_get_sts_totallength(sts_data);
1319 cksum = netxen_get_sts_status(sts_data);
1320 pkt_offset = netxen_get_sts_pkt_offset(sts_data);
1321
d8b100c5 1322 rxbuf = netxen_process_rcv(adapter, ring, index,
a92e9e65 1323 length, cksum, pkt_offset, sds_ring);
d9e651bc 1324
d8b100c5
DP		 1325 if (rxbuf)
1326 list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
1327
3bf26ce3
DP		 1328skip:
1329 for (; desc_cnt > 0; desc_cnt--) {
1330 desc = &sds_ring->desc_head[consumer];
1331 desc->status_desc_data[0] =
1332 cpu_to_le64(STATUS_OWNER_PHANTOM);
1333 consumer = get_next_index(consumer, sds_ring->num_desc);
1334 }
3d396eb1
AK		 1335 count++;
1336 }
0ddc110c 1337
d8b100c5
DP		 1338 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1339 struct nx_host_rds_ring *rds_ring =
1340 &adapter->recv_ctx.rds_rings[ring];
1341
1342 if (!list_empty(&sds_ring->free_list[ring])) {
1343 list_for_each(cur, &sds_ring->free_list[ring]) {
1344 rxbuf = list_entry(cur,
1345 struct netxen_rx_buffer, list);
1346 netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
1347 }
1348 spin_lock(&rds_ring->lock);
1349 netxen_merge_rx_buffers(&sds_ring->free_list[ring],
1350 &rds_ring->free_list);
1351 spin_unlock(&rds_ring->lock);
1352 }
1353
1354 netxen_post_rx_buffers_nodb(adapter, rds_ring);
1355 }
3d396eb1 1356
3d396eb1 1357 if (count) {
d8b100c5 1358 sds_ring->consumer = consumer;
f98a9f69 1359 NXWR32(adapter, sds_ring->crb_sts_consumer, consumer);
3d396eb1
AK		 1360 }
1361
1362 return count;
1363}
1364
1365/* Process Command status ring */
05aaa02d 1366int netxen_process_cmd_ring(struct netxen_adapter *adapter)
3d396eb1 1367{
d877f1e3 1368 u32 sw_consumer, hw_consumer;
ba53e6b4 1369 int count = 0, i;
3d396eb1 1370 struct netxen_cmd_buffer *buffer;
ba53e6b4
DP		 1371 struct pci_dev *pdev = adapter->pdev;
1372 struct net_device *netdev = adapter->netdev;
3d396eb1 1373 struct netxen_skb_frag *frag;
ba53e6b4 1374 int done = 0;
4ea528a1 1375 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
3d396eb1 1376
d8b100c5
DP		 1377 if (!spin_trylock(&adapter->tx_clean_lock))
1378 return 1;
1379
d877f1e3 1380 sw_consumer = tx_ring->sw_consumer;
d877f1e3 1381 hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
3d396eb1 1382
d877f1e3
DP		 1383 while (sw_consumer != hw_consumer) {
1384 buffer = &tx_ring->cmd_buf_arr[sw_consumer];
53a01e00 1385 if (buffer->skb) {
1386 frag = &buffer->frag_array[0];
3d396eb1
AK		 1387 pci_unmap_single(pdev, frag->dma, frag->length,
1388 PCI_DMA_TODEVICE);
96acb6eb 1389 frag->dma = 0ULL;
3d396eb1 1390 for (i = 1; i < buffer->frag_count; i++) {
3d396eb1
AK		 1391 frag++; /* Get the next frag */
1392 pci_unmap_page(pdev, frag->dma, frag->length,
1393 PCI_DMA_TODEVICE);
96acb6eb 1394 frag->dma = 0ULL;
3d396eb1
AK		 1395 }
1396
ba53e6b4 1397 adapter->stats.xmitfinished++;
53a01e00 1398 dev_kfree_skb_any(buffer->skb);
1399 buffer->skb = NULL;
3d396eb1
AK		 1400 }
1401
d877f1e3 1402 sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
ba53e6b4
DP		 1403 if (++count >= MAX_STATUS_HANDLE)
1404 break;
3d396eb1 1405 }
3d396eb1 1406
22527864 1407 if (count && netif_running(netdev)) {
cb2107be
DP		 1408 tx_ring->sw_consumer = sw_consumer;
1409
ba53e6b4 1410 smp_mb();
cb2107be 1411
22527864 1412 if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
b2af9cb0 1413 __netif_tx_lock(tx_ring->txq, smp_processor_id());
cb2107be
DP		 1414 if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
1415 netif_wake_queue(netdev);
b2af9cb0 1416 __netif_tx_unlock(tx_ring->txq);
3d396eb1
AK		 1417 }
1418 }
ed25ffa1
AK		 1419 /*
1420 * If everything is freed up to consumer then check if the ring is full
1421 * If the ring is full then check if more needs to be freed and
1422 * schedule the call back again.
1423 *
1424 * This happens when there are 2 CPUs. One could be freeing and the
1425 * other filling it. If the ring is full when we get out of here and
1426 * the card has already interrupted the host then the host can miss the
1427 * interrupt.
1428 *
1429 * There is still a possible race condition and the host could miss an
1430 * interrupt. The card has to take care of this.
1431 */
d877f1e3
DP		 1432 hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
1433 done = (sw_consumer == hw_consumer);
d8b100c5 1434 spin_unlock(&adapter->tx_clean_lock);
3d396eb1 1435
ed25ffa1 1436 return (done);
3d396eb1
AK		 1437}
1438
becf46a0 1439void
d8b100c5
DP		 1440netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1441 struct nx_host_rds_ring *rds_ring)
3d396eb1 1442{
3d396eb1
AK		 1443 struct rcv_desc *pdesc;
1444 struct netxen_rx_buffer *buffer;
d8b100c5 1445 int producer, count = 0;
ed25ffa1 1446 netxen_ctx_msg msg = 0;
d9e651bc 1447 struct list_head *head;
3d396eb1 1448
48bfd1e0 1449 producer = rds_ring->producer;
d9e651bc 1450
d8b100c5
DP		 1451 spin_lock(&rds_ring->lock);
1452 head = &rds_ring->free_list;
d9e651bc
DP		 1453 while (!list_empty(head)) {
1454
d8b100c5 1455 buffer = list_entry(head->next, struct netxen_rx_buffer, list);
6f703406 1456
d8b100c5
DP		 1457 if (!buffer->skb) {
1458 if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
1459 break;
6f703406
DP		 1460 }
1461
1462 count++;
d9e651bc
DP		 1463 list_del(&buffer->list);
1464
ed25ffa1 1465 /* make a rcv descriptor */
6f703406 1466 pdesc = &rds_ring->desc_head[producer];
d8b100c5 1467 pdesc->addr_buffer = cpu_to_le64(buffer->dma);
ed33ebe4 1468 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
48bfd1e0 1469 pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
6f703406 1470
438627c7 1471 producer = get_next_index(producer, rds_ring->num_desc);
ed25ffa1 1472 }
d8b100c5 1473 spin_unlock(&rds_ring->lock);
9b3ef55c 1474
ed25ffa1 1475 if (count) {
48bfd1e0 1476 rds_ring->producer = producer;
f98a9f69 1477 NXWR32(adapter, rds_ring->crb_rcv_producer,
438627c7 1478 (producer-1) & (rds_ring->num_desc-1));
48bfd1e0
DP		 1479
1480 if (adapter->fw_major < 4) {
ed25ffa1
AK		 1481 /*
1482 * Write a doorbell msg to tell phanmon of change in
1483 * receive ring producer
48bfd1e0 1484 * Only for firmware version < 4.0.0
ed25ffa1
AK		 1485 */
1486 netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
1487 netxen_set_msg_privid(msg);
1488 netxen_set_msg_count(msg,
438627c7
DP		 1489 ((producer - 1) &
1490 (rds_ring->num_desc - 1)));
3176ff3e 1491 netxen_set_msg_ctxid(msg, adapter->portnum);
ed25ffa1
AK		 1492 netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
1493 writel(msg,
1494 DB_NORMALIZE(adapter,
1495 NETXEN_RCV_PRODUCER_OFFSET));
48bfd1e0 1496 }
ed25ffa1
AK		 1497 }
1498}
1499
becf46a0 1500static void
d8b100c5
DP		 1501netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
1502 struct nx_host_rds_ring *rds_ring)
ed25ffa1 1503{
ed25ffa1
AK		 1504 struct rcv_desc *pdesc;
1505 struct netxen_rx_buffer *buffer;
d8b100c5 1506 int producer, count = 0;
d9e651bc 1507 struct list_head *head;
ed25ffa1 1508
48bfd1e0 1509 producer = rds_ring->producer;
d8b100c5
DP		 1510 if (!spin_trylock(&rds_ring->lock))
1511 return;
1512
d9e651bc 1513 head = &rds_ring->free_list;
d9e651bc
DP		 1514 while (!list_empty(head)) {
1515
d8b100c5 1516 buffer = list_entry(head->next, struct netxen_rx_buffer, list);
6f703406 1517
d8b100c5
DP		 1518 if (!buffer->skb) {
1519 if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
1520 break;
6f703406
DP		 1521 }
1522
1523 count++;
d9e651bc
DP		 1524 list_del(&buffer->list);
1525
3d396eb1 1526 /* make a rcv descriptor */
6f703406 1527 pdesc = &rds_ring->desc_head[producer];
ed33ebe4 1528 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
48bfd1e0 1529 pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
3d396eb1 1530 pdesc->addr_buffer = cpu_to_le64(buffer->dma);
6f703406 1531
438627c7 1532 producer = get_next_index(producer, rds_ring->num_desc);
3d396eb1
AK		 1533 }
1534
3d396eb1 1535 if (count) {
48bfd1e0 1536 rds_ring->producer = producer;
f98a9f69 1537 NXWR32(adapter, rds_ring->crb_rcv_producer,
438627c7 1538 (producer - 1) & (rds_ring->num_desc - 1));
3d396eb1 1539 }
d8b100c5 1540 spin_unlock(&rds_ring->lock);
3d396eb1
AK		 1541}
1542
3d396eb1
AK		 1543void netxen_nic_clear_stats(struct netxen_adapter *adapter)
1544{
3d396eb1 1545 memset(&adapter->stats, 0, sizeof(adapter->stats));
3176ff3e 1546 return;
3d396eb1
AK		 1547}
1548
Linux kernel - Deliverables
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