[ALSA] Remove sound/driver.h
[deliverable/linux.git] / drivers / net / pasemi_mac.c
CommitLineData
f5cd7872
OJ
1/*
2 * Copyright (C) 2006-2007 PA Semi, Inc
3 *
4 * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/interrupt.h>
24#include <linux/dmaengine.h>
25#include <linux/delay.h>
26#include <linux/netdevice.h>
27#include <linux/etherdevice.h>
28#include <asm/dma-mapping.h>
29#include <linux/in.h>
30#include <linux/skbuff.h>
31
32#include <linux/ip.h>
33#include <linux/tcp.h>
34#include <net/checksum.h>
28ae79f5 35#include <linux/inet_lro.h>
f5cd7872 36
771f7404 37#include <asm/irq.h>
af289e80 38#include <asm/firmware.h>
40afa531 39#include <asm/pasemi_dma.h>
771f7404 40
f5cd7872
OJ
41#include "pasemi_mac.h"
42
8dc121a4
OJ
43/* We have our own align, since ppc64 in general has it at 0 because
44 * of design flaws in some of the server bridge chips. However, for
45 * PWRficient doing the unaligned copies is more expensive than doing
46 * unaligned DMA, so make sure the data is aligned instead.
47 */
48#define LOCAL_SKB_ALIGN 2
f5cd7872
OJ
49
50/* TODO list
51 *
f5cd7872
OJ
52 * - Multicast support
53 * - Large MTU support
7ddeae2c
OJ
54 * - SW LRO
55 * - Multiqueue RX/TX
f5cd7872
OJ
56 */
57
58
59/* Must be a power of two */
28ae79f5 60#define RX_RING_SIZE 2048
ad5da10a 61#define TX_RING_SIZE 4096
f5cd7872 62
28ae79f5
OJ
63#define LRO_MAX_AGGR 64
64
ceb51361
OJ
65#define DEFAULT_MSG_ENABLE \
66 (NETIF_MSG_DRV | \
67 NETIF_MSG_PROBE | \
68 NETIF_MSG_LINK | \
69 NETIF_MSG_TIMER | \
70 NETIF_MSG_IFDOWN | \
71 NETIF_MSG_IFUP | \
72 NETIF_MSG_RX_ERR | \
73 NETIF_MSG_TX_ERR)
74
34c20624 75#define TX_DESC(tx, num) ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)])
72b05b99 76#define TX_DESC_INFO(tx, num) ((tx)->ring_info[(num) & (TX_RING_SIZE-1)])
34c20624 77#define RX_DESC(rx, num) ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)])
72b05b99
OJ
78#define RX_DESC_INFO(rx, num) ((rx)->ring_info[(num) & (RX_RING_SIZE-1)])
79#define RX_BUFF(rx, num) ((rx)->buffers[(num) & (RX_RING_SIZE-1)])
f5cd7872 80
021fa22e
OJ
81#define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \
82 & ((ring)->size - 1))
83#define RING_AVAIL(ring) ((ring->size) - RING_USED(ring))
84
f5cd7872
OJ
85#define BUF_SIZE 1646 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
86
ceb51361
OJ
87MODULE_LICENSE("GPL");
88MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
89MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
90
91static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */
92module_param(debug, int, 0);
93MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value");
f5cd7872 94
af289e80
OJ
95static int translation_enabled(void)
96{
97#if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE)
98 return 1;
99#else
100 return firmware_has_feature(FW_FEATURE_LPAR);
101#endif
102}
103
34c20624 104static void write_iob_reg(unsigned int reg, unsigned int val)
a85b9422 105{
34c20624 106 pasemi_write_iob_reg(reg, val);
a85b9422
OJ
107}
108
5c15332b 109static unsigned int read_mac_reg(const struct pasemi_mac *mac, unsigned int reg)
a85b9422 110{
34c20624 111 return pasemi_read_mac_reg(mac->dma_if, reg);
a85b9422
OJ
112}
113
5c15332b 114static void write_mac_reg(const struct pasemi_mac *mac, unsigned int reg,
a85b9422
OJ
115 unsigned int val)
116{
34c20624 117 pasemi_write_mac_reg(mac->dma_if, reg, val);
a85b9422
OJ
118}
119
34c20624 120static unsigned int read_dma_reg(unsigned int reg)
a85b9422 121{
34c20624 122 return pasemi_read_dma_reg(reg);
a85b9422
OJ
123}
124
34c20624 125static void write_dma_reg(unsigned int reg, unsigned int val)
a85b9422 126{
34c20624 127 pasemi_write_dma_reg(reg, val);
a85b9422
OJ
128}
129
5c15332b 130static struct pasemi_mac_rxring *rx_ring(const struct pasemi_mac *mac)
72b05b99
OJ
131{
132 return mac->rx;
133}
134
5c15332b 135static struct pasemi_mac_txring *tx_ring(const struct pasemi_mac *mac)
72b05b99
OJ
136{
137 return mac->tx;
138}
139
5c15332b
OJ
140static inline void prefetch_skb(const struct sk_buff *skb)
141{
142 const void *d = skb;
143
144 prefetch(d);
145 prefetch(d+64);
146 prefetch(d+128);
147 prefetch(d+192);
148}
149
34c20624
OJ
150static int mac_to_intf(struct pasemi_mac *mac)
151{
152 struct pci_dev *pdev = mac->pdev;
153 u32 tmp;
154 int nintf, off, i, j;
155 int devfn = pdev->devfn;
156
157 tmp = read_dma_reg(PAS_DMA_CAP_IFI);
158 nintf = (tmp & PAS_DMA_CAP_IFI_NIN_M) >> PAS_DMA_CAP_IFI_NIN_S;
159 off = (tmp & PAS_DMA_CAP_IFI_IOFF_M) >> PAS_DMA_CAP_IFI_IOFF_S;
160
161 /* IOFF contains the offset to the registers containing the
162 * DMA interface-to-MAC-pci-id mappings, and NIN contains number
163 * of total interfaces. Each register contains 4 devfns.
164 * Just do a linear search until we find the devfn of the MAC
165 * we're trying to look up.
166 */
167
168 for (i = 0; i < (nintf+3)/4; i++) {
169 tmp = read_dma_reg(off+4*i);
170 for (j = 0; j < 4; j++) {
171 if (((tmp >> (8*j)) & 0xff) == devfn)
172 return i*4 + j;
173 }
174 }
175 return -1;
176}
177
f5cd7872
OJ
178static int pasemi_get_mac_addr(struct pasemi_mac *mac)
179{
180 struct pci_dev *pdev = mac->pdev;
181 struct device_node *dn = pci_device_to_OF_node(pdev);
1af7f056 182 int len;
f5cd7872
OJ
183 const u8 *maddr;
184 u8 addr[6];
185
186 if (!dn) {
187 dev_dbg(&pdev->dev,
188 "No device node for mac, not configuring\n");
189 return -ENOENT;
190 }
191
1af7f056 192 maddr = of_get_property(dn, "local-mac-address", &len);
193
194 if (maddr && len == 6) {
195 memcpy(mac->mac_addr, maddr, 6);
196 return 0;
197 }
198
199 /* Some old versions of firmware mistakenly uses mac-address
200 * (and as a string) instead of a byte array in local-mac-address.
201 */
a5fd22eb 202
a5fd22eb 203 if (maddr == NULL)
9028780a 204 maddr = of_get_property(dn, "mac-address", NULL);
a5fd22eb 205
f5cd7872
OJ
206 if (maddr == NULL) {
207 dev_warn(&pdev->dev,
208 "no mac address in device tree, not configuring\n");
209 return -ENOENT;
210 }
211
212 if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0],
213 &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) {
214 dev_warn(&pdev->dev,
215 "can't parse mac address, not configuring\n");
216 return -EINVAL;
217 }
218
1af7f056 219 memcpy(mac->mac_addr, addr, 6);
220
f5cd7872
OJ
221 return 0;
222}
223
28ae79f5
OJ
224static int get_skb_hdr(struct sk_buff *skb, void **iphdr,
225 void **tcph, u64 *hdr_flags, void *data)
226{
227 u64 macrx = (u64) data;
228 unsigned int ip_len;
229 struct iphdr *iph;
230
231 /* IPv4 header checksum failed */
232 if ((macrx & XCT_MACRX_HTY_M) != XCT_MACRX_HTY_IPV4_OK)
233 return -1;
234
235 /* non tcp packet */
236 skb_reset_network_header(skb);
237 iph = ip_hdr(skb);
238 if (iph->protocol != IPPROTO_TCP)
239 return -1;
240
241 ip_len = ip_hdrlen(skb);
242 skb_set_transport_header(skb, ip_len);
243 *tcph = tcp_hdr(skb);
244
245 /* check if ip header and tcp header are complete */
246 if (iph->tot_len < ip_len + tcp_hdrlen(skb))
247 return -1;
248
249 *hdr_flags = LRO_IPV4 | LRO_TCP;
250 *iphdr = iph;
251
252 return 0;
253}
254
ad3c20d1 255static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac,
7e9916e9 256 const int nfrags,
ad3c20d1 257 struct sk_buff *skb,
5c15332b 258 const dma_addr_t *dmas)
ad3c20d1
OJ
259{
260 int f;
5c15332b 261 struct pci_dev *pdev = mac->dma_pdev;
ad3c20d1 262
5c15332b 263 pci_unmap_single(pdev, dmas[0], skb_headlen(skb), PCI_DMA_TODEVICE);
ad3c20d1
OJ
264
265 for (f = 0; f < nfrags; f++) {
266 skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
267
5c15332b 268 pci_unmap_page(pdev, dmas[f+1], frag->size, PCI_DMA_TODEVICE);
ad3c20d1
OJ
269 }
270 dev_kfree_skb_irq(skb);
271
272 /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs,
273 * aligned up to a power of 2
274 */
275 return (nfrags + 3) & ~1;
276}
277
5c15332b 278static int pasemi_mac_setup_rx_resources(const struct net_device *dev)
f5cd7872
OJ
279{
280 struct pasemi_mac_rxring *ring;
281 struct pasemi_mac *mac = netdev_priv(dev);
34c20624 282 int chno;
af289e80 283 unsigned int cfg;
f5cd7872 284
34c20624
OJ
285 ring = pasemi_dma_alloc_chan(RXCHAN, sizeof(struct pasemi_mac_rxring),
286 offsetof(struct pasemi_mac_rxring, chan));
f5cd7872 287
34c20624
OJ
288 if (!ring) {
289 dev_err(&mac->pdev->dev, "Can't allocate RX channel\n");
290 goto out_chan;
291 }
292 chno = ring->chan.chno;
f5cd7872
OJ
293
294 spin_lock_init(&ring->lock);
295
021fa22e 296 ring->size = RX_RING_SIZE;
fc9e4d2a 297 ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
f5cd7872
OJ
298 RX_RING_SIZE, GFP_KERNEL);
299
fc9e4d2a
OJ
300 if (!ring->ring_info)
301 goto out_ring_info;
f5cd7872
OJ
302
303 /* Allocate descriptors */
34c20624 304 if (pasemi_dma_alloc_ring(&ring->chan, RX_RING_SIZE))
fc9e4d2a 305 goto out_ring_desc;
f5cd7872 306
f5cd7872
OJ
307 ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev,
308 RX_RING_SIZE * sizeof(u64),
309 &ring->buf_dma, GFP_KERNEL);
310 if (!ring->buffers)
34c20624 311 goto out_ring_desc;
f5cd7872
OJ
312
313 memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64));
314
34c20624
OJ
315 write_dma_reg(PAS_DMA_RXCHAN_BASEL(chno),
316 PAS_DMA_RXCHAN_BASEL_BRBL(ring->chan.ring_dma));
f5cd7872 317
34c20624
OJ
318 write_dma_reg(PAS_DMA_RXCHAN_BASEU(chno),
319 PAS_DMA_RXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32) |
320 PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3));
f5cd7872 321
5c15332b 322 cfg = PAS_DMA_RXCHAN_CFG_HBU(2);
af289e80
OJ
323
324 if (translation_enabled())
325 cfg |= PAS_DMA_RXCHAN_CFG_CTR;
326
34c20624 327 write_dma_reg(PAS_DMA_RXCHAN_CFG(chno), cfg);
f5cd7872 328
34c20624
OJ
329 write_dma_reg(PAS_DMA_RXINT_BASEL(mac->dma_if),
330 PAS_DMA_RXINT_BASEL_BRBL(ring->buf_dma));
f5cd7872 331
34c20624
OJ
332 write_dma_reg(PAS_DMA_RXINT_BASEU(mac->dma_if),
333 PAS_DMA_RXINT_BASEU_BRBH(ring->buf_dma >> 32) |
334 PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
f5cd7872 335
5c15332b 336 cfg = PAS_DMA_RXINT_CFG_DHL(2) | PAS_DMA_RXINT_CFG_L2 |
af289e80
OJ
337 PAS_DMA_RXINT_CFG_LW | PAS_DMA_RXINT_CFG_RBP |
338 PAS_DMA_RXINT_CFG_HEN;
339
340 if (translation_enabled())
341 cfg |= PAS_DMA_RXINT_CFG_ITRR | PAS_DMA_RXINT_CFG_ITR;
342
34c20624 343 write_dma_reg(PAS_DMA_RXINT_CFG(mac->dma_if), cfg);
c0efd52b 344
f5cd7872
OJ
345 ring->next_to_fill = 0;
346 ring->next_to_clean = 0;
72b05b99 347 ring->mac = mac;
f5cd7872
OJ
348 mac->rx = ring;
349
350 return 0;
351
fc9e4d2a
OJ
352out_ring_desc:
353 kfree(ring->ring_info);
354out_ring_info:
34c20624
OJ
355 pasemi_dma_free_chan(&ring->chan);
356out_chan:
f5cd7872
OJ
357 return -ENOMEM;
358}
359
72b05b99 360static struct pasemi_mac_txring *
5c15332b 361pasemi_mac_setup_tx_resources(const struct net_device *dev)
f5cd7872
OJ
362{
363 struct pasemi_mac *mac = netdev_priv(dev);
364 u32 val;
f5cd7872 365 struct pasemi_mac_txring *ring;
af289e80 366 unsigned int cfg;
34c20624 367 int chno;
f5cd7872 368
34c20624
OJ
369 ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_txring),
370 offsetof(struct pasemi_mac_txring, chan));
371
372 if (!ring) {
373 dev_err(&mac->pdev->dev, "Can't allocate TX channel\n");
374 goto out_chan;
375 }
376
377 chno = ring->chan.chno;
f5cd7872
OJ
378
379 spin_lock_init(&ring->lock);
380
021fa22e 381 ring->size = TX_RING_SIZE;
fc9e4d2a 382 ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
f5cd7872 383 TX_RING_SIZE, GFP_KERNEL);
fc9e4d2a
OJ
384 if (!ring->ring_info)
385 goto out_ring_info;
f5cd7872
OJ
386
387 /* Allocate descriptors */
34c20624 388 if (pasemi_dma_alloc_ring(&ring->chan, TX_RING_SIZE))
fc9e4d2a 389 goto out_ring_desc;
f5cd7872 390
34c20624
OJ
391 write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno),
392 PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma));
393 val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32);
fc9e4d2a 394 val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3);
f5cd7872 395
34c20624 396 write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val);
f5cd7872 397
af289e80
OJ
398 cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE |
399 PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
400 PAS_DMA_TXCHAN_CFG_UP |
401 PAS_DMA_TXCHAN_CFG_WT(2);
402
403 if (translation_enabled())
404 cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR;
405
34c20624 406 write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg);
f5cd7872 407
021fa22e 408 ring->next_to_fill = 0;
f5cd7872 409 ring->next_to_clean = 0;
72b05b99 410 ring->mac = mac;
f5cd7872 411
72b05b99 412 return ring;
f5cd7872 413
fc9e4d2a
OJ
414out_ring_desc:
415 kfree(ring->ring_info);
416out_ring_info:
34c20624
OJ
417 pasemi_dma_free_chan(&ring->chan);
418out_chan:
72b05b99 419 return NULL;
f5cd7872
OJ
420}
421
72b05b99 422static void pasemi_mac_free_tx_resources(struct pasemi_mac *mac)
f5cd7872 423{
72b05b99 424 struct pasemi_mac_txring *txring = tx_ring(mac);
ad3c20d1 425 unsigned int i, j;
f5cd7872 426 struct pasemi_mac_buffer *info;
ad3c20d1 427 dma_addr_t dmas[MAX_SKB_FRAGS+1];
7e9916e9 428 int freed, nfrags;
ad5da10a 429 int start, limit;
fc9e4d2a 430
72b05b99
OJ
431 start = txring->next_to_clean;
432 limit = txring->next_to_fill;
ad5da10a
OJ
433
434 /* Compensate for when fill has wrapped and clean has not */
435 if (start > limit)
436 limit += TX_RING_SIZE;
437
438 for (i = start; i < limit; i += freed) {
72b05b99 439 info = &txring->ring_info[(i+1) & (TX_RING_SIZE-1)];
fc9e4d2a 440 if (info->dma && info->skb) {
7e9916e9
OJ
441 nfrags = skb_shinfo(info->skb)->nr_frags;
442 for (j = 0; j <= nfrags; j++)
72b05b99
OJ
443 dmas[j] = txring->ring_info[(i+1+j) &
444 (TX_RING_SIZE-1)].dma;
7e9916e9
OJ
445 freed = pasemi_mac_unmap_tx_skb(mac, nfrags,
446 info->skb, dmas);
ad3c20d1
OJ
447 } else
448 freed = 2;
f5cd7872
OJ
449 }
450
72b05b99 451 kfree(txring->ring_info);
34c20624
OJ
452 pasemi_dma_free_chan(&txring->chan);
453
f5cd7872
OJ
454}
455
72b05b99 456static void pasemi_mac_free_rx_resources(struct pasemi_mac *mac)
f5cd7872 457{
72b05b99 458 struct pasemi_mac_rxring *rx = rx_ring(mac);
f5cd7872
OJ
459 unsigned int i;
460 struct pasemi_mac_buffer *info;
f5cd7872
OJ
461
462 for (i = 0; i < RX_RING_SIZE; i++) {
72b05b99 463 info = &RX_DESC_INFO(rx, i);
fc9e4d2a
OJ
464 if (info->skb && info->dma) {
465 pci_unmap_single(mac->dma_pdev,
466 info->dma,
467 info->skb->len,
468 PCI_DMA_FROMDEVICE);
469 dev_kfree_skb_any(info->skb);
f5cd7872 470 }
fc9e4d2a
OJ
471 info->dma = 0;
472 info->skb = NULL;
f5cd7872
OJ
473 }
474
fc9e4d2a 475 for (i = 0; i < RX_RING_SIZE; i++)
72b05b99 476 RX_DESC(rx, i) = 0;
fc9e4d2a 477
f5cd7872 478 dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64),
72b05b99 479 rx_ring(mac)->buffers, rx_ring(mac)->buf_dma);
f5cd7872 480
72b05b99 481 kfree(rx_ring(mac)->ring_info);
34c20624 482 pasemi_dma_free_chan(&rx_ring(mac)->chan);
f5cd7872
OJ
483 mac->rx = NULL;
484}
485
5c15332b
OJ
486static void pasemi_mac_replenish_rx_ring(const struct net_device *dev,
487 const int limit)
f5cd7872 488{
5c15332b 489 const struct pasemi_mac *mac = netdev_priv(dev);
72b05b99 490 struct pasemi_mac_rxring *rx = rx_ring(mac);
b5254eee 491 int fill, count;
f5cd7872 492
cd4ceb24 493 if (limit <= 0)
f5cd7872
OJ
494 return;
495
72b05b99 496 fill = rx_ring(mac)->next_to_fill;
928773c2 497 for (count = 0; count < limit; count++) {
72b05b99
OJ
498 struct pasemi_mac_buffer *info = &RX_DESC_INFO(rx, fill);
499 u64 *buff = &RX_BUFF(rx, fill);
f5cd7872
OJ
500 struct sk_buff *skb;
501 dma_addr_t dma;
502
fc9e4d2a
OJ
503 /* Entry in use? */
504 WARN_ON(*buff);
505
5d894944
OJ
506 skb = dev_alloc_skb(BUF_SIZE);
507 skb_reserve(skb, LOCAL_SKB_ALIGN);
f5cd7872 508
9f05cfe2 509 if (unlikely(!skb))
f5cd7872 510 break;
f5cd7872 511
8dc121a4
OJ
512 dma = pci_map_single(mac->dma_pdev, skb->data,
513 BUF_SIZE - LOCAL_SKB_ALIGN,
f5cd7872
OJ
514 PCI_DMA_FROMDEVICE);
515
cd4ceb24 516 if (unlikely(dma_mapping_error(dma))) {
f5cd7872 517 dev_kfree_skb_irq(info->skb);
f5cd7872
OJ
518 break;
519 }
520
521 info->skb = skb;
522 info->dma = dma;
523 *buff = XCT_RXB_LEN(BUF_SIZE) | XCT_RXB_ADDR(dma);
fc9e4d2a 524 fill++;
f5cd7872
OJ
525 }
526
527 wmb();
528
34c20624 529 write_dma_reg(PAS_DMA_RXINT_INCR(mac->dma_if), count);
f5cd7872 530
72b05b99 531 rx_ring(mac)->next_to_fill = (rx_ring(mac)->next_to_fill + count) &
b5254eee 532 (RX_RING_SIZE - 1);
f5cd7872
OJ
533}
534
5c15332b 535static void pasemi_mac_restart_rx_intr(const struct pasemi_mac *mac)
1b0335ea 536{
906674ab 537 struct pasemi_mac_rxring *rx = rx_ring(mac);
52a94351 538 unsigned int reg, pcnt;
1b0335ea
OJ
539 /* Re-enable packet count interrupts: finally
540 * ack the packet count interrupt we got in rx_intr.
541 */
542
906674ab 543 pcnt = *rx->chan.status & PAS_STATUS_PCNT_M;
1b0335ea 544
52a94351 545 reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC;
1b0335ea 546
906674ab
OJ
547 if (*rx->chan.status & PAS_STATUS_TIMER)
548 reg |= PAS_IOB_DMA_RXCH_RESET_TINTC;
549
34c20624 550 write_iob_reg(PAS_IOB_DMA_RXCH_RESET(mac->rx->chan.chno), reg);
1b0335ea
OJ
551}
552
5c15332b 553static void pasemi_mac_restart_tx_intr(const struct pasemi_mac *mac)
1b0335ea 554{
52a94351 555 unsigned int reg, pcnt;
1b0335ea
OJ
556
557 /* Re-enable packet count interrupts */
34c20624 558 pcnt = *tx_ring(mac)->chan.status & PAS_STATUS_PCNT_M;
1b0335ea 559
52a94351 560 reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
1b0335ea 561
34c20624 562 write_iob_reg(PAS_IOB_DMA_TXCH_RESET(tx_ring(mac)->chan.chno), reg);
1b0335ea
OJ
563}
564
565
5c15332b
OJ
566static inline void pasemi_mac_rx_error(const struct pasemi_mac *mac,
567 const u64 macrx)
69c29d89
OJ
568{
569 unsigned int rcmdsta, ccmdsta;
34c20624 570 struct pasemi_dmachan *chan = &rx_ring(mac)->chan;
69c29d89
OJ
571
572 if (!netif_msg_rx_err(mac))
573 return;
574
34c20624
OJ
575 rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
576 ccmdsta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno));
69c29d89
OJ
577
578 printk(KERN_ERR "pasemi_mac: rx error. macrx %016lx, rx status %lx\n",
34c20624 579 macrx, *chan->status);
69c29d89
OJ
580
581 printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n",
582 rcmdsta, ccmdsta);
583}
584
5c15332b
OJ
585static inline void pasemi_mac_tx_error(const struct pasemi_mac *mac,
586 const u64 mactx)
69c29d89
OJ
587{
588 unsigned int cmdsta;
34c20624 589 struct pasemi_dmachan *chan = &tx_ring(mac)->chan;
69c29d89
OJ
590
591 if (!netif_msg_tx_err(mac))
592 return;
593
34c20624 594 cmdsta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno));
69c29d89
OJ
595
596 printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016lx, "\
34c20624 597 "tx status 0x%016lx\n", mactx, *chan->status);
69c29d89
OJ
598
599 printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta);
600}
601
5c15332b
OJ
602static int pasemi_mac_clean_rx(struct pasemi_mac_rxring *rx,
603 const int limit)
f5cd7872 604{
5c15332b 605 const struct pasemi_dmachan *chan = &rx->chan;
72b05b99 606 struct pasemi_mac *mac = rx->mac;
5c15332b 607 struct pci_dev *pdev = mac->dma_pdev;
cd4ceb24 608 unsigned int n;
5c15332b 609 int count, buf_index, tot_bytes, packets;
cd4ceb24
OJ
610 struct pasemi_mac_buffer *info;
611 struct sk_buff *skb;
b5254eee 612 unsigned int len;
5c15332b 613 u64 macrx, eval;
cd4ceb24 614 dma_addr_t dma;
5c15332b
OJ
615
616 tot_bytes = 0;
617 packets = 0;
f5cd7872 618
72b05b99 619 spin_lock(&rx->lock);
f5cd7872 620
72b05b99 621 n = rx->next_to_clean;
f5cd7872 622
72b05b99 623 prefetch(&RX_DESC(rx, n));
b5254eee
OJ
624
625 for (count = 0; count < limit; count++) {
72b05b99 626 macrx = RX_DESC(rx, n);
5c15332b 627 prefetch(&RX_DESC(rx, n+4));
f5cd7872 628
69c29d89 629 if ((macrx & XCT_MACRX_E) ||
34c20624 630 (*chan->status & PAS_STATUS_ERROR))
69c29d89
OJ
631 pasemi_mac_rx_error(mac, macrx);
632
cd4ceb24 633 if (!(macrx & XCT_MACRX_O))
f5cd7872
OJ
634 break;
635
f5cd7872
OJ
636 info = NULL;
637
b5254eee 638 BUG_ON(!(macrx & XCT_MACRX_RR_8BRES));
f5cd7872 639
72b05b99 640 eval = (RX_DESC(rx, n+1) & XCT_RXRES_8B_EVAL_M) >>
b5254eee
OJ
641 XCT_RXRES_8B_EVAL_S;
642 buf_index = eval-1;
643
72b05b99
OJ
644 dma = (RX_DESC(rx, n+2) & XCT_PTR_ADDR_M);
645 info = &RX_DESC_INFO(rx, buf_index);
fc9e4d2a 646
9f05cfe2 647 skb = info->skb;
f5cd7872 648
5c15332b 649 prefetch_skb(skb);
f5cd7872 650
cd4ceb24 651 len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S;
f5cd7872 652
5c15332b
OJ
653 pci_unmap_single(pdev, dma, BUF_SIZE-LOCAL_SKB_ALIGN,
654 PCI_DMA_FROMDEVICE);
32bee776
OJ
655
656 if (macrx & XCT_MACRX_CRC) {
657 /* CRC error flagged */
658 mac->netdev->stats.rx_errors++;
659 mac->netdev->stats.rx_crc_errors++;
4352d826 660 /* No need to free skb, it'll be reused */
32bee776
OJ
661 goto next;
662 }
663
5d894944 664 info->skb = NULL;
ad5da10a 665 info->dma = 0;
fc9e4d2a 666
26fcfa95 667 if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) {
38bf3184 668 skb->ip_summed = CHECKSUM_UNNECESSARY;
cd4ceb24 669 skb->csum = (macrx & XCT_MACRX_CSUM_M) >>
f5cd7872
OJ
670 XCT_MACRX_CSUM_S;
671 } else
672 skb->ip_summed = CHECKSUM_NONE;
673
5c15332b
OJ
674 packets++;
675 tot_bytes += len;
676
677 /* Don't include CRC */
678 skb_put(skb, len-4);
f5cd7872 679
26fcfa95 680 skb->protocol = eth_type_trans(skb, mac->netdev);
28ae79f5 681 lro_receive_skb(&mac->lro_mgr, skb, (void *)macrx);
f5cd7872 682
32bee776 683next:
72b05b99
OJ
684 RX_DESC(rx, n) = 0;
685 RX_DESC(rx, n+1) = 0;
cd4ceb24 686
ad5da10a
OJ
687 /* Need to zero it out since hardware doesn't, since the
688 * replenish loop uses it to tell when it's done.
689 */
72b05b99 690 RX_BUFF(rx, buf_index) = 0;
ad5da10a 691
b5254eee 692 n += 4;
f5cd7872
OJ
693 }
694
9a50bebd
OJ
695 if (n > RX_RING_SIZE) {
696 /* Errata 5971 workaround: L2 target of headers */
34c20624 697 write_iob_reg(PAS_IOB_COM_PKTHDRCNT, 0);
9a50bebd
OJ
698 n &= (RX_RING_SIZE-1);
699 }
b5254eee 700
72b05b99 701 rx_ring(mac)->next_to_clean = n;
b5254eee 702
28ae79f5
OJ
703 lro_flush_all(&mac->lro_mgr);
704
b5254eee
OJ
705 /* Increase is in number of 16-byte entries, and since each descriptor
706 * with an 8BRES takes up 3x8 bytes (padded to 4x8), increase with
707 * count*2.
708 */
34c20624 709 write_dma_reg(PAS_DMA_RXCHAN_INCR(mac->rx->chan.chno), count << 1);
b5254eee
OJ
710
711 pasemi_mac_replenish_rx_ring(mac->netdev, count);
f5cd7872 712
5c15332b
OJ
713 mac->netdev->stats.rx_bytes += tot_bytes;
714 mac->netdev->stats.rx_packets += packets;
715
72b05b99 716 spin_unlock(&rx_ring(mac)->lock);
f5cd7872
OJ
717
718 return count;
719}
720
ad3c20d1
OJ
721/* Can't make this too large or we blow the kernel stack limits */
722#define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS)
723
72b05b99 724static int pasemi_mac_clean_tx(struct pasemi_mac_txring *txring)
f5cd7872 725{
34c20624 726 struct pasemi_dmachan *chan = &txring->chan;
72b05b99 727 struct pasemi_mac *mac = txring->mac;
ad3c20d1 728 int i, j;
ad5da10a
OJ
729 unsigned int start, descr_count, buf_count, batch_limit;
730 unsigned int ring_limit;
02df6cfa 731 unsigned int total_count;
ca7e235f 732 unsigned long flags;
ad3c20d1
OJ
733 struct sk_buff *skbs[TX_CLEAN_BATCHSIZE];
734 dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1];
7e9916e9
OJ
735 int nf[TX_CLEAN_BATCHSIZE];
736 int nr_frags;
f5cd7872 737
02df6cfa 738 total_count = 0;
ad5da10a 739 batch_limit = TX_CLEAN_BATCHSIZE;
02df6cfa 740restart:
72b05b99 741 spin_lock_irqsave(&txring->lock, flags);
f5cd7872 742
72b05b99
OJ
743 start = txring->next_to_clean;
744 ring_limit = txring->next_to_fill;
ad5da10a 745
7e9916e9
OJ
746 prefetch(&TX_DESC_INFO(txring, start+1).skb);
747
ad5da10a
OJ
748 /* Compensate for when fill has wrapped but clean has not */
749 if (start > ring_limit)
750 ring_limit += TX_RING_SIZE;
02df6cfa 751
ad3c20d1
OJ
752 buf_count = 0;
753 descr_count = 0;
f5cd7872 754
ad3c20d1 755 for (i = start;
ad5da10a 756 descr_count < batch_limit && i < ring_limit;
ad3c20d1 757 i += buf_count) {
72b05b99 758 u64 mactx = TX_DESC(txring, i);
ad5da10a 759 struct sk_buff *skb;
ad3c20d1 760
7e9916e9
OJ
761 skb = TX_DESC_INFO(txring, i+1).skb;
762 nr_frags = TX_DESC_INFO(txring, i).dma;
763
fc9e4d2a 764 if ((mactx & XCT_MACTX_E) ||
34c20624 765 (*chan->status & PAS_STATUS_ERROR))
fc9e4d2a 766 pasemi_mac_tx_error(mac, mactx);
69c29d89 767
fc9e4d2a 768 if (unlikely(mactx & XCT_MACTX_O))
02df6cfa 769 /* Not yet transmitted */
f5cd7872
OJ
770 break;
771
7e9916e9
OJ
772 buf_count = 2 + nr_frags;
773 /* Since we always fill with an even number of entries, make
774 * sure we skip any unused one at the end as well.
775 */
776 if (buf_count & 1)
777 buf_count++;
ad3c20d1 778
7e9916e9 779 for (j = 0; j <= nr_frags; j++)
72b05b99 780 dmas[descr_count][j] = TX_DESC_INFO(txring, i+1+j).dma;
ad3c20d1 781
7e9916e9
OJ
782 skbs[descr_count] = skb;
783 nf[descr_count] = nr_frags;
784
72b05b99
OJ
785 TX_DESC(txring, i) = 0;
786 TX_DESC(txring, i+1) = 0;
fc9e4d2a 787
ad3c20d1 788 descr_count++;
f5cd7872 789 }
72b05b99 790 txring->next_to_clean = i & (TX_RING_SIZE-1);
ad3c20d1 791
72b05b99 792 spin_unlock_irqrestore(&txring->lock, flags);
0ce68c74
OJ
793 netif_wake_queue(mac->netdev);
794
ad3c20d1 795 for (i = 0; i < descr_count; i++)
7e9916e9 796 pasemi_mac_unmap_tx_skb(mac, nf[i], skbs[i], dmas[i]);
02df6cfa 797
ad3c20d1 798 total_count += descr_count;
02df6cfa
OJ
799
800 /* If the batch was full, try to clean more */
ad5da10a 801 if (descr_count == batch_limit)
02df6cfa
OJ
802 goto restart;
803
804 return total_count;
f5cd7872
OJ
805}
806
807
808static irqreturn_t pasemi_mac_rx_intr(int irq, void *data)
809{
5c15332b 810 const struct pasemi_mac_rxring *rxring = data;
34c20624
OJ
811 struct pasemi_mac *mac = rxring->mac;
812 struct net_device *dev = mac->netdev;
5c15332b 813 const struct pasemi_dmachan *chan = &rxring->chan;
f5cd7872
OJ
814 unsigned int reg;
815
34c20624 816 if (!(*chan->status & PAS_STATUS_CAUSE_M))
f5cd7872
OJ
817 return IRQ_NONE;
818
6dfa7522
OJ
819 /* Don't reset packet count so it won't fire again but clear
820 * all others.
821 */
822
6dfa7522 823 reg = 0;
34c20624 824 if (*chan->status & PAS_STATUS_SOFT)
6dfa7522 825 reg |= PAS_IOB_DMA_RXCH_RESET_SINTC;
34c20624 826 if (*chan->status & PAS_STATUS_ERROR)
6dfa7522 827 reg |= PAS_IOB_DMA_RXCH_RESET_DINTC;
f5cd7872 828
bea3348e 829 netif_rx_schedule(dev, &mac->napi);
6dfa7522 830
34c20624 831 write_iob_reg(PAS_IOB_DMA_RXCH_RESET(chan->chno), reg);
f5cd7872
OJ
832
833 return IRQ_HANDLED;
834}
835
61cec3bd
OJ
836#define TX_CLEAN_INTERVAL HZ
837
838static void pasemi_mac_tx_timer(unsigned long data)
839{
840 struct pasemi_mac_txring *txring = (struct pasemi_mac_txring *)data;
841 struct pasemi_mac *mac = txring->mac;
842
843 pasemi_mac_clean_tx(txring);
844
845 mod_timer(&txring->clean_timer, jiffies + TX_CLEAN_INTERVAL);
846
847 pasemi_mac_restart_tx_intr(mac);
848}
849
f5cd7872
OJ
850static irqreturn_t pasemi_mac_tx_intr(int irq, void *data)
851{
72b05b99 852 struct pasemi_mac_txring *txring = data;
5c15332b 853 const struct pasemi_dmachan *chan = &txring->chan;
61cec3bd
OJ
854 struct pasemi_mac *mac = txring->mac;
855 unsigned int reg;
f5cd7872 856
34c20624 857 if (!(*chan->status & PAS_STATUS_CAUSE_M))
f5cd7872
OJ
858 return IRQ_NONE;
859
61cec3bd 860 reg = 0;
6dfa7522 861
34c20624 862 if (*chan->status & PAS_STATUS_SOFT)
6dfa7522 863 reg |= PAS_IOB_DMA_TXCH_RESET_SINTC;
34c20624 864 if (*chan->status & PAS_STATUS_ERROR)
6dfa7522 865 reg |= PAS_IOB_DMA_TXCH_RESET_DINTC;
f5cd7872 866
61cec3bd
OJ
867 mod_timer(&txring->clean_timer, jiffies + (TX_CLEAN_INTERVAL)*2);
868
869 netif_rx_schedule(mac->netdev, &mac->napi);
870
871 if (reg)
872 write_iob_reg(PAS_IOB_DMA_TXCH_RESET(chan->chno), reg);
f5cd7872 873
f5cd7872
OJ
874 return IRQ_HANDLED;
875}
876
b0cd2f90
OJ
877static void pasemi_mac_intf_disable(struct pasemi_mac *mac)
878{
879 unsigned int flags;
880
881 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
882 flags &= ~PAS_MAC_CFG_PCFG_PE;
883 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
884}
885
886static void pasemi_mac_intf_enable(struct pasemi_mac *mac)
887{
888 unsigned int flags;
889
890 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
891 flags |= PAS_MAC_CFG_PCFG_PE;
892 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
893}
894
bb6e9590
OJ
895static void pasemi_adjust_link(struct net_device *dev)
896{
897 struct pasemi_mac *mac = netdev_priv(dev);
898 int msg;
899 unsigned int flags;
900 unsigned int new_flags;
901
902 if (!mac->phydev->link) {
903 /* If no link, MAC speed settings don't matter. Just report
904 * link down and return.
905 */
906 if (mac->link && netif_msg_link(mac))
907 printk(KERN_INFO "%s: Link is down.\n", dev->name);
908
909 netif_carrier_off(dev);
b0cd2f90 910 pasemi_mac_intf_disable(mac);
bb6e9590
OJ
911 mac->link = 0;
912
913 return;
b0cd2f90
OJ
914 } else {
915 pasemi_mac_intf_enable(mac);
bb6e9590 916 netif_carrier_on(dev);
b0cd2f90 917 }
bb6e9590 918
a85b9422 919 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
bb6e9590
OJ
920 new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M |
921 PAS_MAC_CFG_PCFG_TSR_M);
922
923 if (!mac->phydev->duplex)
924 new_flags |= PAS_MAC_CFG_PCFG_HD;
925
926 switch (mac->phydev->speed) {
927 case 1000:
928 new_flags |= PAS_MAC_CFG_PCFG_SPD_1G |
929 PAS_MAC_CFG_PCFG_TSR_1G;
930 break;
931 case 100:
932 new_flags |= PAS_MAC_CFG_PCFG_SPD_100M |
933 PAS_MAC_CFG_PCFG_TSR_100M;
934 break;
935 case 10:
936 new_flags |= PAS_MAC_CFG_PCFG_SPD_10M |
937 PAS_MAC_CFG_PCFG_TSR_10M;
938 break;
939 default:
940 printk("Unsupported speed %d\n", mac->phydev->speed);
941 }
942
943 /* Print on link or speed/duplex change */
944 msg = mac->link != mac->phydev->link || flags != new_flags;
945
946 mac->duplex = mac->phydev->duplex;
947 mac->speed = mac->phydev->speed;
948 mac->link = mac->phydev->link;
949
950 if (new_flags != flags)
a85b9422 951 write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags);
bb6e9590
OJ
952
953 if (msg && netif_msg_link(mac))
954 printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n",
955 dev->name, mac->speed, mac->duplex ? "full" : "half");
956}
957
958static int pasemi_mac_phy_init(struct net_device *dev)
959{
960 struct pasemi_mac *mac = netdev_priv(dev);
961 struct device_node *dn, *phy_dn;
962 struct phy_device *phydev;
963 unsigned int phy_id;
964 const phandle *ph;
965 const unsigned int *prop;
966 struct resource r;
967 int ret;
968
969 dn = pci_device_to_OF_node(mac->pdev);
9028780a 970 ph = of_get_property(dn, "phy-handle", NULL);
bb6e9590
OJ
971 if (!ph)
972 return -ENODEV;
973 phy_dn = of_find_node_by_phandle(*ph);
974
9028780a 975 prop = of_get_property(phy_dn, "reg", NULL);
bb6e9590
OJ
976 ret = of_address_to_resource(phy_dn->parent, 0, &r);
977 if (ret)
978 goto err;
979
980 phy_id = *prop;
981 snprintf(mac->phy_id, BUS_ID_SIZE, PHY_ID_FMT, (int)r.start, phy_id);
982
983 of_node_put(phy_dn);
984
985 mac->link = 0;
986 mac->speed = 0;
987 mac->duplex = -1;
988
989 phydev = phy_connect(dev, mac->phy_id, &pasemi_adjust_link, 0, PHY_INTERFACE_MODE_SGMII);
990
991 if (IS_ERR(phydev)) {
992 printk(KERN_ERR "%s: Could not attach to phy\n", dev->name);
993 return PTR_ERR(phydev);
994 }
995
996 mac->phydev = phydev;
997
998 return 0;
999
1000err:
1001 of_node_put(phy_dn);
1002 return -ENODEV;
1003}
1004
1005
f5cd7872
OJ
1006static int pasemi_mac_open(struct net_device *dev)
1007{
1008 struct pasemi_mac *mac = netdev_priv(dev);
1009 unsigned int flags;
1010 int ret;
1011
1012 /* enable rx section */
34c20624 1013 write_dma_reg(PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN);
f5cd7872
OJ
1014
1015 /* enable tx section */
34c20624 1016 write_dma_reg(PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN);
f5cd7872
OJ
1017
1018 flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
1019 PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
1020 PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12);
1021
a85b9422 1022 write_mac_reg(mac, PAS_MAC_CFG_TXP, flags);
f5cd7872 1023
f5cd7872
OJ
1024 ret = pasemi_mac_setup_rx_resources(dev);
1025 if (ret)
1026 goto out_rx_resources;
1027
34c20624 1028 mac->tx = pasemi_mac_setup_tx_resources(dev);
72b05b99
OJ
1029
1030 if (!mac->tx)
1031 goto out_tx_ring;
f5cd7872 1032
906674ab
OJ
1033 /* 0x3ff with 33MHz clock is about 31us */
1034 write_iob_reg(PAS_IOB_DMA_COM_TIMEOUTCFG,
1035 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0x3ff));
1036
34c20624 1037 write_iob_reg(PAS_IOB_DMA_RXCH_CFG(mac->rx->chan.chno),
28ae79f5 1038 PAS_IOB_DMA_RXCH_CFG_CNTTH(256));
34c20624
OJ
1039
1040 write_iob_reg(PAS_IOB_DMA_TXCH_CFG(mac->tx->chan.chno),
61cec3bd 1041 PAS_IOB_DMA_TXCH_CFG_CNTTH(32));
34c20624 1042
a85b9422 1043 write_mac_reg(mac, PAS_MAC_IPC_CHNL,
34c20624
OJ
1044 PAS_MAC_IPC_CHNL_DCHNO(mac->rx->chan.chno) |
1045 PAS_MAC_IPC_CHNL_BCH(mac->rx->chan.chno));
f5cd7872
OJ
1046
1047 /* enable rx if */
34c20624
OJ
1048 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
1049 PAS_DMA_RXINT_RCMDSTA_EN |
1050 PAS_DMA_RXINT_RCMDSTA_DROPS_M |
1051 PAS_DMA_RXINT_RCMDSTA_BP |
1052 PAS_DMA_RXINT_RCMDSTA_OO |
1053 PAS_DMA_RXINT_RCMDSTA_BT);
f5cd7872
OJ
1054
1055 /* enable rx channel */
34c20624
OJ
1056 pasemi_dma_start_chan(&rx_ring(mac)->chan, PAS_DMA_RXCHAN_CCMDSTA_DU |
1057 PAS_DMA_RXCHAN_CCMDSTA_OD |
1058 PAS_DMA_RXCHAN_CCMDSTA_FD |
1059 PAS_DMA_RXCHAN_CCMDSTA_DT);
f5cd7872
OJ
1060
1061 /* enable tx channel */
34c20624
OJ
1062 pasemi_dma_start_chan(&tx_ring(mac)->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ |
1063 PAS_DMA_TXCHAN_TCMDSTA_DB |
1064 PAS_DMA_TXCHAN_TCMDSTA_DE |
1065 PAS_DMA_TXCHAN_TCMDSTA_DA);
f5cd7872 1066
928773c2 1067 pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE);
f5cd7872 1068
34c20624
OJ
1069 write_dma_reg(PAS_DMA_RXCHAN_INCR(rx_ring(mac)->chan.chno),
1070 RX_RING_SIZE>>1);
b5254eee 1071
72b05b99
OJ
1072 /* Clear out any residual packet count state from firmware */
1073 pasemi_mac_restart_rx_intr(mac);
1074 pasemi_mac_restart_tx_intr(mac);
1075
b0cd2f90 1076 flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE;
36033766
OJ
1077
1078 if (mac->type == MAC_TYPE_GMAC)
1079 flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G;
1080 else
1081 flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G;
1082
1083 /* Enable interface in MAC */
1084 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
1085
bb6e9590 1086 ret = pasemi_mac_phy_init(dev);
b0cd2f90
OJ
1087 if (ret) {
1088 /* Since we won't get link notification, just enable RX */
1089 pasemi_mac_intf_enable(mac);
1090 if (mac->type == MAC_TYPE_GMAC) {
1091 /* Warn for missing PHY on SGMII (1Gig) ports */
1092 dev_warn(&mac->pdev->dev,
1093 "PHY init failed: %d.\n", ret);
1094 dev_warn(&mac->pdev->dev,
1095 "Defaulting to 1Gbit full duplex\n");
1096 }
8304b633 1097 }
bb6e9590 1098
f5cd7872 1099 netif_start_queue(dev);
bea3348e 1100 napi_enable(&mac->napi);
f5cd7872 1101
72b05b99
OJ
1102 snprintf(mac->tx_irq_name, sizeof(mac->tx_irq_name), "%s tx",
1103 dev->name);
771f7404 1104
34c20624 1105 ret = request_irq(mac->tx->chan.irq, &pasemi_mac_tx_intr, IRQF_DISABLED,
72b05b99 1106 mac->tx_irq_name, mac->tx);
f5cd7872
OJ
1107 if (ret) {
1108 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
34c20624 1109 mac->tx->chan.irq, ret);
f5cd7872
OJ
1110 goto out_tx_int;
1111 }
1112
72b05b99
OJ
1113 snprintf(mac->rx_irq_name, sizeof(mac->rx_irq_name), "%s rx",
1114 dev->name);
1115
34c20624
OJ
1116 ret = request_irq(mac->rx->chan.irq, &pasemi_mac_rx_intr, IRQF_DISABLED,
1117 mac->rx_irq_name, mac->rx);
f5cd7872
OJ
1118 if (ret) {
1119 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
34c20624 1120 mac->rx->chan.irq, ret);
f5cd7872
OJ
1121 goto out_rx_int;
1122 }
1123
bb6e9590
OJ
1124 if (mac->phydev)
1125 phy_start(mac->phydev);
1126
61cec3bd
OJ
1127 init_timer(&mac->tx->clean_timer);
1128 mac->tx->clean_timer.function = pasemi_mac_tx_timer;
1129 mac->tx->clean_timer.data = (unsigned long)mac->tx;
1130 mac->tx->clean_timer.expires = jiffies+HZ;
1131 add_timer(&mac->tx->clean_timer);
1132
f5cd7872
OJ
1133 return 0;
1134
1135out_rx_int:
34c20624 1136 free_irq(mac->tx->chan.irq, mac->tx);
f5cd7872 1137out_tx_int:
bea3348e 1138 napi_disable(&mac->napi);
f5cd7872 1139 netif_stop_queue(dev);
72b05b99
OJ
1140out_tx_ring:
1141 if (mac->tx)
1142 pasemi_mac_free_tx_resources(mac);
1143 pasemi_mac_free_rx_resources(mac);
f5cd7872
OJ
1144out_rx_resources:
1145
1146 return ret;
1147}
1148
1149#define MAX_RETRIES 5000
1150
1151static int pasemi_mac_close(struct net_device *dev)
1152{
1153 struct pasemi_mac *mac = netdev_priv(dev);
9e81d331 1154 unsigned int sta;
f5cd7872 1155 int retries;
34c20624
OJ
1156 int rxch, txch;
1157
1158 rxch = rx_ring(mac)->chan.chno;
1159 txch = tx_ring(mac)->chan.chno;
f5cd7872 1160
bb6e9590
OJ
1161 if (mac->phydev) {
1162 phy_stop(mac->phydev);
1163 phy_disconnect(mac->phydev);
1164 }
1165
61cec3bd
OJ
1166 del_timer_sync(&mac->tx->clean_timer);
1167
f5cd7872 1168 netif_stop_queue(dev);
bea3348e 1169 napi_disable(&mac->napi);
f5cd7872 1170
34c20624 1171 sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
9e81d331
OJ
1172 if (sta & (PAS_DMA_RXINT_RCMDSTA_BP |
1173 PAS_DMA_RXINT_RCMDSTA_OO |
1174 PAS_DMA_RXINT_RCMDSTA_BT))
1175 printk(KERN_DEBUG "pasemi_mac: rcmdsta error: 0x%08x\n", sta);
1176
34c20624 1177 sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch));
9e81d331
OJ
1178 if (sta & (PAS_DMA_RXCHAN_CCMDSTA_DU |
1179 PAS_DMA_RXCHAN_CCMDSTA_OD |
1180 PAS_DMA_RXCHAN_CCMDSTA_FD |
1181 PAS_DMA_RXCHAN_CCMDSTA_DT))
1182 printk(KERN_DEBUG "pasemi_mac: ccmdsta error: 0x%08x\n", sta);
1183
34c20624 1184 sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch));
72b05b99
OJ
1185 if (sta & (PAS_DMA_TXCHAN_TCMDSTA_SZ | PAS_DMA_TXCHAN_TCMDSTA_DB |
1186 PAS_DMA_TXCHAN_TCMDSTA_DE | PAS_DMA_TXCHAN_TCMDSTA_DA))
9e81d331
OJ
1187 printk(KERN_DEBUG "pasemi_mac: tcmdsta error: 0x%08x\n", sta);
1188
f5cd7872 1189 /* Clean out any pending buffers */
72b05b99
OJ
1190 pasemi_mac_clean_tx(tx_ring(mac));
1191 pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE);
f5cd7872
OJ
1192
1193 /* Disable interface */
34c20624 1194 write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch),
72b05b99 1195 PAS_DMA_TXCHAN_TCMDSTA_ST);
34c20624 1196 write_dma_reg( PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
72b05b99 1197 PAS_DMA_RXINT_RCMDSTA_ST);
34c20624 1198 write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch),
72b05b99 1199 PAS_DMA_RXCHAN_CCMDSTA_ST);
f5cd7872
OJ
1200
1201 for (retries = 0; retries < MAX_RETRIES; retries++) {
34c20624 1202 sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(rxch));
9e81d331 1203 if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT))
f5cd7872
OJ
1204 break;
1205 cond_resched();
1206 }
1207
9e81d331 1208 if (sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)
34c20624 1209 dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n");
f5cd7872
OJ
1210
1211 for (retries = 0; retries < MAX_RETRIES; retries++) {
34c20624 1212 sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch));
9e81d331 1213 if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT))
f5cd7872
OJ
1214 break;
1215 cond_resched();
1216 }
1217
9e81d331 1218 if (sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)
f5cd7872 1219 dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n");
f5cd7872
OJ
1220
1221 for (retries = 0; retries < MAX_RETRIES; retries++) {
34c20624 1222 sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
9e81d331 1223 if (!(sta & PAS_DMA_RXINT_RCMDSTA_ACT))
f5cd7872
OJ
1224 break;
1225 cond_resched();
1226 }
1227
9e81d331 1228 if (sta & PAS_DMA_RXINT_RCMDSTA_ACT)
f5cd7872 1229 dev_err(&mac->dma_pdev->dev, "Failed to stop rx interface\n");
f5cd7872
OJ
1230
1231 /* Then, disable the channel. This must be done separately from
1232 * stopping, since you can't disable when active.
1233 */
1234
34c20624
OJ
1235 write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), 0);
1236 write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), 0);
1237 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0);
f5cd7872 1238
34c20624
OJ
1239 free_irq(mac->tx->chan.irq, mac->tx);
1240 free_irq(mac->rx->chan.irq, mac->rx);
f5cd7872
OJ
1241
1242 /* Free resources */
72b05b99
OJ
1243 pasemi_mac_free_rx_resources(mac);
1244 pasemi_mac_free_tx_resources(mac);
f5cd7872
OJ
1245
1246 return 0;
1247}
1248
1249static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
1250{
1251 struct pasemi_mac *mac = netdev_priv(dev);
1252 struct pasemi_mac_txring *txring;
ad3c20d1
OJ
1253 u64 dflags, mactx;
1254 dma_addr_t map[MAX_SKB_FRAGS+1];
1255 unsigned int map_size[MAX_SKB_FRAGS+1];
ca7e235f 1256 unsigned long flags;
ad3c20d1 1257 int i, nfrags;
5c15332b 1258 int fill;
f5cd7872 1259
dbd62af7 1260 dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD;
f5cd7872
OJ
1261
1262 if (skb->ip_summed == CHECKSUM_PARTIAL) {
d56f90a7
ACM
1263 const unsigned char *nh = skb_network_header(skb);
1264
eddc9ec5 1265 switch (ip_hdr(skb)->protocol) {
f5cd7872
OJ
1266 case IPPROTO_TCP:
1267 dflags |= XCT_MACTX_CSUM_TCP;
cfe1fc77 1268 dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
d56f90a7 1269 dflags |= XCT_MACTX_IPO(nh - skb->data);
f5cd7872
OJ
1270 break;
1271 case IPPROTO_UDP:
1272 dflags |= XCT_MACTX_CSUM_UDP;
cfe1fc77 1273 dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
d56f90a7 1274 dflags |= XCT_MACTX_IPO(nh - skb->data);
f5cd7872
OJ
1275 break;
1276 }
1277 }
1278
ad3c20d1
OJ
1279 nfrags = skb_shinfo(skb)->nr_frags;
1280
1281 map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb),
1282 PCI_DMA_TODEVICE);
1283 map_size[0] = skb_headlen(skb);
1284 if (dma_mapping_error(map[0]))
1285 goto out_err_nolock;
1286
1287 for (i = 0; i < nfrags; i++) {
1288 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
f5cd7872 1289
ad3c20d1
OJ
1290 map[i+1] = pci_map_page(mac->dma_pdev, frag->page,
1291 frag->page_offset, frag->size,
1292 PCI_DMA_TODEVICE);
1293 map_size[i+1] = frag->size;
1294 if (dma_mapping_error(map[i+1])) {
1295 nfrags = i;
1296 goto out_err_nolock;
1297 }
1298 }
f5cd7872 1299
26fcfa95 1300 mactx = dflags | XCT_MACTX_LLEN(skb->len);
26fcfa95 1301
72b05b99 1302 txring = tx_ring(mac);
f5cd7872
OJ
1303
1304 spin_lock_irqsave(&txring->lock, flags);
1305
5c15332b
OJ
1306 fill = txring->next_to_fill;
1307
ad5da10a
OJ
1308 /* Avoid stepping on the same cache line that the DMA controller
1309 * is currently about to send, so leave at least 8 words available.
1310 * Total free space needed is mactx + fragments + 8
1311 */
1312 if (RING_AVAIL(txring) < nfrags + 10) {
1313 /* no room -- stop the queue and wait for tx intr */
1314 netif_stop_queue(dev);
1315 goto out_err;
f5cd7872
OJ
1316 }
1317
5c15332b 1318 TX_DESC(txring, fill) = mactx;
7e9916e9 1319 TX_DESC_INFO(txring, fill).dma = nfrags;
5c15332b
OJ
1320 fill++;
1321 TX_DESC_INFO(txring, fill).skb = skb;
ad3c20d1 1322 for (i = 0; i <= nfrags; i++) {
5c15332b 1323 TX_DESC(txring, fill+i) =
72b05b99 1324 XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
5c15332b 1325 TX_DESC_INFO(txring, fill+i).dma = map[i];
ad3c20d1
OJ
1326 }
1327
1328 /* We have to add an even number of 8-byte entries to the ring
1329 * even if the last one is unused. That means always an odd number
1330 * of pointers + one mactx descriptor.
1331 */
1332 if (nfrags & 1)
1333 nfrags++;
fc9e4d2a 1334
5c15332b 1335 txring->next_to_fill = (fill + nfrags + 1) & (TX_RING_SIZE-1);
f5cd7872 1336
09f75cd7
JG
1337 dev->stats.tx_packets++;
1338 dev->stats.tx_bytes += skb->len;
f5cd7872
OJ
1339
1340 spin_unlock_irqrestore(&txring->lock, flags);
1341
34c20624 1342 write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), (nfrags+2) >> 1);
f5cd7872
OJ
1343
1344 return NETDEV_TX_OK;
1345
1346out_err:
1347 spin_unlock_irqrestore(&txring->lock, flags);
ad3c20d1
OJ
1348out_err_nolock:
1349 while (nfrags--)
1350 pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags],
1351 PCI_DMA_TODEVICE);
1352
f5cd7872
OJ
1353 return NETDEV_TX_BUSY;
1354}
1355
f5cd7872
OJ
1356static void pasemi_mac_set_rx_mode(struct net_device *dev)
1357{
5c15332b 1358 const struct pasemi_mac *mac = netdev_priv(dev);
f5cd7872
OJ
1359 unsigned int flags;
1360
a85b9422 1361 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
f5cd7872
OJ
1362
1363 /* Set promiscuous */
1364 if (dev->flags & IFF_PROMISC)
1365 flags |= PAS_MAC_CFG_PCFG_PR;
1366 else
1367 flags &= ~PAS_MAC_CFG_PCFG_PR;
1368
a85b9422 1369 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
f5cd7872
OJ
1370}
1371
1372
bea3348e 1373static int pasemi_mac_poll(struct napi_struct *napi, int budget)
f5cd7872 1374{
bea3348e
SH
1375 struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi);
1376 struct net_device *dev = mac->netdev;
1377 int pkts;
f5cd7872 1378
72b05b99
OJ
1379 pasemi_mac_clean_tx(tx_ring(mac));
1380 pkts = pasemi_mac_clean_rx(rx_ring(mac), budget);
bea3348e 1381 if (pkts < budget) {
f5cd7872 1382 /* all done, no more packets present */
bea3348e 1383 netif_rx_complete(dev, napi);
f5cd7872 1384
1b0335ea 1385 pasemi_mac_restart_rx_intr(mac);
61cec3bd 1386 pasemi_mac_restart_tx_intr(mac);
f5cd7872 1387 }
bea3348e 1388 return pkts;
f5cd7872
OJ
1389}
1390
1391static int __devinit
1392pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1393{
f5cd7872
OJ
1394 struct net_device *dev;
1395 struct pasemi_mac *mac;
1396 int err;
0795af57 1397 DECLARE_MAC_BUF(mac_buf);
f5cd7872
OJ
1398
1399 err = pci_enable_device(pdev);
1400 if (err)
1401 return err;
1402
1403 dev = alloc_etherdev(sizeof(struct pasemi_mac));
1404 if (dev == NULL) {
1405 dev_err(&pdev->dev,
1406 "pasemi_mac: Could not allocate ethernet device.\n");
1407 err = -ENOMEM;
1408 goto out_disable_device;
1409 }
1410
f5cd7872
OJ
1411 pci_set_drvdata(pdev, dev);
1412 SET_NETDEV_DEV(dev, &pdev->dev);
1413
1414 mac = netdev_priv(dev);
1415
1416 mac->pdev = pdev;
1417 mac->netdev = dev;
f5cd7872 1418
bea3348e
SH
1419 netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64);
1420
5c15332b
OJ
1421 dev->features = NETIF_F_IP_CSUM | NETIF_F_LLTX | NETIF_F_SG |
1422 NETIF_F_HIGHDMA;
bea3348e 1423
28ae79f5
OJ
1424 mac->lro_mgr.max_aggr = LRO_MAX_AGGR;
1425 mac->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS;
1426 mac->lro_mgr.lro_arr = mac->lro_desc;
1427 mac->lro_mgr.get_skb_header = get_skb_hdr;
1428 mac->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
1429 mac->lro_mgr.dev = mac->netdev;
1430 mac->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1431 mac->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1432
1433
34c20624
OJ
1434 mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
1435 if (!mac->dma_pdev) {
1436 dev_err(&mac->pdev->dev, "Can't find DMA Controller\n");
1437 err = -ENODEV;
1438 goto out;
1439 }
f5cd7872 1440
34c20624
OJ
1441 mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
1442 if (!mac->iob_pdev) {
1443 dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n");
1444 err = -ENODEV;
1445 goto out;
1446 }
1447
1448 /* get mac addr from device tree */
1449 if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) {
1450 err = -ENODEV;
1451 goto out;
1452 }
1453 memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr));
1454
1455 mac->dma_if = mac_to_intf(mac);
1456 if (mac->dma_if < 0) {
1457 dev_err(&mac->pdev->dev, "Can't map DMA interface\n");
1458 err = -ENODEV;
1459 goto out;
1460 }
f5cd7872
OJ
1461
1462 switch (pdev->device) {
1463 case 0xa005:
1464 mac->type = MAC_TYPE_GMAC;
1465 break;
1466 case 0xa006:
1467 mac->type = MAC_TYPE_XAUI;
1468 break;
1469 default:
1470 err = -ENODEV;
1471 goto out;
1472 }
1473
f5cd7872
OJ
1474 dev->open = pasemi_mac_open;
1475 dev->stop = pasemi_mac_close;
1476 dev->hard_start_xmit = pasemi_mac_start_tx;
f5cd7872 1477 dev->set_multicast_list = pasemi_mac_set_rx_mode;
f5cd7872 1478
b6e05a1b
OJ
1479 if (err)
1480 goto out;
f5cd7872 1481
ceb51361
OJ
1482 mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
1483
bb6e9590
OJ
1484 /* Enable most messages by default */
1485 mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1486
f5cd7872
OJ
1487 err = register_netdev(dev);
1488
1489 if (err) {
1490 dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n",
1491 err);
1492 goto out;
69c29d89 1493 } else if netif_msg_probe(mac)
72b05b99 1494 printk(KERN_INFO "%s: PA Semi %s: intf %d, hw addr %s\n",
f5cd7872 1495 dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI",
72b05b99 1496 mac->dma_if, print_mac(mac_buf, dev->dev_addr));
f5cd7872
OJ
1497
1498 return err;
1499
1500out:
b6e05a1b
OJ
1501 if (mac->iob_pdev)
1502 pci_dev_put(mac->iob_pdev);
1503 if (mac->dma_pdev)
1504 pci_dev_put(mac->dma_pdev);
b6e05a1b 1505
f5cd7872
OJ
1506 free_netdev(dev);
1507out_disable_device:
1508 pci_disable_device(pdev);
1509 return err;
1510
1511}
1512
1513static void __devexit pasemi_mac_remove(struct pci_dev *pdev)
1514{
1515 struct net_device *netdev = pci_get_drvdata(pdev);
1516 struct pasemi_mac *mac;
1517
1518 if (!netdev)
1519 return;
1520
1521 mac = netdev_priv(netdev);
1522
1523 unregister_netdev(netdev);
1524
1525 pci_disable_device(pdev);
1526 pci_dev_put(mac->dma_pdev);
1527 pci_dev_put(mac->iob_pdev);
1528
34c20624
OJ
1529 pasemi_dma_free_chan(&mac->tx->chan);
1530 pasemi_dma_free_chan(&mac->rx->chan);
b6e05a1b 1531
f5cd7872
OJ
1532 pci_set_drvdata(pdev, NULL);
1533 free_netdev(netdev);
1534}
1535
1536static struct pci_device_id pasemi_mac_pci_tbl[] = {
1537 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) },
1538 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) },
fd178254 1539 { },
f5cd7872
OJ
1540};
1541
1542MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl);
1543
1544static struct pci_driver pasemi_mac_driver = {
1545 .name = "pasemi_mac",
1546 .id_table = pasemi_mac_pci_tbl,
1547 .probe = pasemi_mac_probe,
1548 .remove = __devexit_p(pasemi_mac_remove),
1549};
1550
1551static void __exit pasemi_mac_cleanup_module(void)
1552{
1553 pci_unregister_driver(&pasemi_mac_driver);
f5cd7872
OJ
1554}
1555
1556int pasemi_mac_init_module(void)
1557{
34c20624
OJ
1558 int err;
1559
1560 err = pasemi_dma_init();
1561 if (err)
1562 return err;
1563
f5cd7872
OJ
1564 return pci_register_driver(&pasemi_mac_driver);
1565}
1566
f5cd7872
OJ
1567module_init(pasemi_mac_init_module);
1568module_exit(pasemi_mac_cleanup_module);
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