Commit | Line | Data |
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f5cd7872 OJ |
1 | /* |
2 | * Copyright (C) 2006-2007 PA Semi, Inc | |
3 | * | |
4 | * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/dmaengine.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/netdevice.h> | |
27 | #include <linux/etherdevice.h> | |
28 | #include <asm/dma-mapping.h> | |
29 | #include <linux/in.h> | |
30 | #include <linux/skbuff.h> | |
31 | ||
32 | #include <linux/ip.h> | |
33 | #include <linux/tcp.h> | |
34 | #include <net/checksum.h> | |
35 | ||
771f7404 OJ |
36 | #include <asm/irq.h> |
37 | ||
f5cd7872 OJ |
38 | #include "pasemi_mac.h" |
39 | ||
40 | ||
41 | /* TODO list | |
42 | * | |
43 | * - Get rid of pci_{read,write}_config(), map registers with ioremap | |
44 | * for performance | |
45 | * - PHY support | |
46 | * - Multicast support | |
47 | * - Large MTU support | |
48 | * - Other performance improvements | |
49 | */ | |
50 | ||
51 | ||
52 | /* Must be a power of two */ | |
53 | #define RX_RING_SIZE 512 | |
54 | #define TX_RING_SIZE 512 | |
55 | ||
ceb51361 OJ |
56 | #define DEFAULT_MSG_ENABLE \ |
57 | (NETIF_MSG_DRV | \ | |
58 | NETIF_MSG_PROBE | \ | |
59 | NETIF_MSG_LINK | \ | |
60 | NETIF_MSG_TIMER | \ | |
61 | NETIF_MSG_IFDOWN | \ | |
62 | NETIF_MSG_IFUP | \ | |
63 | NETIF_MSG_RX_ERR | \ | |
64 | NETIF_MSG_TX_ERR) | |
65 | ||
f5cd7872 OJ |
66 | #define TX_DESC(mac, num) ((mac)->tx->desc[(num) & (TX_RING_SIZE-1)]) |
67 | #define TX_DESC_INFO(mac, num) ((mac)->tx->desc_info[(num) & (TX_RING_SIZE-1)]) | |
68 | #define RX_DESC(mac, num) ((mac)->rx->desc[(num) & (RX_RING_SIZE-1)]) | |
69 | #define RX_DESC_INFO(mac, num) ((mac)->rx->desc_info[(num) & (RX_RING_SIZE-1)]) | |
70 | #define RX_BUFF(mac, num) ((mac)->rx->buffers[(num) & (RX_RING_SIZE-1)]) | |
71 | ||
72 | #define BUF_SIZE 1646 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */ | |
73 | ||
ceb51361 OJ |
74 | MODULE_LICENSE("GPL"); |
75 | MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>"); | |
76 | MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver"); | |
77 | ||
78 | static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */ | |
79 | module_param(debug, int, 0); | |
80 | MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value"); | |
f5cd7872 OJ |
81 | |
82 | static struct pasdma_status *dma_status; | |
83 | ||
84 | static int pasemi_get_mac_addr(struct pasemi_mac *mac) | |
85 | { | |
86 | struct pci_dev *pdev = mac->pdev; | |
87 | struct device_node *dn = pci_device_to_OF_node(pdev); | |
88 | const u8 *maddr; | |
89 | u8 addr[6]; | |
90 | ||
91 | if (!dn) { | |
92 | dev_dbg(&pdev->dev, | |
93 | "No device node for mac, not configuring\n"); | |
94 | return -ENOENT; | |
95 | } | |
96 | ||
9028780a | 97 | maddr = of_get_property(dn, "local-mac-address", NULL); |
a5fd22eb OJ |
98 | |
99 | /* Fall back to mac-address for older firmware */ | |
100 | if (maddr == NULL) | |
9028780a | 101 | maddr = of_get_property(dn, "mac-address", NULL); |
a5fd22eb | 102 | |
f5cd7872 OJ |
103 | if (maddr == NULL) { |
104 | dev_warn(&pdev->dev, | |
105 | "no mac address in device tree, not configuring\n"); | |
106 | return -ENOENT; | |
107 | } | |
108 | ||
109 | if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0], | |
110 | &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) { | |
111 | dev_warn(&pdev->dev, | |
112 | "can't parse mac address, not configuring\n"); | |
113 | return -EINVAL; | |
114 | } | |
115 | ||
116 | memcpy(mac->mac_addr, addr, sizeof(addr)); | |
117 | return 0; | |
118 | } | |
119 | ||
120 | static int pasemi_mac_setup_rx_resources(struct net_device *dev) | |
121 | { | |
122 | struct pasemi_mac_rxring *ring; | |
123 | struct pasemi_mac *mac = netdev_priv(dev); | |
124 | int chan_id = mac->dma_rxch; | |
125 | ||
126 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); | |
127 | ||
128 | if (!ring) | |
129 | goto out_ring; | |
130 | ||
131 | spin_lock_init(&ring->lock); | |
132 | ||
133 | ring->desc_info = kzalloc(sizeof(struct pasemi_mac_buffer) * | |
134 | RX_RING_SIZE, GFP_KERNEL); | |
135 | ||
136 | if (!ring->desc_info) | |
137 | goto out_desc_info; | |
138 | ||
139 | /* Allocate descriptors */ | |
140 | ring->desc = dma_alloc_coherent(&mac->dma_pdev->dev, | |
141 | RX_RING_SIZE * | |
142 | sizeof(struct pas_dma_xct_descr), | |
143 | &ring->dma, GFP_KERNEL); | |
144 | ||
145 | if (!ring->desc) | |
146 | goto out_desc; | |
147 | ||
148 | memset(ring->desc, 0, RX_RING_SIZE * sizeof(struct pas_dma_xct_descr)); | |
149 | ||
150 | ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev, | |
151 | RX_RING_SIZE * sizeof(u64), | |
152 | &ring->buf_dma, GFP_KERNEL); | |
153 | if (!ring->buffers) | |
154 | goto out_buffers; | |
155 | ||
156 | memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64)); | |
157 | ||
158 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_BASEL(chan_id), | |
159 | PAS_DMA_RXCHAN_BASEL_BRBL(ring->dma)); | |
160 | ||
161 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_BASEU(chan_id), | |
162 | PAS_DMA_RXCHAN_BASEU_BRBH(ring->dma >> 32) | | |
163 | PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 2)); | |
164 | ||
165 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_CFG(chan_id), | |
166 | PAS_DMA_RXCHAN_CFG_HBU(1)); | |
167 | ||
168 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXINT_BASEL(mac->dma_if), | |
169 | PAS_DMA_RXINT_BASEL_BRBL(__pa(ring->buffers))); | |
170 | ||
171 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXINT_BASEU(mac->dma_if), | |
172 | PAS_DMA_RXINT_BASEU_BRBH(__pa(ring->buffers) >> 32) | | |
173 | PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3)); | |
174 | ||
175 | ring->next_to_fill = 0; | |
176 | ring->next_to_clean = 0; | |
177 | ||
178 | snprintf(ring->irq_name, sizeof(ring->irq_name), | |
179 | "%s rx", dev->name); | |
180 | mac->rx = ring; | |
181 | ||
182 | return 0; | |
183 | ||
184 | out_buffers: | |
185 | dma_free_coherent(&mac->dma_pdev->dev, | |
186 | RX_RING_SIZE * sizeof(struct pas_dma_xct_descr), | |
187 | mac->rx->desc, mac->rx->dma); | |
188 | out_desc: | |
189 | kfree(ring->desc_info); | |
190 | out_desc_info: | |
191 | kfree(ring); | |
192 | out_ring: | |
193 | return -ENOMEM; | |
194 | } | |
195 | ||
196 | ||
197 | static int pasemi_mac_setup_tx_resources(struct net_device *dev) | |
198 | { | |
199 | struct pasemi_mac *mac = netdev_priv(dev); | |
200 | u32 val; | |
201 | int chan_id = mac->dma_txch; | |
202 | struct pasemi_mac_txring *ring; | |
203 | ||
204 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); | |
205 | if (!ring) | |
206 | goto out_ring; | |
207 | ||
208 | spin_lock_init(&ring->lock); | |
209 | ||
210 | ring->desc_info = kzalloc(sizeof(struct pasemi_mac_buffer) * | |
211 | TX_RING_SIZE, GFP_KERNEL); | |
212 | if (!ring->desc_info) | |
213 | goto out_desc_info; | |
214 | ||
215 | /* Allocate descriptors */ | |
216 | ring->desc = dma_alloc_coherent(&mac->dma_pdev->dev, | |
217 | TX_RING_SIZE * | |
218 | sizeof(struct pas_dma_xct_descr), | |
219 | &ring->dma, GFP_KERNEL); | |
220 | if (!ring->desc) | |
221 | goto out_desc; | |
222 | ||
223 | memset(ring->desc, 0, TX_RING_SIZE * sizeof(struct pas_dma_xct_descr)); | |
224 | ||
225 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_BASEL(chan_id), | |
226 | PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma)); | |
227 | val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32); | |
228 | val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2); | |
229 | ||
230 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_BASEU(chan_id), val); | |
231 | ||
232 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_CFG(chan_id), | |
233 | PAS_DMA_TXCHAN_CFG_TY_IFACE | | |
234 | PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) | | |
235 | PAS_DMA_TXCHAN_CFG_UP | | |
236 | PAS_DMA_TXCHAN_CFG_WT(2)); | |
237 | ||
238 | ring->next_to_use = 0; | |
239 | ring->next_to_clean = 0; | |
240 | ||
241 | snprintf(ring->irq_name, sizeof(ring->irq_name), | |
242 | "%s tx", dev->name); | |
243 | mac->tx = ring; | |
244 | ||
245 | return 0; | |
246 | ||
247 | out_desc: | |
248 | kfree(ring->desc_info); | |
249 | out_desc_info: | |
250 | kfree(ring); | |
251 | out_ring: | |
252 | return -ENOMEM; | |
253 | } | |
254 | ||
255 | static void pasemi_mac_free_tx_resources(struct net_device *dev) | |
256 | { | |
257 | struct pasemi_mac *mac = netdev_priv(dev); | |
258 | unsigned int i; | |
259 | struct pasemi_mac_buffer *info; | |
260 | struct pas_dma_xct_descr *dp; | |
261 | ||
262 | for (i = 0; i < TX_RING_SIZE; i++) { | |
263 | info = &TX_DESC_INFO(mac, i); | |
264 | dp = &TX_DESC(mac, i); | |
265 | if (info->dma) { | |
266 | if (info->skb) { | |
267 | pci_unmap_single(mac->dma_pdev, | |
268 | info->dma, | |
269 | info->skb->len, | |
270 | PCI_DMA_TODEVICE); | |
271 | dev_kfree_skb_any(info->skb); | |
272 | } | |
273 | info->dma = 0; | |
274 | info->skb = NULL; | |
275 | dp->mactx = 0; | |
276 | dp->ptr = 0; | |
277 | } | |
278 | } | |
279 | ||
280 | dma_free_coherent(&mac->dma_pdev->dev, | |
281 | TX_RING_SIZE * sizeof(struct pas_dma_xct_descr), | |
282 | mac->tx->desc, mac->tx->dma); | |
283 | ||
284 | kfree(mac->tx->desc_info); | |
285 | kfree(mac->tx); | |
286 | mac->tx = NULL; | |
287 | } | |
288 | ||
289 | static void pasemi_mac_free_rx_resources(struct net_device *dev) | |
290 | { | |
291 | struct pasemi_mac *mac = netdev_priv(dev); | |
292 | unsigned int i; | |
293 | struct pasemi_mac_buffer *info; | |
294 | struct pas_dma_xct_descr *dp; | |
295 | ||
296 | for (i = 0; i < RX_RING_SIZE; i++) { | |
297 | info = &RX_DESC_INFO(mac, i); | |
298 | dp = &RX_DESC(mac, i); | |
9f05cfe2 OJ |
299 | if (info->skb) { |
300 | if (info->dma) { | |
f5cd7872 OJ |
301 | pci_unmap_single(mac->dma_pdev, |
302 | info->dma, | |
303 | info->skb->len, | |
304 | PCI_DMA_FROMDEVICE); | |
305 | dev_kfree_skb_any(info->skb); | |
306 | } | |
307 | info->dma = 0; | |
308 | info->skb = NULL; | |
309 | dp->macrx = 0; | |
310 | dp->ptr = 0; | |
311 | } | |
312 | } | |
313 | ||
314 | dma_free_coherent(&mac->dma_pdev->dev, | |
315 | RX_RING_SIZE * sizeof(struct pas_dma_xct_descr), | |
316 | mac->rx->desc, mac->rx->dma); | |
317 | ||
318 | dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64), | |
319 | mac->rx->buffers, mac->rx->buf_dma); | |
320 | ||
321 | kfree(mac->rx->desc_info); | |
322 | kfree(mac->rx); | |
323 | mac->rx = NULL; | |
324 | } | |
325 | ||
326 | static void pasemi_mac_replenish_rx_ring(struct net_device *dev) | |
327 | { | |
328 | struct pasemi_mac *mac = netdev_priv(dev); | |
329 | unsigned int i; | |
330 | int start = mac->rx->next_to_fill; | |
cd4ceb24 | 331 | unsigned int limit, count; |
f5cd7872 | 332 | |
cd4ceb24 | 333 | limit = (mac->rx->next_to_clean + RX_RING_SIZE - |
f5cd7872 OJ |
334 | mac->rx->next_to_fill) & (RX_RING_SIZE - 1); |
335 | ||
336 | /* Check to see if we're doing first-time setup */ | |
337 | if (unlikely(mac->rx->next_to_clean == 0 && mac->rx->next_to_fill == 0)) | |
cd4ceb24 | 338 | limit = RX_RING_SIZE; |
f5cd7872 | 339 | |
cd4ceb24 | 340 | if (limit <= 0) |
f5cd7872 OJ |
341 | return; |
342 | ||
cd4ceb24 OJ |
343 | i = start; |
344 | for (count = limit; count; count--) { | |
f5cd7872 OJ |
345 | struct pasemi_mac_buffer *info = &RX_DESC_INFO(mac, i); |
346 | u64 *buff = &RX_BUFF(mac, i); | |
347 | struct sk_buff *skb; | |
348 | dma_addr_t dma; | |
349 | ||
9f05cfe2 OJ |
350 | /* skb might still be in there for recycle on short receives */ |
351 | if (info->skb) | |
352 | skb = info->skb; | |
353 | else | |
354 | skb = dev_alloc_skb(BUF_SIZE); | |
f5cd7872 | 355 | |
9f05cfe2 | 356 | if (unlikely(!skb)) |
f5cd7872 | 357 | break; |
f5cd7872 | 358 | |
f5cd7872 OJ |
359 | dma = pci_map_single(mac->dma_pdev, skb->data, skb->len, |
360 | PCI_DMA_FROMDEVICE); | |
361 | ||
cd4ceb24 | 362 | if (unlikely(dma_mapping_error(dma))) { |
f5cd7872 | 363 | dev_kfree_skb_irq(info->skb); |
f5cd7872 OJ |
364 | break; |
365 | } | |
366 | ||
367 | info->skb = skb; | |
368 | info->dma = dma; | |
369 | *buff = XCT_RXB_LEN(BUF_SIZE) | XCT_RXB_ADDR(dma); | |
cd4ceb24 | 370 | i++; |
f5cd7872 OJ |
371 | } |
372 | ||
373 | wmb(); | |
374 | ||
375 | pci_write_config_dword(mac->dma_pdev, | |
376 | PAS_DMA_RXCHAN_INCR(mac->dma_rxch), | |
cd4ceb24 | 377 | limit - count); |
f5cd7872 OJ |
378 | pci_write_config_dword(mac->dma_pdev, |
379 | PAS_DMA_RXINT_INCR(mac->dma_if), | |
cd4ceb24 | 380 | limit - count); |
f5cd7872 | 381 | |
cd4ceb24 | 382 | mac->rx->next_to_fill += limit - count; |
f5cd7872 OJ |
383 | } |
384 | ||
1b0335ea OJ |
385 | static void pasemi_mac_restart_rx_intr(struct pasemi_mac *mac) |
386 | { | |
52a94351 | 387 | unsigned int reg, pcnt; |
1b0335ea OJ |
388 | /* Re-enable packet count interrupts: finally |
389 | * ack the packet count interrupt we got in rx_intr. | |
390 | */ | |
391 | ||
52a94351 | 392 | pcnt = *mac->rx_status & PAS_STATUS_PCNT_M; |
1b0335ea | 393 | |
52a94351 | 394 | reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC; |
1b0335ea OJ |
395 | |
396 | pci_write_config_dword(mac->iob_pdev, | |
397 | PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), | |
398 | reg); | |
399 | } | |
400 | ||
401 | static void pasemi_mac_restart_tx_intr(struct pasemi_mac *mac) | |
402 | { | |
52a94351 | 403 | unsigned int reg, pcnt; |
1b0335ea OJ |
404 | |
405 | /* Re-enable packet count interrupts */ | |
52a94351 | 406 | pcnt = *mac->tx_status & PAS_STATUS_PCNT_M; |
1b0335ea | 407 | |
52a94351 | 408 | reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC; |
1b0335ea OJ |
409 | |
410 | pci_write_config_dword(mac->iob_pdev, | |
411 | PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), reg); | |
412 | } | |
413 | ||
414 | ||
f5cd7872 OJ |
415 | static int pasemi_mac_clean_rx(struct pasemi_mac *mac, int limit) |
416 | { | |
cd4ceb24 OJ |
417 | unsigned int n; |
418 | int count; | |
419 | struct pas_dma_xct_descr *dp; | |
420 | struct pasemi_mac_buffer *info; | |
421 | struct sk_buff *skb; | |
422 | unsigned int i, len; | |
423 | u64 macrx; | |
424 | dma_addr_t dma; | |
f5cd7872 OJ |
425 | |
426 | spin_lock(&mac->rx->lock); | |
427 | ||
cd4ceb24 | 428 | n = mac->rx->next_to_clean; |
f5cd7872 | 429 | |
cd4ceb24 | 430 | for (count = limit; count; count--) { |
f5cd7872 OJ |
431 | |
432 | rmb(); | |
433 | ||
cd4ceb24 OJ |
434 | dp = &RX_DESC(mac, n); |
435 | macrx = dp->macrx; | |
f5cd7872 | 436 | |
cd4ceb24 | 437 | if (!(macrx & XCT_MACRX_O)) |
f5cd7872 OJ |
438 | break; |
439 | ||
f5cd7872 OJ |
440 | |
441 | info = NULL; | |
442 | ||
443 | /* We have to scan for our skb since there's no way | |
444 | * to back-map them from the descriptor, and if we | |
445 | * have several receive channels then they might not | |
446 | * show up in the same order as they were put on the | |
447 | * interface ring. | |
448 | */ | |
449 | ||
450 | dma = (dp->ptr & XCT_PTR_ADDR_M); | |
cd4ceb24 OJ |
451 | for (i = n; i < (n + RX_RING_SIZE); i++) { |
452 | info = &RX_DESC_INFO(mac, i); | |
f5cd7872 OJ |
453 | if (info->dma == dma) |
454 | break; | |
455 | } | |
456 | ||
9f05cfe2 | 457 | skb = info->skb; |
cd4ceb24 | 458 | info->dma = 0; |
f5cd7872 | 459 | |
cd4ceb24 | 460 | pci_unmap_single(mac->dma_pdev, dma, skb->len, |
f5cd7872 OJ |
461 | PCI_DMA_FROMDEVICE); |
462 | ||
cd4ceb24 | 463 | len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S; |
f5cd7872 | 464 | |
9f05cfe2 OJ |
465 | if (len < 256) { |
466 | struct sk_buff *new_skb = | |
467 | netdev_alloc_skb(mac->netdev, len + NET_IP_ALIGN); | |
468 | if (new_skb) { | |
469 | skb_reserve(new_skb, NET_IP_ALIGN); | |
470 | memcpy(new_skb->data - NET_IP_ALIGN, | |
471 | skb->data - NET_IP_ALIGN, | |
472 | len + NET_IP_ALIGN); | |
473 | /* save the skb in buffer_info as good */ | |
474 | skb = new_skb; | |
475 | } | |
476 | /* else just continue with the old one */ | |
477 | } else | |
478 | info->skb = NULL; | |
f5cd7872 OJ |
479 | |
480 | skb_put(skb, len); | |
481 | ||
482 | skb->protocol = eth_type_trans(skb, mac->netdev); | |
483 | ||
cd4ceb24 | 484 | if ((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK) { |
f5cd7872 | 485 | skb->ip_summed = CHECKSUM_COMPLETE; |
cd4ceb24 | 486 | skb->csum = (macrx & XCT_MACRX_CSUM_M) >> |
f5cd7872 OJ |
487 | XCT_MACRX_CSUM_S; |
488 | } else | |
489 | skb->ip_summed = CHECKSUM_NONE; | |
490 | ||
491 | mac->stats.rx_bytes += len; | |
492 | mac->stats.rx_packets++; | |
493 | ||
494 | netif_receive_skb(skb); | |
495 | ||
f5cd7872 OJ |
496 | dp->ptr = 0; |
497 | dp->macrx = 0; | |
cd4ceb24 OJ |
498 | |
499 | n++; | |
f5cd7872 OJ |
500 | } |
501 | ||
cd4ceb24 | 502 | mac->rx->next_to_clean += limit - count; |
f5cd7872 OJ |
503 | pasemi_mac_replenish_rx_ring(mac->netdev); |
504 | ||
505 | spin_unlock(&mac->rx->lock); | |
506 | ||
507 | return count; | |
508 | } | |
509 | ||
510 | static int pasemi_mac_clean_tx(struct pasemi_mac *mac) | |
511 | { | |
512 | int i; | |
513 | struct pasemi_mac_buffer *info; | |
514 | struct pas_dma_xct_descr *dp; | |
515 | int start, count; | |
516 | int flags; | |
517 | ||
518 | spin_lock_irqsave(&mac->tx->lock, flags); | |
519 | ||
520 | start = mac->tx->next_to_clean; | |
521 | count = 0; | |
522 | ||
523 | for (i = start; i < mac->tx->next_to_use; i++) { | |
524 | dp = &TX_DESC(mac, i); | |
525 | if (!dp || (dp->mactx & XCT_MACTX_O)) | |
526 | break; | |
527 | ||
528 | count++; | |
529 | ||
530 | info = &TX_DESC_INFO(mac, i); | |
531 | ||
532 | pci_unmap_single(mac->dma_pdev, info->dma, | |
533 | info->skb->len, PCI_DMA_TODEVICE); | |
534 | dev_kfree_skb_irq(info->skb); | |
535 | ||
536 | info->skb = NULL; | |
537 | info->dma = 0; | |
538 | dp->mactx = 0; | |
539 | dp->ptr = 0; | |
540 | } | |
541 | mac->tx->next_to_clean += count; | |
542 | spin_unlock_irqrestore(&mac->tx->lock, flags); | |
543 | ||
0ce68c74 OJ |
544 | netif_wake_queue(mac->netdev); |
545 | ||
f5cd7872 OJ |
546 | return count; |
547 | } | |
548 | ||
549 | ||
550 | static irqreturn_t pasemi_mac_rx_intr(int irq, void *data) | |
551 | { | |
552 | struct net_device *dev = data; | |
553 | struct pasemi_mac *mac = netdev_priv(dev); | |
554 | unsigned int reg; | |
555 | ||
6dfa7522 | 556 | if (!(*mac->rx_status & PAS_STATUS_CAUSE_M)) |
f5cd7872 OJ |
557 | return IRQ_NONE; |
558 | ||
6dfa7522 OJ |
559 | if (*mac->rx_status & PAS_STATUS_ERROR) |
560 | printk("rx_status reported error\n"); | |
561 | ||
562 | /* Don't reset packet count so it won't fire again but clear | |
563 | * all others. | |
564 | */ | |
565 | ||
566 | pci_read_config_dword(mac->dma_pdev, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), ®); | |
f5cd7872 | 567 | |
6dfa7522 OJ |
568 | reg = 0; |
569 | if (*mac->rx_status & PAS_STATUS_SOFT) | |
570 | reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; | |
571 | if (*mac->rx_status & PAS_STATUS_ERROR) | |
572 | reg |= PAS_IOB_DMA_RXCH_RESET_DINTC; | |
f5cd7872 OJ |
573 | if (*mac->rx_status & PAS_STATUS_TIMER) |
574 | reg |= PAS_IOB_DMA_RXCH_RESET_TINTC; | |
575 | ||
6dfa7522 OJ |
576 | netif_rx_schedule(dev); |
577 | ||
f5cd7872 OJ |
578 | pci_write_config_dword(mac->iob_pdev, |
579 | PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg); | |
580 | ||
581 | ||
582 | return IRQ_HANDLED; | |
583 | } | |
584 | ||
585 | static irqreturn_t pasemi_mac_tx_intr(int irq, void *data) | |
586 | { | |
587 | struct net_device *dev = data; | |
588 | struct pasemi_mac *mac = netdev_priv(dev); | |
52a94351 | 589 | unsigned int reg, pcnt; |
f5cd7872 | 590 | |
6dfa7522 | 591 | if (!(*mac->tx_status & PAS_STATUS_CAUSE_M)) |
f5cd7872 OJ |
592 | return IRQ_NONE; |
593 | ||
594 | pasemi_mac_clean_tx(mac); | |
595 | ||
52a94351 OJ |
596 | pcnt = *mac->tx_status & PAS_STATUS_PCNT_M; |
597 | ||
598 | reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC; | |
6dfa7522 OJ |
599 | |
600 | if (*mac->tx_status & PAS_STATUS_SOFT) | |
601 | reg |= PAS_IOB_DMA_TXCH_RESET_SINTC; | |
602 | if (*mac->tx_status & PAS_STATUS_ERROR) | |
603 | reg |= PAS_IOB_DMA_TXCH_RESET_DINTC; | |
f5cd7872 | 604 | |
52a94351 OJ |
605 | pci_write_config_dword(mac->iob_pdev, |
606 | PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), | |
f5cd7872 OJ |
607 | reg); |
608 | ||
f5cd7872 OJ |
609 | return IRQ_HANDLED; |
610 | } | |
611 | ||
bb6e9590 OJ |
612 | static void pasemi_adjust_link(struct net_device *dev) |
613 | { | |
614 | struct pasemi_mac *mac = netdev_priv(dev); | |
615 | int msg; | |
616 | unsigned int flags; | |
617 | unsigned int new_flags; | |
618 | ||
619 | if (!mac->phydev->link) { | |
620 | /* If no link, MAC speed settings don't matter. Just report | |
621 | * link down and return. | |
622 | */ | |
623 | if (mac->link && netif_msg_link(mac)) | |
624 | printk(KERN_INFO "%s: Link is down.\n", dev->name); | |
625 | ||
626 | netif_carrier_off(dev); | |
627 | mac->link = 0; | |
628 | ||
629 | return; | |
630 | } else | |
631 | netif_carrier_on(dev); | |
632 | ||
633 | pci_read_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, &flags); | |
634 | new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M | | |
635 | PAS_MAC_CFG_PCFG_TSR_M); | |
636 | ||
637 | if (!mac->phydev->duplex) | |
638 | new_flags |= PAS_MAC_CFG_PCFG_HD; | |
639 | ||
640 | switch (mac->phydev->speed) { | |
641 | case 1000: | |
642 | new_flags |= PAS_MAC_CFG_PCFG_SPD_1G | | |
643 | PAS_MAC_CFG_PCFG_TSR_1G; | |
644 | break; | |
645 | case 100: | |
646 | new_flags |= PAS_MAC_CFG_PCFG_SPD_100M | | |
647 | PAS_MAC_CFG_PCFG_TSR_100M; | |
648 | break; | |
649 | case 10: | |
650 | new_flags |= PAS_MAC_CFG_PCFG_SPD_10M | | |
651 | PAS_MAC_CFG_PCFG_TSR_10M; | |
652 | break; | |
653 | default: | |
654 | printk("Unsupported speed %d\n", mac->phydev->speed); | |
655 | } | |
656 | ||
657 | /* Print on link or speed/duplex change */ | |
658 | msg = mac->link != mac->phydev->link || flags != new_flags; | |
659 | ||
660 | mac->duplex = mac->phydev->duplex; | |
661 | mac->speed = mac->phydev->speed; | |
662 | mac->link = mac->phydev->link; | |
663 | ||
664 | if (new_flags != flags) | |
665 | pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, new_flags); | |
666 | ||
667 | if (msg && netif_msg_link(mac)) | |
668 | printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n", | |
669 | dev->name, mac->speed, mac->duplex ? "full" : "half"); | |
670 | } | |
671 | ||
672 | static int pasemi_mac_phy_init(struct net_device *dev) | |
673 | { | |
674 | struct pasemi_mac *mac = netdev_priv(dev); | |
675 | struct device_node *dn, *phy_dn; | |
676 | struct phy_device *phydev; | |
677 | unsigned int phy_id; | |
678 | const phandle *ph; | |
679 | const unsigned int *prop; | |
680 | struct resource r; | |
681 | int ret; | |
682 | ||
683 | dn = pci_device_to_OF_node(mac->pdev); | |
9028780a | 684 | ph = of_get_property(dn, "phy-handle", NULL); |
bb6e9590 OJ |
685 | if (!ph) |
686 | return -ENODEV; | |
687 | phy_dn = of_find_node_by_phandle(*ph); | |
688 | ||
9028780a | 689 | prop = of_get_property(phy_dn, "reg", NULL); |
bb6e9590 OJ |
690 | ret = of_address_to_resource(phy_dn->parent, 0, &r); |
691 | if (ret) | |
692 | goto err; | |
693 | ||
694 | phy_id = *prop; | |
695 | snprintf(mac->phy_id, BUS_ID_SIZE, PHY_ID_FMT, (int)r.start, phy_id); | |
696 | ||
697 | of_node_put(phy_dn); | |
698 | ||
699 | mac->link = 0; | |
700 | mac->speed = 0; | |
701 | mac->duplex = -1; | |
702 | ||
703 | phydev = phy_connect(dev, mac->phy_id, &pasemi_adjust_link, 0, PHY_INTERFACE_MODE_SGMII); | |
704 | ||
705 | if (IS_ERR(phydev)) { | |
706 | printk(KERN_ERR "%s: Could not attach to phy\n", dev->name); | |
707 | return PTR_ERR(phydev); | |
708 | } | |
709 | ||
710 | mac->phydev = phydev; | |
711 | ||
712 | return 0; | |
713 | ||
714 | err: | |
715 | of_node_put(phy_dn); | |
716 | return -ENODEV; | |
717 | } | |
718 | ||
719 | ||
f5cd7872 OJ |
720 | static int pasemi_mac_open(struct net_device *dev) |
721 | { | |
722 | struct pasemi_mac *mac = netdev_priv(dev); | |
771f7404 | 723 | int base_irq; |
f5cd7872 OJ |
724 | unsigned int flags; |
725 | int ret; | |
726 | ||
727 | /* enable rx section */ | |
728 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_COM_RXCMD, | |
729 | PAS_DMA_COM_RXCMD_EN); | |
730 | ||
731 | /* enable tx section */ | |
732 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_COM_TXCMD, | |
733 | PAS_DMA_COM_TXCMD_EN); | |
734 | ||
735 | flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) | | |
736 | PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) | | |
737 | PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12); | |
738 | ||
739 | pci_write_config_dword(mac->pdev, PAS_MAC_CFG_TXP, flags); | |
740 | ||
741 | flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PE | | |
742 | PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE; | |
743 | ||
744 | flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G; | |
745 | ||
746 | pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_RXCH_CFG(mac->dma_rxch), | |
6dfa7522 | 747 | PAS_IOB_DMA_RXCH_CFG_CNTTH(1)); |
f5cd7872 | 748 | |
6dfa7522 OJ |
749 | pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_TXCH_CFG(mac->dma_txch), |
750 | PAS_IOB_DMA_TXCH_CFG_CNTTH(32)); | |
f5cd7872 | 751 | |
1b0335ea OJ |
752 | /* Clear out any residual packet count state from firmware */ |
753 | pasemi_mac_restart_rx_intr(mac); | |
754 | pasemi_mac_restart_tx_intr(mac); | |
755 | ||
6dfa7522 | 756 | /* 0xffffff is max value, about 16ms */ |
f5cd7872 | 757 | pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_COM_TIMEOUTCFG, |
6dfa7522 | 758 | PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0xffffff)); |
f5cd7872 OJ |
759 | |
760 | pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, flags); | |
761 | ||
762 | ret = pasemi_mac_setup_rx_resources(dev); | |
763 | if (ret) | |
764 | goto out_rx_resources; | |
765 | ||
766 | ret = pasemi_mac_setup_tx_resources(dev); | |
767 | if (ret) | |
768 | goto out_tx_resources; | |
769 | ||
770 | pci_write_config_dword(mac->pdev, PAS_MAC_IPC_CHNL, | |
771 | PAS_MAC_IPC_CHNL_DCHNO(mac->dma_rxch) | | |
772 | PAS_MAC_IPC_CHNL_BCH(mac->dma_rxch)); | |
773 | ||
774 | /* enable rx if */ | |
775 | pci_write_config_dword(mac->dma_pdev, | |
776 | PAS_DMA_RXINT_RCMDSTA(mac->dma_if), | |
777 | PAS_DMA_RXINT_RCMDSTA_EN); | |
778 | ||
779 | /* enable rx channel */ | |
780 | pci_write_config_dword(mac->dma_pdev, | |
781 | PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), | |
782 | PAS_DMA_RXCHAN_CCMDSTA_EN | | |
783 | PAS_DMA_RXCHAN_CCMDSTA_DU); | |
784 | ||
785 | /* enable tx channel */ | |
786 | pci_write_config_dword(mac->dma_pdev, | |
787 | PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), | |
788 | PAS_DMA_TXCHAN_TCMDSTA_EN); | |
789 | ||
790 | pasemi_mac_replenish_rx_ring(dev); | |
791 | ||
bb6e9590 OJ |
792 | ret = pasemi_mac_phy_init(dev); |
793 | /* Some configs don't have PHYs (XAUI etc), so don't complain about | |
794 | * failed init due to -ENODEV. | |
795 | */ | |
796 | if (ret && ret != -ENODEV) | |
797 | dev_warn(&mac->pdev->dev, "phy init failed: %d\n", ret); | |
798 | ||
f5cd7872 OJ |
799 | netif_start_queue(dev); |
800 | netif_poll_enable(dev); | |
801 | ||
771f7404 OJ |
802 | /* Interrupts are a bit different for our DMA controller: While |
803 | * it's got one a regular PCI device header, the interrupt there | |
804 | * is really the base of the range it's using. Each tx and rx | |
805 | * channel has it's own interrupt source. | |
806 | */ | |
807 | ||
808 | base_irq = virq_to_hw(mac->dma_pdev->irq); | |
809 | ||
810 | mac->tx_irq = irq_create_mapping(NULL, base_irq + mac->dma_txch); | |
811 | mac->rx_irq = irq_create_mapping(NULL, base_irq + 20 + mac->dma_txch); | |
812 | ||
813 | ret = request_irq(mac->tx_irq, &pasemi_mac_tx_intr, IRQF_DISABLED, | |
f5cd7872 OJ |
814 | mac->tx->irq_name, dev); |
815 | if (ret) { | |
816 | dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", | |
771f7404 | 817 | base_irq + mac->dma_txch, ret); |
f5cd7872 OJ |
818 | goto out_tx_int; |
819 | } | |
820 | ||
771f7404 | 821 | ret = request_irq(mac->rx_irq, &pasemi_mac_rx_intr, IRQF_DISABLED, |
f5cd7872 OJ |
822 | mac->rx->irq_name, dev); |
823 | if (ret) { | |
824 | dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", | |
771f7404 | 825 | base_irq + 20 + mac->dma_rxch, ret); |
f5cd7872 OJ |
826 | goto out_rx_int; |
827 | } | |
828 | ||
bb6e9590 OJ |
829 | if (mac->phydev) |
830 | phy_start(mac->phydev); | |
831 | ||
f5cd7872 OJ |
832 | return 0; |
833 | ||
834 | out_rx_int: | |
771f7404 | 835 | free_irq(mac->tx_irq, dev); |
f5cd7872 OJ |
836 | out_tx_int: |
837 | netif_poll_disable(dev); | |
838 | netif_stop_queue(dev); | |
839 | pasemi_mac_free_tx_resources(dev); | |
840 | out_tx_resources: | |
841 | pasemi_mac_free_rx_resources(dev); | |
842 | out_rx_resources: | |
843 | ||
844 | return ret; | |
845 | } | |
846 | ||
847 | #define MAX_RETRIES 5000 | |
848 | ||
849 | static int pasemi_mac_close(struct net_device *dev) | |
850 | { | |
851 | struct pasemi_mac *mac = netdev_priv(dev); | |
852 | unsigned int stat; | |
853 | int retries; | |
854 | ||
bb6e9590 OJ |
855 | if (mac->phydev) { |
856 | phy_stop(mac->phydev); | |
857 | phy_disconnect(mac->phydev); | |
858 | } | |
859 | ||
f5cd7872 OJ |
860 | netif_stop_queue(dev); |
861 | ||
862 | /* Clean out any pending buffers */ | |
863 | pasemi_mac_clean_tx(mac); | |
864 | pasemi_mac_clean_rx(mac, RX_RING_SIZE); | |
865 | ||
866 | /* Disable interface */ | |
867 | pci_write_config_dword(mac->dma_pdev, | |
868 | PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), | |
869 | PAS_DMA_TXCHAN_TCMDSTA_ST); | |
870 | pci_write_config_dword(mac->dma_pdev, | |
871 | PAS_DMA_RXINT_RCMDSTA(mac->dma_if), | |
872 | PAS_DMA_RXINT_RCMDSTA_ST); | |
873 | pci_write_config_dword(mac->dma_pdev, | |
874 | PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), | |
875 | PAS_DMA_RXCHAN_CCMDSTA_ST); | |
876 | ||
877 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
878 | pci_read_config_dword(mac->dma_pdev, | |
879 | PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), | |
880 | &stat); | |
0ce68c74 | 881 | if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)) |
f5cd7872 OJ |
882 | break; |
883 | cond_resched(); | |
884 | } | |
885 | ||
0ce68c74 | 886 | if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT) |
f5cd7872 | 887 | dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n"); |
f5cd7872 OJ |
888 | |
889 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
890 | pci_read_config_dword(mac->dma_pdev, | |
891 | PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), | |
892 | &stat); | |
0ce68c74 | 893 | if (!(stat & PAS_DMA_RXCHAN_CCMDSTA_ACT)) |
f5cd7872 OJ |
894 | break; |
895 | cond_resched(); | |
896 | } | |
897 | ||
0ce68c74 | 898 | if (stat & PAS_DMA_RXCHAN_CCMDSTA_ACT) |
f5cd7872 | 899 | dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n"); |
f5cd7872 OJ |
900 | |
901 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
902 | pci_read_config_dword(mac->dma_pdev, | |
903 | PAS_DMA_RXINT_RCMDSTA(mac->dma_if), | |
904 | &stat); | |
0ce68c74 | 905 | if (!(stat & PAS_DMA_RXINT_RCMDSTA_ACT)) |
f5cd7872 OJ |
906 | break; |
907 | cond_resched(); | |
908 | } | |
909 | ||
0ce68c74 | 910 | if (stat & PAS_DMA_RXINT_RCMDSTA_ACT) |
f5cd7872 | 911 | dev_err(&mac->dma_pdev->dev, "Failed to stop rx interface\n"); |
f5cd7872 OJ |
912 | |
913 | /* Then, disable the channel. This must be done separately from | |
914 | * stopping, since you can't disable when active. | |
915 | */ | |
916 | ||
917 | pci_write_config_dword(mac->dma_pdev, | |
918 | PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), 0); | |
919 | pci_write_config_dword(mac->dma_pdev, | |
920 | PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), 0); | |
921 | pci_write_config_dword(mac->dma_pdev, | |
922 | PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0); | |
923 | ||
771f7404 OJ |
924 | free_irq(mac->tx_irq, dev); |
925 | free_irq(mac->rx_irq, dev); | |
f5cd7872 OJ |
926 | |
927 | /* Free resources */ | |
928 | pasemi_mac_free_rx_resources(dev); | |
929 | pasemi_mac_free_tx_resources(dev); | |
930 | ||
931 | return 0; | |
932 | } | |
933 | ||
934 | static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev) | |
935 | { | |
936 | struct pasemi_mac *mac = netdev_priv(dev); | |
937 | struct pasemi_mac_txring *txring; | |
938 | struct pasemi_mac_buffer *info; | |
939 | struct pas_dma_xct_descr *dp; | |
940 | u64 dflags; | |
941 | dma_addr_t map; | |
942 | int flags; | |
943 | ||
944 | dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_SS | XCT_MACTX_CRC_PAD; | |
945 | ||
946 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
d56f90a7 ACM |
947 | const unsigned char *nh = skb_network_header(skb); |
948 | ||
eddc9ec5 | 949 | switch (ip_hdr(skb)->protocol) { |
f5cd7872 OJ |
950 | case IPPROTO_TCP: |
951 | dflags |= XCT_MACTX_CSUM_TCP; | |
cfe1fc77 | 952 | dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2); |
d56f90a7 | 953 | dflags |= XCT_MACTX_IPO(nh - skb->data); |
f5cd7872 OJ |
954 | break; |
955 | case IPPROTO_UDP: | |
956 | dflags |= XCT_MACTX_CSUM_UDP; | |
cfe1fc77 | 957 | dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2); |
d56f90a7 | 958 | dflags |= XCT_MACTX_IPO(nh - skb->data); |
f5cd7872 OJ |
959 | break; |
960 | } | |
961 | } | |
962 | ||
963 | map = pci_map_single(mac->dma_pdev, skb->data, skb->len, PCI_DMA_TODEVICE); | |
964 | ||
965 | if (dma_mapping_error(map)) | |
966 | return NETDEV_TX_BUSY; | |
967 | ||
968 | txring = mac->tx; | |
969 | ||
970 | spin_lock_irqsave(&txring->lock, flags); | |
971 | ||
972 | if (txring->next_to_clean - txring->next_to_use == TX_RING_SIZE) { | |
973 | spin_unlock_irqrestore(&txring->lock, flags); | |
974 | pasemi_mac_clean_tx(mac); | |
52a94351 | 975 | pasemi_mac_restart_tx_intr(mac); |
f5cd7872 OJ |
976 | spin_lock_irqsave(&txring->lock, flags); |
977 | ||
978 | if (txring->next_to_clean - txring->next_to_use == | |
979 | TX_RING_SIZE) { | |
980 | /* Still no room -- stop the queue and wait for tx | |
981 | * intr when there's room. | |
982 | */ | |
983 | netif_stop_queue(dev); | |
984 | goto out_err; | |
985 | } | |
986 | } | |
987 | ||
988 | ||
989 | dp = &TX_DESC(mac, txring->next_to_use); | |
990 | info = &TX_DESC_INFO(mac, txring->next_to_use); | |
991 | ||
992 | dp->mactx = dflags | XCT_MACTX_LLEN(skb->len); | |
993 | dp->ptr = XCT_PTR_LEN(skb->len) | XCT_PTR_ADDR(map); | |
994 | info->dma = map; | |
995 | info->skb = skb; | |
996 | ||
997 | txring->next_to_use++; | |
998 | mac->stats.tx_packets++; | |
999 | mac->stats.tx_bytes += skb->len; | |
1000 | ||
1001 | spin_unlock_irqrestore(&txring->lock, flags); | |
1002 | ||
1003 | pci_write_config_dword(mac->dma_pdev, | |
1004 | PAS_DMA_TXCHAN_INCR(mac->dma_txch), 1); | |
1005 | ||
1006 | return NETDEV_TX_OK; | |
1007 | ||
1008 | out_err: | |
1009 | spin_unlock_irqrestore(&txring->lock, flags); | |
1010 | pci_unmap_single(mac->dma_pdev, map, skb->len, PCI_DMA_TODEVICE); | |
1011 | return NETDEV_TX_BUSY; | |
1012 | } | |
1013 | ||
1014 | static struct net_device_stats *pasemi_mac_get_stats(struct net_device *dev) | |
1015 | { | |
1016 | struct pasemi_mac *mac = netdev_priv(dev); | |
1017 | ||
1018 | return &mac->stats; | |
1019 | } | |
1020 | ||
ceb51361 | 1021 | |
f5cd7872 OJ |
1022 | static void pasemi_mac_set_rx_mode(struct net_device *dev) |
1023 | { | |
1024 | struct pasemi_mac *mac = netdev_priv(dev); | |
1025 | unsigned int flags; | |
1026 | ||
1027 | pci_read_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, &flags); | |
1028 | ||
1029 | /* Set promiscuous */ | |
1030 | if (dev->flags & IFF_PROMISC) | |
1031 | flags |= PAS_MAC_CFG_PCFG_PR; | |
1032 | else | |
1033 | flags &= ~PAS_MAC_CFG_PCFG_PR; | |
1034 | ||
1035 | pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, flags); | |
1036 | } | |
1037 | ||
1038 | ||
1039 | static int pasemi_mac_poll(struct net_device *dev, int *budget) | |
1040 | { | |
1041 | int pkts, limit = min(*budget, dev->quota); | |
1042 | struct pasemi_mac *mac = netdev_priv(dev); | |
1043 | ||
1044 | pkts = pasemi_mac_clean_rx(mac, limit); | |
1045 | ||
cd4ceb24 OJ |
1046 | dev->quota -= pkts; |
1047 | *budget -= pkts; | |
1048 | ||
f5cd7872 OJ |
1049 | if (pkts < limit) { |
1050 | /* all done, no more packets present */ | |
1051 | netif_rx_complete(dev); | |
1052 | ||
1b0335ea | 1053 | pasemi_mac_restart_rx_intr(mac); |
f5cd7872 OJ |
1054 | return 0; |
1055 | } else { | |
1056 | /* used up our quantum, so reschedule */ | |
f5cd7872 OJ |
1057 | return 1; |
1058 | } | |
1059 | } | |
1060 | ||
1061 | static int __devinit | |
1062 | pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
1063 | { | |
1064 | static int index = 0; | |
1065 | struct net_device *dev; | |
1066 | struct pasemi_mac *mac; | |
1067 | int err; | |
1068 | ||
1069 | err = pci_enable_device(pdev); | |
1070 | if (err) | |
1071 | return err; | |
1072 | ||
1073 | dev = alloc_etherdev(sizeof(struct pasemi_mac)); | |
1074 | if (dev == NULL) { | |
1075 | dev_err(&pdev->dev, | |
1076 | "pasemi_mac: Could not allocate ethernet device.\n"); | |
1077 | err = -ENOMEM; | |
1078 | goto out_disable_device; | |
1079 | } | |
1080 | ||
1081 | SET_MODULE_OWNER(dev); | |
1082 | pci_set_drvdata(pdev, dev); | |
1083 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1084 | ||
1085 | mac = netdev_priv(dev); | |
1086 | ||
1087 | mac->pdev = pdev; | |
1088 | mac->netdev = dev; | |
1089 | mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL); | |
1090 | ||
1091 | if (!mac->dma_pdev) { | |
1092 | dev_err(&pdev->dev, "Can't find DMA Controller\n"); | |
1093 | err = -ENODEV; | |
1094 | goto out_free_netdev; | |
1095 | } | |
1096 | ||
1097 | mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); | |
1098 | ||
1099 | if (!mac->iob_pdev) { | |
1100 | dev_err(&pdev->dev, "Can't find I/O Bridge\n"); | |
1101 | err = -ENODEV; | |
1102 | goto out_put_dma_pdev; | |
1103 | } | |
1104 | ||
1105 | /* These should come out of the device tree eventually */ | |
1106 | mac->dma_txch = index; | |
1107 | mac->dma_rxch = index; | |
1108 | ||
1109 | /* We probe GMAC before XAUI, but the DMA interfaces are | |
1110 | * in XAUI, GMAC order. | |
1111 | */ | |
1112 | if (index < 4) | |
1113 | mac->dma_if = index + 2; | |
1114 | else | |
1115 | mac->dma_if = index - 4; | |
1116 | index++; | |
1117 | ||
1118 | switch (pdev->device) { | |
1119 | case 0xa005: | |
1120 | mac->type = MAC_TYPE_GMAC; | |
1121 | break; | |
1122 | case 0xa006: | |
1123 | mac->type = MAC_TYPE_XAUI; | |
1124 | break; | |
1125 | default: | |
1126 | err = -ENODEV; | |
1127 | goto out; | |
1128 | } | |
1129 | ||
1130 | /* get mac addr from device tree */ | |
1131 | if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) { | |
1132 | err = -ENODEV; | |
1133 | goto out; | |
1134 | } | |
1135 | memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr)); | |
1136 | ||
1137 | dev->open = pasemi_mac_open; | |
1138 | dev->stop = pasemi_mac_close; | |
1139 | dev->hard_start_xmit = pasemi_mac_start_tx; | |
1140 | dev->get_stats = pasemi_mac_get_stats; | |
1141 | dev->set_multicast_list = pasemi_mac_set_rx_mode; | |
1142 | dev->weight = 64; | |
1143 | dev->poll = pasemi_mac_poll; | |
1144 | dev->features = NETIF_F_HW_CSUM; | |
1145 | ||
1146 | /* The dma status structure is located in the I/O bridge, and | |
1147 | * is cache coherent. | |
1148 | */ | |
1149 | if (!dma_status) | |
1150 | /* XXXOJN This should come from the device tree */ | |
1151 | dma_status = __ioremap(0xfd800000, 0x1000, 0); | |
1152 | ||
1153 | mac->rx_status = &dma_status->rx_sta[mac->dma_rxch]; | |
1154 | mac->tx_status = &dma_status->tx_sta[mac->dma_txch]; | |
1155 | ||
ceb51361 OJ |
1156 | mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
1157 | ||
bb6e9590 OJ |
1158 | /* Enable most messages by default */ |
1159 | mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
1160 | ||
f5cd7872 OJ |
1161 | err = register_netdev(dev); |
1162 | ||
1163 | if (err) { | |
1164 | dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n", | |
1165 | err); | |
1166 | goto out; | |
1167 | } else | |
1168 | printk(KERN_INFO "%s: PA Semi %s: intf %d, txch %d, rxch %d, " | |
1169 | "hw addr %02x:%02x:%02x:%02x:%02x:%02x\n", | |
1170 | dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI", | |
1171 | mac->dma_if, mac->dma_txch, mac->dma_rxch, | |
1172 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | |
1173 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | |
1174 | ||
1175 | return err; | |
1176 | ||
1177 | out: | |
1178 | pci_dev_put(mac->iob_pdev); | |
1179 | out_put_dma_pdev: | |
1180 | pci_dev_put(mac->dma_pdev); | |
1181 | out_free_netdev: | |
1182 | free_netdev(dev); | |
1183 | out_disable_device: | |
1184 | pci_disable_device(pdev); | |
1185 | return err; | |
1186 | ||
1187 | } | |
1188 | ||
1189 | static void __devexit pasemi_mac_remove(struct pci_dev *pdev) | |
1190 | { | |
1191 | struct net_device *netdev = pci_get_drvdata(pdev); | |
1192 | struct pasemi_mac *mac; | |
1193 | ||
1194 | if (!netdev) | |
1195 | return; | |
1196 | ||
1197 | mac = netdev_priv(netdev); | |
1198 | ||
1199 | unregister_netdev(netdev); | |
1200 | ||
1201 | pci_disable_device(pdev); | |
1202 | pci_dev_put(mac->dma_pdev); | |
1203 | pci_dev_put(mac->iob_pdev); | |
1204 | ||
1205 | pci_set_drvdata(pdev, NULL); | |
1206 | free_netdev(netdev); | |
1207 | } | |
1208 | ||
1209 | static struct pci_device_id pasemi_mac_pci_tbl[] = { | |
1210 | { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) }, | |
1211 | { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) }, | |
1212 | }; | |
1213 | ||
1214 | MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl); | |
1215 | ||
1216 | static struct pci_driver pasemi_mac_driver = { | |
1217 | .name = "pasemi_mac", | |
1218 | .id_table = pasemi_mac_pci_tbl, | |
1219 | .probe = pasemi_mac_probe, | |
1220 | .remove = __devexit_p(pasemi_mac_remove), | |
1221 | }; | |
1222 | ||
1223 | static void __exit pasemi_mac_cleanup_module(void) | |
1224 | { | |
1225 | pci_unregister_driver(&pasemi_mac_driver); | |
1226 | __iounmap(dma_status); | |
1227 | dma_status = NULL; | |
1228 | } | |
1229 | ||
1230 | int pasemi_mac_init_module(void) | |
1231 | { | |
1232 | return pci_register_driver(&pasemi_mac_driver); | |
1233 | } | |
1234 | ||
f5cd7872 OJ |
1235 | module_init(pasemi_mac_init_module); |
1236 | module_exit(pasemi_mac_cleanup_module); |