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pasemi_mac: update todo list
[deliverable/linux.git] / drivers / net / pasemi_mac.c
CommitLineData
f5cd7872
OJ		 1/*
2 * Copyright (C) 2006-2007 PA Semi, Inc
3 *
4 * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/interrupt.h>
24#include <linux/dmaengine.h>
25#include <linux/delay.h>
26#include <linux/netdevice.h>
27#include <linux/etherdevice.h>
28#include <asm/dma-mapping.h>
29#include <linux/in.h>
30#include <linux/skbuff.h>
31
32#include <linux/ip.h>
33#include <linux/tcp.h>
34#include <net/checksum.h>
35
771f7404
OJ		 36#include <asm/irq.h>
37
f5cd7872
OJ		 38#include "pasemi_mac.h"
39
8dc121a4
OJ		 40/* We have our own align, since ppc64 in general has it at 0 because
41 * of design flaws in some of the server bridge chips. However, for
42 * PWRficient doing the unaligned copies is more expensive than doing
43 * unaligned DMA, so make sure the data is aligned instead.
44 */
45#define LOCAL_SKB_ALIGN 2
f5cd7872
OJ		 46
47/* TODO list
48 *
f5cd7872
OJ		 49 * - Multicast support
50 * - Large MTU support
7ddeae2c
OJ		 51 * - SW LRO
52 * - Multiqueue RX/TX
f5cd7872
OJ		 53 */
54
55
56/* Must be a power of two */
ad5da10a
OJ		 57#define RX_RING_SIZE 4096
58#define TX_RING_SIZE 4096
f5cd7872 59
ceb51361
OJ		 60#define DEFAULT_MSG_ENABLE \
61 (NETIF_MSG_DRV | \
62 NETIF_MSG_PROBE | \
63 NETIF_MSG_LINK | \
64 NETIF_MSG_TIMER | \
65 NETIF_MSG_IFDOWN | \
66 NETIF_MSG_IFUP | \
67 NETIF_MSG_RX_ERR | \
68 NETIF_MSG_TX_ERR)
69
fc9e4d2a
OJ		 70#define TX_RING(mac, num) ((mac)->tx->ring[(num) & (TX_RING_SIZE-1)])
71#define TX_RING_INFO(mac, num) ((mac)->tx->ring_info[(num) & (TX_RING_SIZE-1)])
72#define RX_RING(mac, num) ((mac)->rx->ring[(num) & (RX_RING_SIZE-1)])
73#define RX_RING_INFO(mac, num) ((mac)->rx->ring_info[(num) & (RX_RING_SIZE-1)])
f5cd7872
OJ		 74#define RX_BUFF(mac, num) ((mac)->rx->buffers[(num) & (RX_RING_SIZE-1)])
75
021fa22e
OJ		 76#define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \
77 & ((ring)->size - 1))
78#define RING_AVAIL(ring) ((ring->size) - RING_USED(ring))
79
f5cd7872
OJ		 80#define BUF_SIZE 1646 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
81
ceb51361
OJ		 82MODULE_LICENSE("GPL");
83MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
84MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
85
86static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */
87module_param(debug, int, 0);
88MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value");
f5cd7872
OJ		 89
90static struct pasdma_status *dma_status;
91
a85b9422
OJ		 92static void write_iob_reg(struct pasemi_mac *mac, unsigned int reg,
93 unsigned int val)
94{
b6e05a1b 95 out_le32(mac->iob_regs+reg, val);
a85b9422
OJ		 96}
97
98static unsigned int read_mac_reg(struct pasemi_mac *mac, unsigned int reg)
99{
b6e05a1b 100 return in_le32(mac->regs+reg);
a85b9422
OJ		 101}
102
103static void write_mac_reg(struct pasemi_mac *mac, unsigned int reg,
104 unsigned int val)
105{
b6e05a1b 106 out_le32(mac->regs+reg, val);
a85b9422
OJ		 107}
108
109static unsigned int read_dma_reg(struct pasemi_mac *mac, unsigned int reg)
110{
b6e05a1b 111 return in_le32(mac->dma_regs+reg);
a85b9422
OJ		 112}
113
114static void write_dma_reg(struct pasemi_mac *mac, unsigned int reg,
115 unsigned int val)
116{
b6e05a1b 117 out_le32(mac->dma_regs+reg, val);
a85b9422
OJ		 118}
119
f5cd7872
OJ		 120static int pasemi_get_mac_addr(struct pasemi_mac *mac)
121{
122 struct pci_dev *pdev = mac->pdev;
123 struct device_node *dn = pci_device_to_OF_node(pdev);
1af7f056 124 int len;
f5cd7872
OJ		 125 const u8 *maddr;
126 u8 addr[6];
127
128 if (!dn) {
129 dev_dbg(&pdev->dev,
130 "No device node for mac, not configuring\n");
131 return -ENOENT;
132 }
133
1af7f056 134 maddr = of_get_property(dn, "local-mac-address", &len);
135
136 if (maddr && len == 6) {
137 memcpy(mac->mac_addr, maddr, 6);
138 return 0;
139 }
140
141 /* Some old versions of firmware mistakenly uses mac-address
142 * (and as a string) instead of a byte array in local-mac-address.
143 */
a5fd22eb 144
a5fd22eb 145 if (maddr == NULL)
9028780a 146 maddr = of_get_property(dn, "mac-address", NULL);
a5fd22eb 147
f5cd7872
OJ		 148 if (maddr == NULL) {
149 dev_warn(&pdev->dev,
150 "no mac address in device tree, not configuring\n");
151 return -ENOENT;
152 }
153
1af7f056 154
f5cd7872
OJ		 155 if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0],
156 &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) {
157 dev_warn(&pdev->dev,
158 "can't parse mac address, not configuring\n");
159 return -EINVAL;
160 }
161
1af7f056 162 memcpy(mac->mac_addr, addr, 6);
163
f5cd7872
OJ		 164 return 0;
165}
166
ad3c20d1
OJ		 167static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac,
168 struct sk_buff *skb,
169 dma_addr_t *dmas)
170{
171 int f;
172 int nfrags = skb_shinfo(skb)->nr_frags;
173
174 pci_unmap_single(mac->dma_pdev, dmas[0], skb_headlen(skb),
175 PCI_DMA_TODEVICE);
176
177 for (f = 0; f < nfrags; f++) {
178 skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
179
180 pci_unmap_page(mac->dma_pdev, dmas[f+1], frag->size,
181 PCI_DMA_TODEVICE);
182 }
183 dev_kfree_skb_irq(skb);
184
185 /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs,
186 * aligned up to a power of 2
187 */
188 return (nfrags + 3) & ~1;
189}
190
f5cd7872
OJ		 191static int pasemi_mac_setup_rx_resources(struct net_device *dev)
192{
193 struct pasemi_mac_rxring *ring;
194 struct pasemi_mac *mac = netdev_priv(dev);
195 int chan_id = mac->dma_rxch;
196
197 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
198
199 if (!ring)
200 goto out_ring;
201
202 spin_lock_init(&ring->lock);
203
021fa22e 204 ring->size = RX_RING_SIZE;
fc9e4d2a 205 ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
f5cd7872
OJ		 206 RX_RING_SIZE, GFP_KERNEL);
207
fc9e4d2a
OJ		 208 if (!ring->ring_info)
209 goto out_ring_info;
f5cd7872
OJ		 210
211 /* Allocate descriptors */
fc9e4d2a
OJ		 212 ring->ring = dma_alloc_coherent(&mac->dma_pdev->dev,
213 RX_RING_SIZE * sizeof(u64),
f5cd7872
OJ		 214 &ring->dma, GFP_KERNEL);
215
fc9e4d2a
OJ		 216 if (!ring->ring)
217 goto out_ring_desc;
f5cd7872 218
fc9e4d2a 219 memset(ring->ring, 0, RX_RING_SIZE * sizeof(u64));
f5cd7872
OJ		 220
221 ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev,
222 RX_RING_SIZE * sizeof(u64),
223 &ring->buf_dma, GFP_KERNEL);
224 if (!ring->buffers)
225 goto out_buffers;
226
227 memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64));
228
a85b9422 229 write_dma_reg(mac, PAS_DMA_RXCHAN_BASEL(chan_id), PAS_DMA_RXCHAN_BASEL_BRBL(ring->dma));
f5cd7872 230
a85b9422
OJ		 231 write_dma_reg(mac, PAS_DMA_RXCHAN_BASEU(chan_id),
232 PAS_DMA_RXCHAN_BASEU_BRBH(ring->dma >> 32) |
fc9e4d2a 233 PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3));
f5cd7872 234
a85b9422 235 write_dma_reg(mac, PAS_DMA_RXCHAN_CFG(chan_id),
c0efd52b 236 PAS_DMA_RXCHAN_CFG_HBU(2));
f5cd7872 237
a85b9422
OJ		 238 write_dma_reg(mac, PAS_DMA_RXINT_BASEL(mac->dma_if),
239 PAS_DMA_RXINT_BASEL_BRBL(__pa(ring->buffers)));
f5cd7872 240
a85b9422
OJ		 241 write_dma_reg(mac, PAS_DMA_RXINT_BASEU(mac->dma_if),
242 PAS_DMA_RXINT_BASEU_BRBH(__pa(ring->buffers) >> 32) |
243 PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
f5cd7872 244
c0efd52b 245 write_dma_reg(mac, PAS_DMA_RXINT_CFG(mac->dma_if),
9a50bebd
OJ		 246 PAS_DMA_RXINT_CFG_DHL(3) |
247 PAS_DMA_RXINT_CFG_L2 |
248 PAS_DMA_RXINT_CFG_LW);
c0efd52b 249
f5cd7872
OJ		 250 ring->next_to_fill = 0;
251 ring->next_to_clean = 0;
252
253 snprintf(ring->irq_name, sizeof(ring->irq_name),
254 "%s rx", dev->name);
255 mac->rx = ring;
256
257 return 0;
258
259out_buffers:
260 dma_free_coherent(&mac->dma_pdev->dev,
fc9e4d2a
OJ		 261 RX_RING_SIZE * sizeof(u64),
262 mac->rx->ring, mac->rx->dma);
263out_ring_desc:
264 kfree(ring->ring_info);
265out_ring_info:
f5cd7872
OJ		 266 kfree(ring);
267out_ring:
268 return -ENOMEM;
269}
270
271
272static int pasemi_mac_setup_tx_resources(struct net_device *dev)
273{
274 struct pasemi_mac *mac = netdev_priv(dev);
275 u32 val;
276 int chan_id = mac->dma_txch;
277 struct pasemi_mac_txring *ring;
278
279 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
280 if (!ring)
281 goto out_ring;
282
283 spin_lock_init(&ring->lock);
284
021fa22e 285 ring->size = TX_RING_SIZE;
fc9e4d2a 286 ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
f5cd7872 287 TX_RING_SIZE, GFP_KERNEL);
fc9e4d2a
OJ		 288 if (!ring->ring_info)
289 goto out_ring_info;
f5cd7872
OJ		 290
291 /* Allocate descriptors */
fc9e4d2a
OJ		 292 ring->ring = dma_alloc_coherent(&mac->dma_pdev->dev,
293 TX_RING_SIZE * sizeof(u64),
f5cd7872 294 &ring->dma, GFP_KERNEL);
fc9e4d2a
OJ		 295 if (!ring->ring)
296 goto out_ring_desc;
f5cd7872 297
fc9e4d2a 298 memset(ring->ring, 0, TX_RING_SIZE * sizeof(u64));
f5cd7872 299
a85b9422
OJ		 300 write_dma_reg(mac, PAS_DMA_TXCHAN_BASEL(chan_id),
301 PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma));
f5cd7872 302 val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32);
fc9e4d2a 303 val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3);
f5cd7872 304
a85b9422 305 write_dma_reg(mac, PAS_DMA_TXCHAN_BASEU(chan_id), val);
f5cd7872 306
a85b9422
OJ		 307 write_dma_reg(mac, PAS_DMA_TXCHAN_CFG(chan_id),
308 PAS_DMA_TXCHAN_CFG_TY_IFACE |
309 PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
310 PAS_DMA_TXCHAN_CFG_UP |
311 PAS_DMA_TXCHAN_CFG_WT(2));
f5cd7872 312
021fa22e 313 ring->next_to_fill = 0;
f5cd7872
OJ		 314 ring->next_to_clean = 0;
315
316 snprintf(ring->irq_name, sizeof(ring->irq_name),
317 "%s tx", dev->name);
318 mac->tx = ring;
319
320 return 0;
321
fc9e4d2a
OJ		 322out_ring_desc:
323 kfree(ring->ring_info);
324out_ring_info:
f5cd7872
OJ		 325 kfree(ring);
326out_ring:
327 return -ENOMEM;
328}
329
330static void pasemi_mac_free_tx_resources(struct net_device *dev)
331{
332 struct pasemi_mac *mac = netdev_priv(dev);
ad3c20d1 333 unsigned int i, j;
f5cd7872 334 struct pasemi_mac_buffer *info;
ad3c20d1
OJ		 335 dma_addr_t dmas[MAX_SKB_FRAGS+1];
336 int freed;
ad5da10a 337 int start, limit;
fc9e4d2a 338
ad5da10a
OJ		 339 start = mac->tx->next_to_clean;
340 limit = mac->tx->next_to_fill;
341
342 /* Compensate for when fill has wrapped and clean has not */
343 if (start > limit)
344 limit += TX_RING_SIZE;
345
346 for (i = start; i < limit; i += freed) {
fc9e4d2a
OJ		 347 info = &TX_RING_INFO(mac, i+1);
348 if (info->dma && info->skb) {
ad3c20d1
OJ		 349 for (j = 0; j <= skb_shinfo(info->skb)->nr_frags; j++)
350 dmas[j] = TX_RING_INFO(mac, i+1+j).dma;
351 freed = pasemi_mac_unmap_tx_skb(mac, info->skb, dmas);
352 } else
353 freed = 2;
f5cd7872
OJ		 354 }
355
ad3c20d1
OJ		 356 for (i = 0; i < TX_RING_SIZE; i++)
357 TX_RING(mac, i) = 0;
358
f5cd7872 359 dma_free_coherent(&mac->dma_pdev->dev,
fc9e4d2a
OJ		 360 TX_RING_SIZE * sizeof(u64),
361 mac->tx->ring, mac->tx->dma);
f5cd7872 362
fc9e4d2a 363 kfree(mac->tx->ring_info);
f5cd7872
OJ		 364 kfree(mac->tx);
365 mac->tx = NULL;
366}
367
368static void pasemi_mac_free_rx_resources(struct net_device *dev)
369{
370 struct pasemi_mac *mac = netdev_priv(dev);
371 unsigned int i;
372 struct pasemi_mac_buffer *info;
f5cd7872
OJ		 373
374 for (i = 0; i < RX_RING_SIZE; i++) {
fc9e4d2a
OJ		 375 info = &RX_RING_INFO(mac, i);
376 if (info->skb && info->dma) {
377 pci_unmap_single(mac->dma_pdev,
378 info->dma,
379 info->skb->len,
380 PCI_DMA_FROMDEVICE);
381 dev_kfree_skb_any(info->skb);
f5cd7872 382 }
fc9e4d2a
OJ		 383 info->dma = 0;
384 info->skb = NULL;
f5cd7872
OJ		 385 }
386
fc9e4d2a
OJ		 387 for (i = 0; i < RX_RING_SIZE; i++)
388 RX_RING(mac, i) = 0;
389
f5cd7872 390 dma_free_coherent(&mac->dma_pdev->dev,
fc9e4d2a
OJ		 391 RX_RING_SIZE * sizeof(u64),
392 mac->rx->ring, mac->rx->dma);
f5cd7872
OJ		 393
394 dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64),
395 mac->rx->buffers, mac->rx->buf_dma);
396
fc9e4d2a 397 kfree(mac->rx->ring_info);
f5cd7872
OJ		 398 kfree(mac->rx);
399 mac->rx = NULL;
400}
401
928773c2 402static void pasemi_mac_replenish_rx_ring(struct net_device *dev, int limit)
f5cd7872
OJ		 403{
404 struct pasemi_mac *mac = netdev_priv(dev);
f5cd7872 405 int start = mac->rx->next_to_fill;
fc9e4d2a 406 unsigned int fill, count;
f5cd7872 407
cd4ceb24 408 if (limit <= 0)
f5cd7872
OJ		 409 return;
410
fc9e4d2a 411 fill = start;
928773c2 412 for (count = 0; count < limit; count++) {
fc9e4d2a
OJ		 413 struct pasemi_mac_buffer *info = &RX_RING_INFO(mac, fill);
414 u64 *buff = &RX_BUFF(mac, fill);
f5cd7872
OJ		 415 struct sk_buff *skb;
416 dma_addr_t dma;
417
fc9e4d2a
OJ		 418 /* Entry in use? */
419 WARN_ON(*buff);
420
9f05cfe2
OJ		 421 /* skb might still be in there for recycle on short receives */
422 if (info->skb)
423 skb = info->skb;
8dc121a4 424 else {
9f05cfe2 425 skb = dev_alloc_skb(BUF_SIZE);
8dc121a4
OJ		 426 skb_reserve(skb, LOCAL_SKB_ALIGN);
427 }
f5cd7872 428
9f05cfe2 429 if (unlikely(!skb))
f5cd7872 430 break;
f5cd7872 431
8dc121a4
OJ		 432 dma = pci_map_single(mac->dma_pdev, skb->data,
433 BUF_SIZE - LOCAL_SKB_ALIGN,
f5cd7872
OJ		 434 PCI_DMA_FROMDEVICE);
435
cd4ceb24 436 if (unlikely(dma_mapping_error(dma))) {
f5cd7872 437 dev_kfree_skb_irq(info->skb);
f5cd7872
OJ		 438 break;
439 }
440
441 info->skb = skb;
442 info->dma = dma;
443 *buff = XCT_RXB_LEN(BUF_SIZE) | XCT_RXB_ADDR(dma);
fc9e4d2a 444 fill++;
f5cd7872
OJ		 445 }
446
447 wmb();
448
928773c2
OJ		 449 write_dma_reg(mac, PAS_DMA_RXCHAN_INCR(mac->dma_rxch), count);
450 write_dma_reg(mac, PAS_DMA_RXINT_INCR(mac->dma_if), count);
f5cd7872 451
928773c2 452 mac->rx->next_to_fill += count;
f5cd7872
OJ		 453}
454
1b0335ea
OJ		 455static void pasemi_mac_restart_rx_intr(struct pasemi_mac *mac)
456{
52a94351 457 unsigned int reg, pcnt;
1b0335ea
OJ		 458 /* Re-enable packet count interrupts: finally
459 * ack the packet count interrupt we got in rx_intr.
460 */
461
52a94351 462 pcnt = *mac->rx_status & PAS_STATUS_PCNT_M;
1b0335ea 463
52a94351 464 reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC;
1b0335ea 465
a85b9422 466 write_iob_reg(mac, PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg);
1b0335ea
OJ		 467}
468
469static void pasemi_mac_restart_tx_intr(struct pasemi_mac *mac)
470{
52a94351 471 unsigned int reg, pcnt;
1b0335ea
OJ		 472
473 /* Re-enable packet count interrupts */
52a94351 474 pcnt = *mac->tx_status & PAS_STATUS_PCNT_M;
1b0335ea 475
52a94351 476 reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
1b0335ea 477
a85b9422 478 write_iob_reg(mac, PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), reg);
1b0335ea
OJ		 479}
480
481
69c29d89
OJ		 482static inline void pasemi_mac_rx_error(struct pasemi_mac *mac, u64 macrx)
483{
484 unsigned int rcmdsta, ccmdsta;
485
486 if (!netif_msg_rx_err(mac))
487 return;
488
489 rcmdsta = read_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
490 ccmdsta = read_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch));
491
492 printk(KERN_ERR "pasemi_mac: rx error. macrx %016lx, rx status %lx\n",
493 macrx, *mac->rx_status);
494
495 printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n",
496 rcmdsta, ccmdsta);
497}
498
499static inline void pasemi_mac_tx_error(struct pasemi_mac *mac, u64 mactx)
500{
501 unsigned int cmdsta;
502
503 if (!netif_msg_tx_err(mac))
504 return;
505
506 cmdsta = read_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch));
507
508 printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016lx, "\
509 "tx status 0x%016lx\n", mactx, *mac->tx_status);
510
511 printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta);
512}
513
f5cd7872
OJ		 514static int pasemi_mac_clean_rx(struct pasemi_mac *mac, int limit)
515{
cd4ceb24
OJ		 516 unsigned int n;
517 int count;
cd4ceb24
OJ		 518 struct pasemi_mac_buffer *info;
519 struct sk_buff *skb;
520 unsigned int i, len;
521 u64 macrx;
522 dma_addr_t dma;
f5cd7872
OJ		 523
524 spin_lock(&mac->rx->lock);
525
cd4ceb24 526 n = mac->rx->next_to_clean;
f5cd7872 527
cd4ceb24 528 for (count = limit; count; count--) {
fc9e4d2a 529 macrx = RX_RING(mac, n);
f5cd7872 530
69c29d89
OJ		 531 if ((macrx & XCT_MACRX_E) ||
532 (*mac->rx_status & PAS_STATUS_ERROR))
533 pasemi_mac_rx_error(mac, macrx);
534
cd4ceb24 535 if (!(macrx & XCT_MACRX_O))
f5cd7872
OJ		 536 break;
537
f5cd7872
OJ		 538 info = NULL;
539
540 /* We have to scan for our skb since there's no way
541 * to back-map them from the descriptor, and if we
542 * have several receive channels then they might not
543 * show up in the same order as they were put on the
544 * interface ring.
545 */
546
fc9e4d2a
OJ		 547 dma = (RX_RING(mac, n+1) & XCT_PTR_ADDR_M);
548 for (i = mac->rx->next_to_fill;
549 i < (mac->rx->next_to_fill + RX_RING_SIZE);
550 i++) {
551 info = &RX_RING_INFO(mac, i);
f5cd7872
OJ		 552 if (info->dma == dma)
553 break;
554 }
fc9e4d2a 555
9f05cfe2 556 skb = info->skb;
f5cd7872 557
ad5da10a
OJ		 558 prefetch(skb);
559 prefetch(&skb->data_len);
f5cd7872 560
cd4ceb24 561 len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S;
f5cd7872 562
9f05cfe2 563 if (len < 256) {
8dc121a4
OJ		 564 struct sk_buff *new_skb;
565
566 new_skb = netdev_alloc_skb(mac->netdev,
567 len + LOCAL_SKB_ALIGN);
9f05cfe2 568 if (new_skb) {
8dc121a4 569 skb_reserve(new_skb, LOCAL_SKB_ALIGN);
73344863 570 memcpy(new_skb->data, skb->data, len);
9f05cfe2
OJ		 571 /* save the skb in buffer_info as good */
572 skb = new_skb;
573 }
574 /* else just continue with the old one */
575 } else
576 info->skb = NULL;
f5cd7872 577
ad5da10a
OJ		 578 pci_unmap_single(mac->dma_pdev, dma, len, PCI_DMA_FROMDEVICE);
579
580 info->dma = 0;
fc9e4d2a 581
f5cd7872
OJ		 582 skb_put(skb, len);
583
26fcfa95 584 if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) {
38bf3184 585 skb->ip_summed = CHECKSUM_UNNECESSARY;
cd4ceb24 586 skb->csum = (macrx & XCT_MACRX_CSUM_M) >>
f5cd7872
OJ		 587 XCT_MACRX_CSUM_S;
588 } else
589 skb->ip_summed = CHECKSUM_NONE;
590
09f75cd7
JG		 591 mac->netdev->stats.rx_bytes += len;
592 mac->netdev->stats.rx_packets++;
f5cd7872 593
26fcfa95 594 skb->protocol = eth_type_trans(skb, mac->netdev);
f5cd7872
OJ		 595 netif_receive_skb(skb);
596
fc9e4d2a
OJ		 597 RX_RING(mac, n) = 0;
598 RX_RING(mac, n+1) = 0;
cd4ceb24 599
ad5da10a
OJ		 600 /* Need to zero it out since hardware doesn't, since the
601 * replenish loop uses it to tell when it's done.
602 */
603 RX_BUFF(mac, i) = 0;
604
fc9e4d2a 605 n += 2;
f5cd7872
OJ		 606 }
607
9a50bebd
OJ		 608 if (n > RX_RING_SIZE) {
609 /* Errata 5971 workaround: L2 target of headers */
610 write_iob_reg(mac, PAS_IOB_COM_PKTHDRCNT, 0);
611 n &= (RX_RING_SIZE-1);
612 }
fc9e4d2a 613 mac->rx->next_to_clean = n;
928773c2 614 pasemi_mac_replenish_rx_ring(mac->netdev, limit-count);
f5cd7872
OJ		 615
616 spin_unlock(&mac->rx->lock);
617
618 return count;
619}
620
ad3c20d1
OJ		 621/* Can't make this too large or we blow the kernel stack limits */
622#define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS)
623
f5cd7872
OJ		 624static int pasemi_mac_clean_tx(struct pasemi_mac *mac)
625{
ad3c20d1 626 int i, j;
ad5da10a
OJ		 627 unsigned int start, descr_count, buf_count, batch_limit;
628 unsigned int ring_limit;
02df6cfa 629 unsigned int total_count;
ca7e235f 630 unsigned long flags;
ad3c20d1
OJ		 631 struct sk_buff *skbs[TX_CLEAN_BATCHSIZE];
632 dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1];
f5cd7872 633
02df6cfa 634 total_count = 0;
ad5da10a 635 batch_limit = TX_CLEAN_BATCHSIZE;
02df6cfa 636restart:
f5cd7872
OJ		 637 spin_lock_irqsave(&mac->tx->lock, flags);
638
639 start = mac->tx->next_to_clean;
ad5da10a
OJ		 640 ring_limit = mac->tx->next_to_fill;
641
642 /* Compensate for when fill has wrapped but clean has not */
643 if (start > ring_limit)
644 ring_limit += TX_RING_SIZE;
02df6cfa 645
ad3c20d1
OJ		 646 buf_count = 0;
647 descr_count = 0;
f5cd7872 648
ad3c20d1 649 for (i = start;
ad5da10a 650 descr_count < batch_limit && i < ring_limit;
ad3c20d1 651 i += buf_count) {
fc9e4d2a 652 u64 mactx = TX_RING(mac, i);
ad5da10a 653 struct sk_buff *skb;
ad3c20d1 654
fc9e4d2a 655 if ((mactx & XCT_MACTX_E) ||
69c29d89 656 (*mac->tx_status & PAS_STATUS_ERROR))
fc9e4d2a 657 pasemi_mac_tx_error(mac, mactx);
69c29d89 658
fc9e4d2a 659 if (unlikely(mactx & XCT_MACTX_O))
02df6cfa 660 /* Not yet transmitted */
f5cd7872
OJ		 661 break;
662
ad5da10a
OJ		 663 skb = TX_RING_INFO(mac, i+1).skb;
664 skbs[descr_count] = skb;
ad3c20d1 665
ad5da10a
OJ		 666 buf_count = 2 + skb_shinfo(skb)->nr_frags;
667 for (j = 0; j <= skb_shinfo(skb)->nr_frags; j++)
ad3c20d1
OJ		 668 dmas[descr_count][j] = TX_RING_INFO(mac, i+1+j).dma;
669
fc9e4d2a
OJ		 670 TX_RING(mac, i) = 0;
671 TX_RING(mac, i+1) = 0;
672
ad3c20d1
OJ		 673 /* Since we always fill with an even number of entries, make
674 * sure we skip any unused one at the end as well.
675 */
676 if (buf_count & 1)
677 buf_count++;
678 descr_count++;
f5cd7872 679 }
ad5da10a 680 mac->tx->next_to_clean = i & (TX_RING_SIZE-1);
ad3c20d1 681
f5cd7872 682 spin_unlock_irqrestore(&mac->tx->lock, flags);
0ce68c74
OJ		 683 netif_wake_queue(mac->netdev);
684
ad3c20d1
OJ		 685 for (i = 0; i < descr_count; i++)
686 pasemi_mac_unmap_tx_skb(mac, skbs[i], dmas[i]);
02df6cfa 687
ad3c20d1 688 total_count += descr_count;
02df6cfa
OJ		 689
690 /* If the batch was full, try to clean more */
ad5da10a 691 if (descr_count == batch_limit)
02df6cfa
OJ		 692 goto restart;
693
694 return total_count;
f5cd7872
OJ		 695}
696
697
698static irqreturn_t pasemi_mac_rx_intr(int irq, void *data)
699{
700 struct net_device *dev = data;
701 struct pasemi_mac *mac = netdev_priv(dev);
702 unsigned int reg;
703
6dfa7522 704 if (!(*mac->rx_status & PAS_STATUS_CAUSE_M))
f5cd7872
OJ		 705 return IRQ_NONE;
706
6dfa7522
OJ		 707 /* Don't reset packet count so it won't fire again but clear
708 * all others.
709 */
710
6dfa7522
OJ		 711 reg = 0;
712 if (*mac->rx_status & PAS_STATUS_SOFT)
713 reg |= PAS_IOB_DMA_RXCH_RESET_SINTC;
714 if (*mac->rx_status & PAS_STATUS_ERROR)
715 reg |= PAS_IOB_DMA_RXCH_RESET_DINTC;
f5cd7872
OJ		 716 if (*mac->rx_status & PAS_STATUS_TIMER)
717 reg |= PAS_IOB_DMA_RXCH_RESET_TINTC;
718
bea3348e 719 netif_rx_schedule(dev, &mac->napi);
6dfa7522 720
a85b9422 721 write_iob_reg(mac, PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg);
f5cd7872
OJ		 722
723 return IRQ_HANDLED;
724}
725
726static irqreturn_t pasemi_mac_tx_intr(int irq, void *data)
727{
728 struct net_device *dev = data;
729 struct pasemi_mac *mac = netdev_priv(dev);
52a94351 730 unsigned int reg, pcnt;
f5cd7872 731
6dfa7522 732 if (!(*mac->tx_status & PAS_STATUS_CAUSE_M))
f5cd7872
OJ		 733 return IRQ_NONE;
734
735 pasemi_mac_clean_tx(mac);
736
52a94351
OJ		 737 pcnt = *mac->tx_status & PAS_STATUS_PCNT_M;
738
739 reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
6dfa7522
OJ		 740
741 if (*mac->tx_status & PAS_STATUS_SOFT)
742 reg |= PAS_IOB_DMA_TXCH_RESET_SINTC;
743 if (*mac->tx_status & PAS_STATUS_ERROR)
744 reg |= PAS_IOB_DMA_TXCH_RESET_DINTC;
f5cd7872 745
a85b9422 746 write_iob_reg(mac, PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), reg);
f5cd7872 747
f5cd7872
OJ		 748 return IRQ_HANDLED;
749}
750
bb6e9590
OJ		 751static void pasemi_adjust_link(struct net_device *dev)
752{
753 struct pasemi_mac *mac = netdev_priv(dev);
754 int msg;
755 unsigned int flags;
756 unsigned int new_flags;
757
758 if (!mac->phydev->link) {
759 /* If no link, MAC speed settings don't matter. Just report
760 * link down and return.
761 */
762 if (mac->link && netif_msg_link(mac))
763 printk(KERN_INFO "%s: Link is down.\n", dev->name);
764
765 netif_carrier_off(dev);
766 mac->link = 0;
767
768 return;
769 } else
770 netif_carrier_on(dev);
771
a85b9422 772 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
bb6e9590
OJ		 773 new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M |
774 PAS_MAC_CFG_PCFG_TSR_M);
775
776 if (!mac->phydev->duplex)
777 new_flags |= PAS_MAC_CFG_PCFG_HD;
778
779 switch (mac->phydev->speed) {
780 case 1000:
781 new_flags |= PAS_MAC_CFG_PCFG_SPD_1G |
782 PAS_MAC_CFG_PCFG_TSR_1G;
783 break;
784 case 100:
785 new_flags |= PAS_MAC_CFG_PCFG_SPD_100M |
786 PAS_MAC_CFG_PCFG_TSR_100M;
787 break;
788 case 10:
789 new_flags |= PAS_MAC_CFG_PCFG_SPD_10M |
790 PAS_MAC_CFG_PCFG_TSR_10M;
791 break;
792 default:
793 printk("Unsupported speed %d\n", mac->phydev->speed);
794 }
795
796 /* Print on link or speed/duplex change */
797 msg = mac->link != mac->phydev->link || flags != new_flags;
798
799 mac->duplex = mac->phydev->duplex;
800 mac->speed = mac->phydev->speed;
801 mac->link = mac->phydev->link;
802
803 if (new_flags != flags)
a85b9422 804 write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags);
bb6e9590
OJ		 805
806 if (msg && netif_msg_link(mac))
807 printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n",
808 dev->name, mac->speed, mac->duplex ? "full" : "half");
809}
810
811static int pasemi_mac_phy_init(struct net_device *dev)
812{
813 struct pasemi_mac *mac = netdev_priv(dev);
814 struct device_node *dn, *phy_dn;
815 struct phy_device *phydev;
816 unsigned int phy_id;
817 const phandle *ph;
818 const unsigned int *prop;
819 struct resource r;
820 int ret;
821
822 dn = pci_device_to_OF_node(mac->pdev);
9028780a 823 ph = of_get_property(dn, "phy-handle", NULL);
bb6e9590
OJ		 824 if (!ph)
825 return -ENODEV;
826 phy_dn = of_find_node_by_phandle(*ph);
827
9028780a 828 prop = of_get_property(phy_dn, "reg", NULL);
bb6e9590
OJ		 829 ret = of_address_to_resource(phy_dn->parent, 0, &r);
830 if (ret)
831 goto err;
832
833 phy_id = *prop;
834 snprintf(mac->phy_id, BUS_ID_SIZE, PHY_ID_FMT, (int)r.start, phy_id);
835
836 of_node_put(phy_dn);
837
838 mac->link = 0;
839 mac->speed = 0;
840 mac->duplex = -1;
841
842 phydev = phy_connect(dev, mac->phy_id, &pasemi_adjust_link, 0, PHY_INTERFACE_MODE_SGMII);
843
844 if (IS_ERR(phydev)) {
845 printk(KERN_ERR "%s: Could not attach to phy\n", dev->name);
846 return PTR_ERR(phydev);
847 }
848
849 mac->phydev = phydev;
850
851 return 0;
852
853err:
854 of_node_put(phy_dn);
855 return -ENODEV;
856}
857
858
f5cd7872
OJ		 859static int pasemi_mac_open(struct net_device *dev)
860{
861 struct pasemi_mac *mac = netdev_priv(dev);
771f7404 862 int base_irq;
f5cd7872
OJ		 863 unsigned int flags;
864 int ret;
865
866 /* enable rx section */
a85b9422 867 write_dma_reg(mac, PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN);
f5cd7872
OJ		 868
869 /* enable tx section */
a85b9422 870 write_dma_reg(mac, PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN);
f5cd7872
OJ		 871
872 flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
873 PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
874 PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12);
875
a85b9422 876 write_mac_reg(mac, PAS_MAC_CFG_TXP, flags);
f5cd7872 877
a85b9422
OJ		 878 write_iob_reg(mac, PAS_IOB_DMA_RXCH_CFG(mac->dma_rxch),
879 PAS_IOB_DMA_RXCH_CFG_CNTTH(0));
f5cd7872 880
a85b9422 881 write_iob_reg(mac, PAS_IOB_DMA_TXCH_CFG(mac->dma_txch),
02df6cfa 882 PAS_IOB_DMA_TXCH_CFG_CNTTH(128));
f5cd7872 883
1b0335ea
OJ		 884 /* Clear out any residual packet count state from firmware */
885 pasemi_mac_restart_rx_intr(mac);
886 pasemi_mac_restart_tx_intr(mac);
887
6dfa7522 888 /* 0xffffff is max value, about 16ms */
a85b9422
OJ		 889 write_iob_reg(mac, PAS_IOB_DMA_COM_TIMEOUTCFG,
890 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0xffffff));
f5cd7872 891
f5cd7872
OJ		 892 ret = pasemi_mac_setup_rx_resources(dev);
893 if (ret)
894 goto out_rx_resources;
895
896 ret = pasemi_mac_setup_tx_resources(dev);
897 if (ret)
898 goto out_tx_resources;
899
a85b9422
OJ		 900 write_mac_reg(mac, PAS_MAC_IPC_CHNL,
901 PAS_MAC_IPC_CHNL_DCHNO(mac->dma_rxch) |
902 PAS_MAC_IPC_CHNL_BCH(mac->dma_rxch));
f5cd7872
OJ		 903
904 /* enable rx if */
a85b9422
OJ		 905 write_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
906 PAS_DMA_RXINT_RCMDSTA_EN);
f5cd7872
OJ		 907
908 /* enable rx channel */
a85b9422
OJ		 909 write_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
910 PAS_DMA_RXCHAN_CCMDSTA_EN |
911 PAS_DMA_RXCHAN_CCMDSTA_DU);
f5cd7872
OJ		 912
913 /* enable tx channel */
a85b9422
OJ		 914 write_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
915 PAS_DMA_TXCHAN_TCMDSTA_EN);
f5cd7872 916
928773c2 917 pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE);
f5cd7872 918
36033766
OJ		 919 flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PE |
920 PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE;
921
922 if (mac->type == MAC_TYPE_GMAC)
923 flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G;
924 else
925 flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G;
926
927 /* Enable interface in MAC */
928 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
929
bb6e9590
OJ		 930 ret = pasemi_mac_phy_init(dev);
931 /* Some configs don't have PHYs (XAUI etc), so don't complain about
932 * failed init due to -ENODEV.
933 */
934 if (ret && ret != -ENODEV)
935 dev_warn(&mac->pdev->dev, "phy init failed: %d\n", ret);
936
f5cd7872 937 netif_start_queue(dev);
bea3348e 938 napi_enable(&mac->napi);
f5cd7872 939
771f7404
OJ		 940 /* Interrupts are a bit different for our DMA controller: While
941 * it's got one a regular PCI device header, the interrupt there
942 * is really the base of the range it's using. Each tx and rx
943 * channel has it's own interrupt source.
944 */
945
946 base_irq = virq_to_hw(mac->dma_pdev->irq);
947
948 mac->tx_irq = irq_create_mapping(NULL, base_irq + mac->dma_txch);
949 mac->rx_irq = irq_create_mapping(NULL, base_irq + 20 + mac->dma_txch);
950
951 ret = request_irq(mac->tx_irq, &pasemi_mac_tx_intr, IRQF_DISABLED,
f5cd7872
OJ		 952 mac->tx->irq_name, dev);
953 if (ret) {
954 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
771f7404 955 base_irq + mac->dma_txch, ret);
f5cd7872
OJ		 956 goto out_tx_int;
957 }
958
771f7404 959 ret = request_irq(mac->rx_irq, &pasemi_mac_rx_intr, IRQF_DISABLED,
f5cd7872
OJ		 960 mac->rx->irq_name, dev);
961 if (ret) {
962 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
771f7404 963 base_irq + 20 + mac->dma_rxch, ret);
f5cd7872
OJ		 964 goto out_rx_int;
965 }
966
bb6e9590
OJ		 967 if (mac->phydev)
968 phy_start(mac->phydev);
969
f5cd7872
OJ		 970 return 0;
971
972out_rx_int:
771f7404 973 free_irq(mac->tx_irq, dev);
f5cd7872 974out_tx_int:
bea3348e 975 napi_disable(&mac->napi);
f5cd7872
OJ		 976 netif_stop_queue(dev);
977 pasemi_mac_free_tx_resources(dev);
978out_tx_resources:
979 pasemi_mac_free_rx_resources(dev);
980out_rx_resources:
981
982 return ret;
983}
984
985#define MAX_RETRIES 5000
986
987static int pasemi_mac_close(struct net_device *dev)
988{
989 struct pasemi_mac *mac = netdev_priv(dev);
990 unsigned int stat;
991 int retries;
992
bb6e9590
OJ		 993 if (mac->phydev) {
994 phy_stop(mac->phydev);
995 phy_disconnect(mac->phydev);
996 }
997
f5cd7872 998 netif_stop_queue(dev);
bea3348e 999 napi_disable(&mac->napi);
f5cd7872
OJ		 1000
1001 /* Clean out any pending buffers */
1002 pasemi_mac_clean_tx(mac);
1003 pasemi_mac_clean_rx(mac, RX_RING_SIZE);
1004
1005 /* Disable interface */
a85b9422
OJ		 1006 write_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), PAS_DMA_TXCHAN_TCMDSTA_ST);
1007 write_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), PAS_DMA_RXINT_RCMDSTA_ST);
1008 write_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), PAS_DMA_RXCHAN_CCMDSTA_ST);
f5cd7872
OJ		 1009
1010 for (retries = 0; retries < MAX_RETRIES; retries++) {
a85b9422 1011 stat = read_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch));
0ce68c74 1012 if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT))
f5cd7872
OJ		 1013 break;
1014 cond_resched();
1015 }
1016
0ce68c74 1017 if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)
f5cd7872 1018 dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n");
f5cd7872
OJ		 1019
1020 for (retries = 0; retries < MAX_RETRIES; retries++) {
a85b9422 1021 stat = read_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch));
0ce68c74 1022 if (!(stat & PAS_DMA_RXCHAN_CCMDSTA_ACT))
f5cd7872
OJ		 1023 break;
1024 cond_resched();
1025 }
1026
0ce68c74 1027 if (stat & PAS_DMA_RXCHAN_CCMDSTA_ACT)
f5cd7872 1028 dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n");
f5cd7872
OJ		 1029
1030 for (retries = 0; retries < MAX_RETRIES; retries++) {
a85b9422 1031 stat = read_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
0ce68c74 1032 if (!(stat & PAS_DMA_RXINT_RCMDSTA_ACT))
f5cd7872
OJ		 1033 break;
1034 cond_resched();
1035 }
1036
0ce68c74 1037 if (stat & PAS_DMA_RXINT_RCMDSTA_ACT)
f5cd7872 1038 dev_err(&mac->dma_pdev->dev, "Failed to stop rx interface\n");
f5cd7872
OJ		 1039
1040 /* Then, disable the channel. This must be done separately from
1041 * stopping, since you can't disable when active.
1042 */
1043
a85b9422
OJ		 1044 write_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), 0);
1045 write_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), 0);
1046 write_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0);
f5cd7872 1047
771f7404
OJ		 1048 free_irq(mac->tx_irq, dev);
1049 free_irq(mac->rx_irq, dev);
f5cd7872
OJ		 1050
1051 /* Free resources */
1052 pasemi_mac_free_rx_resources(dev);
1053 pasemi_mac_free_tx_resources(dev);
1054
1055 return 0;
1056}
1057
1058static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
1059{
1060 struct pasemi_mac *mac = netdev_priv(dev);
1061 struct pasemi_mac_txring *txring;
ad3c20d1
OJ		 1062 u64 dflags, mactx;
1063 dma_addr_t map[MAX_SKB_FRAGS+1];
1064 unsigned int map_size[MAX_SKB_FRAGS+1];
ca7e235f 1065 unsigned long flags;
ad3c20d1 1066 int i, nfrags;
f5cd7872
OJ		 1067
1068 dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_SS | XCT_MACTX_CRC_PAD;
1069
1070 if (skb->ip_summed == CHECKSUM_PARTIAL) {
d56f90a7
ACM		 1071 const unsigned char *nh = skb_network_header(skb);
1072
eddc9ec5 1073 switch (ip_hdr(skb)->protocol) {
f5cd7872
OJ		 1074 case IPPROTO_TCP:
1075 dflags |= XCT_MACTX_CSUM_TCP;
cfe1fc77 1076 dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
d56f90a7 1077 dflags |= XCT_MACTX_IPO(nh - skb->data);
f5cd7872
OJ		 1078 break;
1079 case IPPROTO_UDP:
1080 dflags |= XCT_MACTX_CSUM_UDP;
cfe1fc77 1081 dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
d56f90a7 1082 dflags |= XCT_MACTX_IPO(nh - skb->data);
f5cd7872
OJ		 1083 break;
1084 }
1085 }
1086
ad3c20d1
OJ		 1087 nfrags = skb_shinfo(skb)->nr_frags;
1088
1089 map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb),
1090 PCI_DMA_TODEVICE);
1091 map_size[0] = skb_headlen(skb);
1092 if (dma_mapping_error(map[0]))
1093 goto out_err_nolock;
1094
1095 for (i = 0; i < nfrags; i++) {
1096 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
f5cd7872 1097
ad3c20d1
OJ		 1098 map[i+1] = pci_map_page(mac->dma_pdev, frag->page,
1099 frag->page_offset, frag->size,
1100 PCI_DMA_TODEVICE);
1101 map_size[i+1] = frag->size;
1102 if (dma_mapping_error(map[i+1])) {
1103 nfrags = i;
1104 goto out_err_nolock;
1105 }
1106 }
f5cd7872 1107
26fcfa95 1108 mactx = dflags | XCT_MACTX_LLEN(skb->len);
26fcfa95 1109
f5cd7872
OJ		 1110 txring = mac->tx;
1111
1112 spin_lock_irqsave(&txring->lock, flags);
1113
ad5da10a
OJ		 1114 /* Avoid stepping on the same cache line that the DMA controller
1115 * is currently about to send, so leave at least 8 words available.
1116 * Total free space needed is mactx + fragments + 8
1117 */
1118 if (RING_AVAIL(txring) < nfrags + 10) {
1119 /* no room -- stop the queue and wait for tx intr */
1120 netif_stop_queue(dev);
1121 goto out_err;
f5cd7872
OJ		 1122 }
1123
fc9e4d2a 1124 TX_RING(mac, txring->next_to_fill) = mactx;
ad3c20d1
OJ		 1125 txring->next_to_fill++;
1126 TX_RING_INFO(mac, txring->next_to_fill).skb = skb;
1127 for (i = 0; i <= nfrags; i++) {
1128 TX_RING(mac, txring->next_to_fill+i) =
1129 XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
1130 TX_RING_INFO(mac, txring->next_to_fill+i).dma = map[i];
1131 }
1132
1133 /* We have to add an even number of 8-byte entries to the ring
1134 * even if the last one is unused. That means always an odd number
1135 * of pointers + one mactx descriptor.
1136 */
1137 if (nfrags & 1)
1138 nfrags++;
fc9e4d2a 1139
ad5da10a
OJ		 1140 txring->next_to_fill = (txring->next_to_fill + nfrags + 1) &
1141 (TX_RING_SIZE-1);
f5cd7872 1142
09f75cd7
JG		 1143 dev->stats.tx_packets++;
1144 dev->stats.tx_bytes += skb->len;
f5cd7872
OJ		 1145
1146 spin_unlock_irqrestore(&txring->lock, flags);
1147
ad3c20d1 1148 write_dma_reg(mac, PAS_DMA_TXCHAN_INCR(mac->dma_txch), (nfrags+2) >> 1);
f5cd7872
OJ		 1149
1150 return NETDEV_TX_OK;
1151
1152out_err:
1153 spin_unlock_irqrestore(&txring->lock, flags);
ad3c20d1
OJ		 1154out_err_nolock:
1155 while (nfrags--)
1156 pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags],
1157 PCI_DMA_TODEVICE);
1158
f5cd7872
OJ		 1159 return NETDEV_TX_BUSY;
1160}
1161
f5cd7872
OJ		 1162static void pasemi_mac_set_rx_mode(struct net_device *dev)
1163{
1164 struct pasemi_mac *mac = netdev_priv(dev);
1165 unsigned int flags;
1166
a85b9422 1167 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
f5cd7872
OJ		 1168
1169 /* Set promiscuous */
1170 if (dev->flags & IFF_PROMISC)
1171 flags |= PAS_MAC_CFG_PCFG_PR;
1172 else
1173 flags &= ~PAS_MAC_CFG_PCFG_PR;
1174
a85b9422 1175 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
f5cd7872
OJ		 1176}
1177
1178
bea3348e 1179static int pasemi_mac_poll(struct napi_struct *napi, int budget)
f5cd7872 1180{
bea3348e
SH		 1181 struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi);
1182 struct net_device *dev = mac->netdev;
1183 int pkts;
f5cd7872 1184
829185e9 1185 pasemi_mac_clean_tx(mac);
bea3348e
SH		 1186 pkts = pasemi_mac_clean_rx(mac, budget);
1187 if (pkts < budget) {
f5cd7872 1188 /* all done, no more packets present */
bea3348e 1189 netif_rx_complete(dev, napi);
f5cd7872 1190
1b0335ea 1191 pasemi_mac_restart_rx_intr(mac);
f5cd7872 1192 }
bea3348e 1193 return pkts;
f5cd7872
OJ		 1194}
1195
b6e05a1b
OJ		 1196static void __iomem * __devinit map_onedev(struct pci_dev *p, int index)
1197{
1198 struct device_node *dn;
1199 void __iomem *ret;
1200
1201 dn = pci_device_to_OF_node(p);
1202 if (!dn)
1203 goto fallback;
1204
1205 ret = of_iomap(dn, index);
1206 if (!ret)
1207 goto fallback;
1208
1209 return ret;
1210fallback:
1211 /* This is hardcoded and ugly, but we have some firmware versions
1212 * that don't provide the register space in the device tree. Luckily
1213 * they are at well-known locations so we can just do the math here.
1214 */
1215 return ioremap(0xe0000000 + (p->devfn << 12), 0x2000);
1216}
1217
1218static int __devinit pasemi_mac_map_regs(struct pasemi_mac *mac)
1219{
1220 struct resource res;
1221 struct device_node *dn;
1222 int err;
1223
1224 mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
1225 if (!mac->dma_pdev) {
1226 dev_err(&mac->pdev->dev, "Can't find DMA Controller\n");
1227 return -ENODEV;
1228 }
1229
1230 mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
1231 if (!mac->iob_pdev) {
1232 dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n");
1233 return -ENODEV;
1234 }
1235
1236 mac->regs = map_onedev(mac->pdev, 0);
1237 mac->dma_regs = map_onedev(mac->dma_pdev, 0);
1238 mac->iob_regs = map_onedev(mac->iob_pdev, 0);
1239
1240 if (!mac->regs || !mac->dma_regs || !mac->iob_regs) {
1241 dev_err(&mac->pdev->dev, "Can't map registers\n");
1242 return -ENODEV;
1243 }
1244
1245 /* The dma status structure is located in the I/O bridge, and
1246 * is cache coherent.
1247 */
1248 if (!dma_status) {
1249 dn = pci_device_to_OF_node(mac->iob_pdev);
1250 if (dn)
1251 err = of_address_to_resource(dn, 1, &res);
1252 if (!dn || err) {
1253 /* Fallback for old firmware */
1254 res.start = 0xfd800000;
1255 res.end = res.start + 0x1000;
1256 }
1257 dma_status = __ioremap(res.start, res.end-res.start, 0);
1258 }
1259
1260 return 0;
1261}
1262
f5cd7872
OJ		 1263static int __devinit
1264pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1265{
1266 static int index = 0;
1267 struct net_device *dev;
1268 struct pasemi_mac *mac;
1269 int err;
0795af57 1270 DECLARE_MAC_BUF(mac_buf);
f5cd7872
OJ		 1271
1272 err = pci_enable_device(pdev);
1273 if (err)
1274 return err;
1275
1276 dev = alloc_etherdev(sizeof(struct pasemi_mac));
1277 if (dev == NULL) {
1278 dev_err(&pdev->dev,
1279 "pasemi_mac: Could not allocate ethernet device.\n");
1280 err = -ENOMEM;
1281 goto out_disable_device;
1282 }
1283
f5cd7872
OJ		 1284 pci_set_drvdata(pdev, dev);
1285 SET_NETDEV_DEV(dev, &pdev->dev);
1286
1287 mac = netdev_priv(dev);
1288
1289 mac->pdev = pdev;
1290 mac->netdev = dev;
f5cd7872 1291
bea3348e
SH		 1292 netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64);
1293
ad3c20d1 1294 dev->features = NETIF_F_HW_CSUM | NETIF_F_LLTX | NETIF_F_SG;
bea3348e 1295
f5cd7872
OJ		 1296 /* These should come out of the device tree eventually */
1297 mac->dma_txch = index;
1298 mac->dma_rxch = index;
1299
1300 /* We probe GMAC before XAUI, but the DMA interfaces are
1301 * in XAUI, GMAC order.
1302 */
1303 if (index < 4)
1304 mac->dma_if = index + 2;
1305 else
1306 mac->dma_if = index - 4;
1307 index++;
1308
1309 switch (pdev->device) {
1310 case 0xa005:
1311 mac->type = MAC_TYPE_GMAC;
1312 break;
1313 case 0xa006:
1314 mac->type = MAC_TYPE_XAUI;
1315 break;
1316 default:
1317 err = -ENODEV;
1318 goto out;
1319 }
1320
1321 /* get mac addr from device tree */
1322 if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) {
1323 err = -ENODEV;
1324 goto out;
1325 }
1326 memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr));
1327
1328 dev->open = pasemi_mac_open;
1329 dev->stop = pasemi_mac_close;
1330 dev->hard_start_xmit = pasemi_mac_start_tx;
f5cd7872 1331 dev->set_multicast_list = pasemi_mac_set_rx_mode;
f5cd7872 1332
b6e05a1b
OJ		 1333 err = pasemi_mac_map_regs(mac);
1334 if (err)
1335 goto out;
f5cd7872
OJ		 1336
1337 mac->rx_status = &dma_status->rx_sta[mac->dma_rxch];
1338 mac->tx_status = &dma_status->tx_sta[mac->dma_txch];
1339
ceb51361
OJ		 1340 mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
1341
bb6e9590
OJ		 1342 /* Enable most messages by default */
1343 mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1344
f5cd7872
OJ		 1345 err = register_netdev(dev);
1346
1347 if (err) {
1348 dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n",
1349 err);
1350 goto out;
69c29d89 1351 } else if netif_msg_probe(mac)
f5cd7872 1352 printk(KERN_INFO "%s: PA Semi %s: intf %d, txch %d, rxch %d, "
0795af57 1353 "hw addr %s\n",
f5cd7872
OJ		 1354 dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI",
1355 mac->dma_if, mac->dma_txch, mac->dma_rxch,
0795af57 1356 print_mac(mac_buf, dev->dev_addr));
f5cd7872
OJ		 1357
1358 return err;
1359
1360out:
b6e05a1b
OJ		 1361 if (mac->iob_pdev)
1362 pci_dev_put(mac->iob_pdev);
1363 if (mac->dma_pdev)
1364 pci_dev_put(mac->dma_pdev);
1365 if (mac->dma_regs)
1366 iounmap(mac->dma_regs);
1367 if (mac->iob_regs)
1368 iounmap(mac->iob_regs);
1369 if (mac->regs)
1370 iounmap(mac->regs);
1371
f5cd7872
OJ		 1372 free_netdev(dev);
1373out_disable_device:
1374 pci_disable_device(pdev);
1375 return err;
1376
1377}
1378
1379static void __devexit pasemi_mac_remove(struct pci_dev *pdev)
1380{
1381 struct net_device *netdev = pci_get_drvdata(pdev);
1382 struct pasemi_mac *mac;
1383
1384 if (!netdev)
1385 return;
1386
1387 mac = netdev_priv(netdev);
1388
1389 unregister_netdev(netdev);
1390
1391 pci_disable_device(pdev);
1392 pci_dev_put(mac->dma_pdev);
1393 pci_dev_put(mac->iob_pdev);
1394
b6e05a1b
OJ		 1395 iounmap(mac->regs);
1396 iounmap(mac->dma_regs);
1397 iounmap(mac->iob_regs);
1398
f5cd7872
OJ		 1399 pci_set_drvdata(pdev, NULL);
1400 free_netdev(netdev);
1401}
1402
1403static struct pci_device_id pasemi_mac_pci_tbl[] = {
1404 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) },
1405 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) },
fd178254 1406 { },
f5cd7872
OJ		 1407};
1408
1409MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl);
1410
1411static struct pci_driver pasemi_mac_driver = {
1412 .name = "pasemi_mac",
1413 .id_table = pasemi_mac_pci_tbl,
1414 .probe = pasemi_mac_probe,
1415 .remove = __devexit_p(pasemi_mac_remove),
1416};
1417
1418static void __exit pasemi_mac_cleanup_module(void)
1419{
1420 pci_unregister_driver(&pasemi_mac_driver);
1421 __iounmap(dma_status);
1422 dma_status = NULL;
1423}
1424
1425int pasemi_mac_init_module(void)
1426{
1427 return pci_register_driver(&pasemi_mac_driver);
1428}
1429
f5cd7872
OJ		 1430module_init(pasemi_mac_init_module);
1431module_exit(pasemi_mac_cleanup_module);
Linux kernel - Deliverables
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