[deliverable/linux.git] / drivers / net / pasemi_mac.h

/*
 * Copyright (C) 2006 PA Semi, Inc
 *
 * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
 * hardware register layouts.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#ifndef PASEMI_MAC_H
#define PASEMI_MAC_H

#include <linux/ethtool.h>
#include <linux/netdevice.h>
#include <linux/spinlock.h>
#include <linux/phy.h>

#define MAX_LRO_DESCRIPTORS 8

struct pasemi_mac_txring {
	struct pasemi_dmachan chan; /* Must be first */
	spinlock_t	 lock;
	unsigned int	 size;
	unsigned int	 next_to_fill;
	unsigned int	 next_to_clean;
	struct pasemi_mac_buffer *ring_info;
	struct pasemi_mac *mac;	/* Needed in intr handler */
	struct timer_list clean_timer;
};

struct pasemi_mac_rxring {
	struct pasemi_dmachan chan; /* Must be first */
	spinlock_t	 lock;
	u64		*buffers;	/* RX interface buffer ring */
	dma_addr_t	 buf_dma;
	unsigned int	 size;
	unsigned int	 next_to_fill;
	unsigned int	 next_to_clean;
	struct pasemi_mac_buffer *ring_info;
	struct pasemi_mac *mac;	/* Needed in intr handler */
};

struct pasemi_mac {
	struct net_device *netdev;
	struct pci_dev *pdev;
	struct pci_dev *dma_pdev;
	struct pci_dev *iob_pdev;
	struct phy_device *phydev;
	struct napi_struct napi;

	u8		type;
#define MAC_TYPE_GMAC	1
#define MAC_TYPE_XAUI	2
	u32	dma_if;

	u8		mac_addr[6];

	struct net_lro_mgr	lro_mgr;
	struct net_lro_desc	lro_desc[MAX_LRO_DESCRIPTORS];
	struct timer_list	rxtimer;
	unsigned int		lro_max_aggr;

	struct pasemi_mac_txring *tx;
	struct pasemi_mac_rxring *rx;
	char		tx_irq_name[10];		/* "eth%d tx" */
	char		rx_irq_name[10];		/* "eth%d rx" */
	int	link;
	int	speed;
	int	duplex;

	unsigned int	msg_enable;
	char	phy_id[BUS_ID_SIZE];
};

/* Software status descriptor (ring_info) */
struct pasemi_mac_buffer {
	struct sk_buff *skb;
	dma_addr_t	dma;
};


/* PCI register offsets and formats */


/* MAC CFG register offsets */
enum {
	PAS_MAC_CFG_PCFG = 0x80,
	PAS_MAC_CFG_TXP = 0x98,
	PAS_MAC_IPC_CHNL = 0x208,
};

/* MAC CFG register fields */
#define PAS_MAC_CFG_PCFG_PE		0x80000000
#define PAS_MAC_CFG_PCFG_CE		0x40000000
#define PAS_MAC_CFG_PCFG_BU		0x20000000
#define PAS_MAC_CFG_PCFG_TT		0x10000000
#define PAS_MAC_CFG_PCFG_TSR_M		0x0c000000
#define PAS_MAC_CFG_PCFG_TSR_10M	0x00000000
#define PAS_MAC_CFG_PCFG_TSR_100M	0x04000000
#define PAS_MAC_CFG_PCFG_TSR_1G		0x08000000
#define PAS_MAC_CFG_PCFG_TSR_10G	0x0c000000
#define PAS_MAC_CFG_PCFG_T24		0x02000000
#define PAS_MAC_CFG_PCFG_PR		0x01000000
#define PAS_MAC_CFG_PCFG_CRO_M		0x00ff0000
#define PAS_MAC_CFG_PCFG_CRO_S	16
#define PAS_MAC_CFG_PCFG_IPO_M		0x0000ff00
#define PAS_MAC_CFG_PCFG_IPO_S	8
#define PAS_MAC_CFG_PCFG_S1		0x00000080
#define PAS_MAC_CFG_PCFG_IO_M		0x00000060
#define PAS_MAC_CFG_PCFG_IO_MAC		0x00000000
#define PAS_MAC_CFG_PCFG_IO_OFF		0x00000020
#define PAS_MAC_CFG_PCFG_IO_IND_ETH	0x00000040
#define PAS_MAC_CFG_PCFG_IO_IND_IP	0x00000060
#define PAS_MAC_CFG_PCFG_LP		0x00000010
#define PAS_MAC_CFG_PCFG_TS		0x00000008
#define PAS_MAC_CFG_PCFG_HD		0x00000004
#define PAS_MAC_CFG_PCFG_SPD_M		0x00000003
#define PAS_MAC_CFG_PCFG_SPD_10M	0x00000000
#define PAS_MAC_CFG_PCFG_SPD_100M	0x00000001
#define PAS_MAC_CFG_PCFG_SPD_1G		0x00000002
#define PAS_MAC_CFG_PCFG_SPD_10G	0x00000003
#define PAS_MAC_CFG_TXP_FCF		0x01000000
#define PAS_MAC_CFG_TXP_FCE		0x00800000
#define PAS_MAC_CFG_TXP_FC		0x00400000
#define PAS_MAC_CFG_TXP_FPC_M		0x00300000
#define PAS_MAC_CFG_TXP_FPC_S		20
#define PAS_MAC_CFG_TXP_FPC(x)		(((x) << PAS_MAC_CFG_TXP_FPC_S) & \
					 PAS_MAC_CFG_TXP_FPC_M)
#define PAS_MAC_CFG_TXP_RT		0x00080000
#define PAS_MAC_CFG_TXP_BL		0x00040000
#define PAS_MAC_CFG_TXP_SL_M		0x00030000
#define PAS_MAC_CFG_TXP_SL_S		16
#define PAS_MAC_CFG_TXP_SL(x)		(((x) << PAS_MAC_CFG_TXP_SL_S) & \
					 PAS_MAC_CFG_TXP_SL_M)
#define PAS_MAC_CFG_TXP_COB_M		0x0000f000
#define PAS_MAC_CFG_TXP_COB_S		12
#define PAS_MAC_CFG_TXP_COB(x)		(((x) << PAS_MAC_CFG_TXP_COB_S) & \
					 PAS_MAC_CFG_TXP_COB_M)
#define PAS_MAC_CFG_TXP_TIFT_M		0x00000f00
#define PAS_MAC_CFG_TXP_TIFT_S		8
#define PAS_MAC_CFG_TXP_TIFT(x)		(((x) << PAS_MAC_CFG_TXP_TIFT_S) & \
					 PAS_MAC_CFG_TXP_TIFT_M)
#define PAS_MAC_CFG_TXP_TIFG_M		0x000000ff
#define PAS_MAC_CFG_TXP_TIFG_S		0
#define PAS_MAC_CFG_TXP_TIFG(x)		(((x) << PAS_MAC_CFG_TXP_TIFG_S) & \
					 PAS_MAC_CFG_TXP_TIFG_M)

#define PAS_MAC_IPC_CHNL_DCHNO_M	0x003f0000
#define PAS_MAC_IPC_CHNL_DCHNO_S	16
#define PAS_MAC_IPC_CHNL_DCHNO(x)	(((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \
					 PAS_MAC_IPC_CHNL_DCHNO_M)
#define PAS_MAC_IPC_CHNL_BCH_M		0x0000003f
#define PAS_MAC_IPC_CHNL_BCH_S		0
#define PAS_MAC_IPC_CHNL_BCH(x)		(((x) << PAS_MAC_IPC_CHNL_BCH_S) & \
					 PAS_MAC_IPC_CHNL_BCH_M)

#endif /* PASEMI_MAC_H */
Commit	Line	Data
f5cd7872 OJ	1	/*
	2	* Copyright (C) 2006 PA Semi, Inc
	3	*
	4	* Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
	5	* hardware register layouts.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
	21	#ifndef PASEMI_MAC_H
	22	#define PASEMI_MAC_H
	23
	24	#include <linux/ethtool.h>
	25	#include <linux/netdevice.h>
	26	#include <linux/spinlock.h>
bb6e9590	27	#include <linux/phy.h>
f5cd7872	28
28ae79f5 OJ	29	#define MAX_LRO_DESCRIPTORS 8
28ae79f5 OJ	30
f5cd7872	31	struct pasemi_mac_txring {
34c20624	32	struct pasemi_dmachan chan; /* Must be first */
f5cd7872	33	spinlock_t lock;
f5cd7872	34	unsigned int size;
021fa22e	35	unsigned int next_to_fill;
f5cd7872	36	unsigned int next_to_clean;
fc9e4d2a	37	struct pasemi_mac_buffer *ring_info;
72b05b99	38	struct pasemi_mac mac; / Needed in intr handler */
61cec3bd	39	struct timer_list clean_timer;
f5cd7872 OJ	40	};
	41
	42	struct pasemi_mac_rxring {
34c20624	43	struct pasemi_dmachan chan; /* Must be first */
f5cd7872	44	spinlock_t lock;
f5cd7872 OJ	45	u64 buffers; / RX interface buffer ring */
	46	dma_addr_t buf_dma;
	47	unsigned int size;
	48	unsigned int next_to_fill;
	49	unsigned int next_to_clean;
fc9e4d2a	50	struct pasemi_mac_buffer *ring_info;
72b05b99	51	struct pasemi_mac mac; / Needed in intr handler */
f5cd7872 OJ	52	};
	53
	54	struct pasemi_mac {
	55	struct net_device *netdev;
	56	struct pci_dev *pdev;
	57	struct pci_dev *dma_pdev;
	58	struct pci_dev *iob_pdev;
bb6e9590	59	struct phy_device *phydev;
bea3348e	60	struct napi_struct napi;
f5cd7872	61
f5cd7872 OJ	62	u8 type;
	63	#define MAC_TYPE_GMAC 1
	64	#define MAC_TYPE_XAUI 2
72b05b99	65	u32 dma_if;
f5cd7872 OJ	66
	67	u8 mac_addr[6];
	68
28ae79f5 OJ	69	struct net_lro_mgr lro_mgr;
28ae79f5 OJ	70	struct net_lro_desc lro_desc[MAX_LRO_DESCRIPTORS];
f5cd7872	71	struct timer_list rxtimer;
28ae79f5	72	unsigned int lro_max_aggr;
f5cd7872 OJ	73
	74	struct pasemi_mac_txring *tx;
	75	struct pasemi_mac_rxring *rx;
72b05b99 OJ	76	char tx_irq_name[10]; /* "eth%d tx" */
72b05b99 OJ	77	char rx_irq_name[10]; /* "eth%d rx" */
bb6e9590 OJ	78	int link;
	79	int speed;
	80	int duplex;
ceb51361 OJ	81
ceb51361 OJ	82	unsigned int msg_enable;
bb6e9590	83	char phy_id[BUS_ID_SIZE];
f5cd7872 OJ	84	};
f5cd7872 OJ	85
fc9e4d2a	86	/* Software status descriptor (ring_info) */
f5cd7872 OJ	87	struct pasemi_mac_buffer {
	88	struct sk_buff *skb;
	89	dma_addr_t dma;
	90	};
	91
	92
40afa531 OJ	93	/* PCI register offsets and formats */
40afa531 OJ	94
f5cd7872	95
f5cd7872	96	/* MAC CFG register offsets */
f5cd7872 OJ	97	enum {
	98	PAS_MAC_CFG_PCFG = 0x80,
	99	PAS_MAC_CFG_TXP = 0x98,
	100	PAS_MAC_IPC_CHNL = 0x208,
	101	};
	102
	103	/* MAC CFG register fields */
	104	#define PAS_MAC_CFG_PCFG_PE 0x80000000
	105	#define PAS_MAC_CFG_PCFG_CE 0x40000000
	106	#define PAS_MAC_CFG_PCFG_BU 0x20000000
	107	#define PAS_MAC_CFG_PCFG_TT 0x10000000
	108	#define PAS_MAC_CFG_PCFG_TSR_M 0x0c000000
	109	#define PAS_MAC_CFG_PCFG_TSR_10M 0x00000000
	110	#define PAS_MAC_CFG_PCFG_TSR_100M 0x04000000
	111	#define PAS_MAC_CFG_PCFG_TSR_1G 0x08000000
	112	#define PAS_MAC_CFG_PCFG_TSR_10G 0x0c000000
	113	#define PAS_MAC_CFG_PCFG_T24 0x02000000
	114	#define PAS_MAC_CFG_PCFG_PR 0x01000000
	115	#define PAS_MAC_CFG_PCFG_CRO_M 0x00ff0000
	116	#define PAS_MAC_CFG_PCFG_CRO_S 16
	117	#define PAS_MAC_CFG_PCFG_IPO_M 0x0000ff00
	118	#define PAS_MAC_CFG_PCFG_IPO_S 8
	119	#define PAS_MAC_CFG_PCFG_S1 0x00000080
	120	#define PAS_MAC_CFG_PCFG_IO_M 0x00000060
	121	#define PAS_MAC_CFG_PCFG_IO_MAC 0x00000000
	122	#define PAS_MAC_CFG_PCFG_IO_OFF 0x00000020
	123	#define PAS_MAC_CFG_PCFG_IO_IND_ETH 0x00000040
	124	#define PAS_MAC_CFG_PCFG_IO_IND_IP 0x00000060
	125	#define PAS_MAC_CFG_PCFG_LP 0x00000010
	126	#define PAS_MAC_CFG_PCFG_TS 0x00000008
	127	#define PAS_MAC_CFG_PCFG_HD 0x00000004
	128	#define PAS_MAC_CFG_PCFG_SPD_M 0x00000003
	129	#define PAS_MAC_CFG_PCFG_SPD_10M 0x00000000
	130	#define PAS_MAC_CFG_PCFG_SPD_100M 0x00000001
	131	#define PAS_MAC_CFG_PCFG_SPD_1G 0x00000002
	132	#define PAS_MAC_CFG_PCFG_SPD_10G 0x00000003
	133	#define PAS_MAC_CFG_TXP_FCF 0x01000000
	134	#define PAS_MAC_CFG_TXP_FCE 0x00800000
	135	#define PAS_MAC_CFG_TXP_FC 0x00400000
	136	#define PAS_MAC_CFG_TXP_FPC_M 0x00300000
	137	#define PAS_MAC_CFG_TXP_FPC_S 20
	138	#define PAS_MAC_CFG_TXP_FPC(x) (((x) << PAS_MAC_CFG_TXP_FPC_S) & \
	139	PAS_MAC_CFG_TXP_FPC_M)
	140	#define PAS_MAC_CFG_TXP_RT 0x00080000
	141	#define PAS_MAC_CFG_TXP_BL 0x00040000
	142	#define PAS_MAC_CFG_TXP_SL_M 0x00030000
	143	#define PAS_MAC_CFG_TXP_SL_S 16
	144	#define PAS_MAC_CFG_TXP_SL(x) (((x) << PAS_MAC_CFG_TXP_SL_S) & \
	145	PAS_MAC_CFG_TXP_SL_M)
	146	#define PAS_MAC_CFG_TXP_COB_M 0x0000f000
	147	#define PAS_MAC_CFG_TXP_COB_S 12
	148	#define PAS_MAC_CFG_TXP_COB(x) (((x) << PAS_MAC_CFG_TXP_COB_S) & \
	149	PAS_MAC_CFG_TXP_COB_M)
	150	#define PAS_MAC_CFG_TXP_TIFT_M 0x00000f00
	151	#define PAS_MAC_CFG_TXP_TIFT_S 8
	152	#define PAS_MAC_CFG_TXP_TIFT(x) (((x) << PAS_MAC_CFG_TXP_TIFT_S) & \
	153	PAS_MAC_CFG_TXP_TIFT_M)
	154	#define PAS_MAC_CFG_TXP_TIFG_M 0x000000ff
	155	#define PAS_MAC_CFG_TXP_TIFG_S 0
	156	#define PAS_MAC_CFG_TXP_TIFG(x) (((x) << PAS_MAC_CFG_TXP_TIFG_S) & \
	157	PAS_MAC_CFG_TXP_TIFG_M)
	158
	159	#define PAS_MAC_IPC_CHNL_DCHNO_M 0x003f0000
	160	#define PAS_MAC_IPC_CHNL_DCHNO_S 16
161	#define PAS_MAC_IPC_CHNL_DCHNO(x) (((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \
162	PAS_MAC_IPC_CHNL_DCHNO_M)
163	#define PAS_MAC_IPC_CHNL_BCH_M 0x0000003f
164	#define PAS_MAC_IPC_CHNL_BCH_S 0
165	#define PAS_MAC_IPC_CHNL_BCH(x) (((x) << PAS_MAC_IPC_CHNL_BCH_S) & \
166	PAS_MAC_IPC_CHNL_BCH_M)
167
f5cd7872	168	#endif /* PASEMI_MAC_H */