projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
pch_gbe: added the process of FIFO over run error
[deliverable/linux.git] / drivers / net / pch_gbe / pch_gbe_main.c
CommitLineData
77555ee7
MO		 1/*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
a1dcfcb7 3 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
77555ee7
MO		 4 *
5 * This code was derived from the Intel e1000e Linux driver.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21#include "pch_gbe.h"
22#include "pch_gbe_api.h"
23
24#define DRV_VERSION "1.00"
25const char pch_driver_version[] = DRV_VERSION;
26
27#define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802 /* Pci device ID */
28#define PCH_GBE_MAR_ENTRIES 16
29#define PCH_GBE_SHORT_PKT 64
30#define DSC_INIT16 0xC000
31#define PCH_GBE_DMA_ALIGN 0
ac096642 32#define PCH_GBE_DMA_PADDING 2
77555ee7
MO		 33#define PCH_GBE_WATCHDOG_PERIOD (1 * HZ) /* watchdog time */
34#define PCH_GBE_COPYBREAK_DEFAULT 256
35#define PCH_GBE_PCI_BAR 1
124d770a 36#define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */
77555ee7 37
b0e6baf5
T		 38/* Macros for ML7223 */
39#define PCI_VENDOR_ID_ROHM 0x10db
40#define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013
41
77555ee7
MO		 42#define PCH_GBE_TX_WEIGHT 64
43#define PCH_GBE_RX_WEIGHT 64
44#define PCH_GBE_RX_BUFFER_WRITE 16
45
46/* Initialize the wake-on-LAN settings */
47#define PCH_GBE_WL_INIT_SETTING (PCH_GBE_WLC_MP)
48
49#define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
50 PCH_GBE_CHIP_TYPE_INTERNAL | \
ce3dad0f 51 PCH_GBE_RGMII_MODE_RGMII \
77555ee7
MO		 52 )
53
54/* Ethertype field values */
124d770a 55#define PCH_GBE_MAX_RX_BUFFER_SIZE 0x2880
77555ee7
MO		 56#define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318
57#define PCH_GBE_FRAME_SIZE_2048 2048
58#define PCH_GBE_FRAME_SIZE_4096 4096
59#define PCH_GBE_FRAME_SIZE_8192 8192
60
61#define PCH_GBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
62#define PCH_GBE_RX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
63#define PCH_GBE_TX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
64#define PCH_GBE_DESC_UNUSED(R) \
65 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
66 (R)->next_to_clean - (R)->next_to_use - 1)
67
68/* Pause packet value */
69#define PCH_GBE_PAUSE_PKT1_VALUE 0x00C28001
70#define PCH_GBE_PAUSE_PKT2_VALUE 0x00000100
71#define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888
72#define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF
73
74#define PCH_GBE_ETH_ALEN 6
75
76/* This defines the bits that are set in the Interrupt Mask
77 * Set/Read Register. Each bit is documented below:
78 * o RXT0 = Receiver Timer Interrupt (ring 0)
79 * o TXDW = Transmit Descriptor Written Back
80 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
81 * o RXSEQ = Receive Sequence Error
82 * o LSC = Link Status Change
83 */
84#define PCH_GBE_INT_ENABLE_MASK ( \
85 PCH_GBE_INT_RX_DMA_CMPLT | \
86 PCH_GBE_INT_RX_DSC_EMP | \
124d770a 87 PCH_GBE_INT_RX_FIFO_ERR | \
77555ee7
MO		 88 PCH_GBE_INT_WOL_DET | \
89 PCH_GBE_INT_TX_CMPLT \
90 )
91
124d770a 92#define PCH_GBE_INT_DISABLE_ALL 0
77555ee7
MO		 93
94static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
95
191cc687 96static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
97static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
98 int data);
98200ec2
TO		 99
100inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
101{
102 iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
103}
104
77555ee7
MO		 105/**
106 * pch_gbe_mac_read_mac_addr - Read MAC address
107 * @hw: Pointer to the HW structure
108 * Returns
109 * 0: Successful.
110 */
111s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
112{
113 u32 adr1a, adr1b;
114
115 adr1a = ioread32(&hw->reg->mac_adr[0].high);
116 adr1b = ioread32(&hw->reg->mac_adr[0].low);
117
118 hw->mac.addr[0] = (u8)(adr1a & 0xFF);
119 hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
120 hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
121 hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
122 hw->mac.addr[4] = (u8)(adr1b & 0xFF);
123 hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
124
125 pr_debug("hw->mac.addr : %pM\n", hw->mac.addr);
126 return 0;
127}
128
129/**
130 * pch_gbe_wait_clr_bit - Wait to clear a bit
131 * @reg: Pointer of register
132 * @busy: Busy bit
133 */
191cc687 134static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
77555ee7
MO		 135{
136 u32 tmp;
137 /* wait busy */
138 tmp = 1000;
139 while ((ioread32(reg) & bit) && --tmp)
140 cpu_relax();
141 if (!tmp)
142 pr_err("Error: busy bit is not cleared\n");
143}
124d770a
TO		 144
145/**
146 * pch_gbe_wait_clr_bit_irq - Wait to clear a bit for interrupt context
147 * @reg: Pointer of register
148 * @busy: Busy bit
149 */
150static int pch_gbe_wait_clr_bit_irq(void *reg, u32 bit)
151{
152 u32 tmp;
153 int ret = -1;
154 /* wait busy */
155 tmp = 20;
156 while ((ioread32(reg) & bit) && --tmp)
157 udelay(5);
158 if (!tmp)
159 pr_err("Error: busy bit is not cleared\n");
160 else
161 ret = 0;
162 return ret;
163}
164
77555ee7
MO		 165/**
166 * pch_gbe_mac_mar_set - Set MAC address register
167 * @hw: Pointer to the HW structure
168 * @addr: Pointer to the MAC address
169 * @index: MAC address array register
170 */
191cc687 171static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
77555ee7
MO		 172{
173 u32 mar_low, mar_high, adrmask;
174
175 pr_debug("index : 0x%x\n", index);
176
177 /*
178 * HW expects these in little endian so we reverse the byte order
179 * from network order (big endian) to little endian
180 */
181 mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
182 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
183 mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
184 /* Stop the MAC Address of index. */
185 adrmask = ioread32(&hw->reg->ADDR_MASK);
186 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
187 /* wait busy */
188 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
189 /* Set the MAC address to the MAC address 1A/1B register */
190 iowrite32(mar_high, &hw->reg->mac_adr[index].high);
191 iowrite32(mar_low, &hw->reg->mac_adr[index].low);
192 /* Start the MAC address of index */
193 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
194 /* wait busy */
195 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
196}
197
198/**
199 * pch_gbe_mac_reset_hw - Reset hardware
200 * @hw: Pointer to the HW structure
201 */
191cc687 202static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
77555ee7
MO		 203{
204 /* Read the MAC address. and store to the private data */
205 pch_gbe_mac_read_mac_addr(hw);
206 iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
207#ifdef PCH_GBE_MAC_IFOP_RGMII
208 iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
209#endif
210 pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
211 /* Setup the receive address */
212 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
213 return;
214}
215
124d770a
TO		 216static void pch_gbe_mac_reset_rx(struct pch_gbe_hw *hw)
217{
218 /* Read the MAC address. and store to the private data */
219 pch_gbe_mac_read_mac_addr(hw);
220 iowrite32(PCH_GBE_RX_RST, &hw->reg->RESET);
221 pch_gbe_wait_clr_bit_irq(&hw->reg->RESET, PCH_GBE_RX_RST);
222 /* Setup the MAC address */
223 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
224 return;
225}
226
77555ee7
MO		 227/**
228 * pch_gbe_mac_init_rx_addrs - Initialize receive address's
229 * @hw: Pointer to the HW structure
230 * @mar_count: Receive address registers
231 */
191cc687 232static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
77555ee7
MO		 233{
234 u32 i;
235
236 /* Setup the receive address */
237 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
238
239 /* Zero out the other receive addresses */
240 for (i = 1; i < mar_count; i++) {
241 iowrite32(0, &hw->reg->mac_adr[i].high);
242 iowrite32(0, &hw->reg->mac_adr[i].low);
243 }
244 iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
245 /* wait busy */
246 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
247}
248
249
250/**
251 * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
252 * @hw: Pointer to the HW structure
253 * @mc_addr_list: Array of multicast addresses to program
254 * @mc_addr_count: Number of multicast addresses to program
255 * @mar_used_count: The first MAC Address register free to program
256 * @mar_total_num: Total number of supported MAC Address Registers
257 */
191cc687 258static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
259 u8 *mc_addr_list, u32 mc_addr_count,
260 u32 mar_used_count, u32 mar_total_num)
77555ee7
MO		 261{
262 u32 i, adrmask;
263
264 /* Load the first set of multicast addresses into the exact
265 * filters (RAR). If there are not enough to fill the RAR
266 * array, clear the filters.
267 */
268 for (i = mar_used_count; i < mar_total_num; i++) {
269 if (mc_addr_count) {
270 pch_gbe_mac_mar_set(hw, mc_addr_list, i);
271 mc_addr_count--;
272 mc_addr_list += PCH_GBE_ETH_ALEN;
273 } else {
274 /* Clear MAC address mask */
275 adrmask = ioread32(&hw->reg->ADDR_MASK);
276 iowrite32((adrmask | (0x0001 << i)),
277 &hw->reg->ADDR_MASK);
278 /* wait busy */
279 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
280 /* Clear MAC address */
281 iowrite32(0, &hw->reg->mac_adr[i].high);
282 iowrite32(0, &hw->reg->mac_adr[i].low);
283 }
284 }
285}
286
287/**
288 * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
289 * @hw: Pointer to the HW structure
290 * Returns
291 * 0: Successful.
292 * Negative value: Failed.
293 */
294s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
295{
296 struct pch_gbe_mac_info *mac = &hw->mac;
297 u32 rx_fctrl;
298
299 pr_debug("mac->fc = %u\n", mac->fc);
300
301 rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
302
303 switch (mac->fc) {
304 case PCH_GBE_FC_NONE:
305 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
306 mac->tx_fc_enable = false;
307 break;
308 case PCH_GBE_FC_RX_PAUSE:
309 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
310 mac->tx_fc_enable = false;
311 break;
312 case PCH_GBE_FC_TX_PAUSE:
313 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
314 mac->tx_fc_enable = true;
315 break;
316 case PCH_GBE_FC_FULL:
317 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
318 mac->tx_fc_enable = true;
319 break;
320 default:
321 pr_err("Flow control param set incorrectly\n");
322 return -EINVAL;
323 }
324 if (mac->link_duplex == DUPLEX_HALF)
325 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
326 iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
327 pr_debug("RX_FCTRL reg : 0x%08x mac->tx_fc_enable : %d\n",
328 ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
329 return 0;
330}
331
332/**
333 * pch_gbe_mac_set_wol_event - Set wake-on-lan event
334 * @hw: Pointer to the HW structure
335 * @wu_evt: Wake up event
336 */
191cc687 337static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
77555ee7
MO		 338{
339 u32 addr_mask;
340
341 pr_debug("wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n",
342 wu_evt, ioread32(&hw->reg->ADDR_MASK));
343
344 if (wu_evt) {
345 /* Set Wake-On-Lan address mask */
346 addr_mask = ioread32(&hw->reg->ADDR_MASK);
347 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
348 /* wait busy */
349 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
350 iowrite32(0, &hw->reg->WOL_ST);
351 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
352 iowrite32(0x02, &hw->reg->TCPIP_ACC);
353 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
354 } else {
355 iowrite32(0, &hw->reg->WOL_CTRL);
356 iowrite32(0, &hw->reg->WOL_ST);
357 }
358 return;
359}
360
361/**
362 * pch_gbe_mac_ctrl_miim - Control MIIM interface
363 * @hw: Pointer to the HW structure
364 * @addr: Address of PHY
365 * @dir: Operetion. (Write or Read)
366 * @reg: Access register of PHY
367 * @data: Write data.
368 *
369 * Returns: Read date.
370 */
371u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
372 u16 data)
373{
374 u32 data_out = 0;
375 unsigned int i;
376 unsigned long flags;
377
378 spin_lock_irqsave(&hw->miim_lock, flags);
379
380 for (i = 100; i; --i) {
381 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
382 break;
383 udelay(20);
384 }
385 if (i == 0) {
386 pr_err("pch-gbe.miim won't go Ready\n");
387 spin_unlock_irqrestore(&hw->miim_lock, flags);
388 return 0; /* No way to indicate timeout error */
389 }
390 iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
391 (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
392 dir | data), &hw->reg->MIIM);
393 for (i = 0; i < 100; i++) {
394 udelay(20);
395 data_out = ioread32(&hw->reg->MIIM);
396 if ((data_out & PCH_GBE_MIIM_OPER_READY))
397 break;
398 }
399 spin_unlock_irqrestore(&hw->miim_lock, flags);
400
401 pr_debug("PHY %s: reg=%d, data=0x%04X\n",
402 dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
403 dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
404 return (u16) data_out;
405}
406
407/**
408 * pch_gbe_mac_set_pause_packet - Set pause packet
409 * @hw: Pointer to the HW structure
410 */
191cc687 411static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
77555ee7
MO		 412{
413 unsigned long tmp2, tmp3;
414
415 /* Set Pause packet */
416 tmp2 = hw->mac.addr[1];
417 tmp2 = (tmp2 << 8) | hw->mac.addr[0];
418 tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
419
420 tmp3 = hw->mac.addr[5];
421 tmp3 = (tmp3 << 8) | hw->mac.addr[4];
422 tmp3 = (tmp3 << 8) | hw->mac.addr[3];
423 tmp3 = (tmp3 << 8) | hw->mac.addr[2];
424
425 iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
426 iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
427 iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
428 iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
429 iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
430
431 /* Transmit Pause Packet */
432 iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
433
434 pr_debug("PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
435 ioread32(&hw->reg->PAUSE_PKT1), ioread32(&hw->reg->PAUSE_PKT2),
436 ioread32(&hw->reg->PAUSE_PKT3), ioread32(&hw->reg->PAUSE_PKT4),
437 ioread32(&hw->reg->PAUSE_PKT5));
438
439 return;
440}
441
442
443/**
444 * pch_gbe_alloc_queues - Allocate memory for all rings
445 * @adapter: Board private structure to initialize
446 * Returns
447 * 0: Successfully
448 * Negative value: Failed
449 */
450static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
451{
452 int size;
453
454 size = (int)sizeof(struct pch_gbe_tx_ring);
455 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
456 if (!adapter->tx_ring)
457 return -ENOMEM;
458 size = (int)sizeof(struct pch_gbe_rx_ring);
459 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
460 if (!adapter->rx_ring) {
461 kfree(adapter->tx_ring);
462 return -ENOMEM;
463 }
464 return 0;
465}
466
467/**
468 * pch_gbe_init_stats - Initialize status
469 * @adapter: Board private structure to initialize
470 */
471static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
472{
473 memset(&adapter->stats, 0, sizeof(adapter->stats));
474 return;
475}
476
477/**
478 * pch_gbe_init_phy - Initialize PHY
479 * @adapter: Board private structure to initialize
480 * Returns
481 * 0: Successfully
482 * Negative value: Failed
483 */
484static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
485{
486 struct net_device *netdev = adapter->netdev;
487 u32 addr;
488 u16 bmcr, stat;
489
490 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
491 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
492 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
493 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
494 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
495 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
496 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
497 break;
498 }
499 adapter->hw.phy.addr = adapter->mii.phy_id;
500 pr_debug("phy_addr = %d\n", adapter->mii.phy_id);
501 if (addr == 32)
502 return -EAGAIN;
503 /* Selected the phy and isolate the rest */
504 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
505 if (addr != adapter->mii.phy_id) {
506 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
507 BMCR_ISOLATE);
508 } else {
509 bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
510 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
511 bmcr & ~BMCR_ISOLATE);
512 }
513 }
514
515 /* MII setup */
516 adapter->mii.phy_id_mask = 0x1F;
517 adapter->mii.reg_num_mask = 0x1F;
518 adapter->mii.dev = adapter->netdev;
519 adapter->mii.mdio_read = pch_gbe_mdio_read;
520 adapter->mii.mdio_write = pch_gbe_mdio_write;
521 adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
522 return 0;
523}
524
525/**
526 * pch_gbe_mdio_read - The read function for mii
527 * @netdev: Network interface device structure
528 * @addr: Phy ID
529 * @reg: Access location
530 * Returns
531 * 0: Successfully
532 * Negative value: Failed
533 */
191cc687 534static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
77555ee7
MO		 535{
536 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
537 struct pch_gbe_hw *hw = &adapter->hw;
538
539 return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
540 (u16) 0);
541}
542
543/**
544 * pch_gbe_mdio_write - The write function for mii
545 * @netdev: Network interface device structure
546 * @addr: Phy ID (not used)
547 * @reg: Access location
548 * @data: Write data
549 */
191cc687 550static void pch_gbe_mdio_write(struct net_device *netdev,
551 int addr, int reg, int data)
77555ee7
MO		 552{
553 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
554 struct pch_gbe_hw *hw = &adapter->hw;
555
556 pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
557}
558
559/**
560 * pch_gbe_reset_task - Reset processing at the time of transmission timeout
561 * @work: Pointer of board private structure
562 */
563static void pch_gbe_reset_task(struct work_struct *work)
564{
565 struct pch_gbe_adapter *adapter;
566 adapter = container_of(work, struct pch_gbe_adapter, reset_task);
567
75d1a752 568 rtnl_lock();
77555ee7 569 pch_gbe_reinit_locked(adapter);
75d1a752 570 rtnl_unlock();
77555ee7
MO		 571}
572
573/**
574 * pch_gbe_reinit_locked- Re-initialization
575 * @adapter: Board private structure
576 */
577void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
578{
75d1a752
TO		 579 pch_gbe_down(adapter);
580 pch_gbe_up(adapter);
77555ee7
MO		 581}
582
583/**
584 * pch_gbe_reset - Reset GbE
585 * @adapter: Board private structure
586 */
587void pch_gbe_reset(struct pch_gbe_adapter *adapter)
588{
589 pch_gbe_mac_reset_hw(&adapter->hw);
590 /* Setup the receive address. */
591 pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
592 if (pch_gbe_hal_init_hw(&adapter->hw))
593 pr_err("Hardware Error\n");
594}
595
596/**
597 * pch_gbe_free_irq - Free an interrupt
598 * @adapter: Board private structure
599 */
600static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
601{
602 struct net_device *netdev = adapter->netdev;
603
604 free_irq(adapter->pdev->irq, netdev);
605 if (adapter->have_msi) {
606 pci_disable_msi(adapter->pdev);
607 pr_debug("call pci_disable_msi\n");
608 }
609}
610
611/**
612 * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
613 * @adapter: Board private structure
614 */
615static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
616{
617 struct pch_gbe_hw *hw = &adapter->hw;
618
619 atomic_inc(&adapter->irq_sem);
620 iowrite32(0, &hw->reg->INT_EN);
621 ioread32(&hw->reg->INT_ST);
622 synchronize_irq(adapter->pdev->irq);
623
624 pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
625}
626
627/**
628 * pch_gbe_irq_enable - Enable default interrupt generation settings
629 * @adapter: Board private structure
630 */
631static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
632{
633 struct pch_gbe_hw *hw = &adapter->hw;
634
635 if (likely(atomic_dec_and_test(&adapter->irq_sem)))
636 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
637 ioread32(&hw->reg->INT_ST);
638 pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
639}
640
641
642
643/**
644 * pch_gbe_setup_tctl - configure the Transmit control registers
645 * @adapter: Board private structure
646 */
647static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
648{
649 struct pch_gbe_hw *hw = &adapter->hw;
650 u32 tx_mode, tcpip;
651
652 tx_mode = PCH_GBE_TM_LONG_PKT |
653 PCH_GBE_TM_ST_AND_FD |
654 PCH_GBE_TM_SHORT_PKT |
655 PCH_GBE_TM_TH_TX_STRT_8 |
656 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
657
658 iowrite32(tx_mode, &hw->reg->TX_MODE);
659
660 tcpip = ioread32(&hw->reg->TCPIP_ACC);
661 tcpip |= PCH_GBE_TX_TCPIPACC_EN;
662 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
663 return;
664}
665
666/**
667 * pch_gbe_configure_tx - Configure Transmit Unit after Reset
668 * @adapter: Board private structure
669 */
670static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
671{
672 struct pch_gbe_hw *hw = &adapter->hw;
673 u32 tdba, tdlen, dctrl;
674
675 pr_debug("dma addr = 0x%08llx size = 0x%08x\n",
676 (unsigned long long)adapter->tx_ring->dma,
677 adapter->tx_ring->size);
678
679 /* Setup the HW Tx Head and Tail descriptor pointers */
680 tdba = adapter->tx_ring->dma;
681 tdlen = adapter->tx_ring->size - 0x10;
682 iowrite32(tdba, &hw->reg->TX_DSC_BASE);
683 iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
684 iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
685
686 /* Enables Transmission DMA */
687 dctrl = ioread32(&hw->reg->DMA_CTRL);
688 dctrl |= PCH_GBE_TX_DMA_EN;
689 iowrite32(dctrl, &hw->reg->DMA_CTRL);
690}
691
692/**
693 * pch_gbe_setup_rctl - Configure the receive control registers
694 * @adapter: Board private structure
695 */
696static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
697{
756a6b03 698 struct net_device *netdev = adapter->netdev;
77555ee7
MO		 699 struct pch_gbe_hw *hw = &adapter->hw;
700 u32 rx_mode, tcpip;
701
702 rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
703 PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
704
705 iowrite32(rx_mode, &hw->reg->RX_MODE);
706
707 tcpip = ioread32(&hw->reg->TCPIP_ACC);
708
124d770a
TO		 709 tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
710 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
77555ee7
MO		 711 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
712 return;
713}
714
715/**
716 * pch_gbe_configure_rx - Configure Receive Unit after Reset
717 * @adapter: Board private structure
718 */
719static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
720{
721 struct pch_gbe_hw *hw = &adapter->hw;
722 u32 rdba, rdlen, rctl, rxdma;
723
724 pr_debug("dma adr = 0x%08llx size = 0x%08x\n",
725 (unsigned long long)adapter->rx_ring->dma,
726 adapter->rx_ring->size);
727
728 pch_gbe_mac_force_mac_fc(hw);
729
730 /* Disables Receive MAC */
731 rctl = ioread32(&hw->reg->MAC_RX_EN);
732 iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
733
734 /* Disables Receive DMA */
735 rxdma = ioread32(&hw->reg->DMA_CTRL);
736 rxdma &= ~PCH_GBE_RX_DMA_EN;
737 iowrite32(rxdma, &hw->reg->DMA_CTRL);
738
739 pr_debug("MAC_RX_EN reg = 0x%08x DMA_CTRL reg = 0x%08x\n",
740 ioread32(&hw->reg->MAC_RX_EN),
741 ioread32(&hw->reg->DMA_CTRL));
742
743 /* Setup the HW Rx Head and Tail Descriptor Pointers and
744 * the Base and Length of the Rx Descriptor Ring */
745 rdba = adapter->rx_ring->dma;
746 rdlen = adapter->rx_ring->size - 0x10;
747 iowrite32(rdba, &hw->reg->RX_DSC_BASE);
748 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
749 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
77555ee7
MO		 750}
751
752/**
753 * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
754 * @adapter: Board private structure
755 * @buffer_info: Buffer information structure
756 */
757static void pch_gbe_unmap_and_free_tx_resource(
758 struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
759{
760 if (buffer_info->mapped) {
761 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
762 buffer_info->length, DMA_TO_DEVICE);
763 buffer_info->mapped = false;
764 }
765 if (buffer_info->skb) {
766 dev_kfree_skb_any(buffer_info->skb);
767 buffer_info->skb = NULL;
768 }
769}
770
771/**
772 * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
773 * @adapter: Board private structure
774 * @buffer_info: Buffer information structure
775 */
776static void pch_gbe_unmap_and_free_rx_resource(
777 struct pch_gbe_adapter *adapter,
778 struct pch_gbe_buffer *buffer_info)
779{
780 if (buffer_info->mapped) {
781 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
782 buffer_info->length, DMA_FROM_DEVICE);
783 buffer_info->mapped = false;
784 }
785 if (buffer_info->skb) {
786 dev_kfree_skb_any(buffer_info->skb);
787 buffer_info->skb = NULL;
788 }
789}
790
791/**
792 * pch_gbe_clean_tx_ring - Free Tx Buffers
793 * @adapter: Board private structure
794 * @tx_ring: Ring to be cleaned
795 */
796static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
797 struct pch_gbe_tx_ring *tx_ring)
798{
799 struct pch_gbe_hw *hw = &adapter->hw;
800 struct pch_gbe_buffer *buffer_info;
801 unsigned long size;
802 unsigned int i;
803
804 /* Free all the Tx ring sk_buffs */
805 for (i = 0; i < tx_ring->count; i++) {
806 buffer_info = &tx_ring->buffer_info[i];
807 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
808 }
809 pr_debug("call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
810
811 size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
812 memset(tx_ring->buffer_info, 0, size);
813
814 /* Zero out the descriptor ring */
815 memset(tx_ring->desc, 0, tx_ring->size);
816 tx_ring->next_to_use = 0;
817 tx_ring->next_to_clean = 0;
818 iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
819 iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
820}
821
822/**
823 * pch_gbe_clean_rx_ring - Free Rx Buffers
824 * @adapter: Board private structure
825 * @rx_ring: Ring to free buffers from
826 */
827static void
828pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
829 struct pch_gbe_rx_ring *rx_ring)
830{
831 struct pch_gbe_hw *hw = &adapter->hw;
832 struct pch_gbe_buffer *buffer_info;
833 unsigned long size;
834 unsigned int i;
835
836 /* Free all the Rx ring sk_buffs */
837 for (i = 0; i < rx_ring->count; i++) {
838 buffer_info = &rx_ring->buffer_info[i];
839 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
840 }
841 pr_debug("call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
842 size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
843 memset(rx_ring->buffer_info, 0, size);
844
845 /* Zero out the descriptor ring */
846 memset(rx_ring->desc, 0, rx_ring->size);
847 rx_ring->next_to_clean = 0;
848 rx_ring->next_to_use = 0;
849 iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
850 iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
851}
852
853static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
854 u16 duplex)
855{
856 struct pch_gbe_hw *hw = &adapter->hw;
857 unsigned long rgmii = 0;
858
859 /* Set the RGMII control. */
860#ifdef PCH_GBE_MAC_IFOP_RGMII
861 switch (speed) {
862 case SPEED_10:
863 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
864 PCH_GBE_MAC_RGMII_CTRL_SETTING);
865 break;
866 case SPEED_100:
867 rgmii = (PCH_GBE_RGMII_RATE_25M |
868 PCH_GBE_MAC_RGMII_CTRL_SETTING);
869 break;
870 case SPEED_1000:
871 rgmii = (PCH_GBE_RGMII_RATE_125M |
872 PCH_GBE_MAC_RGMII_CTRL_SETTING);
873 break;
874 }
875 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
876#else /* GMII */
877 rgmii = 0;
878 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
879#endif
880}
881static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
882 u16 duplex)
883{
884 struct net_device *netdev = adapter->netdev;
885 struct pch_gbe_hw *hw = &adapter->hw;
886 unsigned long mode = 0;
887
888 /* Set the communication mode */
889 switch (speed) {
890 case SPEED_10:
891 mode = PCH_GBE_MODE_MII_ETHER;
892 netdev->tx_queue_len = 10;
893 break;
894 case SPEED_100:
895 mode = PCH_GBE_MODE_MII_ETHER;
896 netdev->tx_queue_len = 100;
897 break;
898 case SPEED_1000:
899 mode = PCH_GBE_MODE_GMII_ETHER;
900 break;
901 }
902 if (duplex == DUPLEX_FULL)
903 mode |= PCH_GBE_MODE_FULL_DUPLEX;
904 else
905 mode |= PCH_GBE_MODE_HALF_DUPLEX;
906 iowrite32(mode, &hw->reg->MODE);
907}
908
909/**
910 * pch_gbe_watchdog - Watchdog process
911 * @data: Board private structure
912 */
913static void pch_gbe_watchdog(unsigned long data)
914{
915 struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data;
916 struct net_device *netdev = adapter->netdev;
917 struct pch_gbe_hw *hw = &adapter->hw;
77555ee7
MO		 918
919 pr_debug("right now = %ld\n", jiffies);
920
921 pch_gbe_update_stats(adapter);
922 if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
8ae6daca 923 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
77555ee7
MO		 924 netdev->tx_queue_len = adapter->tx_queue_len;
925 /* mii library handles link maintenance tasks */
926 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
927 pr_err("ethtool get setting Error\n");
928 mod_timer(&adapter->watchdog_timer,
929 round_jiffies(jiffies +
930 PCH_GBE_WATCHDOG_PERIOD));
931 return;
932 }
8ae6daca 933 hw->mac.link_speed = ethtool_cmd_speed(&cmd);
77555ee7
MO		 934 hw->mac.link_duplex = cmd.duplex;
935 /* Set the RGMII control. */
936 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
937 hw->mac.link_duplex);
938 /* Set the communication mode */
939 pch_gbe_set_mode(adapter, hw->mac.link_speed,
940 hw->mac.link_duplex);
941 netdev_dbg(netdev,
942 "Link is Up %d Mbps %s-Duplex\n",
8ae6daca 943 hw->mac.link_speed,
77555ee7
MO		 944 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
945 netif_carrier_on(netdev);
946 netif_wake_queue(netdev);
947 } else if ((!mii_link_ok(&adapter->mii)) &&
948 (netif_carrier_ok(netdev))) {
949 netdev_dbg(netdev, "NIC Link is Down\n");
950 hw->mac.link_speed = SPEED_10;
951 hw->mac.link_duplex = DUPLEX_HALF;
952 netif_carrier_off(netdev);
953 netif_stop_queue(netdev);
954 }
955 mod_timer(&adapter->watchdog_timer,
956 round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
957}
958
959/**
960 * pch_gbe_tx_queue - Carry out queuing of the transmission data
961 * @adapter: Board private structure
962 * @tx_ring: Tx descriptor ring structure
963 * @skb: Sockt buffer structure
964 */
965static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
966 struct pch_gbe_tx_ring *tx_ring,
967 struct sk_buff *skb)
968{
969 struct pch_gbe_hw *hw = &adapter->hw;
970 struct pch_gbe_tx_desc *tx_desc;
971 struct pch_gbe_buffer *buffer_info;
972 struct sk_buff *tmp_skb;
973 unsigned int frame_ctrl;
974 unsigned int ring_num;
975 unsigned long flags;
976
977 /*-- Set frame control --*/
978 frame_ctrl = 0;
979 if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
980 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
756a6b03 981 if (skb->ip_summed == CHECKSUM_NONE)
77555ee7
MO		 982 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
983
984 /* Performs checksum processing */
985 /*
986 * It is because the hardware accelerator does not support a checksum,
987 * when the received data size is less than 64 bytes.
988 */
756a6b03 989 if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) {
77555ee7
MO		 990 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
991 PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
992 if (skb->protocol == htons(ETH_P_IP)) {
993 struct iphdr *iph = ip_hdr(skb);
994 unsigned int offset;
995 iph->check = 0;
996 iph->check = ip_fast_csum((u8 *) iph, iph->ihl);
997 offset = skb_transport_offset(skb);
998 if (iph->protocol == IPPROTO_TCP) {
999 skb->csum = 0;
1000 tcp_hdr(skb)->check = 0;
1001 skb->csum = skb_checksum(skb, offset,
1002 skb->len - offset, 0);
1003 tcp_hdr(skb)->check =
1004 csum_tcpudp_magic(iph->saddr,
1005 iph->daddr,
1006 skb->len - offset,
1007 IPPROTO_TCP,
1008 skb->csum);
1009 } else if (iph->protocol == IPPROTO_UDP) {
1010 skb->csum = 0;
1011 udp_hdr(skb)->check = 0;
1012 skb->csum =
1013 skb_checksum(skb, offset,
1014 skb->len - offset, 0);
1015 udp_hdr(skb)->check =
1016 csum_tcpudp_magic(iph->saddr,
1017 iph->daddr,
1018 skb->len - offset,
1019 IPPROTO_UDP,
1020 skb->csum);
1021 }
1022 }
1023 }
1024 spin_lock_irqsave(&tx_ring->tx_lock, flags);
1025 ring_num = tx_ring->next_to_use;
1026 if (unlikely((ring_num + 1) == tx_ring->count))
1027 tx_ring->next_to_use = 0;
1028 else
1029 tx_ring->next_to_use = ring_num + 1;
1030
1031 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1032 buffer_info = &tx_ring->buffer_info[ring_num];
1033 tmp_skb = buffer_info->skb;
1034
1035 /* [Header:14][payload] ---> [Header:14][paddong:2][payload] */
1036 memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1037 tmp_skb->data[ETH_HLEN] = 0x00;
1038 tmp_skb->data[ETH_HLEN + 1] = 0x00;
1039 tmp_skb->len = skb->len;
1040 memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1041 (skb->len - ETH_HLEN));
25985edc 1042 /*-- Set Buffer information --*/
77555ee7
MO		 1043 buffer_info->length = tmp_skb->len;
1044 buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1045 buffer_info->length,
1046 DMA_TO_DEVICE);
1047 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1048 pr_err("TX DMA map failed\n");
1049 buffer_info->dma = 0;
1050 buffer_info->time_stamp = 0;
1051 tx_ring->next_to_use = ring_num;
1052 return;
1053 }
1054 buffer_info->mapped = true;
1055 buffer_info->time_stamp = jiffies;
1056
1057 /*-- Set Tx descriptor --*/
1058 tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1059 tx_desc->buffer_addr = (buffer_info->dma);
1060 tx_desc->length = (tmp_skb->len);
1061 tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1062 tx_desc->tx_frame_ctrl = (frame_ctrl);
1063 tx_desc->gbec_status = (DSC_INIT16);
1064
1065 if (unlikely(++ring_num == tx_ring->count))
1066 ring_num = 0;
1067
1068 /* Update software pointer of TX descriptor */
1069 iowrite32(tx_ring->dma +
1070 (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1071 &hw->reg->TX_DSC_SW_P);
1072 dev_kfree_skb_any(skb);
1073}
1074
1075/**
1076 * pch_gbe_update_stats - Update the board statistics counters
1077 * @adapter: Board private structure
1078 */
1079void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1080{
1081 struct net_device *netdev = adapter->netdev;
1082 struct pci_dev *pdev = adapter->pdev;
1083 struct pch_gbe_hw_stats *stats = &adapter->stats;
1084 unsigned long flags;
1085
1086 /*
1087 * Prevent stats update while adapter is being reset, or if the pci
1088 * connection is down.
1089 */
1090 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1091 return;
1092
1093 spin_lock_irqsave(&adapter->stats_lock, flags);
1094
1095 /* Update device status "adapter->stats" */
1096 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1097 stats->tx_errors = stats->tx_length_errors +
1098 stats->tx_aborted_errors +
1099 stats->tx_carrier_errors + stats->tx_timeout_count;
1100
1101 /* Update network device status "adapter->net_stats" */
1102 netdev->stats.rx_packets = stats->rx_packets;
1103 netdev->stats.rx_bytes = stats->rx_bytes;
1104 netdev->stats.rx_dropped = stats->rx_dropped;
1105 netdev->stats.tx_packets = stats->tx_packets;
1106 netdev->stats.tx_bytes = stats->tx_bytes;
1107 netdev->stats.tx_dropped = stats->tx_dropped;
1108 /* Fill out the OS statistics structure */
1109 netdev->stats.multicast = stats->multicast;
1110 netdev->stats.collisions = stats->collisions;
1111 /* Rx Errors */
1112 netdev->stats.rx_errors = stats->rx_errors;
1113 netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1114 netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1115 /* Tx Errors */
1116 netdev->stats.tx_errors = stats->tx_errors;
1117 netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1118 netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1119
1120 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1121}
1122
124d770a
TO		 1123static void pch_gbe_stop_receive(struct pch_gbe_adapter *adapter)
1124{
1125 struct pch_gbe_hw *hw = &adapter->hw;
1126 u32 rxdma;
1127 u16 value;
1128 int ret;
1129
1130 /* Disable Receive DMA */
1131 rxdma = ioread32(&hw->reg->DMA_CTRL);
1132 rxdma &= ~PCH_GBE_RX_DMA_EN;
1133 iowrite32(rxdma, &hw->reg->DMA_CTRL);
1134 /* Wait Rx DMA BUS is IDLE */
1135 ret = pch_gbe_wait_clr_bit_irq(&hw->reg->RX_DMA_ST, PCH_GBE_IDLE_CHECK);
1136 if (ret) {
1137 /* Disable Bus master */
1138 pci_read_config_word(adapter->pdev, PCI_COMMAND, &value);
1139 value &= ~PCI_COMMAND_MASTER;
1140 pci_write_config_word(adapter->pdev, PCI_COMMAND, value);
1141 /* Stop Receive */
1142 pch_gbe_mac_reset_rx(hw);
1143 /* Enable Bus master */
1144 value |= PCI_COMMAND_MASTER;
1145 pci_write_config_word(adapter->pdev, PCI_COMMAND, value);
1146 } else {
1147 /* Stop Receive */
1148 pch_gbe_mac_reset_rx(hw);
1149 }
1150}
1151
5229d87e
TO		 1152static void pch_gbe_start_receive(struct pch_gbe_hw *hw)
1153{
1154 u32 rxdma;
1155
1156 /* Enables Receive DMA */
1157 rxdma = ioread32(&hw->reg->DMA_CTRL);
1158 rxdma |= PCH_GBE_RX_DMA_EN;
1159 iowrite32(rxdma, &hw->reg->DMA_CTRL);
1160 /* Enables Receive */
1161 iowrite32(PCH_GBE_MRE_MAC_RX_EN, &hw->reg->MAC_RX_EN);
1162 return;
1163}
1164
77555ee7
MO		 1165/**
1166 * pch_gbe_intr - Interrupt Handler
1167 * @irq: Interrupt number
1168 * @data: Pointer to a network interface device structure
1169 * Returns
1170 * - IRQ_HANDLED: Our interrupt
1171 * - IRQ_NONE: Not our interrupt
1172 */
1173static irqreturn_t pch_gbe_intr(int irq, void *data)
1174{
1175 struct net_device *netdev = data;
1176 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1177 struct pch_gbe_hw *hw = &adapter->hw;
1178 u32 int_st;
1179 u32 int_en;
1180
1181 /* Check request status */
1182 int_st = ioread32(&hw->reg->INT_ST);
1183 int_st = int_st & ioread32(&hw->reg->INT_EN);
1184 /* When request status is no interruption factor */
1185 if (unlikely(!int_st))
1186 return IRQ_NONE; /* Not our interrupt. End processing. */
1187 pr_debug("%s occur int_st = 0x%08x\n", __func__, int_st);
1188 if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1189 adapter->stats.intr_rx_frame_err_count++;
1190 if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
124d770a
TO		 1191 if (!adapter->rx_stop_flag) {
1192 adapter->stats.intr_rx_fifo_err_count++;
1193 pr_debug("Rx fifo over run\n");
1194 adapter->rx_stop_flag = true;
1195 int_en = ioread32(&hw->reg->INT_EN);
1196 iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR),
1197 &hw->reg->INT_EN);
1198 pch_gbe_stop_receive(adapter);
1199 }
77555ee7
MO		 1200 if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1201 adapter->stats.intr_rx_dma_err_count++;
1202 if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1203 adapter->stats.intr_tx_fifo_err_count++;
1204 if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1205 adapter->stats.intr_tx_dma_err_count++;
1206 if (int_st & PCH_GBE_INT_TCPIP_ERR)
1207 adapter->stats.intr_tcpip_err_count++;
1208 /* When Rx descriptor is empty */
1209 if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1210 adapter->stats.intr_rx_dsc_empty_count++;
124d770a 1211 pr_debug("Rx descriptor is empty\n");
77555ee7
MO		 1212 int_en = ioread32(&hw->reg->INT_EN);
1213 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1214 if (hw->mac.tx_fc_enable) {
1215 /* Set Pause packet */
1216 pch_gbe_mac_set_pause_packet(hw);
1217 }
1218 if ((int_en & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))
1219 == 0) {
1220 return IRQ_HANDLED;
1221 }
1222 }
1223
1224 /* When request status is Receive interruption */
1225 if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))) {
1226 if (likely(napi_schedule_prep(&adapter->napi))) {
1227 /* Enable only Rx Descriptor empty */
1228 atomic_inc(&adapter->irq_sem);
1229 int_en = ioread32(&hw->reg->INT_EN);
1230 int_en &=
1231 ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1232 iowrite32(int_en, &hw->reg->INT_EN);
1233 /* Start polling for NAPI */
1234 __napi_schedule(&adapter->napi);
1235 }
1236 }
1237 pr_debug("return = 0x%08x INT_EN reg = 0x%08x\n",
1238 IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1239 return IRQ_HANDLED;
1240}
1241
1242/**
1243 * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1244 * @adapter: Board private structure
1245 * @rx_ring: Rx descriptor ring
1246 * @cleaned_count: Cleaned count
1247 */
1248static void
1249pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1250 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1251{
1252 struct net_device *netdev = adapter->netdev;
1253 struct pci_dev *pdev = adapter->pdev;
1254 struct pch_gbe_hw *hw = &adapter->hw;
1255 struct pch_gbe_rx_desc *rx_desc;
1256 struct pch_gbe_buffer *buffer_info;
1257 struct sk_buff *skb;
1258 unsigned int i;
1259 unsigned int bufsz;
1260
124d770a 1261 bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
77555ee7
MO		 1262 i = rx_ring->next_to_use;
1263
1264 while ((cleaned_count--)) {
1265 buffer_info = &rx_ring->buffer_info[i];
124d770a
TO		 1266 skb = netdev_alloc_skb(netdev, bufsz);
1267 if (unlikely(!skb)) {
1268 /* Better luck next round */
1269 adapter->stats.rx_alloc_buff_failed++;
1270 break;
77555ee7 1271 }
124d770a
TO		 1272 /* align */
1273 skb_reserve(skb, NET_IP_ALIGN);
1274 buffer_info->skb = skb;
1275
77555ee7 1276 buffer_info->dma = dma_map_single(&pdev->dev,
124d770a 1277 buffer_info->rx_buffer,
77555ee7
MO		 1278 buffer_info->length,
1279 DMA_FROM_DEVICE);
1280 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1281 dev_kfree_skb(skb);
1282 buffer_info->skb = NULL;
1283 buffer_info->dma = 0;
1284 adapter->stats.rx_alloc_buff_failed++;
1285 break; /* while !buffer_info->skb */
1286 }
1287 buffer_info->mapped = true;
1288 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1289 rx_desc->buffer_addr = (buffer_info->dma);
1290 rx_desc->gbec_status = DSC_INIT16;
1291
1292 pr_debug("i = %d buffer_info->dma = 0x08%llx buffer_info->length = 0x%x\n",
1293 i, (unsigned long long)buffer_info->dma,
1294 buffer_info->length);
1295
1296 if (unlikely(++i == rx_ring->count))
1297 i = 0;
1298 }
1299 if (likely(rx_ring->next_to_use != i)) {
1300 rx_ring->next_to_use = i;
1301 if (unlikely(i-- == 0))
1302 i = (rx_ring->count - 1);
1303 iowrite32(rx_ring->dma +
1304 (int)sizeof(struct pch_gbe_rx_desc) * i,
1305 &hw->reg->RX_DSC_SW_P);
1306 }
1307 return;
1308}
1309
124d770a
TO		 1310static int
1311pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter,
1312 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1313{
1314 struct pci_dev *pdev = adapter->pdev;
1315 struct pch_gbe_buffer *buffer_info;
1316 unsigned int i;
1317 unsigned int bufsz;
1318 unsigned int size;
1319
1320 bufsz = adapter->rx_buffer_len;
1321
1322 size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY;
1323 rx_ring->rx_buff_pool = dma_alloc_coherent(&pdev->dev, size,
1324 &rx_ring->rx_buff_pool_logic,
1325 GFP_KERNEL);
1326 if (!rx_ring->rx_buff_pool) {
1327 pr_err("Unable to allocate memory for the receive poll buffer\n");
1328 return -ENOMEM;
1329 }
1330 memset(rx_ring->rx_buff_pool, 0, size);
1331 rx_ring->rx_buff_pool_size = size;
1332 for (i = 0; i < rx_ring->count; i++) {
1333 buffer_info = &rx_ring->buffer_info[i];
1334 buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i;
1335 buffer_info->length = bufsz;
1336 }
1337 return 0;
1338}
1339
77555ee7
MO		 1340/**
1341 * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1342 * @adapter: Board private structure
1343 * @tx_ring: Tx descriptor ring
1344 */
1345static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1346 struct pch_gbe_tx_ring *tx_ring)
1347{
1348 struct pch_gbe_buffer *buffer_info;
1349 struct sk_buff *skb;
1350 unsigned int i;
1351 unsigned int bufsz;
1352 struct pch_gbe_tx_desc *tx_desc;
1353
1354 bufsz =
1355 adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1356
1357 for (i = 0; i < tx_ring->count; i++) {
1358 buffer_info = &tx_ring->buffer_info[i];
1359 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1360 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1361 buffer_info->skb = skb;
1362 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1363 tx_desc->gbec_status = (DSC_INIT16);
1364 }
1365 return;
1366}
1367
1368/**
1369 * pch_gbe_clean_tx - Reclaim resources after transmit completes
1370 * @adapter: Board private structure
1371 * @tx_ring: Tx descriptor ring
1372 * Returns
1373 * true: Cleaned the descriptor
1374 * false: Not cleaned the descriptor
1375 */
1376static bool
1377pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1378 struct pch_gbe_tx_ring *tx_ring)
1379{
1380 struct pch_gbe_tx_desc *tx_desc;
1381 struct pch_gbe_buffer *buffer_info;
1382 struct sk_buff *skb;
1383 unsigned int i;
1384 unsigned int cleaned_count = 0;
1385 bool cleaned = false;
1386
1387 pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1388
1389 i = tx_ring->next_to_clean;
1390 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1391 pr_debug("gbec_status:0x%04x dma_status:0x%04x\n",
1392 tx_desc->gbec_status, tx_desc->dma_status);
1393
1394 while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1395 pr_debug("gbec_status:0x%04x\n", tx_desc->gbec_status);
1396 cleaned = true;
1397 buffer_info = &tx_ring->buffer_info[i];
1398 skb = buffer_info->skb;
1399
1400 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1401 adapter->stats.tx_aborted_errors++;
1402 pr_err("Transfer Abort Error\n");
1403 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1404 ) {
1405 adapter->stats.tx_carrier_errors++;
1406 pr_err("Transfer Carrier Sense Error\n");
1407 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1408 ) {
1409 adapter->stats.tx_aborted_errors++;
1410 pr_err("Transfer Collision Abort Error\n");
1411 } else if ((tx_desc->gbec_status &
1412 (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1413 PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1414 adapter->stats.collisions++;
1415 adapter->stats.tx_packets++;
1416 adapter->stats.tx_bytes += skb->len;
1417 pr_debug("Transfer Collision\n");
1418 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1419 ) {
1420 adapter->stats.tx_packets++;
1421 adapter->stats.tx_bytes += skb->len;
1422 }
1423 if (buffer_info->mapped) {
1424 pr_debug("unmap buffer_info->dma : %d\n", i);
1425 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1426 buffer_info->length, DMA_TO_DEVICE);
1427 buffer_info->mapped = false;
1428 }
1429 if (buffer_info->skb) {
1430 pr_debug("trim buffer_info->skb : %d\n", i);
1431 skb_trim(buffer_info->skb, 0);
1432 }
1433 tx_desc->gbec_status = DSC_INIT16;
1434 if (unlikely(++i == tx_ring->count))
1435 i = 0;
1436 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1437
1438 /* weight of a sort for tx, to avoid endless transmit cleanup */
1439 if (cleaned_count++ == PCH_GBE_TX_WEIGHT)
1440 break;
1441 }
1442 pr_debug("called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1443 cleaned_count);
1444 /* Recover from running out of Tx resources in xmit_frame */
1445 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev)))) {
1446 netif_wake_queue(adapter->netdev);
1447 adapter->stats.tx_restart_count++;
1448 pr_debug("Tx wake queue\n");
1449 }
1450 spin_lock(&adapter->tx_queue_lock);
1451 tx_ring->next_to_clean = i;
1452 spin_unlock(&adapter->tx_queue_lock);
1453 pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1454 return cleaned;
1455}
1456
1457/**
1458 * pch_gbe_clean_rx - Send received data up the network stack; legacy
1459 * @adapter: Board private structure
1460 * @rx_ring: Rx descriptor ring
1461 * @work_done: Completed count
1462 * @work_to_do: Request count
1463 * Returns
1464 * true: Cleaned the descriptor
1465 * false: Not cleaned the descriptor
1466 */
1467static bool
1468pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1469 struct pch_gbe_rx_ring *rx_ring,
1470 int *work_done, int work_to_do)
1471{
1472 struct net_device *netdev = adapter->netdev;
1473 struct pci_dev *pdev = adapter->pdev;
1474 struct pch_gbe_buffer *buffer_info;
1475 struct pch_gbe_rx_desc *rx_desc;
1476 u32 length;
77555ee7
MO		 1477 unsigned int i;
1478 unsigned int cleaned_count = 0;
1479 bool cleaned = false;
124d770a 1480 struct sk_buff *skb;
77555ee7
MO		 1481 u8 dma_status;
1482 u16 gbec_status;
1483 u32 tcp_ip_status;
77555ee7
MO		 1484
1485 i = rx_ring->next_to_clean;
1486
1487 while (*work_done < work_to_do) {
1488 /* Check Rx descriptor status */
1489 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1490 if (rx_desc->gbec_status == DSC_INIT16)
1491 break;
1492 cleaned = true;
1493 cleaned_count++;
1494
1495 dma_status = rx_desc->dma_status;
1496 gbec_status = rx_desc->gbec_status;
1497 tcp_ip_status = rx_desc->tcp_ip_status;
1498 rx_desc->gbec_status = DSC_INIT16;
1499 buffer_info = &rx_ring->buffer_info[i];
1500 skb = buffer_info->skb;
124d770a 1501 buffer_info->skb = NULL;
77555ee7
MO		 1502
1503 /* unmap dma */
1504 dma_unmap_single(&pdev->dev, buffer_info->dma,
1505 buffer_info->length, DMA_FROM_DEVICE);
1506 buffer_info->mapped = false;
77555ee7
MO		 1507
1508 pr_debug("RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x "
1509 "TCP:0x%08x] BufInf = 0x%p\n",
1510 i, dma_status, gbec_status, tcp_ip_status,
1511 buffer_info);
1512 /* Error check */
1513 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1514 adapter->stats.rx_frame_errors++;
1515 pr_err("Receive Not Octal Error\n");
1516 } else if (unlikely(gbec_status &
1517 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1518 adapter->stats.rx_frame_errors++;
1519 pr_err("Receive Nibble Error\n");
1520 } else if (unlikely(gbec_status &
1521 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1522 adapter->stats.rx_crc_errors++;
1523 pr_err("Receive CRC Error\n");
1524 } else {
1525 /* get receive length */
124d770a
TO		 1526 /* length convert[-3], length includes FCS length */
1527 length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN;
1528 if (rx_desc->rx_words_eob & 0x02)
1529 length = length - 4;
1530 /*
1531 * buffer_info->rx_buffer: [Header:14][payload]
1532 * skb->data: [Reserve:2][Header:14][payload]
1533 */
1534 memcpy(skb->data, buffer_info->rx_buffer, length);
1535
77555ee7
MO		 1536 /* update status of driver */
1537 adapter->stats.rx_bytes += length;
1538 adapter->stats.rx_packets++;
1539 if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1540 adapter->stats.multicast++;
1541 /* Write meta date of skb */
1542 skb_put(skb, length);
1543 skb->protocol = eth_type_trans(skb, netdev);
5d05a04d 1544 if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
77555ee7 1545 skb->ip_summed = CHECKSUM_NONE;
5d05a04d
TO		 1546 else
1547 skb->ip_summed = CHECKSUM_UNNECESSARY;
1548
77555ee7
MO		 1549 napi_gro_receive(&adapter->napi, skb);
1550 (*work_done)++;
1551 pr_debug("Receive skb->ip_summed: %d length: %d\n",
1552 skb->ip_summed, length);
1553 }
77555ee7
MO		 1554 /* return some buffers to hardware, one at a time is too slow */
1555 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1556 pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1557 cleaned_count);
1558 cleaned_count = 0;
1559 }
1560 if (++i == rx_ring->count)
1561 i = 0;
1562 }
1563 rx_ring->next_to_clean = i;
1564 if (cleaned_count)
1565 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1566 return cleaned;
1567}
1568
1569/**
1570 * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1571 * @adapter: Board private structure
1572 * @tx_ring: Tx descriptor ring (for a specific queue) to setup
1573 * Returns
1574 * 0: Successfully
1575 * Negative value: Failed
1576 */
1577int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1578 struct pch_gbe_tx_ring *tx_ring)
1579{
1580 struct pci_dev *pdev = adapter->pdev;
1581 struct pch_gbe_tx_desc *tx_desc;
1582 int size;
1583 int desNo;
1584
1585 size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
89bf67f1 1586 tx_ring->buffer_info = vzalloc(size);
77555ee7 1587 if (!tx_ring->buffer_info) {
25985edc 1588 pr_err("Unable to allocate memory for the buffer information\n");
77555ee7
MO		 1589 return -ENOMEM;
1590 }
77555ee7
MO		 1591
1592 tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1593
1594 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
1595 &tx_ring->dma, GFP_KERNEL);
1596 if (!tx_ring->desc) {
1597 vfree(tx_ring->buffer_info);
1598 pr_err("Unable to allocate memory for the transmit descriptor ring\n");
1599 return -ENOMEM;
1600 }
1601 memset(tx_ring->desc, 0, tx_ring->size);
1602
1603 tx_ring->next_to_use = 0;
1604 tx_ring->next_to_clean = 0;
1605 spin_lock_init(&tx_ring->tx_lock);
1606
1607 for (desNo = 0; desNo < tx_ring->count; desNo++) {
1608 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1609 tx_desc->gbec_status = DSC_INIT16;
1610 }
1611 pr_debug("tx_ring->desc = 0x%p tx_ring->dma = 0x%08llx\n"
1612 "next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1613 tx_ring->desc, (unsigned long long)tx_ring->dma,
1614 tx_ring->next_to_clean, tx_ring->next_to_use);
1615 return 0;
1616}
1617
1618/**
1619 * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1620 * @adapter: Board private structure
1621 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1622 * Returns
1623 * 0: Successfully
1624 * Negative value: Failed
1625 */
1626int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1627 struct pch_gbe_rx_ring *rx_ring)
1628{
1629 struct pci_dev *pdev = adapter->pdev;
1630 struct pch_gbe_rx_desc *rx_desc;
1631 int size;
1632 int desNo;
1633
1634 size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
89bf67f1 1635 rx_ring->buffer_info = vzalloc(size);
77555ee7
MO		 1636 if (!rx_ring->buffer_info) {
1637 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1638 return -ENOMEM;
1639 }
77555ee7
MO		 1640 rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1641 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
1642 &rx_ring->dma, GFP_KERNEL);
1643
1644 if (!rx_ring->desc) {
1645 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1646 vfree(rx_ring->buffer_info);
1647 return -ENOMEM;
1648 }
1649 memset(rx_ring->desc, 0, rx_ring->size);
1650 rx_ring->next_to_clean = 0;
1651 rx_ring->next_to_use = 0;
1652 for (desNo = 0; desNo < rx_ring->count; desNo++) {
1653 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1654 rx_desc->gbec_status = DSC_INIT16;
1655 }
1656 pr_debug("rx_ring->desc = 0x%p rx_ring->dma = 0x%08llx "
1657 "next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1658 rx_ring->desc, (unsigned long long)rx_ring->dma,
1659 rx_ring->next_to_clean, rx_ring->next_to_use);
1660 return 0;
1661}
1662
1663/**
1664 * pch_gbe_free_tx_resources - Free Tx Resources
1665 * @adapter: Board private structure
1666 * @tx_ring: Tx descriptor ring for a specific queue
1667 */
1668void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1669 struct pch_gbe_tx_ring *tx_ring)
1670{
1671 struct pci_dev *pdev = adapter->pdev;
1672
1673 pch_gbe_clean_tx_ring(adapter, tx_ring);
1674 vfree(tx_ring->buffer_info);
1675 tx_ring->buffer_info = NULL;
1676 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1677 tx_ring->desc = NULL;
1678}
1679
1680/**
1681 * pch_gbe_free_rx_resources - Free Rx Resources
1682 * @adapter: Board private structure
1683 * @rx_ring: Ring to clean the resources from
1684 */
1685void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1686 struct pch_gbe_rx_ring *rx_ring)
1687{
1688 struct pci_dev *pdev = adapter->pdev;
1689
1690 pch_gbe_clean_rx_ring(adapter, rx_ring);
1691 vfree(rx_ring->buffer_info);
1692 rx_ring->buffer_info = NULL;
1693 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1694 rx_ring->desc = NULL;
1695}
1696
1697/**
1698 * pch_gbe_request_irq - Allocate an interrupt line
1699 * @adapter: Board private structure
1700 * Returns
1701 * 0: Successfully
1702 * Negative value: Failed
1703 */
1704static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1705{
1706 struct net_device *netdev = adapter->netdev;
1707 int err;
1708 int flags;
1709
1710 flags = IRQF_SHARED;
1711 adapter->have_msi = false;
1712 err = pci_enable_msi(adapter->pdev);
1713 pr_debug("call pci_enable_msi\n");
1714 if (err) {
1715 pr_debug("call pci_enable_msi - Error: %d\n", err);
1716 } else {
1717 flags = 0;
1718 adapter->have_msi = true;
1719 }
1720 err = request_irq(adapter->pdev->irq, &pch_gbe_intr,
1721 flags, netdev->name, netdev);
1722 if (err)
1723 pr_err("Unable to allocate interrupt Error: %d\n", err);
1724 pr_debug("adapter->have_msi : %d flags : 0x%04x return : 0x%04x\n",
1725 adapter->have_msi, flags, err);
1726 return err;
1727}
1728
1729
1730static void pch_gbe_set_multi(struct net_device *netdev);
1731/**
1732 * pch_gbe_up - Up GbE network device
1733 * @adapter: Board private structure
1734 * Returns
1735 * 0: Successfully
1736 * Negative value: Failed
1737 */
1738int pch_gbe_up(struct pch_gbe_adapter *adapter)
1739{
1740 struct net_device *netdev = adapter->netdev;
1741 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1742 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1743 int err;
1744
1745 /* hardware has been reset, we need to reload some things */
1746 pch_gbe_set_multi(netdev);
1747
1748 pch_gbe_setup_tctl(adapter);
1749 pch_gbe_configure_tx(adapter);
1750 pch_gbe_setup_rctl(adapter);
1751 pch_gbe_configure_rx(adapter);
1752
1753 err = pch_gbe_request_irq(adapter);
1754 if (err) {
1755 pr_err("Error: can't bring device up\n");
1756 return err;
1757 }
124d770a
TO		 1758 err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count);
1759 if (err) {
1760 pr_err("Error: can't bring device up\n");
1761 return err;
1762 }
77555ee7
MO		 1763 pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1764 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1765 adapter->tx_queue_len = netdev->tx_queue_len;
5229d87e 1766 pch_gbe_start_receive(&adapter->hw);
77555ee7
MO		 1767
1768 mod_timer(&adapter->watchdog_timer, jiffies);
1769
1770 napi_enable(&adapter->napi);
1771 pch_gbe_irq_enable(adapter);
1772 netif_start_queue(adapter->netdev);
1773
1774 return 0;
1775}
1776
1777/**
1778 * pch_gbe_down - Down GbE network device
1779 * @adapter: Board private structure
1780 */
1781void pch_gbe_down(struct pch_gbe_adapter *adapter)
1782{
1783 struct net_device *netdev = adapter->netdev;
124d770a 1784 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
77555ee7
MO		 1785
1786 /* signal that we're down so the interrupt handler does not
1787 * reschedule our watchdog timer */
1788 napi_disable(&adapter->napi);
1789 atomic_set(&adapter->irq_sem, 0);
1790
1791 pch_gbe_irq_disable(adapter);
1792 pch_gbe_free_irq(adapter);
1793
1794 del_timer_sync(&adapter->watchdog_timer);
1795
1796 netdev->tx_queue_len = adapter->tx_queue_len;
1797 netif_carrier_off(netdev);
1798 netif_stop_queue(netdev);
1799
1800 pch_gbe_reset(adapter);
1801 pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
1802 pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
124d770a
TO		 1803
1804 pci_free_consistent(adapter->pdev, rx_ring->rx_buff_pool_size,
1805 rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic);
1806 rx_ring->rx_buff_pool_logic = 0;
1807 rx_ring->rx_buff_pool_size = 0;
1808 rx_ring->rx_buff_pool = NULL;
77555ee7
MO		 1809}
1810
1811/**
1812 * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
1813 * @adapter: Board private structure to initialize
1814 * Returns
1815 * 0: Successfully
1816 * Negative value: Failed
1817 */
1818static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
1819{
1820 struct pch_gbe_hw *hw = &adapter->hw;
1821 struct net_device *netdev = adapter->netdev;
1822
1823 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
1824 hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1825 hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1826
1827 /* Initialize the hardware-specific values */
1828 if (pch_gbe_hal_setup_init_funcs(hw)) {
1829 pr_err("Hardware Initialization Failure\n");
1830 return -EIO;
1831 }
1832 if (pch_gbe_alloc_queues(adapter)) {
1833 pr_err("Unable to allocate memory for queues\n");
1834 return -ENOMEM;
1835 }
1836 spin_lock_init(&adapter->hw.miim_lock);
1837 spin_lock_init(&adapter->tx_queue_lock);
1838 spin_lock_init(&adapter->stats_lock);
1839 spin_lock_init(&adapter->ethtool_lock);
1840 atomic_set(&adapter->irq_sem, 0);
1841 pch_gbe_irq_disable(adapter);
1842
1843 pch_gbe_init_stats(adapter);
1844
1845 pr_debug("rx_buffer_len : %d mac.min_frame_size : %d mac.max_frame_size : %d\n",
1846 (u32) adapter->rx_buffer_len,
1847 hw->mac.min_frame_size, hw->mac.max_frame_size);
1848 return 0;
1849}
1850
1851/**
1852 * pch_gbe_open - Called when a network interface is made active
1853 * @netdev: Network interface device structure
1854 * Returns
1855 * 0: Successfully
1856 * Negative value: Failed
1857 */
1858static int pch_gbe_open(struct net_device *netdev)
1859{
1860 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1861 struct pch_gbe_hw *hw = &adapter->hw;
1862 int err;
1863
1864 /* allocate transmit descriptors */
1865 err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
1866 if (err)
1867 goto err_setup_tx;
1868 /* allocate receive descriptors */
1869 err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
1870 if (err)
1871 goto err_setup_rx;
1872 pch_gbe_hal_power_up_phy(hw);
1873 err = pch_gbe_up(adapter);
1874 if (err)
1875 goto err_up;
1876 pr_debug("Success End\n");
1877 return 0;
1878
1879err_up:
1880 if (!adapter->wake_up_evt)
1881 pch_gbe_hal_power_down_phy(hw);
1882 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1883err_setup_rx:
1884 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1885err_setup_tx:
1886 pch_gbe_reset(adapter);
1887 pr_err("Error End\n");
1888 return err;
1889}
1890
1891/**
1892 * pch_gbe_stop - Disables a network interface
1893 * @netdev: Network interface device structure
1894 * Returns
1895 * 0: Successfully
1896 */
1897static int pch_gbe_stop(struct net_device *netdev)
1898{
1899 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1900 struct pch_gbe_hw *hw = &adapter->hw;
1901
1902 pch_gbe_down(adapter);
1903 if (!adapter->wake_up_evt)
1904 pch_gbe_hal_power_down_phy(hw);
1905 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1906 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1907 return 0;
1908}
1909
1910/**
1911 * pch_gbe_xmit_frame - Packet transmitting start
1912 * @skb: Socket buffer structure
1913 * @netdev: Network interface device structure
1914 * Returns
1915 * - NETDEV_TX_OK: Normal end
1916 * - NETDEV_TX_BUSY: Error end
1917 */
1918static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1919{
1920 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1921 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1922 unsigned long flags;
1923
1924 if (unlikely(skb->len > (adapter->hw.mac.max_frame_size - 4))) {
77555ee7
MO		 1925 pr_err("Transfer length Error: skb len: %d > max: %d\n",
1926 skb->len, adapter->hw.mac.max_frame_size);
419c2046 1927 dev_kfree_skb_any(skb);
77555ee7
MO		 1928 adapter->stats.tx_length_errors++;
1929 return NETDEV_TX_OK;
1930 }
1931 if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags)) {
1932 /* Collision - tell upper layer to requeue */
1933 return NETDEV_TX_LOCKED;
1934 }
1935 if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
1936 netif_stop_queue(netdev);
1937 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1938 pr_debug("Return : BUSY next_to use : 0x%08x next_to clean : 0x%08x\n",
1939 tx_ring->next_to_use, tx_ring->next_to_clean);
1940 return NETDEV_TX_BUSY;
1941 }
1942 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1943
1944 /* CRC,ITAG no support */
1945 pch_gbe_tx_queue(adapter, tx_ring, skb);
1946 return NETDEV_TX_OK;
1947}
1948
1949/**
1950 * pch_gbe_get_stats - Get System Network Statistics
1951 * @netdev: Network interface device structure
1952 * Returns: The current stats
1953 */
1954static struct net_device_stats *pch_gbe_get_stats(struct net_device *netdev)
1955{
1956 /* only return the current stats */
1957 return &netdev->stats;
1958}
1959
1960/**
1961 * pch_gbe_set_multi - Multicast and Promiscuous mode set
1962 * @netdev: Network interface device structure
1963 */
1964static void pch_gbe_set_multi(struct net_device *netdev)
1965{
1966 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1967 struct pch_gbe_hw *hw = &adapter->hw;
1968 struct netdev_hw_addr *ha;
1969 u8 *mta_list;
1970 u32 rctl;
1971 int i;
1972 int mc_count;
1973
1974 pr_debug("netdev->flags : 0x%08x\n", netdev->flags);
1975
1976 /* Check for Promiscuous and All Multicast modes */
1977 rctl = ioread32(&hw->reg->RX_MODE);
1978 mc_count = netdev_mc_count(netdev);
1979 if ((netdev->flags & IFF_PROMISC)) {
1980 rctl &= ~PCH_GBE_ADD_FIL_EN;
1981 rctl &= ~PCH_GBE_MLT_FIL_EN;
1982 } else if ((netdev->flags & IFF_ALLMULTI)) {
1983 /* all the multicasting receive permissions */
1984 rctl |= PCH_GBE_ADD_FIL_EN;
1985 rctl &= ~PCH_GBE_MLT_FIL_EN;
1986 } else {
1987 if (mc_count >= PCH_GBE_MAR_ENTRIES) {
1988 /* all the multicasting receive permissions */
1989 rctl |= PCH_GBE_ADD_FIL_EN;
1990 rctl &= ~PCH_GBE_MLT_FIL_EN;
1991 } else {
1992 rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
1993 }
1994 }
1995 iowrite32(rctl, &hw->reg->RX_MODE);
1996
1997 if (mc_count >= PCH_GBE_MAR_ENTRIES)
1998 return;
1999 mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC);
2000 if (!mta_list)
2001 return;
2002
2003 /* The shared function expects a packed array of only addresses. */
2004 i = 0;
2005 netdev_for_each_mc_addr(ha, netdev) {
2006 if (i == mc_count)
2007 break;
2008 memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
2009 }
2010 pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
2011 PCH_GBE_MAR_ENTRIES);
2012 kfree(mta_list);
2013
2014 pr_debug("RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x netdev->mc_count : 0x%08x\n",
2015 ioread32(&hw->reg->RX_MODE), mc_count);
2016}
2017
2018/**
2019 * pch_gbe_set_mac - Change the Ethernet Address of the NIC
2020 * @netdev: Network interface device structure
2021 * @addr: Pointer to an address structure
2022 * Returns
2023 * 0: Successfully
2024 * -EADDRNOTAVAIL: Failed
2025 */
2026static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
2027{
2028 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2029 struct sockaddr *skaddr = addr;
2030 int ret_val;
2031
2032 if (!is_valid_ether_addr(skaddr->sa_data)) {
2033 ret_val = -EADDRNOTAVAIL;
2034 } else {
2035 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
2036 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
2037 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2038 ret_val = 0;
2039 }
2040 pr_debug("ret_val : 0x%08x\n", ret_val);
2041 pr_debug("dev_addr : %pM\n", netdev->dev_addr);
2042 pr_debug("mac_addr : %pM\n", adapter->hw.mac.addr);
2043 pr_debug("MAC_ADR1AB reg : 0x%08x 0x%08x\n",
2044 ioread32(&adapter->hw.reg->mac_adr[0].high),
2045 ioread32(&adapter->hw.reg->mac_adr[0].low));
2046 return ret_val;
2047}
2048
2049/**
2050 * pch_gbe_change_mtu - Change the Maximum Transfer Unit
2051 * @netdev: Network interface device structure
2052 * @new_mtu: New value for maximum frame size
2053 * Returns
2054 * 0: Successfully
2055 * -EINVAL: Failed
2056 */
2057static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2058{
2059 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2060 int max_frame;
124d770a
TO		 2061 unsigned long old_rx_buffer_len = adapter->rx_buffer_len;
2062 int err;
77555ee7
MO		 2063
2064 max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2065 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2066 (max_frame > PCH_GBE_MAX_JUMBO_FRAME_SIZE)) {
2067 pr_err("Invalid MTU setting\n");
2068 return -EINVAL;
2069 }
2070 if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2071 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2072 else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2073 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2074 else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2075 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2076 else
124d770a
TO		 2077 adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE;
2078
2079 if (netif_running(netdev)) {
2080 pch_gbe_down(adapter);
2081 err = pch_gbe_up(adapter);
2082 if (err) {
2083 adapter->rx_buffer_len = old_rx_buffer_len;
2084 pch_gbe_up(adapter);
2085 return -ENOMEM;
2086 } else {
2087 netdev->mtu = new_mtu;
2088 adapter->hw.mac.max_frame_size = max_frame;
2089 }
2090 } else {
77555ee7 2091 pch_gbe_reset(adapter);
124d770a
TO		 2092 netdev->mtu = new_mtu;
2093 adapter->hw.mac.max_frame_size = max_frame;
2094 }
77555ee7
MO		 2095
2096 pr_debug("max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n",
2097 max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2098 adapter->hw.mac.max_frame_size);
2099 return 0;
2100}
2101
756a6b03
MM		 2102/**
2103 * pch_gbe_set_features - Reset device after features changed
2104 * @netdev: Network interface device structure
2105 * @features: New features
2106 * Returns
2107 * 0: HW state updated successfully
2108 */
2109static int pch_gbe_set_features(struct net_device *netdev, u32 features)
2110{
2111 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2112 u32 changed = features ^ netdev->features;
2113
2114 if (!(changed & NETIF_F_RXCSUM))
2115 return 0;
2116
2117 if (netif_running(netdev))
2118 pch_gbe_reinit_locked(adapter);
2119 else
2120 pch_gbe_reset(adapter);
2121
2122 return 0;
2123}
2124
77555ee7
MO		 2125/**
2126 * pch_gbe_ioctl - Controls register through a MII interface
2127 * @netdev: Network interface device structure
2128 * @ifr: Pointer to ifr structure
2129 * @cmd: Control command
2130 * Returns
2131 * 0: Successfully
2132 * Negative value: Failed
2133 */
2134static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2135{
2136 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2137
2138 pr_debug("cmd : 0x%04x\n", cmd);
2139
2140 return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2141}
2142
2143/**
2144 * pch_gbe_tx_timeout - Respond to a Tx Hang
2145 * @netdev: Network interface device structure
2146 */
2147static void pch_gbe_tx_timeout(struct net_device *netdev)
2148{
2149 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2150
2151 /* Do the reset outside of interrupt context */
2152 adapter->stats.tx_timeout_count++;
2153 schedule_work(&adapter->reset_task);
2154}
2155
2156/**
2157 * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2158 * @napi: Pointer of polling device struct
2159 * @budget: The maximum number of a packet
2160 * Returns
2161 * false: Exit the polling mode
2162 * true: Continue the polling mode
2163 */
2164static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2165{
2166 struct pch_gbe_adapter *adapter =
2167 container_of(napi, struct pch_gbe_adapter, napi);
2168 struct net_device *netdev = adapter->netdev;
2169 int work_done = 0;
2170 bool poll_end_flag = false;
2171 bool cleaned = false;
124d770a 2172 u32 int_en;
77555ee7
MO		 2173
2174 pr_debug("budget : %d\n", budget);
2175
2176 /* Keep link state information with original netdev */
2177 if (!netif_carrier_ok(netdev)) {
2178 poll_end_flag = true;
2179 } else {
77555ee7 2180 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
124d770a
TO		 2181 if (adapter->rx_stop_flag) {
2182 adapter->rx_stop_flag = false;
2183 pch_gbe_start_receive(&adapter->hw);
2184 int_en = ioread32(&adapter->hw.reg->INT_EN);
2185 iowrite32((int_en | PCH_GBE_INT_RX_FIFO_ERR),
2186 &adapter->hw.reg->INT_EN);
2187 }
2188 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
77555ee7
MO		 2189
2190 if (cleaned)
2191 work_done = budget;
2192 /* If no Tx and not enough Rx work done,
2193 * exit the polling mode
2194 */
2195 if ((work_done < budget) || !netif_running(netdev))
2196 poll_end_flag = true;
2197 }
2198
2199 if (poll_end_flag) {
2200 napi_complete(napi);
2201 pch_gbe_irq_enable(adapter);
2202 }
2203
2204 pr_debug("poll_end_flag : %d work_done : %d budget : %d\n",
2205 poll_end_flag, work_done, budget);
2206
2207 return work_done;
2208}
2209
2210#ifdef CONFIG_NET_POLL_CONTROLLER
2211/**
2212 * pch_gbe_netpoll - Used by things like netconsole to send skbs
2213 * @netdev: Network interface device structure
2214 */
2215static void pch_gbe_netpoll(struct net_device *netdev)
2216{
2217 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2218
2219 disable_irq(adapter->pdev->irq);
2220 pch_gbe_intr(adapter->pdev->irq, netdev);
2221 enable_irq(adapter->pdev->irq);
2222}
2223#endif
2224
2225static const struct net_device_ops pch_gbe_netdev_ops = {
2226 .ndo_open = pch_gbe_open,
2227 .ndo_stop = pch_gbe_stop,
2228 .ndo_start_xmit = pch_gbe_xmit_frame,
2229 .ndo_get_stats = pch_gbe_get_stats,
2230 .ndo_set_mac_address = pch_gbe_set_mac,
2231 .ndo_tx_timeout = pch_gbe_tx_timeout,
2232 .ndo_change_mtu = pch_gbe_change_mtu,
756a6b03 2233 .ndo_set_features = pch_gbe_set_features,
77555ee7
MO		 2234 .ndo_do_ioctl = pch_gbe_ioctl,
2235 .ndo_set_multicast_list = &pch_gbe_set_multi,
2236#ifdef CONFIG_NET_POLL_CONTROLLER
2237 .ndo_poll_controller = pch_gbe_netpoll,
2238#endif
2239};
2240
2241static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2242 pci_channel_state_t state)
2243{
2244 struct net_device *netdev = pci_get_drvdata(pdev);
2245 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2246
2247 netif_device_detach(netdev);
2248 if (netif_running(netdev))
2249 pch_gbe_down(adapter);
2250 pci_disable_device(pdev);
2251 /* Request a slot slot reset. */
2252 return PCI_ERS_RESULT_NEED_RESET;
2253}
2254
2255static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2256{
2257 struct net_device *netdev = pci_get_drvdata(pdev);
2258 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2259 struct pch_gbe_hw *hw = &adapter->hw;
2260
2261 if (pci_enable_device(pdev)) {
2262 pr_err("Cannot re-enable PCI device after reset\n");
2263 return PCI_ERS_RESULT_DISCONNECT;
2264 }
2265 pci_set_master(pdev);
2266 pci_enable_wake(pdev, PCI_D0, 0);
2267 pch_gbe_hal_power_up_phy(hw);
2268 pch_gbe_reset(adapter);
2269 /* Clear wake up status */
2270 pch_gbe_mac_set_wol_event(hw, 0);
2271
2272 return PCI_ERS_RESULT_RECOVERED;
2273}
2274
2275static void pch_gbe_io_resume(struct pci_dev *pdev)
2276{
2277 struct net_device *netdev = pci_get_drvdata(pdev);
2278 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2279
2280 if (netif_running(netdev)) {
2281 if (pch_gbe_up(adapter)) {
2282 pr_debug("can't bring device back up after reset\n");
2283 return;
2284 }
2285 }
2286 netif_device_attach(netdev);
2287}
2288
2289static int __pch_gbe_suspend(struct pci_dev *pdev)
2290{
2291 struct net_device *netdev = pci_get_drvdata(pdev);
2292 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2293 struct pch_gbe_hw *hw = &adapter->hw;
2294 u32 wufc = adapter->wake_up_evt;
2295 int retval = 0;
2296
2297 netif_device_detach(netdev);
2298 if (netif_running(netdev))
2299 pch_gbe_down(adapter);
2300 if (wufc) {
2301 pch_gbe_set_multi(netdev);
2302 pch_gbe_setup_rctl(adapter);
2303 pch_gbe_configure_rx(adapter);
2304 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2305 hw->mac.link_duplex);
2306 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2307 hw->mac.link_duplex);
2308 pch_gbe_mac_set_wol_event(hw, wufc);
2309 pci_disable_device(pdev);
2310 } else {
2311 pch_gbe_hal_power_down_phy(hw);
2312 pch_gbe_mac_set_wol_event(hw, wufc);
2313 pci_disable_device(pdev);
2314 }
2315 return retval;
2316}
2317
2318#ifdef CONFIG_PM
2319static int pch_gbe_suspend(struct device *device)
2320{
2321 struct pci_dev *pdev = to_pci_dev(device);
2322
2323 return __pch_gbe_suspend(pdev);
2324}
2325
2326static int pch_gbe_resume(struct device *device)
2327{
2328 struct pci_dev *pdev = to_pci_dev(device);
2329 struct net_device *netdev = pci_get_drvdata(pdev);
2330 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2331 struct pch_gbe_hw *hw = &adapter->hw;
2332 u32 err;
2333
2334 err = pci_enable_device(pdev);
2335 if (err) {
2336 pr_err("Cannot enable PCI device from suspend\n");
2337 return err;
2338 }
2339 pci_set_master(pdev);
2340 pch_gbe_hal_power_up_phy(hw);
2341 pch_gbe_reset(adapter);
2342 /* Clear wake on lan control and status */
2343 pch_gbe_mac_set_wol_event(hw, 0);
2344
2345 if (netif_running(netdev))
2346 pch_gbe_up(adapter);
2347 netif_device_attach(netdev);
2348
2349 return 0;
2350}
2351#endif /* CONFIG_PM */
2352
2353static void pch_gbe_shutdown(struct pci_dev *pdev)
2354{
2355 __pch_gbe_suspend(pdev);
2356 if (system_state == SYSTEM_POWER_OFF) {
2357 pci_wake_from_d3(pdev, true);
2358 pci_set_power_state(pdev, PCI_D3hot);
2359 }
2360}
2361
2362static void pch_gbe_remove(struct pci_dev *pdev)
2363{
2364 struct net_device *netdev = pci_get_drvdata(pdev);
2365 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2366
2321f3b4 2367 cancel_work_sync(&adapter->reset_task);
77555ee7
MO		 2368 unregister_netdev(netdev);
2369
2370 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2371
2372 kfree(adapter->tx_ring);
2373 kfree(adapter->rx_ring);
2374
2375 iounmap(adapter->hw.reg);
2376 pci_release_regions(pdev);
2377 free_netdev(netdev);
2378 pci_disable_device(pdev);
2379}
2380
2381static int pch_gbe_probe(struct pci_dev *pdev,
2382 const struct pci_device_id *pci_id)
2383{
2384 struct net_device *netdev;
2385 struct pch_gbe_adapter *adapter;
2386 int ret;
2387
2388 ret = pci_enable_device(pdev);
2389 if (ret)
2390 return ret;
2391
2392 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2393 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2394 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2395 if (ret) {
2396 ret = pci_set_consistent_dma_mask(pdev,
2397 DMA_BIT_MASK(32));
2398 if (ret) {
2399 dev_err(&pdev->dev, "ERR: No usable DMA "
2400 "configuration, aborting\n");
2401 goto err_disable_device;
2402 }
2403 }
2404 }
2405
2406 ret = pci_request_regions(pdev, KBUILD_MODNAME);
2407 if (ret) {
2408 dev_err(&pdev->dev,
2409 "ERR: Can't reserve PCI I/O and memory resources\n");
2410 goto err_disable_device;
2411 }
2412 pci_set_master(pdev);
2413
2414 netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2415 if (!netdev) {
2416 ret = -ENOMEM;
2417 dev_err(&pdev->dev,
2418 "ERR: Can't allocate and set up an Ethernet device\n");
2419 goto err_release_pci;
2420 }
2421 SET_NETDEV_DEV(netdev, &pdev->dev);
2422
2423 pci_set_drvdata(pdev, netdev);
2424 adapter = netdev_priv(netdev);
2425 adapter->netdev = netdev;
2426 adapter->pdev = pdev;
2427 adapter->hw.back = adapter;
2428 adapter->hw.reg = pci_iomap(pdev, PCH_GBE_PCI_BAR, 0);
2429 if (!adapter->hw.reg) {
2430 ret = -EIO;
2431 dev_err(&pdev->dev, "Can't ioremap\n");
2432 goto err_free_netdev;
2433 }
2434
2435 netdev->netdev_ops = &pch_gbe_netdev_ops;
2436 netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2437 netif_napi_add(netdev, &adapter->napi,
2438 pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
756a6b03
MM		 2439 netdev->hw_features = NETIF_F_RXCSUM |
2440 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2441 netdev->features = netdev->hw_features;
77555ee7
MO		 2442 pch_gbe_set_ethtool_ops(netdev);
2443
98200ec2 2444 pch_gbe_mac_load_mac_addr(&adapter->hw);
77555ee7
MO		 2445 pch_gbe_mac_reset_hw(&adapter->hw);
2446
2447 /* setup the private structure */
2448 ret = pch_gbe_sw_init(adapter);
2449 if (ret)
2450 goto err_iounmap;
2451
2452 /* Initialize PHY */
2453 ret = pch_gbe_init_phy(adapter);
2454 if (ret) {
2455 dev_err(&pdev->dev, "PHY initialize error\n");
2456 goto err_free_adapter;
2457 }
2458 pch_gbe_hal_get_bus_info(&adapter->hw);
2459
2460 /* Read the MAC address. and store to the private data */
2461 ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2462 if (ret) {
2463 dev_err(&pdev->dev, "MAC address Read Error\n");
2464 goto err_free_adapter;
2465 }
2466
2467 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2468 if (!is_valid_ether_addr(netdev->dev_addr)) {
2469 dev_err(&pdev->dev, "Invalid MAC Address\n");
2470 ret = -EIO;
2471 goto err_free_adapter;
2472 }
2473 setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog,
2474 (unsigned long)adapter);
2475
2476 INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2477
2478 pch_gbe_check_options(adapter);
2479
77555ee7
MO		 2480 /* initialize the wol settings based on the eeprom settings */
2481 adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2482 dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2483
2484 /* reset the hardware with the new settings */
2485 pch_gbe_reset(adapter);
2486
2487 ret = register_netdev(netdev);
2488 if (ret)
2489 goto err_free_adapter;
2490 /* tell the stack to leave us alone until pch_gbe_open() is called */
2491 netif_carrier_off(netdev);
2492 netif_stop_queue(netdev);
2493
2494 dev_dbg(&pdev->dev, "OKIsemi(R) PCH Network Connection\n");
2495
2496 device_set_wakeup_enable(&pdev->dev, 1);
2497 return 0;
2498
2499err_free_adapter:
2500 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2501 kfree(adapter->tx_ring);
2502 kfree(adapter->rx_ring);
2503err_iounmap:
2504 iounmap(adapter->hw.reg);
2505err_free_netdev:
2506 free_netdev(netdev);
2507err_release_pci:
2508 pci_release_regions(pdev);
2509err_disable_device:
2510 pci_disable_device(pdev);
2511 return ret;
2512}
2513
7fc44633 2514static DEFINE_PCI_DEVICE_TABLE(pch_gbe_pcidev_id) = {
77555ee7
MO		 2515 {.vendor = PCI_VENDOR_ID_INTEL,
2516 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2517 .subvendor = PCI_ANY_ID,
2518 .subdevice = PCI_ANY_ID,
2519 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2520 .class_mask = (0xFFFF00)
2521 },
b0e6baf5
T		 2522 {.vendor = PCI_VENDOR_ID_ROHM,
2523 .device = PCI_DEVICE_ID_ROHM_ML7223_GBE,
2524 .subvendor = PCI_ANY_ID,
2525 .subdevice = PCI_ANY_ID,
2526 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2527 .class_mask = (0xFFFF00)
2528 },
77555ee7
MO		 2529 /* required last entry */
2530 {0}
2531};
2532
2533#ifdef CONFIG_PM
2534static const struct dev_pm_ops pch_gbe_pm_ops = {
2535 .suspend = pch_gbe_suspend,
2536 .resume = pch_gbe_resume,
2537 .freeze = pch_gbe_suspend,
2538 .thaw = pch_gbe_resume,
2539 .poweroff = pch_gbe_suspend,
2540 .restore = pch_gbe_resume,
2541};
2542#endif
2543
2544static struct pci_error_handlers pch_gbe_err_handler = {
2545 .error_detected = pch_gbe_io_error_detected,
2546 .slot_reset = pch_gbe_io_slot_reset,
2547 .resume = pch_gbe_io_resume
2548};
2549
f7594d42 2550static struct pci_driver pch_gbe_driver = {
77555ee7
MO		 2551 .name = KBUILD_MODNAME,
2552 .id_table = pch_gbe_pcidev_id,
2553 .probe = pch_gbe_probe,
2554 .remove = pch_gbe_remove,
aa338601 2555#ifdef CONFIG_PM
77555ee7
MO		 2556 .driver.pm = &pch_gbe_pm_ops,
2557#endif
2558 .shutdown = pch_gbe_shutdown,
2559 .err_handler = &pch_gbe_err_handler
2560};
2561
2562
2563static int __init pch_gbe_init_module(void)
2564{
2565 int ret;
2566
f7594d42 2567 ret = pci_register_driver(&pch_gbe_driver);
77555ee7
MO		 2568 if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
2569 if (copybreak == 0) {
2570 pr_info("copybreak disabled\n");
2571 } else {
2572 pr_info("copybreak enabled for packets <= %u bytes\n",
2573 copybreak);
2574 }
2575 }
2576 return ret;
2577}
2578
2579static void __exit pch_gbe_exit_module(void)
2580{
f7594d42 2581 pci_unregister_driver(&pch_gbe_driver);
77555ee7
MO		 2582}
2583
2584module_init(pch_gbe_init_module);
2585module_exit(pch_gbe_exit_module);
2586
a1dcfcb7
TO		 2587MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2588MODULE_AUTHOR("OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com>");
77555ee7
MO		 2589MODULE_LICENSE("GPL");
2590MODULE_VERSION(DRV_VERSION);
2591MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2592
2593module_param(copybreak, uint, 0644);
2594MODULE_PARM_DESC(copybreak,
2595 "Maximum size of packet that is copied to a new buffer on receive");
2596
2597/* pch_gbe_main.c */
Linux kernel - Deliverables
This page took 0.280381 seconds and 5 git commands to generate.