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ethtool: cosmetics: enforce const-ness in ethtool_cmd_speed
[deliverable/linux.git] / drivers / net / pch_gbe / pch_gbe_main.c
CommitLineData
77555ee7
MO		 1/*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
a1dcfcb7 3 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
77555ee7
MO		 4 *
5 * This code was derived from the Intel e1000e Linux driver.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21#include "pch_gbe.h"
22#include "pch_gbe_api.h"
23
24#define DRV_VERSION "1.00"
25const char pch_driver_version[] = DRV_VERSION;
26
27#define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802 /* Pci device ID */
28#define PCH_GBE_MAR_ENTRIES 16
29#define PCH_GBE_SHORT_PKT 64
30#define DSC_INIT16 0xC000
31#define PCH_GBE_DMA_ALIGN 0
ac096642 32#define PCH_GBE_DMA_PADDING 2
77555ee7
MO		 33#define PCH_GBE_WATCHDOG_PERIOD (1 * HZ) /* watchdog time */
34#define PCH_GBE_COPYBREAK_DEFAULT 256
35#define PCH_GBE_PCI_BAR 1
36
37#define PCH_GBE_TX_WEIGHT 64
38#define PCH_GBE_RX_WEIGHT 64
39#define PCH_GBE_RX_BUFFER_WRITE 16
40
41/* Initialize the wake-on-LAN settings */
42#define PCH_GBE_WL_INIT_SETTING (PCH_GBE_WLC_MP)
43
44#define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
45 PCH_GBE_CHIP_TYPE_INTERNAL | \
46 PCH_GBE_RGMII_MODE_RGMII | \
47 PCH_GBE_CRS_SEL \
48 )
49
50/* Ethertype field values */
51#define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318
52#define PCH_GBE_FRAME_SIZE_2048 2048
53#define PCH_GBE_FRAME_SIZE_4096 4096
54#define PCH_GBE_FRAME_SIZE_8192 8192
55
56#define PCH_GBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
57#define PCH_GBE_RX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
58#define PCH_GBE_TX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
59#define PCH_GBE_DESC_UNUSED(R) \
60 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
61 (R)->next_to_clean - (R)->next_to_use - 1)
62
63/* Pause packet value */
64#define PCH_GBE_PAUSE_PKT1_VALUE 0x00C28001
65#define PCH_GBE_PAUSE_PKT2_VALUE 0x00000100
66#define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888
67#define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF
68
69#define PCH_GBE_ETH_ALEN 6
70
71/* This defines the bits that are set in the Interrupt Mask
72 * Set/Read Register. Each bit is documented below:
73 * o RXT0 = Receiver Timer Interrupt (ring 0)
74 * o TXDW = Transmit Descriptor Written Back
75 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
76 * o RXSEQ = Receive Sequence Error
77 * o LSC = Link Status Change
78 */
79#define PCH_GBE_INT_ENABLE_MASK ( \
80 PCH_GBE_INT_RX_DMA_CMPLT | \
81 PCH_GBE_INT_RX_DSC_EMP | \
82 PCH_GBE_INT_WOL_DET | \
83 PCH_GBE_INT_TX_CMPLT \
84 )
85
86
87static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
88
191cc687 89static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
90static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
91 int data);
98200ec2
TO		 92
93inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
94{
95 iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
96}
97
77555ee7
MO		 98/**
99 * pch_gbe_mac_read_mac_addr - Read MAC address
100 * @hw: Pointer to the HW structure
101 * Returns
102 * 0: Successful.
103 */
104s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
105{
106 u32 adr1a, adr1b;
107
108 adr1a = ioread32(&hw->reg->mac_adr[0].high);
109 adr1b = ioread32(&hw->reg->mac_adr[0].low);
110
111 hw->mac.addr[0] = (u8)(adr1a & 0xFF);
112 hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
113 hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
114 hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
115 hw->mac.addr[4] = (u8)(adr1b & 0xFF);
116 hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
117
118 pr_debug("hw->mac.addr : %pM\n", hw->mac.addr);
119 return 0;
120}
121
122/**
123 * pch_gbe_wait_clr_bit - Wait to clear a bit
124 * @reg: Pointer of register
125 * @busy: Busy bit
126 */
191cc687 127static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
77555ee7
MO		 128{
129 u32 tmp;
130 /* wait busy */
131 tmp = 1000;
132 while ((ioread32(reg) & bit) && --tmp)
133 cpu_relax();
134 if (!tmp)
135 pr_err("Error: busy bit is not cleared\n");
136}
137/**
138 * pch_gbe_mac_mar_set - Set MAC address register
139 * @hw: Pointer to the HW structure
140 * @addr: Pointer to the MAC address
141 * @index: MAC address array register
142 */
191cc687 143static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
77555ee7
MO		 144{
145 u32 mar_low, mar_high, adrmask;
146
147 pr_debug("index : 0x%x\n", index);
148
149 /*
150 * HW expects these in little endian so we reverse the byte order
151 * from network order (big endian) to little endian
152 */
153 mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
154 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
155 mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
156 /* Stop the MAC Address of index. */
157 adrmask = ioread32(&hw->reg->ADDR_MASK);
158 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
159 /* wait busy */
160 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
161 /* Set the MAC address to the MAC address 1A/1B register */
162 iowrite32(mar_high, &hw->reg->mac_adr[index].high);
163 iowrite32(mar_low, &hw->reg->mac_adr[index].low);
164 /* Start the MAC address of index */
165 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
166 /* wait busy */
167 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
168}
169
170/**
171 * pch_gbe_mac_reset_hw - Reset hardware
172 * @hw: Pointer to the HW structure
173 */
191cc687 174static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
77555ee7
MO		 175{
176 /* Read the MAC address. and store to the private data */
177 pch_gbe_mac_read_mac_addr(hw);
178 iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
179#ifdef PCH_GBE_MAC_IFOP_RGMII
180 iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
181#endif
182 pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
183 /* Setup the receive address */
184 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
185 return;
186}
187
188/**
189 * pch_gbe_mac_init_rx_addrs - Initialize receive address's
190 * @hw: Pointer to the HW structure
191 * @mar_count: Receive address registers
192 */
191cc687 193static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
77555ee7
MO		 194{
195 u32 i;
196
197 /* Setup the receive address */
198 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
199
200 /* Zero out the other receive addresses */
201 for (i = 1; i < mar_count; i++) {
202 iowrite32(0, &hw->reg->mac_adr[i].high);
203 iowrite32(0, &hw->reg->mac_adr[i].low);
204 }
205 iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
206 /* wait busy */
207 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
208}
209
210
211/**
212 * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
213 * @hw: Pointer to the HW structure
214 * @mc_addr_list: Array of multicast addresses to program
215 * @mc_addr_count: Number of multicast addresses to program
216 * @mar_used_count: The first MAC Address register free to program
217 * @mar_total_num: Total number of supported MAC Address Registers
218 */
191cc687 219static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
220 u8 *mc_addr_list, u32 mc_addr_count,
221 u32 mar_used_count, u32 mar_total_num)
77555ee7
MO		 222{
223 u32 i, adrmask;
224
225 /* Load the first set of multicast addresses into the exact
226 * filters (RAR). If there are not enough to fill the RAR
227 * array, clear the filters.
228 */
229 for (i = mar_used_count; i < mar_total_num; i++) {
230 if (mc_addr_count) {
231 pch_gbe_mac_mar_set(hw, mc_addr_list, i);
232 mc_addr_count--;
233 mc_addr_list += PCH_GBE_ETH_ALEN;
234 } else {
235 /* Clear MAC address mask */
236 adrmask = ioread32(&hw->reg->ADDR_MASK);
237 iowrite32((adrmask | (0x0001 << i)),
238 &hw->reg->ADDR_MASK);
239 /* wait busy */
240 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
241 /* Clear MAC address */
242 iowrite32(0, &hw->reg->mac_adr[i].high);
243 iowrite32(0, &hw->reg->mac_adr[i].low);
244 }
245 }
246}
247
248/**
249 * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
250 * @hw: Pointer to the HW structure
251 * Returns
252 * 0: Successful.
253 * Negative value: Failed.
254 */
255s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
256{
257 struct pch_gbe_mac_info *mac = &hw->mac;
258 u32 rx_fctrl;
259
260 pr_debug("mac->fc = %u\n", mac->fc);
261
262 rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
263
264 switch (mac->fc) {
265 case PCH_GBE_FC_NONE:
266 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
267 mac->tx_fc_enable = false;
268 break;
269 case PCH_GBE_FC_RX_PAUSE:
270 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
271 mac->tx_fc_enable = false;
272 break;
273 case PCH_GBE_FC_TX_PAUSE:
274 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
275 mac->tx_fc_enable = true;
276 break;
277 case PCH_GBE_FC_FULL:
278 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
279 mac->tx_fc_enable = true;
280 break;
281 default:
282 pr_err("Flow control param set incorrectly\n");
283 return -EINVAL;
284 }
285 if (mac->link_duplex == DUPLEX_HALF)
286 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
287 iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
288 pr_debug("RX_FCTRL reg : 0x%08x mac->tx_fc_enable : %d\n",
289 ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
290 return 0;
291}
292
293/**
294 * pch_gbe_mac_set_wol_event - Set wake-on-lan event
295 * @hw: Pointer to the HW structure
296 * @wu_evt: Wake up event
297 */
191cc687 298static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
77555ee7
MO		 299{
300 u32 addr_mask;
301
302 pr_debug("wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n",
303 wu_evt, ioread32(&hw->reg->ADDR_MASK));
304
305 if (wu_evt) {
306 /* Set Wake-On-Lan address mask */
307 addr_mask = ioread32(&hw->reg->ADDR_MASK);
308 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
309 /* wait busy */
310 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
311 iowrite32(0, &hw->reg->WOL_ST);
312 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
313 iowrite32(0x02, &hw->reg->TCPIP_ACC);
314 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
315 } else {
316 iowrite32(0, &hw->reg->WOL_CTRL);
317 iowrite32(0, &hw->reg->WOL_ST);
318 }
319 return;
320}
321
322/**
323 * pch_gbe_mac_ctrl_miim - Control MIIM interface
324 * @hw: Pointer to the HW structure
325 * @addr: Address of PHY
326 * @dir: Operetion. (Write or Read)
327 * @reg: Access register of PHY
328 * @data: Write data.
329 *
330 * Returns: Read date.
331 */
332u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
333 u16 data)
334{
335 u32 data_out = 0;
336 unsigned int i;
337 unsigned long flags;
338
339 spin_lock_irqsave(&hw->miim_lock, flags);
340
341 for (i = 100; i; --i) {
342 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
343 break;
344 udelay(20);
345 }
346 if (i == 0) {
347 pr_err("pch-gbe.miim won't go Ready\n");
348 spin_unlock_irqrestore(&hw->miim_lock, flags);
349 return 0; /* No way to indicate timeout error */
350 }
351 iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
352 (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
353 dir | data), &hw->reg->MIIM);
354 for (i = 0; i < 100; i++) {
355 udelay(20);
356 data_out = ioread32(&hw->reg->MIIM);
357 if ((data_out & PCH_GBE_MIIM_OPER_READY))
358 break;
359 }
360 spin_unlock_irqrestore(&hw->miim_lock, flags);
361
362 pr_debug("PHY %s: reg=%d, data=0x%04X\n",
363 dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
364 dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
365 return (u16) data_out;
366}
367
368/**
369 * pch_gbe_mac_set_pause_packet - Set pause packet
370 * @hw: Pointer to the HW structure
371 */
191cc687 372static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
77555ee7
MO		 373{
374 unsigned long tmp2, tmp3;
375
376 /* Set Pause packet */
377 tmp2 = hw->mac.addr[1];
378 tmp2 = (tmp2 << 8) | hw->mac.addr[0];
379 tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
380
381 tmp3 = hw->mac.addr[5];
382 tmp3 = (tmp3 << 8) | hw->mac.addr[4];
383 tmp3 = (tmp3 << 8) | hw->mac.addr[3];
384 tmp3 = (tmp3 << 8) | hw->mac.addr[2];
385
386 iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
387 iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
388 iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
389 iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
390 iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
391
392 /* Transmit Pause Packet */
393 iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
394
395 pr_debug("PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
396 ioread32(&hw->reg->PAUSE_PKT1), ioread32(&hw->reg->PAUSE_PKT2),
397 ioread32(&hw->reg->PAUSE_PKT3), ioread32(&hw->reg->PAUSE_PKT4),
398 ioread32(&hw->reg->PAUSE_PKT5));
399
400 return;
401}
402
403
404/**
405 * pch_gbe_alloc_queues - Allocate memory for all rings
406 * @adapter: Board private structure to initialize
407 * Returns
408 * 0: Successfully
409 * Negative value: Failed
410 */
411static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
412{
413 int size;
414
415 size = (int)sizeof(struct pch_gbe_tx_ring);
416 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
417 if (!adapter->tx_ring)
418 return -ENOMEM;
419 size = (int)sizeof(struct pch_gbe_rx_ring);
420 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
421 if (!adapter->rx_ring) {
422 kfree(adapter->tx_ring);
423 return -ENOMEM;
424 }
425 return 0;
426}
427
428/**
429 * pch_gbe_init_stats - Initialize status
430 * @adapter: Board private structure to initialize
431 */
432static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
433{
434 memset(&adapter->stats, 0, sizeof(adapter->stats));
435 return;
436}
437
438/**
439 * pch_gbe_init_phy - Initialize PHY
440 * @adapter: Board private structure to initialize
441 * Returns
442 * 0: Successfully
443 * Negative value: Failed
444 */
445static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
446{
447 struct net_device *netdev = adapter->netdev;
448 u32 addr;
449 u16 bmcr, stat;
450
451 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
452 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
453 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
454 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
455 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
456 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
457 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
458 break;
459 }
460 adapter->hw.phy.addr = adapter->mii.phy_id;
461 pr_debug("phy_addr = %d\n", adapter->mii.phy_id);
462 if (addr == 32)
463 return -EAGAIN;
464 /* Selected the phy and isolate the rest */
465 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
466 if (addr != adapter->mii.phy_id) {
467 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
468 BMCR_ISOLATE);
469 } else {
470 bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
471 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
472 bmcr & ~BMCR_ISOLATE);
473 }
474 }
475
476 /* MII setup */
477 adapter->mii.phy_id_mask = 0x1F;
478 adapter->mii.reg_num_mask = 0x1F;
479 adapter->mii.dev = adapter->netdev;
480 adapter->mii.mdio_read = pch_gbe_mdio_read;
481 adapter->mii.mdio_write = pch_gbe_mdio_write;
482 adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
483 return 0;
484}
485
486/**
487 * pch_gbe_mdio_read - The read function for mii
488 * @netdev: Network interface device structure
489 * @addr: Phy ID
490 * @reg: Access location
491 * Returns
492 * 0: Successfully
493 * Negative value: Failed
494 */
191cc687 495static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
77555ee7
MO		 496{
497 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
498 struct pch_gbe_hw *hw = &adapter->hw;
499
500 return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
501 (u16) 0);
502}
503
504/**
505 * pch_gbe_mdio_write - The write function for mii
506 * @netdev: Network interface device structure
507 * @addr: Phy ID (not used)
508 * @reg: Access location
509 * @data: Write data
510 */
191cc687 511static void pch_gbe_mdio_write(struct net_device *netdev,
512 int addr, int reg, int data)
77555ee7
MO		 513{
514 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
515 struct pch_gbe_hw *hw = &adapter->hw;
516
517 pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
518}
519
520/**
521 * pch_gbe_reset_task - Reset processing at the time of transmission timeout
522 * @work: Pointer of board private structure
523 */
524static void pch_gbe_reset_task(struct work_struct *work)
525{
526 struct pch_gbe_adapter *adapter;
527 adapter = container_of(work, struct pch_gbe_adapter, reset_task);
528
75d1a752 529 rtnl_lock();
77555ee7 530 pch_gbe_reinit_locked(adapter);
75d1a752 531 rtnl_unlock();
77555ee7
MO		 532}
533
534/**
535 * pch_gbe_reinit_locked- Re-initialization
536 * @adapter: Board private structure
537 */
538void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
539{
75d1a752
TO		 540 pch_gbe_down(adapter);
541 pch_gbe_up(adapter);
77555ee7
MO		 542}
543
544/**
545 * pch_gbe_reset - Reset GbE
546 * @adapter: Board private structure
547 */
548void pch_gbe_reset(struct pch_gbe_adapter *adapter)
549{
550 pch_gbe_mac_reset_hw(&adapter->hw);
551 /* Setup the receive address. */
552 pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
553 if (pch_gbe_hal_init_hw(&adapter->hw))
554 pr_err("Hardware Error\n");
555}
556
557/**
558 * pch_gbe_free_irq - Free an interrupt
559 * @adapter: Board private structure
560 */
561static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
562{
563 struct net_device *netdev = adapter->netdev;
564
565 free_irq(adapter->pdev->irq, netdev);
566 if (adapter->have_msi) {
567 pci_disable_msi(adapter->pdev);
568 pr_debug("call pci_disable_msi\n");
569 }
570}
571
572/**
573 * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
574 * @adapter: Board private structure
575 */
576static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
577{
578 struct pch_gbe_hw *hw = &adapter->hw;
579
580 atomic_inc(&adapter->irq_sem);
581 iowrite32(0, &hw->reg->INT_EN);
582 ioread32(&hw->reg->INT_ST);
583 synchronize_irq(adapter->pdev->irq);
584
585 pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
586}
587
588/**
589 * pch_gbe_irq_enable - Enable default interrupt generation settings
590 * @adapter: Board private structure
591 */
592static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
593{
594 struct pch_gbe_hw *hw = &adapter->hw;
595
596 if (likely(atomic_dec_and_test(&adapter->irq_sem)))
597 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
598 ioread32(&hw->reg->INT_ST);
599 pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
600}
601
602
603
604/**
605 * pch_gbe_setup_tctl - configure the Transmit control registers
606 * @adapter: Board private structure
607 */
608static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
609{
610 struct pch_gbe_hw *hw = &adapter->hw;
611 u32 tx_mode, tcpip;
612
613 tx_mode = PCH_GBE_TM_LONG_PKT |
614 PCH_GBE_TM_ST_AND_FD |
615 PCH_GBE_TM_SHORT_PKT |
616 PCH_GBE_TM_TH_TX_STRT_8 |
617 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
618
619 iowrite32(tx_mode, &hw->reg->TX_MODE);
620
621 tcpip = ioread32(&hw->reg->TCPIP_ACC);
622 tcpip |= PCH_GBE_TX_TCPIPACC_EN;
623 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
624 return;
625}
626
627/**
628 * pch_gbe_configure_tx - Configure Transmit Unit after Reset
629 * @adapter: Board private structure
630 */
631static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
632{
633 struct pch_gbe_hw *hw = &adapter->hw;
634 u32 tdba, tdlen, dctrl;
635
636 pr_debug("dma addr = 0x%08llx size = 0x%08x\n",
637 (unsigned long long)adapter->tx_ring->dma,
638 adapter->tx_ring->size);
639
640 /* Setup the HW Tx Head and Tail descriptor pointers */
641 tdba = adapter->tx_ring->dma;
642 tdlen = adapter->tx_ring->size - 0x10;
643 iowrite32(tdba, &hw->reg->TX_DSC_BASE);
644 iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
645 iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
646
647 /* Enables Transmission DMA */
648 dctrl = ioread32(&hw->reg->DMA_CTRL);
649 dctrl |= PCH_GBE_TX_DMA_EN;
650 iowrite32(dctrl, &hw->reg->DMA_CTRL);
651}
652
653/**
654 * pch_gbe_setup_rctl - Configure the receive control registers
655 * @adapter: Board private structure
656 */
657static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
658{
756a6b03 659 struct net_device *netdev = adapter->netdev;
77555ee7
MO		 660 struct pch_gbe_hw *hw = &adapter->hw;
661 u32 rx_mode, tcpip;
662
663 rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
664 PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
665
666 iowrite32(rx_mode, &hw->reg->RX_MODE);
667
668 tcpip = ioread32(&hw->reg->TCPIP_ACC);
669
756a6b03 670 if (netdev->features & NETIF_F_RXCSUM) {
77555ee7
MO		 671 tcpip &= ~PCH_GBE_RX_TCPIPACC_OFF;
672 tcpip |= PCH_GBE_RX_TCPIPACC_EN;
673 } else {
674 tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
675 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
676 }
677 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
678 return;
679}
680
681/**
682 * pch_gbe_configure_rx - Configure Receive Unit after Reset
683 * @adapter: Board private structure
684 */
685static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
686{
687 struct pch_gbe_hw *hw = &adapter->hw;
688 u32 rdba, rdlen, rctl, rxdma;
689
690 pr_debug("dma adr = 0x%08llx size = 0x%08x\n",
691 (unsigned long long)adapter->rx_ring->dma,
692 adapter->rx_ring->size);
693
694 pch_gbe_mac_force_mac_fc(hw);
695
696 /* Disables Receive MAC */
697 rctl = ioread32(&hw->reg->MAC_RX_EN);
698 iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
699
700 /* Disables Receive DMA */
701 rxdma = ioread32(&hw->reg->DMA_CTRL);
702 rxdma &= ~PCH_GBE_RX_DMA_EN;
703 iowrite32(rxdma, &hw->reg->DMA_CTRL);
704
705 pr_debug("MAC_RX_EN reg = 0x%08x DMA_CTRL reg = 0x%08x\n",
706 ioread32(&hw->reg->MAC_RX_EN),
707 ioread32(&hw->reg->DMA_CTRL));
708
709 /* Setup the HW Rx Head and Tail Descriptor Pointers and
710 * the Base and Length of the Rx Descriptor Ring */
711 rdba = adapter->rx_ring->dma;
712 rdlen = adapter->rx_ring->size - 0x10;
713 iowrite32(rdba, &hw->reg->RX_DSC_BASE);
714 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
715 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
716
717 /* Enables Receive DMA */
718 rxdma = ioread32(&hw->reg->DMA_CTRL);
719 rxdma |= PCH_GBE_RX_DMA_EN;
720 iowrite32(rxdma, &hw->reg->DMA_CTRL);
721 /* Enables Receive */
722 iowrite32(PCH_GBE_MRE_MAC_RX_EN, &hw->reg->MAC_RX_EN);
723}
724
725/**
726 * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
727 * @adapter: Board private structure
728 * @buffer_info: Buffer information structure
729 */
730static void pch_gbe_unmap_and_free_tx_resource(
731 struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
732{
733 if (buffer_info->mapped) {
734 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
735 buffer_info->length, DMA_TO_DEVICE);
736 buffer_info->mapped = false;
737 }
738 if (buffer_info->skb) {
739 dev_kfree_skb_any(buffer_info->skb);
740 buffer_info->skb = NULL;
741 }
742}
743
744/**
745 * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
746 * @adapter: Board private structure
747 * @buffer_info: Buffer information structure
748 */
749static void pch_gbe_unmap_and_free_rx_resource(
750 struct pch_gbe_adapter *adapter,
751 struct pch_gbe_buffer *buffer_info)
752{
753 if (buffer_info->mapped) {
754 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
755 buffer_info->length, DMA_FROM_DEVICE);
756 buffer_info->mapped = false;
757 }
758 if (buffer_info->skb) {
759 dev_kfree_skb_any(buffer_info->skb);
760 buffer_info->skb = NULL;
761 }
762}
763
764/**
765 * pch_gbe_clean_tx_ring - Free Tx Buffers
766 * @adapter: Board private structure
767 * @tx_ring: Ring to be cleaned
768 */
769static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
770 struct pch_gbe_tx_ring *tx_ring)
771{
772 struct pch_gbe_hw *hw = &adapter->hw;
773 struct pch_gbe_buffer *buffer_info;
774 unsigned long size;
775 unsigned int i;
776
777 /* Free all the Tx ring sk_buffs */
778 for (i = 0; i < tx_ring->count; i++) {
779 buffer_info = &tx_ring->buffer_info[i];
780 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
781 }
782 pr_debug("call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
783
784 size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
785 memset(tx_ring->buffer_info, 0, size);
786
787 /* Zero out the descriptor ring */
788 memset(tx_ring->desc, 0, tx_ring->size);
789 tx_ring->next_to_use = 0;
790 tx_ring->next_to_clean = 0;
791 iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
792 iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
793}
794
795/**
796 * pch_gbe_clean_rx_ring - Free Rx Buffers
797 * @adapter: Board private structure
798 * @rx_ring: Ring to free buffers from
799 */
800static void
801pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
802 struct pch_gbe_rx_ring *rx_ring)
803{
804 struct pch_gbe_hw *hw = &adapter->hw;
805 struct pch_gbe_buffer *buffer_info;
806 unsigned long size;
807 unsigned int i;
808
809 /* Free all the Rx ring sk_buffs */
810 for (i = 0; i < rx_ring->count; i++) {
811 buffer_info = &rx_ring->buffer_info[i];
812 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
813 }
814 pr_debug("call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
815 size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
816 memset(rx_ring->buffer_info, 0, size);
817
818 /* Zero out the descriptor ring */
819 memset(rx_ring->desc, 0, rx_ring->size);
820 rx_ring->next_to_clean = 0;
821 rx_ring->next_to_use = 0;
822 iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
823 iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
824}
825
826static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
827 u16 duplex)
828{
829 struct pch_gbe_hw *hw = &adapter->hw;
830 unsigned long rgmii = 0;
831
832 /* Set the RGMII control. */
833#ifdef PCH_GBE_MAC_IFOP_RGMII
834 switch (speed) {
835 case SPEED_10:
836 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
837 PCH_GBE_MAC_RGMII_CTRL_SETTING);
838 break;
839 case SPEED_100:
840 rgmii = (PCH_GBE_RGMII_RATE_25M |
841 PCH_GBE_MAC_RGMII_CTRL_SETTING);
842 break;
843 case SPEED_1000:
844 rgmii = (PCH_GBE_RGMII_RATE_125M |
845 PCH_GBE_MAC_RGMII_CTRL_SETTING);
846 break;
847 }
848 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
849#else /* GMII */
850 rgmii = 0;
851 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
852#endif
853}
854static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
855 u16 duplex)
856{
857 struct net_device *netdev = adapter->netdev;
858 struct pch_gbe_hw *hw = &adapter->hw;
859 unsigned long mode = 0;
860
861 /* Set the communication mode */
862 switch (speed) {
863 case SPEED_10:
864 mode = PCH_GBE_MODE_MII_ETHER;
865 netdev->tx_queue_len = 10;
866 break;
867 case SPEED_100:
868 mode = PCH_GBE_MODE_MII_ETHER;
869 netdev->tx_queue_len = 100;
870 break;
871 case SPEED_1000:
872 mode = PCH_GBE_MODE_GMII_ETHER;
873 break;
874 }
875 if (duplex == DUPLEX_FULL)
876 mode |= PCH_GBE_MODE_FULL_DUPLEX;
877 else
878 mode |= PCH_GBE_MODE_HALF_DUPLEX;
879 iowrite32(mode, &hw->reg->MODE);
880}
881
882/**
883 * pch_gbe_watchdog - Watchdog process
884 * @data: Board private structure
885 */
886static void pch_gbe_watchdog(unsigned long data)
887{
888 struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data;
889 struct net_device *netdev = adapter->netdev;
890 struct pch_gbe_hw *hw = &adapter->hw;
891 struct ethtool_cmd cmd;
892
893 pr_debug("right now = %ld\n", jiffies);
894
895 pch_gbe_update_stats(adapter);
896 if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
897 netdev->tx_queue_len = adapter->tx_queue_len;
898 /* mii library handles link maintenance tasks */
899 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
900 pr_err("ethtool get setting Error\n");
901 mod_timer(&adapter->watchdog_timer,
902 round_jiffies(jiffies +
903 PCH_GBE_WATCHDOG_PERIOD));
904 return;
905 }
906 hw->mac.link_speed = cmd.speed;
907 hw->mac.link_duplex = cmd.duplex;
908 /* Set the RGMII control. */
909 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
910 hw->mac.link_duplex);
911 /* Set the communication mode */
912 pch_gbe_set_mode(adapter, hw->mac.link_speed,
913 hw->mac.link_duplex);
914 netdev_dbg(netdev,
915 "Link is Up %d Mbps %s-Duplex\n",
916 cmd.speed,
917 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
918 netif_carrier_on(netdev);
919 netif_wake_queue(netdev);
920 } else if ((!mii_link_ok(&adapter->mii)) &&
921 (netif_carrier_ok(netdev))) {
922 netdev_dbg(netdev, "NIC Link is Down\n");
923 hw->mac.link_speed = SPEED_10;
924 hw->mac.link_duplex = DUPLEX_HALF;
925 netif_carrier_off(netdev);
926 netif_stop_queue(netdev);
927 }
928 mod_timer(&adapter->watchdog_timer,
929 round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
930}
931
932/**
933 * pch_gbe_tx_queue - Carry out queuing of the transmission data
934 * @adapter: Board private structure
935 * @tx_ring: Tx descriptor ring structure
936 * @skb: Sockt buffer structure
937 */
938static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
939 struct pch_gbe_tx_ring *tx_ring,
940 struct sk_buff *skb)
941{
942 struct pch_gbe_hw *hw = &adapter->hw;
943 struct pch_gbe_tx_desc *tx_desc;
944 struct pch_gbe_buffer *buffer_info;
945 struct sk_buff *tmp_skb;
946 unsigned int frame_ctrl;
947 unsigned int ring_num;
948 unsigned long flags;
949
950 /*-- Set frame control --*/
951 frame_ctrl = 0;
952 if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
953 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
756a6b03 954 if (skb->ip_summed == CHECKSUM_NONE)
77555ee7
MO		 955 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
956
957 /* Performs checksum processing */
958 /*
959 * It is because the hardware accelerator does not support a checksum,
960 * when the received data size is less than 64 bytes.
961 */
756a6b03 962 if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) {
77555ee7
MO		 963 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
964 PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
965 if (skb->protocol == htons(ETH_P_IP)) {
966 struct iphdr *iph = ip_hdr(skb);
967 unsigned int offset;
968 iph->check = 0;
969 iph->check = ip_fast_csum((u8 *) iph, iph->ihl);
970 offset = skb_transport_offset(skb);
971 if (iph->protocol == IPPROTO_TCP) {
972 skb->csum = 0;
973 tcp_hdr(skb)->check = 0;
974 skb->csum = skb_checksum(skb, offset,
975 skb->len - offset, 0);
976 tcp_hdr(skb)->check =
977 csum_tcpudp_magic(iph->saddr,
978 iph->daddr,
979 skb->len - offset,
980 IPPROTO_TCP,
981 skb->csum);
982 } else if (iph->protocol == IPPROTO_UDP) {
983 skb->csum = 0;
984 udp_hdr(skb)->check = 0;
985 skb->csum =
986 skb_checksum(skb, offset,
987 skb->len - offset, 0);
988 udp_hdr(skb)->check =
989 csum_tcpudp_magic(iph->saddr,
990 iph->daddr,
991 skb->len - offset,
992 IPPROTO_UDP,
993 skb->csum);
994 }
995 }
996 }
997 spin_lock_irqsave(&tx_ring->tx_lock, flags);
998 ring_num = tx_ring->next_to_use;
999 if (unlikely((ring_num + 1) == tx_ring->count))
1000 tx_ring->next_to_use = 0;
1001 else
1002 tx_ring->next_to_use = ring_num + 1;
1003
1004 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1005 buffer_info = &tx_ring->buffer_info[ring_num];
1006 tmp_skb = buffer_info->skb;
1007
1008 /* [Header:14][payload] ---> [Header:14][paddong:2][payload] */
1009 memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1010 tmp_skb->data[ETH_HLEN] = 0x00;
1011 tmp_skb->data[ETH_HLEN + 1] = 0x00;
1012 tmp_skb->len = skb->len;
1013 memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1014 (skb->len - ETH_HLEN));
25985edc 1015 /*-- Set Buffer information --*/
77555ee7
MO		 1016 buffer_info->length = tmp_skb->len;
1017 buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1018 buffer_info->length,
1019 DMA_TO_DEVICE);
1020 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1021 pr_err("TX DMA map failed\n");
1022 buffer_info->dma = 0;
1023 buffer_info->time_stamp = 0;
1024 tx_ring->next_to_use = ring_num;
1025 return;
1026 }
1027 buffer_info->mapped = true;
1028 buffer_info->time_stamp = jiffies;
1029
1030 /*-- Set Tx descriptor --*/
1031 tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1032 tx_desc->buffer_addr = (buffer_info->dma);
1033 tx_desc->length = (tmp_skb->len);
1034 tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1035 tx_desc->tx_frame_ctrl = (frame_ctrl);
1036 tx_desc->gbec_status = (DSC_INIT16);
1037
1038 if (unlikely(++ring_num == tx_ring->count))
1039 ring_num = 0;
1040
1041 /* Update software pointer of TX descriptor */
1042 iowrite32(tx_ring->dma +
1043 (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1044 &hw->reg->TX_DSC_SW_P);
1045 dev_kfree_skb_any(skb);
1046}
1047
1048/**
1049 * pch_gbe_update_stats - Update the board statistics counters
1050 * @adapter: Board private structure
1051 */
1052void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1053{
1054 struct net_device *netdev = adapter->netdev;
1055 struct pci_dev *pdev = adapter->pdev;
1056 struct pch_gbe_hw_stats *stats = &adapter->stats;
1057 unsigned long flags;
1058
1059 /*
1060 * Prevent stats update while adapter is being reset, or if the pci
1061 * connection is down.
1062 */
1063 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1064 return;
1065
1066 spin_lock_irqsave(&adapter->stats_lock, flags);
1067
1068 /* Update device status "adapter->stats" */
1069 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1070 stats->tx_errors = stats->tx_length_errors +
1071 stats->tx_aborted_errors +
1072 stats->tx_carrier_errors + stats->tx_timeout_count;
1073
1074 /* Update network device status "adapter->net_stats" */
1075 netdev->stats.rx_packets = stats->rx_packets;
1076 netdev->stats.rx_bytes = stats->rx_bytes;
1077 netdev->stats.rx_dropped = stats->rx_dropped;
1078 netdev->stats.tx_packets = stats->tx_packets;
1079 netdev->stats.tx_bytes = stats->tx_bytes;
1080 netdev->stats.tx_dropped = stats->tx_dropped;
1081 /* Fill out the OS statistics structure */
1082 netdev->stats.multicast = stats->multicast;
1083 netdev->stats.collisions = stats->collisions;
1084 /* Rx Errors */
1085 netdev->stats.rx_errors = stats->rx_errors;
1086 netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1087 netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1088 /* Tx Errors */
1089 netdev->stats.tx_errors = stats->tx_errors;
1090 netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1091 netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1092
1093 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1094}
1095
1096/**
1097 * pch_gbe_intr - Interrupt Handler
1098 * @irq: Interrupt number
1099 * @data: Pointer to a network interface device structure
1100 * Returns
1101 * - IRQ_HANDLED: Our interrupt
1102 * - IRQ_NONE: Not our interrupt
1103 */
1104static irqreturn_t pch_gbe_intr(int irq, void *data)
1105{
1106 struct net_device *netdev = data;
1107 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1108 struct pch_gbe_hw *hw = &adapter->hw;
1109 u32 int_st;
1110 u32 int_en;
1111
1112 /* Check request status */
1113 int_st = ioread32(&hw->reg->INT_ST);
1114 int_st = int_st & ioread32(&hw->reg->INT_EN);
1115 /* When request status is no interruption factor */
1116 if (unlikely(!int_st))
1117 return IRQ_NONE; /* Not our interrupt. End processing. */
1118 pr_debug("%s occur int_st = 0x%08x\n", __func__, int_st);
1119 if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1120 adapter->stats.intr_rx_frame_err_count++;
1121 if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1122 adapter->stats.intr_rx_fifo_err_count++;
1123 if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1124 adapter->stats.intr_rx_dma_err_count++;
1125 if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1126 adapter->stats.intr_tx_fifo_err_count++;
1127 if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1128 adapter->stats.intr_tx_dma_err_count++;
1129 if (int_st & PCH_GBE_INT_TCPIP_ERR)
1130 adapter->stats.intr_tcpip_err_count++;
1131 /* When Rx descriptor is empty */
1132 if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1133 adapter->stats.intr_rx_dsc_empty_count++;
1134 pr_err("Rx descriptor is empty\n");
1135 int_en = ioread32(&hw->reg->INT_EN);
1136 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1137 if (hw->mac.tx_fc_enable) {
1138 /* Set Pause packet */
1139 pch_gbe_mac_set_pause_packet(hw);
1140 }
1141 if ((int_en & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))
1142 == 0) {
1143 return IRQ_HANDLED;
1144 }
1145 }
1146
1147 /* When request status is Receive interruption */
1148 if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))) {
1149 if (likely(napi_schedule_prep(&adapter->napi))) {
1150 /* Enable only Rx Descriptor empty */
1151 atomic_inc(&adapter->irq_sem);
1152 int_en = ioread32(&hw->reg->INT_EN);
1153 int_en &=
1154 ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1155 iowrite32(int_en, &hw->reg->INT_EN);
1156 /* Start polling for NAPI */
1157 __napi_schedule(&adapter->napi);
1158 }
1159 }
1160 pr_debug("return = 0x%08x INT_EN reg = 0x%08x\n",
1161 IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1162 return IRQ_HANDLED;
1163}
1164
1165/**
1166 * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1167 * @adapter: Board private structure
1168 * @rx_ring: Rx descriptor ring
1169 * @cleaned_count: Cleaned count
1170 */
1171static void
1172pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1173 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1174{
1175 struct net_device *netdev = adapter->netdev;
1176 struct pci_dev *pdev = adapter->pdev;
1177 struct pch_gbe_hw *hw = &adapter->hw;
1178 struct pch_gbe_rx_desc *rx_desc;
1179 struct pch_gbe_buffer *buffer_info;
1180 struct sk_buff *skb;
1181 unsigned int i;
1182 unsigned int bufsz;
1183
1184 bufsz = adapter->rx_buffer_len + PCH_GBE_DMA_ALIGN;
1185 i = rx_ring->next_to_use;
1186
1187 while ((cleaned_count--)) {
1188 buffer_info = &rx_ring->buffer_info[i];
1189 skb = buffer_info->skb;
1190 if (skb) {
1191 skb_trim(skb, 0);
1192 } else {
1193 skb = netdev_alloc_skb(netdev, bufsz);
1194 if (unlikely(!skb)) {
1195 /* Better luck next round */
1196 adapter->stats.rx_alloc_buff_failed++;
1197 break;
1198 }
1199 /* 64byte align */
1200 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1201
1202 buffer_info->skb = skb;
1203 buffer_info->length = adapter->rx_buffer_len;
1204 }
1205 buffer_info->dma = dma_map_single(&pdev->dev,
1206 skb->data,
1207 buffer_info->length,
1208 DMA_FROM_DEVICE);
1209 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1210 dev_kfree_skb(skb);
1211 buffer_info->skb = NULL;
1212 buffer_info->dma = 0;
1213 adapter->stats.rx_alloc_buff_failed++;
1214 break; /* while !buffer_info->skb */
1215 }
1216 buffer_info->mapped = true;
1217 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1218 rx_desc->buffer_addr = (buffer_info->dma);
1219 rx_desc->gbec_status = DSC_INIT16;
1220
1221 pr_debug("i = %d buffer_info->dma = 0x08%llx buffer_info->length = 0x%x\n",
1222 i, (unsigned long long)buffer_info->dma,
1223 buffer_info->length);
1224
1225 if (unlikely(++i == rx_ring->count))
1226 i = 0;
1227 }
1228 if (likely(rx_ring->next_to_use != i)) {
1229 rx_ring->next_to_use = i;
1230 if (unlikely(i-- == 0))
1231 i = (rx_ring->count - 1);
1232 iowrite32(rx_ring->dma +
1233 (int)sizeof(struct pch_gbe_rx_desc) * i,
1234 &hw->reg->RX_DSC_SW_P);
1235 }
1236 return;
1237}
1238
1239/**
1240 * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1241 * @adapter: Board private structure
1242 * @tx_ring: Tx descriptor ring
1243 */
1244static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1245 struct pch_gbe_tx_ring *tx_ring)
1246{
1247 struct pch_gbe_buffer *buffer_info;
1248 struct sk_buff *skb;
1249 unsigned int i;
1250 unsigned int bufsz;
1251 struct pch_gbe_tx_desc *tx_desc;
1252
1253 bufsz =
1254 adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1255
1256 for (i = 0; i < tx_ring->count; i++) {
1257 buffer_info = &tx_ring->buffer_info[i];
1258 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1259 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1260 buffer_info->skb = skb;
1261 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1262 tx_desc->gbec_status = (DSC_INIT16);
1263 }
1264 return;
1265}
1266
1267/**
1268 * pch_gbe_clean_tx - Reclaim resources after transmit completes
1269 * @adapter: Board private structure
1270 * @tx_ring: Tx descriptor ring
1271 * Returns
1272 * true: Cleaned the descriptor
1273 * false: Not cleaned the descriptor
1274 */
1275static bool
1276pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1277 struct pch_gbe_tx_ring *tx_ring)
1278{
1279 struct pch_gbe_tx_desc *tx_desc;
1280 struct pch_gbe_buffer *buffer_info;
1281 struct sk_buff *skb;
1282 unsigned int i;
1283 unsigned int cleaned_count = 0;
1284 bool cleaned = false;
1285
1286 pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1287
1288 i = tx_ring->next_to_clean;
1289 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1290 pr_debug("gbec_status:0x%04x dma_status:0x%04x\n",
1291 tx_desc->gbec_status, tx_desc->dma_status);
1292
1293 while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1294 pr_debug("gbec_status:0x%04x\n", tx_desc->gbec_status);
1295 cleaned = true;
1296 buffer_info = &tx_ring->buffer_info[i];
1297 skb = buffer_info->skb;
1298
1299 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1300 adapter->stats.tx_aborted_errors++;
1301 pr_err("Transfer Abort Error\n");
1302 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1303 ) {
1304 adapter->stats.tx_carrier_errors++;
1305 pr_err("Transfer Carrier Sense Error\n");
1306 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1307 ) {
1308 adapter->stats.tx_aborted_errors++;
1309 pr_err("Transfer Collision Abort Error\n");
1310 } else if ((tx_desc->gbec_status &
1311 (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1312 PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1313 adapter->stats.collisions++;
1314 adapter->stats.tx_packets++;
1315 adapter->stats.tx_bytes += skb->len;
1316 pr_debug("Transfer Collision\n");
1317 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1318 ) {
1319 adapter->stats.tx_packets++;
1320 adapter->stats.tx_bytes += skb->len;
1321 }
1322 if (buffer_info->mapped) {
1323 pr_debug("unmap buffer_info->dma : %d\n", i);
1324 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1325 buffer_info->length, DMA_TO_DEVICE);
1326 buffer_info->mapped = false;
1327 }
1328 if (buffer_info->skb) {
1329 pr_debug("trim buffer_info->skb : %d\n", i);
1330 skb_trim(buffer_info->skb, 0);
1331 }
1332 tx_desc->gbec_status = DSC_INIT16;
1333 if (unlikely(++i == tx_ring->count))
1334 i = 0;
1335 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1336
1337 /* weight of a sort for tx, to avoid endless transmit cleanup */
1338 if (cleaned_count++ == PCH_GBE_TX_WEIGHT)
1339 break;
1340 }
1341 pr_debug("called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1342 cleaned_count);
1343 /* Recover from running out of Tx resources in xmit_frame */
1344 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev)))) {
1345 netif_wake_queue(adapter->netdev);
1346 adapter->stats.tx_restart_count++;
1347 pr_debug("Tx wake queue\n");
1348 }
1349 spin_lock(&adapter->tx_queue_lock);
1350 tx_ring->next_to_clean = i;
1351 spin_unlock(&adapter->tx_queue_lock);
1352 pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1353 return cleaned;
1354}
1355
1356/**
1357 * pch_gbe_clean_rx - Send received data up the network stack; legacy
1358 * @adapter: Board private structure
1359 * @rx_ring: Rx descriptor ring
1360 * @work_done: Completed count
1361 * @work_to_do: Request count
1362 * Returns
1363 * true: Cleaned the descriptor
1364 * false: Not cleaned the descriptor
1365 */
1366static bool
1367pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1368 struct pch_gbe_rx_ring *rx_ring,
1369 int *work_done, int work_to_do)
1370{
1371 struct net_device *netdev = adapter->netdev;
1372 struct pci_dev *pdev = adapter->pdev;
1373 struct pch_gbe_buffer *buffer_info;
1374 struct pch_gbe_rx_desc *rx_desc;
1375 u32 length;
77555ee7
MO		 1376 unsigned int i;
1377 unsigned int cleaned_count = 0;
1378 bool cleaned = false;
ac096642 1379 struct sk_buff *skb, *new_skb;
77555ee7
MO		 1380 u8 dma_status;
1381 u16 gbec_status;
1382 u32 tcp_ip_status;
77555ee7
MO		 1383
1384 i = rx_ring->next_to_clean;
1385
1386 while (*work_done < work_to_do) {
1387 /* Check Rx descriptor status */
1388 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1389 if (rx_desc->gbec_status == DSC_INIT16)
1390 break;
1391 cleaned = true;
1392 cleaned_count++;
1393
1394 dma_status = rx_desc->dma_status;
1395 gbec_status = rx_desc->gbec_status;
1396 tcp_ip_status = rx_desc->tcp_ip_status;
1397 rx_desc->gbec_status = DSC_INIT16;
1398 buffer_info = &rx_ring->buffer_info[i];
1399 skb = buffer_info->skb;
1400
1401 /* unmap dma */
1402 dma_unmap_single(&pdev->dev, buffer_info->dma,
1403 buffer_info->length, DMA_FROM_DEVICE);
1404 buffer_info->mapped = false;
1405 /* Prefetch the packet */
1406 prefetch(skb->data);
1407
1408 pr_debug("RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x "
1409 "TCP:0x%08x] BufInf = 0x%p\n",
1410 i, dma_status, gbec_status, tcp_ip_status,
1411 buffer_info);
1412 /* Error check */
1413 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1414 adapter->stats.rx_frame_errors++;
1415 pr_err("Receive Not Octal Error\n");
1416 } else if (unlikely(gbec_status &
1417 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1418 adapter->stats.rx_frame_errors++;
1419 pr_err("Receive Nibble Error\n");
1420 } else if (unlikely(gbec_status &
1421 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1422 adapter->stats.rx_crc_errors++;
1423 pr_err("Receive CRC Error\n");
1424 } else {
1425 /* get receive length */
ac096642
TO		 1426 /* length convert[-3] */
1427 length = (rx_desc->rx_words_eob) - 3;
77555ee7
MO		 1428
1429 /* Decide the data conversion method */
756a6b03 1430 if (!(netdev->features & NETIF_F_RXCSUM)) {
77555ee7 1431 /* [Header:14][payload] */
ac096642
TO		 1432 if (NET_IP_ALIGN) {
1433 /* Because alignment differs,
1434 * the new_skb is newly allocated,
1435 * and data is copied to new_skb.*/
1436 new_skb = netdev_alloc_skb(netdev,
1437 length + NET_IP_ALIGN);
1438 if (!new_skb) {
1439 /* dorrop error */
1440 pr_err("New skb allocation "
1441 "Error\n");
1442 goto dorrop;
1443 }
1444 skb_reserve(new_skb, NET_IP_ALIGN);
1445 memcpy(new_skb->data, skb->data,
1446 length);
1447 skb = new_skb;
1448 } else {
1449 /* DMA buffer is used as SKB as it is.*/
1450 buffer_info->skb = NULL;
1451 }
77555ee7
MO		 1452 } else {
1453 /* [Header:14][padding:2][payload] */
ac096642
TO		 1454 /* The length includes padding length */
1455 length = length - PCH_GBE_DMA_PADDING;
1456 if ((length < copybreak) ||
1457 (NET_IP_ALIGN != PCH_GBE_DMA_PADDING)) {
1458 /* Because alignment differs,
1459 * the new_skb is newly allocated,
1460 * and data is copied to new_skb.
1461 * Padding data is deleted
1462 * at the time of a copy.*/
1463 new_skb = netdev_alloc_skb(netdev,
1464 length + NET_IP_ALIGN);
1465 if (!new_skb) {
1466 /* dorrop error */
1467 pr_err("New skb allocation "
1468 "Error\n");
1469 goto dorrop;
77555ee7 1470 }
ac096642 1471 skb_reserve(new_skb, NET_IP_ALIGN);
77555ee7 1472 memcpy(new_skb->data, skb->data,
ac096642
TO		 1473 ETH_HLEN);
1474 memcpy(&new_skb->data[ETH_HLEN],
1475 &skb->data[ETH_HLEN +
1476 PCH_GBE_DMA_PADDING],
1477 length - ETH_HLEN);
77555ee7 1478 skb = new_skb;
ac096642
TO		 1479 } else {
1480 /* Padding data is deleted
1481 * by moving header data.*/
1482 memmove(&skb->data[PCH_GBE_DMA_PADDING],
1483 &skb->data[0], ETH_HLEN);
1484 skb_reserve(skb, NET_IP_ALIGN);
1485 buffer_info->skb = NULL;
77555ee7 1486 }
77555ee7 1487 }
ac096642
TO		 1488 /* The length includes FCS length */
1489 length = length - ETH_FCS_LEN;
77555ee7
MO		 1490 /* update status of driver */
1491 adapter->stats.rx_bytes += length;
1492 adapter->stats.rx_packets++;
1493 if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1494 adapter->stats.multicast++;
1495 /* Write meta date of skb */
1496 skb_put(skb, length);
1497 skb->protocol = eth_type_trans(skb, netdev);
1498 if ((tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK) ==
1499 PCH_GBE_RXD_ACC_STAT_TCPIPOK) {
1500 skb->ip_summed = CHECKSUM_UNNECESSARY;
1501 } else {
1502 skb->ip_summed = CHECKSUM_NONE;
1503 }
1504 napi_gro_receive(&adapter->napi, skb);
1505 (*work_done)++;
1506 pr_debug("Receive skb->ip_summed: %d length: %d\n",
1507 skb->ip_summed, length);
1508 }
1509dorrop:
1510 /* return some buffers to hardware, one at a time is too slow */
1511 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1512 pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1513 cleaned_count);
1514 cleaned_count = 0;
1515 }
1516 if (++i == rx_ring->count)
1517 i = 0;
1518 }
1519 rx_ring->next_to_clean = i;
1520 if (cleaned_count)
1521 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1522 return cleaned;
1523}
1524
1525/**
1526 * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1527 * @adapter: Board private structure
1528 * @tx_ring: Tx descriptor ring (for a specific queue) to setup
1529 * Returns
1530 * 0: Successfully
1531 * Negative value: Failed
1532 */
1533int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1534 struct pch_gbe_tx_ring *tx_ring)
1535{
1536 struct pci_dev *pdev = adapter->pdev;
1537 struct pch_gbe_tx_desc *tx_desc;
1538 int size;
1539 int desNo;
1540
1541 size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
89bf67f1 1542 tx_ring->buffer_info = vzalloc(size);
77555ee7 1543 if (!tx_ring->buffer_info) {
25985edc 1544 pr_err("Unable to allocate memory for the buffer information\n");
77555ee7
MO		 1545 return -ENOMEM;
1546 }
77555ee7
MO		 1547
1548 tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1549
1550 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
1551 &tx_ring->dma, GFP_KERNEL);
1552 if (!tx_ring->desc) {
1553 vfree(tx_ring->buffer_info);
1554 pr_err("Unable to allocate memory for the transmit descriptor ring\n");
1555 return -ENOMEM;
1556 }
1557 memset(tx_ring->desc, 0, tx_ring->size);
1558
1559 tx_ring->next_to_use = 0;
1560 tx_ring->next_to_clean = 0;
1561 spin_lock_init(&tx_ring->tx_lock);
1562
1563 for (desNo = 0; desNo < tx_ring->count; desNo++) {
1564 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1565 tx_desc->gbec_status = DSC_INIT16;
1566 }
1567 pr_debug("tx_ring->desc = 0x%p tx_ring->dma = 0x%08llx\n"
1568 "next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1569 tx_ring->desc, (unsigned long long)tx_ring->dma,
1570 tx_ring->next_to_clean, tx_ring->next_to_use);
1571 return 0;
1572}
1573
1574/**
1575 * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1576 * @adapter: Board private structure
1577 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1578 * Returns
1579 * 0: Successfully
1580 * Negative value: Failed
1581 */
1582int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1583 struct pch_gbe_rx_ring *rx_ring)
1584{
1585 struct pci_dev *pdev = adapter->pdev;
1586 struct pch_gbe_rx_desc *rx_desc;
1587 int size;
1588 int desNo;
1589
1590 size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
89bf67f1 1591 rx_ring->buffer_info = vzalloc(size);
77555ee7
MO		 1592 if (!rx_ring->buffer_info) {
1593 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1594 return -ENOMEM;
1595 }
77555ee7
MO		 1596 rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1597 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
1598 &rx_ring->dma, GFP_KERNEL);
1599
1600 if (!rx_ring->desc) {
1601 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1602 vfree(rx_ring->buffer_info);
1603 return -ENOMEM;
1604 }
1605 memset(rx_ring->desc, 0, rx_ring->size);
1606 rx_ring->next_to_clean = 0;
1607 rx_ring->next_to_use = 0;
1608 for (desNo = 0; desNo < rx_ring->count; desNo++) {
1609 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1610 rx_desc->gbec_status = DSC_INIT16;
1611 }
1612 pr_debug("rx_ring->desc = 0x%p rx_ring->dma = 0x%08llx "
1613 "next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1614 rx_ring->desc, (unsigned long long)rx_ring->dma,
1615 rx_ring->next_to_clean, rx_ring->next_to_use);
1616 return 0;
1617}
1618
1619/**
1620 * pch_gbe_free_tx_resources - Free Tx Resources
1621 * @adapter: Board private structure
1622 * @tx_ring: Tx descriptor ring for a specific queue
1623 */
1624void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1625 struct pch_gbe_tx_ring *tx_ring)
1626{
1627 struct pci_dev *pdev = adapter->pdev;
1628
1629 pch_gbe_clean_tx_ring(adapter, tx_ring);
1630 vfree(tx_ring->buffer_info);
1631 tx_ring->buffer_info = NULL;
1632 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1633 tx_ring->desc = NULL;
1634}
1635
1636/**
1637 * pch_gbe_free_rx_resources - Free Rx Resources
1638 * @adapter: Board private structure
1639 * @rx_ring: Ring to clean the resources from
1640 */
1641void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1642 struct pch_gbe_rx_ring *rx_ring)
1643{
1644 struct pci_dev *pdev = adapter->pdev;
1645
1646 pch_gbe_clean_rx_ring(adapter, rx_ring);
1647 vfree(rx_ring->buffer_info);
1648 rx_ring->buffer_info = NULL;
1649 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1650 rx_ring->desc = NULL;
1651}
1652
1653/**
1654 * pch_gbe_request_irq - Allocate an interrupt line
1655 * @adapter: Board private structure
1656 * Returns
1657 * 0: Successfully
1658 * Negative value: Failed
1659 */
1660static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1661{
1662 struct net_device *netdev = adapter->netdev;
1663 int err;
1664 int flags;
1665
1666 flags = IRQF_SHARED;
1667 adapter->have_msi = false;
1668 err = pci_enable_msi(adapter->pdev);
1669 pr_debug("call pci_enable_msi\n");
1670 if (err) {
1671 pr_debug("call pci_enable_msi - Error: %d\n", err);
1672 } else {
1673 flags = 0;
1674 adapter->have_msi = true;
1675 }
1676 err = request_irq(adapter->pdev->irq, &pch_gbe_intr,
1677 flags, netdev->name, netdev);
1678 if (err)
1679 pr_err("Unable to allocate interrupt Error: %d\n", err);
1680 pr_debug("adapter->have_msi : %d flags : 0x%04x return : 0x%04x\n",
1681 adapter->have_msi, flags, err);
1682 return err;
1683}
1684
1685
1686static void pch_gbe_set_multi(struct net_device *netdev);
1687/**
1688 * pch_gbe_up - Up GbE network device
1689 * @adapter: Board private structure
1690 * Returns
1691 * 0: Successfully
1692 * Negative value: Failed
1693 */
1694int pch_gbe_up(struct pch_gbe_adapter *adapter)
1695{
1696 struct net_device *netdev = adapter->netdev;
1697 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1698 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1699 int err;
1700
1701 /* hardware has been reset, we need to reload some things */
1702 pch_gbe_set_multi(netdev);
1703
1704 pch_gbe_setup_tctl(adapter);
1705 pch_gbe_configure_tx(adapter);
1706 pch_gbe_setup_rctl(adapter);
1707 pch_gbe_configure_rx(adapter);
1708
1709 err = pch_gbe_request_irq(adapter);
1710 if (err) {
1711 pr_err("Error: can't bring device up\n");
1712 return err;
1713 }
1714 pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1715 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1716 adapter->tx_queue_len = netdev->tx_queue_len;
1717
1718 mod_timer(&adapter->watchdog_timer, jiffies);
1719
1720 napi_enable(&adapter->napi);
1721 pch_gbe_irq_enable(adapter);
1722 netif_start_queue(adapter->netdev);
1723
1724 return 0;
1725}
1726
1727/**
1728 * pch_gbe_down - Down GbE network device
1729 * @adapter: Board private structure
1730 */
1731void pch_gbe_down(struct pch_gbe_adapter *adapter)
1732{
1733 struct net_device *netdev = adapter->netdev;
1734
1735 /* signal that we're down so the interrupt handler does not
1736 * reschedule our watchdog timer */
1737 napi_disable(&adapter->napi);
1738 atomic_set(&adapter->irq_sem, 0);
1739
1740 pch_gbe_irq_disable(adapter);
1741 pch_gbe_free_irq(adapter);
1742
1743 del_timer_sync(&adapter->watchdog_timer);
1744
1745 netdev->tx_queue_len = adapter->tx_queue_len;
1746 netif_carrier_off(netdev);
1747 netif_stop_queue(netdev);
1748
1749 pch_gbe_reset(adapter);
1750 pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
1751 pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
1752}
1753
1754/**
1755 * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
1756 * @adapter: Board private structure to initialize
1757 * Returns
1758 * 0: Successfully
1759 * Negative value: Failed
1760 */
1761static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
1762{
1763 struct pch_gbe_hw *hw = &adapter->hw;
1764 struct net_device *netdev = adapter->netdev;
1765
1766 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
1767 hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1768 hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1769
1770 /* Initialize the hardware-specific values */
1771 if (pch_gbe_hal_setup_init_funcs(hw)) {
1772 pr_err("Hardware Initialization Failure\n");
1773 return -EIO;
1774 }
1775 if (pch_gbe_alloc_queues(adapter)) {
1776 pr_err("Unable to allocate memory for queues\n");
1777 return -ENOMEM;
1778 }
1779 spin_lock_init(&adapter->hw.miim_lock);
1780 spin_lock_init(&adapter->tx_queue_lock);
1781 spin_lock_init(&adapter->stats_lock);
1782 spin_lock_init(&adapter->ethtool_lock);
1783 atomic_set(&adapter->irq_sem, 0);
1784 pch_gbe_irq_disable(adapter);
1785
1786 pch_gbe_init_stats(adapter);
1787
1788 pr_debug("rx_buffer_len : %d mac.min_frame_size : %d mac.max_frame_size : %d\n",
1789 (u32) adapter->rx_buffer_len,
1790 hw->mac.min_frame_size, hw->mac.max_frame_size);
1791 return 0;
1792}
1793
1794/**
1795 * pch_gbe_open - Called when a network interface is made active
1796 * @netdev: Network interface device structure
1797 * Returns
1798 * 0: Successfully
1799 * Negative value: Failed
1800 */
1801static int pch_gbe_open(struct net_device *netdev)
1802{
1803 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1804 struct pch_gbe_hw *hw = &adapter->hw;
1805 int err;
1806
1807 /* allocate transmit descriptors */
1808 err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
1809 if (err)
1810 goto err_setup_tx;
1811 /* allocate receive descriptors */
1812 err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
1813 if (err)
1814 goto err_setup_rx;
1815 pch_gbe_hal_power_up_phy(hw);
1816 err = pch_gbe_up(adapter);
1817 if (err)
1818 goto err_up;
1819 pr_debug("Success End\n");
1820 return 0;
1821
1822err_up:
1823 if (!adapter->wake_up_evt)
1824 pch_gbe_hal_power_down_phy(hw);
1825 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1826err_setup_rx:
1827 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1828err_setup_tx:
1829 pch_gbe_reset(adapter);
1830 pr_err("Error End\n");
1831 return err;
1832}
1833
1834/**
1835 * pch_gbe_stop - Disables a network interface
1836 * @netdev: Network interface device structure
1837 * Returns
1838 * 0: Successfully
1839 */
1840static int pch_gbe_stop(struct net_device *netdev)
1841{
1842 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1843 struct pch_gbe_hw *hw = &adapter->hw;
1844
1845 pch_gbe_down(adapter);
1846 if (!adapter->wake_up_evt)
1847 pch_gbe_hal_power_down_phy(hw);
1848 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1849 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1850 return 0;
1851}
1852
1853/**
1854 * pch_gbe_xmit_frame - Packet transmitting start
1855 * @skb: Socket buffer structure
1856 * @netdev: Network interface device structure
1857 * Returns
1858 * - NETDEV_TX_OK: Normal end
1859 * - NETDEV_TX_BUSY: Error end
1860 */
1861static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1862{
1863 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1864 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1865 unsigned long flags;
1866
1867 if (unlikely(skb->len > (adapter->hw.mac.max_frame_size - 4))) {
77555ee7
MO		 1868 pr_err("Transfer length Error: skb len: %d > max: %d\n",
1869 skb->len, adapter->hw.mac.max_frame_size);
419c2046 1870 dev_kfree_skb_any(skb);
77555ee7
MO		 1871 adapter->stats.tx_length_errors++;
1872 return NETDEV_TX_OK;
1873 }
1874 if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags)) {
1875 /* Collision - tell upper layer to requeue */
1876 return NETDEV_TX_LOCKED;
1877 }
1878 if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
1879 netif_stop_queue(netdev);
1880 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1881 pr_debug("Return : BUSY next_to use : 0x%08x next_to clean : 0x%08x\n",
1882 tx_ring->next_to_use, tx_ring->next_to_clean);
1883 return NETDEV_TX_BUSY;
1884 }
1885 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1886
1887 /* CRC,ITAG no support */
1888 pch_gbe_tx_queue(adapter, tx_ring, skb);
1889 return NETDEV_TX_OK;
1890}
1891
1892/**
1893 * pch_gbe_get_stats - Get System Network Statistics
1894 * @netdev: Network interface device structure
1895 * Returns: The current stats
1896 */
1897static struct net_device_stats *pch_gbe_get_stats(struct net_device *netdev)
1898{
1899 /* only return the current stats */
1900 return &netdev->stats;
1901}
1902
1903/**
1904 * pch_gbe_set_multi - Multicast and Promiscuous mode set
1905 * @netdev: Network interface device structure
1906 */
1907static void pch_gbe_set_multi(struct net_device *netdev)
1908{
1909 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1910 struct pch_gbe_hw *hw = &adapter->hw;
1911 struct netdev_hw_addr *ha;
1912 u8 *mta_list;
1913 u32 rctl;
1914 int i;
1915 int mc_count;
1916
1917 pr_debug("netdev->flags : 0x%08x\n", netdev->flags);
1918
1919 /* Check for Promiscuous and All Multicast modes */
1920 rctl = ioread32(&hw->reg->RX_MODE);
1921 mc_count = netdev_mc_count(netdev);
1922 if ((netdev->flags & IFF_PROMISC)) {
1923 rctl &= ~PCH_GBE_ADD_FIL_EN;
1924 rctl &= ~PCH_GBE_MLT_FIL_EN;
1925 } else if ((netdev->flags & IFF_ALLMULTI)) {
1926 /* all the multicasting receive permissions */
1927 rctl |= PCH_GBE_ADD_FIL_EN;
1928 rctl &= ~PCH_GBE_MLT_FIL_EN;
1929 } else {
1930 if (mc_count >= PCH_GBE_MAR_ENTRIES) {
1931 /* all the multicasting receive permissions */
1932 rctl |= PCH_GBE_ADD_FIL_EN;
1933 rctl &= ~PCH_GBE_MLT_FIL_EN;
1934 } else {
1935 rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
1936 }
1937 }
1938 iowrite32(rctl, &hw->reg->RX_MODE);
1939
1940 if (mc_count >= PCH_GBE_MAR_ENTRIES)
1941 return;
1942 mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC);
1943 if (!mta_list)
1944 return;
1945
1946 /* The shared function expects a packed array of only addresses. */
1947 i = 0;
1948 netdev_for_each_mc_addr(ha, netdev) {
1949 if (i == mc_count)
1950 break;
1951 memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
1952 }
1953 pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
1954 PCH_GBE_MAR_ENTRIES);
1955 kfree(mta_list);
1956
1957 pr_debug("RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x netdev->mc_count : 0x%08x\n",
1958 ioread32(&hw->reg->RX_MODE), mc_count);
1959}
1960
1961/**
1962 * pch_gbe_set_mac - Change the Ethernet Address of the NIC
1963 * @netdev: Network interface device structure
1964 * @addr: Pointer to an address structure
1965 * Returns
1966 * 0: Successfully
1967 * -EADDRNOTAVAIL: Failed
1968 */
1969static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
1970{
1971 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1972 struct sockaddr *skaddr = addr;
1973 int ret_val;
1974
1975 if (!is_valid_ether_addr(skaddr->sa_data)) {
1976 ret_val = -EADDRNOTAVAIL;
1977 } else {
1978 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
1979 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
1980 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1981 ret_val = 0;
1982 }
1983 pr_debug("ret_val : 0x%08x\n", ret_val);
1984 pr_debug("dev_addr : %pM\n", netdev->dev_addr);
1985 pr_debug("mac_addr : %pM\n", adapter->hw.mac.addr);
1986 pr_debug("MAC_ADR1AB reg : 0x%08x 0x%08x\n",
1987 ioread32(&adapter->hw.reg->mac_adr[0].high),
1988 ioread32(&adapter->hw.reg->mac_adr[0].low));
1989 return ret_val;
1990}
1991
1992/**
1993 * pch_gbe_change_mtu - Change the Maximum Transfer Unit
1994 * @netdev: Network interface device structure
1995 * @new_mtu: New value for maximum frame size
1996 * Returns
1997 * 0: Successfully
1998 * -EINVAL: Failed
1999 */
2000static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2001{
2002 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2003 int max_frame;
2004
2005 max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2006 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2007 (max_frame > PCH_GBE_MAX_JUMBO_FRAME_SIZE)) {
2008 pr_err("Invalid MTU setting\n");
2009 return -EINVAL;
2010 }
2011 if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2012 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2013 else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2014 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2015 else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2016 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2017 else
2018 adapter->rx_buffer_len = PCH_GBE_MAX_JUMBO_FRAME_SIZE;
2019 netdev->mtu = new_mtu;
2020 adapter->hw.mac.max_frame_size = max_frame;
2021
2022 if (netif_running(netdev))
2023 pch_gbe_reinit_locked(adapter);
2024 else
2025 pch_gbe_reset(adapter);
2026
2027 pr_debug("max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n",
2028 max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2029 adapter->hw.mac.max_frame_size);
2030 return 0;
2031}
2032
756a6b03
MM		 2033/**
2034 * pch_gbe_set_features - Reset device after features changed
2035 * @netdev: Network interface device structure
2036 * @features: New features
2037 * Returns
2038 * 0: HW state updated successfully
2039 */
2040static int pch_gbe_set_features(struct net_device *netdev, u32 features)
2041{
2042 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2043 u32 changed = features ^ netdev->features;
2044
2045 if (!(changed & NETIF_F_RXCSUM))
2046 return 0;
2047
2048 if (netif_running(netdev))
2049 pch_gbe_reinit_locked(adapter);
2050 else
2051 pch_gbe_reset(adapter);
2052
2053 return 0;
2054}
2055
77555ee7
MO		 2056/**
2057 * pch_gbe_ioctl - Controls register through a MII interface
2058 * @netdev: Network interface device structure
2059 * @ifr: Pointer to ifr structure
2060 * @cmd: Control command
2061 * Returns
2062 * 0: Successfully
2063 * Negative value: Failed
2064 */
2065static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2066{
2067 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2068
2069 pr_debug("cmd : 0x%04x\n", cmd);
2070
2071 return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2072}
2073
2074/**
2075 * pch_gbe_tx_timeout - Respond to a Tx Hang
2076 * @netdev: Network interface device structure
2077 */
2078static void pch_gbe_tx_timeout(struct net_device *netdev)
2079{
2080 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2081
2082 /* Do the reset outside of interrupt context */
2083 adapter->stats.tx_timeout_count++;
2084 schedule_work(&adapter->reset_task);
2085}
2086
2087/**
2088 * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2089 * @napi: Pointer of polling device struct
2090 * @budget: The maximum number of a packet
2091 * Returns
2092 * false: Exit the polling mode
2093 * true: Continue the polling mode
2094 */
2095static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2096{
2097 struct pch_gbe_adapter *adapter =
2098 container_of(napi, struct pch_gbe_adapter, napi);
2099 struct net_device *netdev = adapter->netdev;
2100 int work_done = 0;
2101 bool poll_end_flag = false;
2102 bool cleaned = false;
2103
2104 pr_debug("budget : %d\n", budget);
2105
2106 /* Keep link state information with original netdev */
2107 if (!netif_carrier_ok(netdev)) {
2108 poll_end_flag = true;
2109 } else {
2110 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2111 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2112
2113 if (cleaned)
2114 work_done = budget;
2115 /* If no Tx and not enough Rx work done,
2116 * exit the polling mode
2117 */
2118 if ((work_done < budget) || !netif_running(netdev))
2119 poll_end_flag = true;
2120 }
2121
2122 if (poll_end_flag) {
2123 napi_complete(napi);
2124 pch_gbe_irq_enable(adapter);
2125 }
2126
2127 pr_debug("poll_end_flag : %d work_done : %d budget : %d\n",
2128 poll_end_flag, work_done, budget);
2129
2130 return work_done;
2131}
2132
2133#ifdef CONFIG_NET_POLL_CONTROLLER
2134/**
2135 * pch_gbe_netpoll - Used by things like netconsole to send skbs
2136 * @netdev: Network interface device structure
2137 */
2138static void pch_gbe_netpoll(struct net_device *netdev)
2139{
2140 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2141
2142 disable_irq(adapter->pdev->irq);
2143 pch_gbe_intr(adapter->pdev->irq, netdev);
2144 enable_irq(adapter->pdev->irq);
2145}
2146#endif
2147
2148static const struct net_device_ops pch_gbe_netdev_ops = {
2149 .ndo_open = pch_gbe_open,
2150 .ndo_stop = pch_gbe_stop,
2151 .ndo_start_xmit = pch_gbe_xmit_frame,
2152 .ndo_get_stats = pch_gbe_get_stats,
2153 .ndo_set_mac_address = pch_gbe_set_mac,
2154 .ndo_tx_timeout = pch_gbe_tx_timeout,
2155 .ndo_change_mtu = pch_gbe_change_mtu,
756a6b03 2156 .ndo_set_features = pch_gbe_set_features,
77555ee7
MO		 2157 .ndo_do_ioctl = pch_gbe_ioctl,
2158 .ndo_set_multicast_list = &pch_gbe_set_multi,
2159#ifdef CONFIG_NET_POLL_CONTROLLER
2160 .ndo_poll_controller = pch_gbe_netpoll,
2161#endif
2162};
2163
2164static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2165 pci_channel_state_t state)
2166{
2167 struct net_device *netdev = pci_get_drvdata(pdev);
2168 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2169
2170 netif_device_detach(netdev);
2171 if (netif_running(netdev))
2172 pch_gbe_down(adapter);
2173 pci_disable_device(pdev);
2174 /* Request a slot slot reset. */
2175 return PCI_ERS_RESULT_NEED_RESET;
2176}
2177
2178static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2179{
2180 struct net_device *netdev = pci_get_drvdata(pdev);
2181 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2182 struct pch_gbe_hw *hw = &adapter->hw;
2183
2184 if (pci_enable_device(pdev)) {
2185 pr_err("Cannot re-enable PCI device after reset\n");
2186 return PCI_ERS_RESULT_DISCONNECT;
2187 }
2188 pci_set_master(pdev);
2189 pci_enable_wake(pdev, PCI_D0, 0);
2190 pch_gbe_hal_power_up_phy(hw);
2191 pch_gbe_reset(adapter);
2192 /* Clear wake up status */
2193 pch_gbe_mac_set_wol_event(hw, 0);
2194
2195 return PCI_ERS_RESULT_RECOVERED;
2196}
2197
2198static void pch_gbe_io_resume(struct pci_dev *pdev)
2199{
2200 struct net_device *netdev = pci_get_drvdata(pdev);
2201 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2202
2203 if (netif_running(netdev)) {
2204 if (pch_gbe_up(adapter)) {
2205 pr_debug("can't bring device back up after reset\n");
2206 return;
2207 }
2208 }
2209 netif_device_attach(netdev);
2210}
2211
2212static int __pch_gbe_suspend(struct pci_dev *pdev)
2213{
2214 struct net_device *netdev = pci_get_drvdata(pdev);
2215 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2216 struct pch_gbe_hw *hw = &adapter->hw;
2217 u32 wufc = adapter->wake_up_evt;
2218 int retval = 0;
2219
2220 netif_device_detach(netdev);
2221 if (netif_running(netdev))
2222 pch_gbe_down(adapter);
2223 if (wufc) {
2224 pch_gbe_set_multi(netdev);
2225 pch_gbe_setup_rctl(adapter);
2226 pch_gbe_configure_rx(adapter);
2227 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2228 hw->mac.link_duplex);
2229 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2230 hw->mac.link_duplex);
2231 pch_gbe_mac_set_wol_event(hw, wufc);
2232 pci_disable_device(pdev);
2233 } else {
2234 pch_gbe_hal_power_down_phy(hw);
2235 pch_gbe_mac_set_wol_event(hw, wufc);
2236 pci_disable_device(pdev);
2237 }
2238 return retval;
2239}
2240
2241#ifdef CONFIG_PM
2242static int pch_gbe_suspend(struct device *device)
2243{
2244 struct pci_dev *pdev = to_pci_dev(device);
2245
2246 return __pch_gbe_suspend(pdev);
2247}
2248
2249static int pch_gbe_resume(struct device *device)
2250{
2251 struct pci_dev *pdev = to_pci_dev(device);
2252 struct net_device *netdev = pci_get_drvdata(pdev);
2253 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2254 struct pch_gbe_hw *hw = &adapter->hw;
2255 u32 err;
2256
2257 err = pci_enable_device(pdev);
2258 if (err) {
2259 pr_err("Cannot enable PCI device from suspend\n");
2260 return err;
2261 }
2262 pci_set_master(pdev);
2263 pch_gbe_hal_power_up_phy(hw);
2264 pch_gbe_reset(adapter);
2265 /* Clear wake on lan control and status */
2266 pch_gbe_mac_set_wol_event(hw, 0);
2267
2268 if (netif_running(netdev))
2269 pch_gbe_up(adapter);
2270 netif_device_attach(netdev);
2271
2272 return 0;
2273}
2274#endif /* CONFIG_PM */
2275
2276static void pch_gbe_shutdown(struct pci_dev *pdev)
2277{
2278 __pch_gbe_suspend(pdev);
2279 if (system_state == SYSTEM_POWER_OFF) {
2280 pci_wake_from_d3(pdev, true);
2281 pci_set_power_state(pdev, PCI_D3hot);
2282 }
2283}
2284
2285static void pch_gbe_remove(struct pci_dev *pdev)
2286{
2287 struct net_device *netdev = pci_get_drvdata(pdev);
2288 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2289
2321f3b4 2290 cancel_work_sync(&adapter->reset_task);
77555ee7
MO		 2291 unregister_netdev(netdev);
2292
2293 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2294
2295 kfree(adapter->tx_ring);
2296 kfree(adapter->rx_ring);
2297
2298 iounmap(adapter->hw.reg);
2299 pci_release_regions(pdev);
2300 free_netdev(netdev);
2301 pci_disable_device(pdev);
2302}
2303
2304static int pch_gbe_probe(struct pci_dev *pdev,
2305 const struct pci_device_id *pci_id)
2306{
2307 struct net_device *netdev;
2308 struct pch_gbe_adapter *adapter;
2309 int ret;
2310
2311 ret = pci_enable_device(pdev);
2312 if (ret)
2313 return ret;
2314
2315 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2316 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2317 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2318 if (ret) {
2319 ret = pci_set_consistent_dma_mask(pdev,
2320 DMA_BIT_MASK(32));
2321 if (ret) {
2322 dev_err(&pdev->dev, "ERR: No usable DMA "
2323 "configuration, aborting\n");
2324 goto err_disable_device;
2325 }
2326 }
2327 }
2328
2329 ret = pci_request_regions(pdev, KBUILD_MODNAME);
2330 if (ret) {
2331 dev_err(&pdev->dev,
2332 "ERR: Can't reserve PCI I/O and memory resources\n");
2333 goto err_disable_device;
2334 }
2335 pci_set_master(pdev);
2336
2337 netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2338 if (!netdev) {
2339 ret = -ENOMEM;
2340 dev_err(&pdev->dev,
2341 "ERR: Can't allocate and set up an Ethernet device\n");
2342 goto err_release_pci;
2343 }
2344 SET_NETDEV_DEV(netdev, &pdev->dev);
2345
2346 pci_set_drvdata(pdev, netdev);
2347 adapter = netdev_priv(netdev);
2348 adapter->netdev = netdev;
2349 adapter->pdev = pdev;
2350 adapter->hw.back = adapter;
2351 adapter->hw.reg = pci_iomap(pdev, PCH_GBE_PCI_BAR, 0);
2352 if (!adapter->hw.reg) {
2353 ret = -EIO;
2354 dev_err(&pdev->dev, "Can't ioremap\n");
2355 goto err_free_netdev;
2356 }
2357
2358 netdev->netdev_ops = &pch_gbe_netdev_ops;
2359 netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2360 netif_napi_add(netdev, &adapter->napi,
2361 pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
756a6b03
MM		 2362 netdev->hw_features = NETIF_F_RXCSUM |
2363 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2364 netdev->features = netdev->hw_features;
77555ee7
MO		 2365 pch_gbe_set_ethtool_ops(netdev);
2366
98200ec2 2367 pch_gbe_mac_load_mac_addr(&adapter->hw);
77555ee7
MO		 2368 pch_gbe_mac_reset_hw(&adapter->hw);
2369
2370 /* setup the private structure */
2371 ret = pch_gbe_sw_init(adapter);
2372 if (ret)
2373 goto err_iounmap;
2374
2375 /* Initialize PHY */
2376 ret = pch_gbe_init_phy(adapter);
2377 if (ret) {
2378 dev_err(&pdev->dev, "PHY initialize error\n");
2379 goto err_free_adapter;
2380 }
2381 pch_gbe_hal_get_bus_info(&adapter->hw);
2382
2383 /* Read the MAC address. and store to the private data */
2384 ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2385 if (ret) {
2386 dev_err(&pdev->dev, "MAC address Read Error\n");
2387 goto err_free_adapter;
2388 }
2389
2390 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2391 if (!is_valid_ether_addr(netdev->dev_addr)) {
2392 dev_err(&pdev->dev, "Invalid MAC Address\n");
2393 ret = -EIO;
2394 goto err_free_adapter;
2395 }
2396 setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog,
2397 (unsigned long)adapter);
2398
2399 INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2400
2401 pch_gbe_check_options(adapter);
2402
77555ee7
MO		 2403 /* initialize the wol settings based on the eeprom settings */
2404 adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2405 dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2406
2407 /* reset the hardware with the new settings */
2408 pch_gbe_reset(adapter);
2409
2410 ret = register_netdev(netdev);
2411 if (ret)
2412 goto err_free_adapter;
2413 /* tell the stack to leave us alone until pch_gbe_open() is called */
2414 netif_carrier_off(netdev);
2415 netif_stop_queue(netdev);
2416
2417 dev_dbg(&pdev->dev, "OKIsemi(R) PCH Network Connection\n");
2418
2419 device_set_wakeup_enable(&pdev->dev, 1);
2420 return 0;
2421
2422err_free_adapter:
2423 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2424 kfree(adapter->tx_ring);
2425 kfree(adapter->rx_ring);
2426err_iounmap:
2427 iounmap(adapter->hw.reg);
2428err_free_netdev:
2429 free_netdev(netdev);
2430err_release_pci:
2431 pci_release_regions(pdev);
2432err_disable_device:
2433 pci_disable_device(pdev);
2434 return ret;
2435}
2436
7fc44633 2437static DEFINE_PCI_DEVICE_TABLE(pch_gbe_pcidev_id) = {
77555ee7
MO		 2438 {.vendor = PCI_VENDOR_ID_INTEL,
2439 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2440 .subvendor = PCI_ANY_ID,
2441 .subdevice = PCI_ANY_ID,
2442 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2443 .class_mask = (0xFFFF00)
2444 },
2445 /* required last entry */
2446 {0}
2447};
2448
2449#ifdef CONFIG_PM
2450static const struct dev_pm_ops pch_gbe_pm_ops = {
2451 .suspend = pch_gbe_suspend,
2452 .resume = pch_gbe_resume,
2453 .freeze = pch_gbe_suspend,
2454 .thaw = pch_gbe_resume,
2455 .poweroff = pch_gbe_suspend,
2456 .restore = pch_gbe_resume,
2457};
2458#endif
2459
2460static struct pci_error_handlers pch_gbe_err_handler = {
2461 .error_detected = pch_gbe_io_error_detected,
2462 .slot_reset = pch_gbe_io_slot_reset,
2463 .resume = pch_gbe_io_resume
2464};
2465
f7594d42 2466static struct pci_driver pch_gbe_driver = {
77555ee7
MO		 2467 .name = KBUILD_MODNAME,
2468 .id_table = pch_gbe_pcidev_id,
2469 .probe = pch_gbe_probe,
2470 .remove = pch_gbe_remove,
aa338601 2471#ifdef CONFIG_PM
77555ee7
MO		 2472 .driver.pm = &pch_gbe_pm_ops,
2473#endif
2474 .shutdown = pch_gbe_shutdown,
2475 .err_handler = &pch_gbe_err_handler
2476};
2477
2478
2479static int __init pch_gbe_init_module(void)
2480{
2481 int ret;
2482
f7594d42 2483 ret = pci_register_driver(&pch_gbe_driver);
77555ee7
MO		 2484 if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
2485 if (copybreak == 0) {
2486 pr_info("copybreak disabled\n");
2487 } else {
2488 pr_info("copybreak enabled for packets <= %u bytes\n",
2489 copybreak);
2490 }
2491 }
2492 return ret;
2493}
2494
2495static void __exit pch_gbe_exit_module(void)
2496{
f7594d42 2497 pci_unregister_driver(&pch_gbe_driver);
77555ee7
MO		 2498}
2499
2500module_init(pch_gbe_init_module);
2501module_exit(pch_gbe_exit_module);
2502
a1dcfcb7
TO		 2503MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2504MODULE_AUTHOR("OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com>");
77555ee7
MO		 2505MODULE_LICENSE("GPL");
2506MODULE_VERSION(DRV_VERSION);
2507MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2508
2509module_param(copybreak, uint, 0644);
2510MODULE_PARM_DESC(copybreak,
2511 "Maximum size of packet that is copied to a new buffer on receive");
2512
2513/* pch_gbe_main.c */
Linux kernel - Deliverables
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