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PCH_GbE : Fixed the issue of collision detection
[deliverable/linux.git] / drivers / net / pch_gbe / pch_gbe_main.c
CommitLineData
77555ee7
MO		 1/*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
a1dcfcb7 3 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
77555ee7
MO		 4 *
5 * This code was derived from the Intel e1000e Linux driver.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21#include "pch_gbe.h"
22#include "pch_gbe_api.h"
23
24#define DRV_VERSION "1.00"
25const char pch_driver_version[] = DRV_VERSION;
26
27#define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802 /* Pci device ID */
28#define PCH_GBE_MAR_ENTRIES 16
29#define PCH_GBE_SHORT_PKT 64
30#define DSC_INIT16 0xC000
31#define PCH_GBE_DMA_ALIGN 0
ac096642 32#define PCH_GBE_DMA_PADDING 2
77555ee7
MO		 33#define PCH_GBE_WATCHDOG_PERIOD (1 * HZ) /* watchdog time */
34#define PCH_GBE_COPYBREAK_DEFAULT 256
35#define PCH_GBE_PCI_BAR 1
36
37#define PCH_GBE_TX_WEIGHT 64
38#define PCH_GBE_RX_WEIGHT 64
39#define PCH_GBE_RX_BUFFER_WRITE 16
40
41/* Initialize the wake-on-LAN settings */
42#define PCH_GBE_WL_INIT_SETTING (PCH_GBE_WLC_MP)
43
44#define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
45 PCH_GBE_CHIP_TYPE_INTERNAL | \
ce3dad0f 46 PCH_GBE_RGMII_MODE_RGMII \
77555ee7
MO		 47 )
48
49/* Ethertype field values */
50#define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318
51#define PCH_GBE_FRAME_SIZE_2048 2048
52#define PCH_GBE_FRAME_SIZE_4096 4096
53#define PCH_GBE_FRAME_SIZE_8192 8192
54
55#define PCH_GBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
56#define PCH_GBE_RX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
57#define PCH_GBE_TX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
58#define PCH_GBE_DESC_UNUSED(R) \
59 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
60 (R)->next_to_clean - (R)->next_to_use - 1)
61
62/* Pause packet value */
63#define PCH_GBE_PAUSE_PKT1_VALUE 0x00C28001
64#define PCH_GBE_PAUSE_PKT2_VALUE 0x00000100
65#define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888
66#define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF
67
68#define PCH_GBE_ETH_ALEN 6
69
70/* This defines the bits that are set in the Interrupt Mask
71 * Set/Read Register. Each bit is documented below:
72 * o RXT0 = Receiver Timer Interrupt (ring 0)
73 * o TXDW = Transmit Descriptor Written Back
74 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
75 * o RXSEQ = Receive Sequence Error
76 * o LSC = Link Status Change
77 */
78#define PCH_GBE_INT_ENABLE_MASK ( \
79 PCH_GBE_INT_RX_DMA_CMPLT | \
80 PCH_GBE_INT_RX_DSC_EMP | \
81 PCH_GBE_INT_WOL_DET | \
82 PCH_GBE_INT_TX_CMPLT \
83 )
84
85
86static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
87
191cc687 88static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
89static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
90 int data);
98200ec2
TO		 91
92inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
93{
94 iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
95}
96
77555ee7
MO		 97/**
98 * pch_gbe_mac_read_mac_addr - Read MAC address
99 * @hw: Pointer to the HW structure
100 * Returns
101 * 0: Successful.
102 */
103s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
104{
105 u32 adr1a, adr1b;
106
107 adr1a = ioread32(&hw->reg->mac_adr[0].high);
108 adr1b = ioread32(&hw->reg->mac_adr[0].low);
109
110 hw->mac.addr[0] = (u8)(adr1a & 0xFF);
111 hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
112 hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
113 hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
114 hw->mac.addr[4] = (u8)(adr1b & 0xFF);
115 hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
116
117 pr_debug("hw->mac.addr : %pM\n", hw->mac.addr);
118 return 0;
119}
120
121/**
122 * pch_gbe_wait_clr_bit - Wait to clear a bit
123 * @reg: Pointer of register
124 * @busy: Busy bit
125 */
191cc687 126static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
77555ee7
MO		 127{
128 u32 tmp;
129 /* wait busy */
130 tmp = 1000;
131 while ((ioread32(reg) & bit) && --tmp)
132 cpu_relax();
133 if (!tmp)
134 pr_err("Error: busy bit is not cleared\n");
135}
136/**
137 * pch_gbe_mac_mar_set - Set MAC address register
138 * @hw: Pointer to the HW structure
139 * @addr: Pointer to the MAC address
140 * @index: MAC address array register
141 */
191cc687 142static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
77555ee7
MO		 143{
144 u32 mar_low, mar_high, adrmask;
145
146 pr_debug("index : 0x%x\n", index);
147
148 /*
149 * HW expects these in little endian so we reverse the byte order
150 * from network order (big endian) to little endian
151 */
152 mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
153 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
154 mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
155 /* Stop the MAC Address of index. */
156 adrmask = ioread32(&hw->reg->ADDR_MASK);
157 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
158 /* wait busy */
159 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
160 /* Set the MAC address to the MAC address 1A/1B register */
161 iowrite32(mar_high, &hw->reg->mac_adr[index].high);
162 iowrite32(mar_low, &hw->reg->mac_adr[index].low);
163 /* Start the MAC address of index */
164 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
165 /* wait busy */
166 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
167}
168
169/**
170 * pch_gbe_mac_reset_hw - Reset hardware
171 * @hw: Pointer to the HW structure
172 */
191cc687 173static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
77555ee7
MO		 174{
175 /* Read the MAC address. and store to the private data */
176 pch_gbe_mac_read_mac_addr(hw);
177 iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
178#ifdef PCH_GBE_MAC_IFOP_RGMII
179 iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
180#endif
181 pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
182 /* Setup the receive address */
183 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
184 return;
185}
186
187/**
188 * pch_gbe_mac_init_rx_addrs - Initialize receive address's
189 * @hw: Pointer to the HW structure
190 * @mar_count: Receive address registers
191 */
191cc687 192static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
77555ee7
MO		 193{
194 u32 i;
195
196 /* Setup the receive address */
197 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
198
199 /* Zero out the other receive addresses */
200 for (i = 1; i < mar_count; i++) {
201 iowrite32(0, &hw->reg->mac_adr[i].high);
202 iowrite32(0, &hw->reg->mac_adr[i].low);
203 }
204 iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
205 /* wait busy */
206 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
207}
208
209
210/**
211 * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
212 * @hw: Pointer to the HW structure
213 * @mc_addr_list: Array of multicast addresses to program
214 * @mc_addr_count: Number of multicast addresses to program
215 * @mar_used_count: The first MAC Address register free to program
216 * @mar_total_num: Total number of supported MAC Address Registers
217 */
191cc687 218static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
219 u8 *mc_addr_list, u32 mc_addr_count,
220 u32 mar_used_count, u32 mar_total_num)
77555ee7
MO		 221{
222 u32 i, adrmask;
223
224 /* Load the first set of multicast addresses into the exact
225 * filters (RAR). If there are not enough to fill the RAR
226 * array, clear the filters.
227 */
228 for (i = mar_used_count; i < mar_total_num; i++) {
229 if (mc_addr_count) {
230 pch_gbe_mac_mar_set(hw, mc_addr_list, i);
231 mc_addr_count--;
232 mc_addr_list += PCH_GBE_ETH_ALEN;
233 } else {
234 /* Clear MAC address mask */
235 adrmask = ioread32(&hw->reg->ADDR_MASK);
236 iowrite32((adrmask | (0x0001 << i)),
237 &hw->reg->ADDR_MASK);
238 /* wait busy */
239 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
240 /* Clear MAC address */
241 iowrite32(0, &hw->reg->mac_adr[i].high);
242 iowrite32(0, &hw->reg->mac_adr[i].low);
243 }
244 }
245}
246
247/**
248 * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
249 * @hw: Pointer to the HW structure
250 * Returns
251 * 0: Successful.
252 * Negative value: Failed.
253 */
254s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
255{
256 struct pch_gbe_mac_info *mac = &hw->mac;
257 u32 rx_fctrl;
258
259 pr_debug("mac->fc = %u\n", mac->fc);
260
261 rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
262
263 switch (mac->fc) {
264 case PCH_GBE_FC_NONE:
265 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
266 mac->tx_fc_enable = false;
267 break;
268 case PCH_GBE_FC_RX_PAUSE:
269 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
270 mac->tx_fc_enable = false;
271 break;
272 case PCH_GBE_FC_TX_PAUSE:
273 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
274 mac->tx_fc_enable = true;
275 break;
276 case PCH_GBE_FC_FULL:
277 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
278 mac->tx_fc_enable = true;
279 break;
280 default:
281 pr_err("Flow control param set incorrectly\n");
282 return -EINVAL;
283 }
284 if (mac->link_duplex == DUPLEX_HALF)
285 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
286 iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
287 pr_debug("RX_FCTRL reg : 0x%08x mac->tx_fc_enable : %d\n",
288 ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
289 return 0;
290}
291
292/**
293 * pch_gbe_mac_set_wol_event - Set wake-on-lan event
294 * @hw: Pointer to the HW structure
295 * @wu_evt: Wake up event
296 */
191cc687 297static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
77555ee7
MO		 298{
299 u32 addr_mask;
300
301 pr_debug("wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n",
302 wu_evt, ioread32(&hw->reg->ADDR_MASK));
303
304 if (wu_evt) {
305 /* Set Wake-On-Lan address mask */
306 addr_mask = ioread32(&hw->reg->ADDR_MASK);
307 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
308 /* wait busy */
309 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
310 iowrite32(0, &hw->reg->WOL_ST);
311 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
312 iowrite32(0x02, &hw->reg->TCPIP_ACC);
313 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
314 } else {
315 iowrite32(0, &hw->reg->WOL_CTRL);
316 iowrite32(0, &hw->reg->WOL_ST);
317 }
318 return;
319}
320
321/**
322 * pch_gbe_mac_ctrl_miim - Control MIIM interface
323 * @hw: Pointer to the HW structure
324 * @addr: Address of PHY
325 * @dir: Operetion. (Write or Read)
326 * @reg: Access register of PHY
327 * @data: Write data.
328 *
329 * Returns: Read date.
330 */
331u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
332 u16 data)
333{
334 u32 data_out = 0;
335 unsigned int i;
336 unsigned long flags;
337
338 spin_lock_irqsave(&hw->miim_lock, flags);
339
340 for (i = 100; i; --i) {
341 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
342 break;
343 udelay(20);
344 }
345 if (i == 0) {
346 pr_err("pch-gbe.miim won't go Ready\n");
347 spin_unlock_irqrestore(&hw->miim_lock, flags);
348 return 0; /* No way to indicate timeout error */
349 }
350 iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
351 (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
352 dir | data), &hw->reg->MIIM);
353 for (i = 0; i < 100; i++) {
354 udelay(20);
355 data_out = ioread32(&hw->reg->MIIM);
356 if ((data_out & PCH_GBE_MIIM_OPER_READY))
357 break;
358 }
359 spin_unlock_irqrestore(&hw->miim_lock, flags);
360
361 pr_debug("PHY %s: reg=%d, data=0x%04X\n",
362 dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
363 dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
364 return (u16) data_out;
365}
366
367/**
368 * pch_gbe_mac_set_pause_packet - Set pause packet
369 * @hw: Pointer to the HW structure
370 */
191cc687 371static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
77555ee7
MO		 372{
373 unsigned long tmp2, tmp3;
374
375 /* Set Pause packet */
376 tmp2 = hw->mac.addr[1];
377 tmp2 = (tmp2 << 8) | hw->mac.addr[0];
378 tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
379
380 tmp3 = hw->mac.addr[5];
381 tmp3 = (tmp3 << 8) | hw->mac.addr[4];
382 tmp3 = (tmp3 << 8) | hw->mac.addr[3];
383 tmp3 = (tmp3 << 8) | hw->mac.addr[2];
384
385 iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
386 iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
387 iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
388 iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
389 iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
390
391 /* Transmit Pause Packet */
392 iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
393
394 pr_debug("PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
395 ioread32(&hw->reg->PAUSE_PKT1), ioread32(&hw->reg->PAUSE_PKT2),
396 ioread32(&hw->reg->PAUSE_PKT3), ioread32(&hw->reg->PAUSE_PKT4),
397 ioread32(&hw->reg->PAUSE_PKT5));
398
399 return;
400}
401
402
403/**
404 * pch_gbe_alloc_queues - Allocate memory for all rings
405 * @adapter: Board private structure to initialize
406 * Returns
407 * 0: Successfully
408 * Negative value: Failed
409 */
410static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
411{
412 int size;
413
414 size = (int)sizeof(struct pch_gbe_tx_ring);
415 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
416 if (!adapter->tx_ring)
417 return -ENOMEM;
418 size = (int)sizeof(struct pch_gbe_rx_ring);
419 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
420 if (!adapter->rx_ring) {
421 kfree(adapter->tx_ring);
422 return -ENOMEM;
423 }
424 return 0;
425}
426
427/**
428 * pch_gbe_init_stats - Initialize status
429 * @adapter: Board private structure to initialize
430 */
431static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
432{
433 memset(&adapter->stats, 0, sizeof(adapter->stats));
434 return;
435}
436
437/**
438 * pch_gbe_init_phy - Initialize PHY
439 * @adapter: Board private structure to initialize
440 * Returns
441 * 0: Successfully
442 * Negative value: Failed
443 */
444static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
445{
446 struct net_device *netdev = adapter->netdev;
447 u32 addr;
448 u16 bmcr, stat;
449
450 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
451 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
452 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
453 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
454 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
455 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
456 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
457 break;
458 }
459 adapter->hw.phy.addr = adapter->mii.phy_id;
460 pr_debug("phy_addr = %d\n", adapter->mii.phy_id);
461 if (addr == 32)
462 return -EAGAIN;
463 /* Selected the phy and isolate the rest */
464 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
465 if (addr != adapter->mii.phy_id) {
466 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
467 BMCR_ISOLATE);
468 } else {
469 bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
470 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
471 bmcr & ~BMCR_ISOLATE);
472 }
473 }
474
475 /* MII setup */
476 adapter->mii.phy_id_mask = 0x1F;
477 adapter->mii.reg_num_mask = 0x1F;
478 adapter->mii.dev = adapter->netdev;
479 adapter->mii.mdio_read = pch_gbe_mdio_read;
480 adapter->mii.mdio_write = pch_gbe_mdio_write;
481 adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
482 return 0;
483}
484
485/**
486 * pch_gbe_mdio_read - The read function for mii
487 * @netdev: Network interface device structure
488 * @addr: Phy ID
489 * @reg: Access location
490 * Returns
491 * 0: Successfully
492 * Negative value: Failed
493 */
191cc687 494static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
77555ee7
MO		 495{
496 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
497 struct pch_gbe_hw *hw = &adapter->hw;
498
499 return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
500 (u16) 0);
501}
502
503/**
504 * pch_gbe_mdio_write - The write function for mii
505 * @netdev: Network interface device structure
506 * @addr: Phy ID (not used)
507 * @reg: Access location
508 * @data: Write data
509 */
191cc687 510static void pch_gbe_mdio_write(struct net_device *netdev,
511 int addr, int reg, int data)
77555ee7
MO		 512{
513 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
514 struct pch_gbe_hw *hw = &adapter->hw;
515
516 pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
517}
518
519/**
520 * pch_gbe_reset_task - Reset processing at the time of transmission timeout
521 * @work: Pointer of board private structure
522 */
523static void pch_gbe_reset_task(struct work_struct *work)
524{
525 struct pch_gbe_adapter *adapter;
526 adapter = container_of(work, struct pch_gbe_adapter, reset_task);
527
75d1a752 528 rtnl_lock();
77555ee7 529 pch_gbe_reinit_locked(adapter);
75d1a752 530 rtnl_unlock();
77555ee7
MO		 531}
532
533/**
534 * pch_gbe_reinit_locked- Re-initialization
535 * @adapter: Board private structure
536 */
537void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
538{
75d1a752
TO		 539 pch_gbe_down(adapter);
540 pch_gbe_up(adapter);
77555ee7
MO		 541}
542
543/**
544 * pch_gbe_reset - Reset GbE
545 * @adapter: Board private structure
546 */
547void pch_gbe_reset(struct pch_gbe_adapter *adapter)
548{
549 pch_gbe_mac_reset_hw(&adapter->hw);
550 /* Setup the receive address. */
551 pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
552 if (pch_gbe_hal_init_hw(&adapter->hw))
553 pr_err("Hardware Error\n");
554}
555
556/**
557 * pch_gbe_free_irq - Free an interrupt
558 * @adapter: Board private structure
559 */
560static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
561{
562 struct net_device *netdev = adapter->netdev;
563
564 free_irq(adapter->pdev->irq, netdev);
565 if (adapter->have_msi) {
566 pci_disable_msi(adapter->pdev);
567 pr_debug("call pci_disable_msi\n");
568 }
569}
570
571/**
572 * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
573 * @adapter: Board private structure
574 */
575static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
576{
577 struct pch_gbe_hw *hw = &adapter->hw;
578
579 atomic_inc(&adapter->irq_sem);
580 iowrite32(0, &hw->reg->INT_EN);
581 ioread32(&hw->reg->INT_ST);
582 synchronize_irq(adapter->pdev->irq);
583
584 pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
585}
586
587/**
588 * pch_gbe_irq_enable - Enable default interrupt generation settings
589 * @adapter: Board private structure
590 */
591static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
592{
593 struct pch_gbe_hw *hw = &adapter->hw;
594
595 if (likely(atomic_dec_and_test(&adapter->irq_sem)))
596 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
597 ioread32(&hw->reg->INT_ST);
598 pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
599}
600
601
602
603/**
604 * pch_gbe_setup_tctl - configure the Transmit control registers
605 * @adapter: Board private structure
606 */
607static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
608{
609 struct pch_gbe_hw *hw = &adapter->hw;
610 u32 tx_mode, tcpip;
611
612 tx_mode = PCH_GBE_TM_LONG_PKT |
613 PCH_GBE_TM_ST_AND_FD |
614 PCH_GBE_TM_SHORT_PKT |
615 PCH_GBE_TM_TH_TX_STRT_8 |
616 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
617
618 iowrite32(tx_mode, &hw->reg->TX_MODE);
619
620 tcpip = ioread32(&hw->reg->TCPIP_ACC);
621 tcpip |= PCH_GBE_TX_TCPIPACC_EN;
622 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
623 return;
624}
625
626/**
627 * pch_gbe_configure_tx - Configure Transmit Unit after Reset
628 * @adapter: Board private structure
629 */
630static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
631{
632 struct pch_gbe_hw *hw = &adapter->hw;
633 u32 tdba, tdlen, dctrl;
634
635 pr_debug("dma addr = 0x%08llx size = 0x%08x\n",
636 (unsigned long long)adapter->tx_ring->dma,
637 adapter->tx_ring->size);
638
639 /* Setup the HW Tx Head and Tail descriptor pointers */
640 tdba = adapter->tx_ring->dma;
641 tdlen = adapter->tx_ring->size - 0x10;
642 iowrite32(tdba, &hw->reg->TX_DSC_BASE);
643 iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
644 iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
645
646 /* Enables Transmission DMA */
647 dctrl = ioread32(&hw->reg->DMA_CTRL);
648 dctrl |= PCH_GBE_TX_DMA_EN;
649 iowrite32(dctrl, &hw->reg->DMA_CTRL);
650}
651
652/**
653 * pch_gbe_setup_rctl - Configure the receive control registers
654 * @adapter: Board private structure
655 */
656static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
657{
658 struct pch_gbe_hw *hw = &adapter->hw;
659 u32 rx_mode, tcpip;
660
661 rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
662 PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
663
664 iowrite32(rx_mode, &hw->reg->RX_MODE);
665
666 tcpip = ioread32(&hw->reg->TCPIP_ACC);
667
668 if (adapter->rx_csum) {
669 tcpip &= ~PCH_GBE_RX_TCPIPACC_OFF;
670 tcpip |= PCH_GBE_RX_TCPIPACC_EN;
671 } else {
672 tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
673 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
674 }
675 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
676 return;
677}
678
679/**
680 * pch_gbe_configure_rx - Configure Receive Unit after Reset
681 * @adapter: Board private structure
682 */
683static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
684{
685 struct pch_gbe_hw *hw = &adapter->hw;
686 u32 rdba, rdlen, rctl, rxdma;
687
688 pr_debug("dma adr = 0x%08llx size = 0x%08x\n",
689 (unsigned long long)adapter->rx_ring->dma,
690 adapter->rx_ring->size);
691
692 pch_gbe_mac_force_mac_fc(hw);
693
694 /* Disables Receive MAC */
695 rctl = ioread32(&hw->reg->MAC_RX_EN);
696 iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
697
698 /* Disables Receive DMA */
699 rxdma = ioread32(&hw->reg->DMA_CTRL);
700 rxdma &= ~PCH_GBE_RX_DMA_EN;
701 iowrite32(rxdma, &hw->reg->DMA_CTRL);
702
703 pr_debug("MAC_RX_EN reg = 0x%08x DMA_CTRL reg = 0x%08x\n",
704 ioread32(&hw->reg->MAC_RX_EN),
705 ioread32(&hw->reg->DMA_CTRL));
706
707 /* Setup the HW Rx Head and Tail Descriptor Pointers and
708 * the Base and Length of the Rx Descriptor Ring */
709 rdba = adapter->rx_ring->dma;
710 rdlen = adapter->rx_ring->size - 0x10;
711 iowrite32(rdba, &hw->reg->RX_DSC_BASE);
712 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
713 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
714
715 /* Enables Receive DMA */
716 rxdma = ioread32(&hw->reg->DMA_CTRL);
717 rxdma |= PCH_GBE_RX_DMA_EN;
718 iowrite32(rxdma, &hw->reg->DMA_CTRL);
719 /* Enables Receive */
720 iowrite32(PCH_GBE_MRE_MAC_RX_EN, &hw->reg->MAC_RX_EN);
721}
722
723/**
724 * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
725 * @adapter: Board private structure
726 * @buffer_info: Buffer information structure
727 */
728static void pch_gbe_unmap_and_free_tx_resource(
729 struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
730{
731 if (buffer_info->mapped) {
732 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
733 buffer_info->length, DMA_TO_DEVICE);
734 buffer_info->mapped = false;
735 }
736 if (buffer_info->skb) {
737 dev_kfree_skb_any(buffer_info->skb);
738 buffer_info->skb = NULL;
739 }
740}
741
742/**
743 * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
744 * @adapter: Board private structure
745 * @buffer_info: Buffer information structure
746 */
747static void pch_gbe_unmap_and_free_rx_resource(
748 struct pch_gbe_adapter *adapter,
749 struct pch_gbe_buffer *buffer_info)
750{
751 if (buffer_info->mapped) {
752 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
753 buffer_info->length, DMA_FROM_DEVICE);
754 buffer_info->mapped = false;
755 }
756 if (buffer_info->skb) {
757 dev_kfree_skb_any(buffer_info->skb);
758 buffer_info->skb = NULL;
759 }
760}
761
762/**
763 * pch_gbe_clean_tx_ring - Free Tx Buffers
764 * @adapter: Board private structure
765 * @tx_ring: Ring to be cleaned
766 */
767static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
768 struct pch_gbe_tx_ring *tx_ring)
769{
770 struct pch_gbe_hw *hw = &adapter->hw;
771 struct pch_gbe_buffer *buffer_info;
772 unsigned long size;
773 unsigned int i;
774
775 /* Free all the Tx ring sk_buffs */
776 for (i = 0; i < tx_ring->count; i++) {
777 buffer_info = &tx_ring->buffer_info[i];
778 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
779 }
780 pr_debug("call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
781
782 size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
783 memset(tx_ring->buffer_info, 0, size);
784
785 /* Zero out the descriptor ring */
786 memset(tx_ring->desc, 0, tx_ring->size);
787 tx_ring->next_to_use = 0;
788 tx_ring->next_to_clean = 0;
789 iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
790 iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
791}
792
793/**
794 * pch_gbe_clean_rx_ring - Free Rx Buffers
795 * @adapter: Board private structure
796 * @rx_ring: Ring to free buffers from
797 */
798static void
799pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
800 struct pch_gbe_rx_ring *rx_ring)
801{
802 struct pch_gbe_hw *hw = &adapter->hw;
803 struct pch_gbe_buffer *buffer_info;
804 unsigned long size;
805 unsigned int i;
806
807 /* Free all the Rx ring sk_buffs */
808 for (i = 0; i < rx_ring->count; i++) {
809 buffer_info = &rx_ring->buffer_info[i];
810 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
811 }
812 pr_debug("call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
813 size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
814 memset(rx_ring->buffer_info, 0, size);
815
816 /* Zero out the descriptor ring */
817 memset(rx_ring->desc, 0, rx_ring->size);
818 rx_ring->next_to_clean = 0;
819 rx_ring->next_to_use = 0;
820 iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
821 iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
822}
823
824static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
825 u16 duplex)
826{
827 struct pch_gbe_hw *hw = &adapter->hw;
828 unsigned long rgmii = 0;
829
830 /* Set the RGMII control. */
831#ifdef PCH_GBE_MAC_IFOP_RGMII
832 switch (speed) {
833 case SPEED_10:
834 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
835 PCH_GBE_MAC_RGMII_CTRL_SETTING);
836 break;
837 case SPEED_100:
838 rgmii = (PCH_GBE_RGMII_RATE_25M |
839 PCH_GBE_MAC_RGMII_CTRL_SETTING);
840 break;
841 case SPEED_1000:
842 rgmii = (PCH_GBE_RGMII_RATE_125M |
843 PCH_GBE_MAC_RGMII_CTRL_SETTING);
844 break;
845 }
846 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
847#else /* GMII */
848 rgmii = 0;
849 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
850#endif
851}
852static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
853 u16 duplex)
854{
855 struct net_device *netdev = adapter->netdev;
856 struct pch_gbe_hw *hw = &adapter->hw;
857 unsigned long mode = 0;
858
859 /* Set the communication mode */
860 switch (speed) {
861 case SPEED_10:
862 mode = PCH_GBE_MODE_MII_ETHER;
863 netdev->tx_queue_len = 10;
864 break;
865 case SPEED_100:
866 mode = PCH_GBE_MODE_MII_ETHER;
867 netdev->tx_queue_len = 100;
868 break;
869 case SPEED_1000:
870 mode = PCH_GBE_MODE_GMII_ETHER;
871 break;
872 }
873 if (duplex == DUPLEX_FULL)
874 mode |= PCH_GBE_MODE_FULL_DUPLEX;
875 else
876 mode |= PCH_GBE_MODE_HALF_DUPLEX;
877 iowrite32(mode, &hw->reg->MODE);
878}
879
880/**
881 * pch_gbe_watchdog - Watchdog process
882 * @data: Board private structure
883 */
884static void pch_gbe_watchdog(unsigned long data)
885{
886 struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data;
887 struct net_device *netdev = adapter->netdev;
888 struct pch_gbe_hw *hw = &adapter->hw;
889 struct ethtool_cmd cmd;
890
891 pr_debug("right now = %ld\n", jiffies);
892
893 pch_gbe_update_stats(adapter);
894 if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
895 netdev->tx_queue_len = adapter->tx_queue_len;
896 /* mii library handles link maintenance tasks */
897 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
898 pr_err("ethtool get setting Error\n");
899 mod_timer(&adapter->watchdog_timer,
900 round_jiffies(jiffies +
901 PCH_GBE_WATCHDOG_PERIOD));
902 return;
903 }
904 hw->mac.link_speed = cmd.speed;
905 hw->mac.link_duplex = cmd.duplex;
906 /* Set the RGMII control. */
907 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
908 hw->mac.link_duplex);
909 /* Set the communication mode */
910 pch_gbe_set_mode(adapter, hw->mac.link_speed,
911 hw->mac.link_duplex);
912 netdev_dbg(netdev,
913 "Link is Up %d Mbps %s-Duplex\n",
914 cmd.speed,
915 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
916 netif_carrier_on(netdev);
917 netif_wake_queue(netdev);
918 } else if ((!mii_link_ok(&adapter->mii)) &&
919 (netif_carrier_ok(netdev))) {
920 netdev_dbg(netdev, "NIC Link is Down\n");
921 hw->mac.link_speed = SPEED_10;
922 hw->mac.link_duplex = DUPLEX_HALF;
923 netif_carrier_off(netdev);
924 netif_stop_queue(netdev);
925 }
926 mod_timer(&adapter->watchdog_timer,
927 round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
928}
929
930/**
931 * pch_gbe_tx_queue - Carry out queuing of the transmission data
932 * @adapter: Board private structure
933 * @tx_ring: Tx descriptor ring structure
934 * @skb: Sockt buffer structure
935 */
936static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
937 struct pch_gbe_tx_ring *tx_ring,
938 struct sk_buff *skb)
939{
940 struct pch_gbe_hw *hw = &adapter->hw;
941 struct pch_gbe_tx_desc *tx_desc;
942 struct pch_gbe_buffer *buffer_info;
943 struct sk_buff *tmp_skb;
944 unsigned int frame_ctrl;
945 unsigned int ring_num;
946 unsigned long flags;
947
948 /*-- Set frame control --*/
949 frame_ctrl = 0;
950 if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
951 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
952 if (unlikely(!adapter->tx_csum))
953 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
954
955 /* Performs checksum processing */
956 /*
957 * It is because the hardware accelerator does not support a checksum,
958 * when the received data size is less than 64 bytes.
959 */
960 if ((skb->len < PCH_GBE_SHORT_PKT) && (adapter->tx_csum)) {
961 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
962 PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
963 if (skb->protocol == htons(ETH_P_IP)) {
964 struct iphdr *iph = ip_hdr(skb);
965 unsigned int offset;
966 iph->check = 0;
967 iph->check = ip_fast_csum((u8 *) iph, iph->ihl);
968 offset = skb_transport_offset(skb);
969 if (iph->protocol == IPPROTO_TCP) {
970 skb->csum = 0;
971 tcp_hdr(skb)->check = 0;
972 skb->csum = skb_checksum(skb, offset,
973 skb->len - offset, 0);
974 tcp_hdr(skb)->check =
975 csum_tcpudp_magic(iph->saddr,
976 iph->daddr,
977 skb->len - offset,
978 IPPROTO_TCP,
979 skb->csum);
980 } else if (iph->protocol == IPPROTO_UDP) {
981 skb->csum = 0;
982 udp_hdr(skb)->check = 0;
983 skb->csum =
984 skb_checksum(skb, offset,
985 skb->len - offset, 0);
986 udp_hdr(skb)->check =
987 csum_tcpudp_magic(iph->saddr,
988 iph->daddr,
989 skb->len - offset,
990 IPPROTO_UDP,
991 skb->csum);
992 }
993 }
994 }
995 spin_lock_irqsave(&tx_ring->tx_lock, flags);
996 ring_num = tx_ring->next_to_use;
997 if (unlikely((ring_num + 1) == tx_ring->count))
998 tx_ring->next_to_use = 0;
999 else
1000 tx_ring->next_to_use = ring_num + 1;
1001
1002 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1003 buffer_info = &tx_ring->buffer_info[ring_num];
1004 tmp_skb = buffer_info->skb;
1005
1006 /* [Header:14][payload] ---> [Header:14][paddong:2][payload] */
1007 memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1008 tmp_skb->data[ETH_HLEN] = 0x00;
1009 tmp_skb->data[ETH_HLEN + 1] = 0x00;
1010 tmp_skb->len = skb->len;
1011 memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1012 (skb->len - ETH_HLEN));
25985edc 1013 /*-- Set Buffer information --*/
77555ee7
MO		 1014 buffer_info->length = tmp_skb->len;
1015 buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1016 buffer_info->length,
1017 DMA_TO_DEVICE);
1018 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1019 pr_err("TX DMA map failed\n");
1020 buffer_info->dma = 0;
1021 buffer_info->time_stamp = 0;
1022 tx_ring->next_to_use = ring_num;
1023 return;
1024 }
1025 buffer_info->mapped = true;
1026 buffer_info->time_stamp = jiffies;
1027
1028 /*-- Set Tx descriptor --*/
1029 tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1030 tx_desc->buffer_addr = (buffer_info->dma);
1031 tx_desc->length = (tmp_skb->len);
1032 tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1033 tx_desc->tx_frame_ctrl = (frame_ctrl);
1034 tx_desc->gbec_status = (DSC_INIT16);
1035
1036 if (unlikely(++ring_num == tx_ring->count))
1037 ring_num = 0;
1038
1039 /* Update software pointer of TX descriptor */
1040 iowrite32(tx_ring->dma +
1041 (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1042 &hw->reg->TX_DSC_SW_P);
1043 dev_kfree_skb_any(skb);
1044}
1045
1046/**
1047 * pch_gbe_update_stats - Update the board statistics counters
1048 * @adapter: Board private structure
1049 */
1050void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1051{
1052 struct net_device *netdev = adapter->netdev;
1053 struct pci_dev *pdev = adapter->pdev;
1054 struct pch_gbe_hw_stats *stats = &adapter->stats;
1055 unsigned long flags;
1056
1057 /*
1058 * Prevent stats update while adapter is being reset, or if the pci
1059 * connection is down.
1060 */
1061 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1062 return;
1063
1064 spin_lock_irqsave(&adapter->stats_lock, flags);
1065
1066 /* Update device status "adapter->stats" */
1067 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1068 stats->tx_errors = stats->tx_length_errors +
1069 stats->tx_aborted_errors +
1070 stats->tx_carrier_errors + stats->tx_timeout_count;
1071
1072 /* Update network device status "adapter->net_stats" */
1073 netdev->stats.rx_packets = stats->rx_packets;
1074 netdev->stats.rx_bytes = stats->rx_bytes;
1075 netdev->stats.rx_dropped = stats->rx_dropped;
1076 netdev->stats.tx_packets = stats->tx_packets;
1077 netdev->stats.tx_bytes = stats->tx_bytes;
1078 netdev->stats.tx_dropped = stats->tx_dropped;
1079 /* Fill out the OS statistics structure */
1080 netdev->stats.multicast = stats->multicast;
1081 netdev->stats.collisions = stats->collisions;
1082 /* Rx Errors */
1083 netdev->stats.rx_errors = stats->rx_errors;
1084 netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1085 netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1086 /* Tx Errors */
1087 netdev->stats.tx_errors = stats->tx_errors;
1088 netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1089 netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1090
1091 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1092}
1093
1094/**
1095 * pch_gbe_intr - Interrupt Handler
1096 * @irq: Interrupt number
1097 * @data: Pointer to a network interface device structure
1098 * Returns
1099 * - IRQ_HANDLED: Our interrupt
1100 * - IRQ_NONE: Not our interrupt
1101 */
1102static irqreturn_t pch_gbe_intr(int irq, void *data)
1103{
1104 struct net_device *netdev = data;
1105 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1106 struct pch_gbe_hw *hw = &adapter->hw;
1107 u32 int_st;
1108 u32 int_en;
1109
1110 /* Check request status */
1111 int_st = ioread32(&hw->reg->INT_ST);
1112 int_st = int_st & ioread32(&hw->reg->INT_EN);
1113 /* When request status is no interruption factor */
1114 if (unlikely(!int_st))
1115 return IRQ_NONE; /* Not our interrupt. End processing. */
1116 pr_debug("%s occur int_st = 0x%08x\n", __func__, int_st);
1117 if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1118 adapter->stats.intr_rx_frame_err_count++;
1119 if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1120 adapter->stats.intr_rx_fifo_err_count++;
1121 if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1122 adapter->stats.intr_rx_dma_err_count++;
1123 if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1124 adapter->stats.intr_tx_fifo_err_count++;
1125 if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1126 adapter->stats.intr_tx_dma_err_count++;
1127 if (int_st & PCH_GBE_INT_TCPIP_ERR)
1128 adapter->stats.intr_tcpip_err_count++;
1129 /* When Rx descriptor is empty */
1130 if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1131 adapter->stats.intr_rx_dsc_empty_count++;
1132 pr_err("Rx descriptor is empty\n");
1133 int_en = ioread32(&hw->reg->INT_EN);
1134 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1135 if (hw->mac.tx_fc_enable) {
1136 /* Set Pause packet */
1137 pch_gbe_mac_set_pause_packet(hw);
1138 }
1139 if ((int_en & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))
1140 == 0) {
1141 return IRQ_HANDLED;
1142 }
1143 }
1144
1145 /* When request status is Receive interruption */
1146 if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))) {
1147 if (likely(napi_schedule_prep(&adapter->napi))) {
1148 /* Enable only Rx Descriptor empty */
1149 atomic_inc(&adapter->irq_sem);
1150 int_en = ioread32(&hw->reg->INT_EN);
1151 int_en &=
1152 ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1153 iowrite32(int_en, &hw->reg->INT_EN);
1154 /* Start polling for NAPI */
1155 __napi_schedule(&adapter->napi);
1156 }
1157 }
1158 pr_debug("return = 0x%08x INT_EN reg = 0x%08x\n",
1159 IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1160 return IRQ_HANDLED;
1161}
1162
1163/**
1164 * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1165 * @adapter: Board private structure
1166 * @rx_ring: Rx descriptor ring
1167 * @cleaned_count: Cleaned count
1168 */
1169static void
1170pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1171 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1172{
1173 struct net_device *netdev = adapter->netdev;
1174 struct pci_dev *pdev = adapter->pdev;
1175 struct pch_gbe_hw *hw = &adapter->hw;
1176 struct pch_gbe_rx_desc *rx_desc;
1177 struct pch_gbe_buffer *buffer_info;
1178 struct sk_buff *skb;
1179 unsigned int i;
1180 unsigned int bufsz;
1181
1182 bufsz = adapter->rx_buffer_len + PCH_GBE_DMA_ALIGN;
1183 i = rx_ring->next_to_use;
1184
1185 while ((cleaned_count--)) {
1186 buffer_info = &rx_ring->buffer_info[i];
1187 skb = buffer_info->skb;
1188 if (skb) {
1189 skb_trim(skb, 0);
1190 } else {
1191 skb = netdev_alloc_skb(netdev, bufsz);
1192 if (unlikely(!skb)) {
1193 /* Better luck next round */
1194 adapter->stats.rx_alloc_buff_failed++;
1195 break;
1196 }
1197 /* 64byte align */
1198 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1199
1200 buffer_info->skb = skb;
1201 buffer_info->length = adapter->rx_buffer_len;
1202 }
1203 buffer_info->dma = dma_map_single(&pdev->dev,
1204 skb->data,
1205 buffer_info->length,
1206 DMA_FROM_DEVICE);
1207 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1208 dev_kfree_skb(skb);
1209 buffer_info->skb = NULL;
1210 buffer_info->dma = 0;
1211 adapter->stats.rx_alloc_buff_failed++;
1212 break; /* while !buffer_info->skb */
1213 }
1214 buffer_info->mapped = true;
1215 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1216 rx_desc->buffer_addr = (buffer_info->dma);
1217 rx_desc->gbec_status = DSC_INIT16;
1218
1219 pr_debug("i = %d buffer_info->dma = 0x08%llx buffer_info->length = 0x%x\n",
1220 i, (unsigned long long)buffer_info->dma,
1221 buffer_info->length);
1222
1223 if (unlikely(++i == rx_ring->count))
1224 i = 0;
1225 }
1226 if (likely(rx_ring->next_to_use != i)) {
1227 rx_ring->next_to_use = i;
1228 if (unlikely(i-- == 0))
1229 i = (rx_ring->count - 1);
1230 iowrite32(rx_ring->dma +
1231 (int)sizeof(struct pch_gbe_rx_desc) * i,
1232 &hw->reg->RX_DSC_SW_P);
1233 }
1234 return;
1235}
1236
1237/**
1238 * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1239 * @adapter: Board private structure
1240 * @tx_ring: Tx descriptor ring
1241 */
1242static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1243 struct pch_gbe_tx_ring *tx_ring)
1244{
1245 struct pch_gbe_buffer *buffer_info;
1246 struct sk_buff *skb;
1247 unsigned int i;
1248 unsigned int bufsz;
1249 struct pch_gbe_tx_desc *tx_desc;
1250
1251 bufsz =
1252 adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1253
1254 for (i = 0; i < tx_ring->count; i++) {
1255 buffer_info = &tx_ring->buffer_info[i];
1256 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1257 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1258 buffer_info->skb = skb;
1259 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1260 tx_desc->gbec_status = (DSC_INIT16);
1261 }
1262 return;
1263}
1264
1265/**
1266 * pch_gbe_clean_tx - Reclaim resources after transmit completes
1267 * @adapter: Board private structure
1268 * @tx_ring: Tx descriptor ring
1269 * Returns
1270 * true: Cleaned the descriptor
1271 * false: Not cleaned the descriptor
1272 */
1273static bool
1274pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1275 struct pch_gbe_tx_ring *tx_ring)
1276{
1277 struct pch_gbe_tx_desc *tx_desc;
1278 struct pch_gbe_buffer *buffer_info;
1279 struct sk_buff *skb;
1280 unsigned int i;
1281 unsigned int cleaned_count = 0;
1282 bool cleaned = false;
1283
1284 pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1285
1286 i = tx_ring->next_to_clean;
1287 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1288 pr_debug("gbec_status:0x%04x dma_status:0x%04x\n",
1289 tx_desc->gbec_status, tx_desc->dma_status);
1290
1291 while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1292 pr_debug("gbec_status:0x%04x\n", tx_desc->gbec_status);
1293 cleaned = true;
1294 buffer_info = &tx_ring->buffer_info[i];
1295 skb = buffer_info->skb;
1296
1297 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1298 adapter->stats.tx_aborted_errors++;
1299 pr_err("Transfer Abort Error\n");
1300 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1301 ) {
1302 adapter->stats.tx_carrier_errors++;
1303 pr_err("Transfer Carrier Sense Error\n");
1304 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1305 ) {
1306 adapter->stats.tx_aborted_errors++;
1307 pr_err("Transfer Collision Abort Error\n");
1308 } else if ((tx_desc->gbec_status &
1309 (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1310 PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1311 adapter->stats.collisions++;
1312 adapter->stats.tx_packets++;
1313 adapter->stats.tx_bytes += skb->len;
1314 pr_debug("Transfer Collision\n");
1315 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1316 ) {
1317 adapter->stats.tx_packets++;
1318 adapter->stats.tx_bytes += skb->len;
1319 }
1320 if (buffer_info->mapped) {
1321 pr_debug("unmap buffer_info->dma : %d\n", i);
1322 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1323 buffer_info->length, DMA_TO_DEVICE);
1324 buffer_info->mapped = false;
1325 }
1326 if (buffer_info->skb) {
1327 pr_debug("trim buffer_info->skb : %d\n", i);
1328 skb_trim(buffer_info->skb, 0);
1329 }
1330 tx_desc->gbec_status = DSC_INIT16;
1331 if (unlikely(++i == tx_ring->count))
1332 i = 0;
1333 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1334
1335 /* weight of a sort for tx, to avoid endless transmit cleanup */
1336 if (cleaned_count++ == PCH_GBE_TX_WEIGHT)
1337 break;
1338 }
1339 pr_debug("called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1340 cleaned_count);
1341 /* Recover from running out of Tx resources in xmit_frame */
1342 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev)))) {
1343 netif_wake_queue(adapter->netdev);
1344 adapter->stats.tx_restart_count++;
1345 pr_debug("Tx wake queue\n");
1346 }
1347 spin_lock(&adapter->tx_queue_lock);
1348 tx_ring->next_to_clean = i;
1349 spin_unlock(&adapter->tx_queue_lock);
1350 pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1351 return cleaned;
1352}
1353
1354/**
1355 * pch_gbe_clean_rx - Send received data up the network stack; legacy
1356 * @adapter: Board private structure
1357 * @rx_ring: Rx descriptor ring
1358 * @work_done: Completed count
1359 * @work_to_do: Request count
1360 * Returns
1361 * true: Cleaned the descriptor
1362 * false: Not cleaned the descriptor
1363 */
1364static bool
1365pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1366 struct pch_gbe_rx_ring *rx_ring,
1367 int *work_done, int work_to_do)
1368{
1369 struct net_device *netdev = adapter->netdev;
1370 struct pci_dev *pdev = adapter->pdev;
1371 struct pch_gbe_buffer *buffer_info;
1372 struct pch_gbe_rx_desc *rx_desc;
1373 u32 length;
77555ee7
MO		 1374 unsigned int i;
1375 unsigned int cleaned_count = 0;
1376 bool cleaned = false;
ac096642 1377 struct sk_buff *skb, *new_skb;
77555ee7
MO		 1378 u8 dma_status;
1379 u16 gbec_status;
1380 u32 tcp_ip_status;
77555ee7
MO		 1381
1382 i = rx_ring->next_to_clean;
1383
1384 while (*work_done < work_to_do) {
1385 /* Check Rx descriptor status */
1386 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1387 if (rx_desc->gbec_status == DSC_INIT16)
1388 break;
1389 cleaned = true;
1390 cleaned_count++;
1391
1392 dma_status = rx_desc->dma_status;
1393 gbec_status = rx_desc->gbec_status;
1394 tcp_ip_status = rx_desc->tcp_ip_status;
1395 rx_desc->gbec_status = DSC_INIT16;
1396 buffer_info = &rx_ring->buffer_info[i];
1397 skb = buffer_info->skb;
1398
1399 /* unmap dma */
1400 dma_unmap_single(&pdev->dev, buffer_info->dma,
1401 buffer_info->length, DMA_FROM_DEVICE);
1402 buffer_info->mapped = false;
1403 /* Prefetch the packet */
1404 prefetch(skb->data);
1405
1406 pr_debug("RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x "
1407 "TCP:0x%08x] BufInf = 0x%p\n",
1408 i, dma_status, gbec_status, tcp_ip_status,
1409 buffer_info);
1410 /* Error check */
1411 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1412 adapter->stats.rx_frame_errors++;
1413 pr_err("Receive Not Octal Error\n");
1414 } else if (unlikely(gbec_status &
1415 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1416 adapter->stats.rx_frame_errors++;
1417 pr_err("Receive Nibble Error\n");
1418 } else if (unlikely(gbec_status &
1419 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1420 adapter->stats.rx_crc_errors++;
1421 pr_err("Receive CRC Error\n");
1422 } else {
1423 /* get receive length */
ac096642
TO		 1424 /* length convert[-3] */
1425 length = (rx_desc->rx_words_eob) - 3;
77555ee7
MO		 1426
1427 /* Decide the data conversion method */
1428 if (!adapter->rx_csum) {
1429 /* [Header:14][payload] */
ac096642
TO		 1430 if (NET_IP_ALIGN) {
1431 /* Because alignment differs,
1432 * the new_skb is newly allocated,
1433 * and data is copied to new_skb.*/
1434 new_skb = netdev_alloc_skb(netdev,
1435 length + NET_IP_ALIGN);
1436 if (!new_skb) {
1437 /* dorrop error */
1438 pr_err("New skb allocation "
1439 "Error\n");
1440 goto dorrop;
1441 }
1442 skb_reserve(new_skb, NET_IP_ALIGN);
1443 memcpy(new_skb->data, skb->data,
1444 length);
1445 skb = new_skb;
1446 } else {
1447 /* DMA buffer is used as SKB as it is.*/
1448 buffer_info->skb = NULL;
1449 }
77555ee7
MO		 1450 } else {
1451 /* [Header:14][padding:2][payload] */
ac096642
TO		 1452 /* The length includes padding length */
1453 length = length - PCH_GBE_DMA_PADDING;
1454 if ((length < copybreak) ||
1455 (NET_IP_ALIGN != PCH_GBE_DMA_PADDING)) {
1456 /* Because alignment differs,
1457 * the new_skb is newly allocated,
1458 * and data is copied to new_skb.
1459 * Padding data is deleted
1460 * at the time of a copy.*/
1461 new_skb = netdev_alloc_skb(netdev,
1462 length + NET_IP_ALIGN);
1463 if (!new_skb) {
1464 /* dorrop error */
1465 pr_err("New skb allocation "
1466 "Error\n");
1467 goto dorrop;
77555ee7 1468 }
ac096642 1469 skb_reserve(new_skb, NET_IP_ALIGN);
77555ee7 1470 memcpy(new_skb->data, skb->data,
ac096642
TO		 1471 ETH_HLEN);
1472 memcpy(&new_skb->data[ETH_HLEN],
1473 &skb->data[ETH_HLEN +
1474 PCH_GBE_DMA_PADDING],
1475 length - ETH_HLEN);
77555ee7 1476 skb = new_skb;
ac096642
TO		 1477 } else {
1478 /* Padding data is deleted
1479 * by moving header data.*/
1480 memmove(&skb->data[PCH_GBE_DMA_PADDING],
1481 &skb->data[0], ETH_HLEN);
1482 skb_reserve(skb, NET_IP_ALIGN);
1483 buffer_info->skb = NULL;
77555ee7 1484 }
77555ee7 1485 }
ac096642
TO		 1486 /* The length includes FCS length */
1487 length = length - ETH_FCS_LEN;
77555ee7
MO		 1488 /* update status of driver */
1489 adapter->stats.rx_bytes += length;
1490 adapter->stats.rx_packets++;
1491 if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1492 adapter->stats.multicast++;
1493 /* Write meta date of skb */
1494 skb_put(skb, length);
1495 skb->protocol = eth_type_trans(skb, netdev);
1496 if ((tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK) ==
1497 PCH_GBE_RXD_ACC_STAT_TCPIPOK) {
1498 skb->ip_summed = CHECKSUM_UNNECESSARY;
1499 } else {
1500 skb->ip_summed = CHECKSUM_NONE;
1501 }
1502 napi_gro_receive(&adapter->napi, skb);
1503 (*work_done)++;
1504 pr_debug("Receive skb->ip_summed: %d length: %d\n",
1505 skb->ip_summed, length);
1506 }
1507dorrop:
1508 /* return some buffers to hardware, one at a time is too slow */
1509 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1510 pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1511 cleaned_count);
1512 cleaned_count = 0;
1513 }
1514 if (++i == rx_ring->count)
1515 i = 0;
1516 }
1517 rx_ring->next_to_clean = i;
1518 if (cleaned_count)
1519 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1520 return cleaned;
1521}
1522
1523/**
1524 * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1525 * @adapter: Board private structure
1526 * @tx_ring: Tx descriptor ring (for a specific queue) to setup
1527 * Returns
1528 * 0: Successfully
1529 * Negative value: Failed
1530 */
1531int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1532 struct pch_gbe_tx_ring *tx_ring)
1533{
1534 struct pci_dev *pdev = adapter->pdev;
1535 struct pch_gbe_tx_desc *tx_desc;
1536 int size;
1537 int desNo;
1538
1539 size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
89bf67f1 1540 tx_ring->buffer_info = vzalloc(size);
77555ee7 1541 if (!tx_ring->buffer_info) {
25985edc 1542 pr_err("Unable to allocate memory for the buffer information\n");
77555ee7
MO		 1543 return -ENOMEM;
1544 }
77555ee7
MO		 1545
1546 tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1547
1548 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
1549 &tx_ring->dma, GFP_KERNEL);
1550 if (!tx_ring->desc) {
1551 vfree(tx_ring->buffer_info);
1552 pr_err("Unable to allocate memory for the transmit descriptor ring\n");
1553 return -ENOMEM;
1554 }
1555 memset(tx_ring->desc, 0, tx_ring->size);
1556
1557 tx_ring->next_to_use = 0;
1558 tx_ring->next_to_clean = 0;
1559 spin_lock_init(&tx_ring->tx_lock);
1560
1561 for (desNo = 0; desNo < tx_ring->count; desNo++) {
1562 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1563 tx_desc->gbec_status = DSC_INIT16;
1564 }
1565 pr_debug("tx_ring->desc = 0x%p tx_ring->dma = 0x%08llx\n"
1566 "next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1567 tx_ring->desc, (unsigned long long)tx_ring->dma,
1568 tx_ring->next_to_clean, tx_ring->next_to_use);
1569 return 0;
1570}
1571
1572/**
1573 * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1574 * @adapter: Board private structure
1575 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1576 * Returns
1577 * 0: Successfully
1578 * Negative value: Failed
1579 */
1580int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1581 struct pch_gbe_rx_ring *rx_ring)
1582{
1583 struct pci_dev *pdev = adapter->pdev;
1584 struct pch_gbe_rx_desc *rx_desc;
1585 int size;
1586 int desNo;
1587
1588 size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
89bf67f1 1589 rx_ring->buffer_info = vzalloc(size);
77555ee7
MO		 1590 if (!rx_ring->buffer_info) {
1591 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1592 return -ENOMEM;
1593 }
77555ee7
MO		 1594 rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1595 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
1596 &rx_ring->dma, GFP_KERNEL);
1597
1598 if (!rx_ring->desc) {
1599 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1600 vfree(rx_ring->buffer_info);
1601 return -ENOMEM;
1602 }
1603 memset(rx_ring->desc, 0, rx_ring->size);
1604 rx_ring->next_to_clean = 0;
1605 rx_ring->next_to_use = 0;
1606 for (desNo = 0; desNo < rx_ring->count; desNo++) {
1607 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1608 rx_desc->gbec_status = DSC_INIT16;
1609 }
1610 pr_debug("rx_ring->desc = 0x%p rx_ring->dma = 0x%08llx "
1611 "next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1612 rx_ring->desc, (unsigned long long)rx_ring->dma,
1613 rx_ring->next_to_clean, rx_ring->next_to_use);
1614 return 0;
1615}
1616
1617/**
1618 * pch_gbe_free_tx_resources - Free Tx Resources
1619 * @adapter: Board private structure
1620 * @tx_ring: Tx descriptor ring for a specific queue
1621 */
1622void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1623 struct pch_gbe_tx_ring *tx_ring)
1624{
1625 struct pci_dev *pdev = adapter->pdev;
1626
1627 pch_gbe_clean_tx_ring(adapter, tx_ring);
1628 vfree(tx_ring->buffer_info);
1629 tx_ring->buffer_info = NULL;
1630 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1631 tx_ring->desc = NULL;
1632}
1633
1634/**
1635 * pch_gbe_free_rx_resources - Free Rx Resources
1636 * @adapter: Board private structure
1637 * @rx_ring: Ring to clean the resources from
1638 */
1639void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1640 struct pch_gbe_rx_ring *rx_ring)
1641{
1642 struct pci_dev *pdev = adapter->pdev;
1643
1644 pch_gbe_clean_rx_ring(adapter, rx_ring);
1645 vfree(rx_ring->buffer_info);
1646 rx_ring->buffer_info = NULL;
1647 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1648 rx_ring->desc = NULL;
1649}
1650
1651/**
1652 * pch_gbe_request_irq - Allocate an interrupt line
1653 * @adapter: Board private structure
1654 * Returns
1655 * 0: Successfully
1656 * Negative value: Failed
1657 */
1658static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1659{
1660 struct net_device *netdev = adapter->netdev;
1661 int err;
1662 int flags;
1663
1664 flags = IRQF_SHARED;
1665 adapter->have_msi = false;
1666 err = pci_enable_msi(adapter->pdev);
1667 pr_debug("call pci_enable_msi\n");
1668 if (err) {
1669 pr_debug("call pci_enable_msi - Error: %d\n", err);
1670 } else {
1671 flags = 0;
1672 adapter->have_msi = true;
1673 }
1674 err = request_irq(adapter->pdev->irq, &pch_gbe_intr,
1675 flags, netdev->name, netdev);
1676 if (err)
1677 pr_err("Unable to allocate interrupt Error: %d\n", err);
1678 pr_debug("adapter->have_msi : %d flags : 0x%04x return : 0x%04x\n",
1679 adapter->have_msi, flags, err);
1680 return err;
1681}
1682
1683
1684static void pch_gbe_set_multi(struct net_device *netdev);
1685/**
1686 * pch_gbe_up - Up GbE network device
1687 * @adapter: Board private structure
1688 * Returns
1689 * 0: Successfully
1690 * Negative value: Failed
1691 */
1692int pch_gbe_up(struct pch_gbe_adapter *adapter)
1693{
1694 struct net_device *netdev = adapter->netdev;
1695 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1696 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1697 int err;
1698
1699 /* hardware has been reset, we need to reload some things */
1700 pch_gbe_set_multi(netdev);
1701
1702 pch_gbe_setup_tctl(adapter);
1703 pch_gbe_configure_tx(adapter);
1704 pch_gbe_setup_rctl(adapter);
1705 pch_gbe_configure_rx(adapter);
1706
1707 err = pch_gbe_request_irq(adapter);
1708 if (err) {
1709 pr_err("Error: can't bring device up\n");
1710 return err;
1711 }
1712 pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1713 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1714 adapter->tx_queue_len = netdev->tx_queue_len;
1715
1716 mod_timer(&adapter->watchdog_timer, jiffies);
1717
1718 napi_enable(&adapter->napi);
1719 pch_gbe_irq_enable(adapter);
1720 netif_start_queue(adapter->netdev);
1721
1722 return 0;
1723}
1724
1725/**
1726 * pch_gbe_down - Down GbE network device
1727 * @adapter: Board private structure
1728 */
1729void pch_gbe_down(struct pch_gbe_adapter *adapter)
1730{
1731 struct net_device *netdev = adapter->netdev;
1732
1733 /* signal that we're down so the interrupt handler does not
1734 * reschedule our watchdog timer */
1735 napi_disable(&adapter->napi);
1736 atomic_set(&adapter->irq_sem, 0);
1737
1738 pch_gbe_irq_disable(adapter);
1739 pch_gbe_free_irq(adapter);
1740
1741 del_timer_sync(&adapter->watchdog_timer);
1742
1743 netdev->tx_queue_len = adapter->tx_queue_len;
1744 netif_carrier_off(netdev);
1745 netif_stop_queue(netdev);
1746
1747 pch_gbe_reset(adapter);
1748 pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
1749 pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
1750}
1751
1752/**
1753 * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
1754 * @adapter: Board private structure to initialize
1755 * Returns
1756 * 0: Successfully
1757 * Negative value: Failed
1758 */
1759static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
1760{
1761 struct pch_gbe_hw *hw = &adapter->hw;
1762 struct net_device *netdev = adapter->netdev;
1763
1764 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
1765 hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1766 hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1767
1768 /* Initialize the hardware-specific values */
1769 if (pch_gbe_hal_setup_init_funcs(hw)) {
1770 pr_err("Hardware Initialization Failure\n");
1771 return -EIO;
1772 }
1773 if (pch_gbe_alloc_queues(adapter)) {
1774 pr_err("Unable to allocate memory for queues\n");
1775 return -ENOMEM;
1776 }
1777 spin_lock_init(&adapter->hw.miim_lock);
1778 spin_lock_init(&adapter->tx_queue_lock);
1779 spin_lock_init(&adapter->stats_lock);
1780 spin_lock_init(&adapter->ethtool_lock);
1781 atomic_set(&adapter->irq_sem, 0);
1782 pch_gbe_irq_disable(adapter);
1783
1784 pch_gbe_init_stats(adapter);
1785
1786 pr_debug("rx_buffer_len : %d mac.min_frame_size : %d mac.max_frame_size : %d\n",
1787 (u32) adapter->rx_buffer_len,
1788 hw->mac.min_frame_size, hw->mac.max_frame_size);
1789 return 0;
1790}
1791
1792/**
1793 * pch_gbe_open - Called when a network interface is made active
1794 * @netdev: Network interface device structure
1795 * Returns
1796 * 0: Successfully
1797 * Negative value: Failed
1798 */
1799static int pch_gbe_open(struct net_device *netdev)
1800{
1801 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1802 struct pch_gbe_hw *hw = &adapter->hw;
1803 int err;
1804
1805 /* allocate transmit descriptors */
1806 err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
1807 if (err)
1808 goto err_setup_tx;
1809 /* allocate receive descriptors */
1810 err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
1811 if (err)
1812 goto err_setup_rx;
1813 pch_gbe_hal_power_up_phy(hw);
1814 err = pch_gbe_up(adapter);
1815 if (err)
1816 goto err_up;
1817 pr_debug("Success End\n");
1818 return 0;
1819
1820err_up:
1821 if (!adapter->wake_up_evt)
1822 pch_gbe_hal_power_down_phy(hw);
1823 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1824err_setup_rx:
1825 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1826err_setup_tx:
1827 pch_gbe_reset(adapter);
1828 pr_err("Error End\n");
1829 return err;
1830}
1831
1832/**
1833 * pch_gbe_stop - Disables a network interface
1834 * @netdev: Network interface device structure
1835 * Returns
1836 * 0: Successfully
1837 */
1838static int pch_gbe_stop(struct net_device *netdev)
1839{
1840 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1841 struct pch_gbe_hw *hw = &adapter->hw;
1842
1843 pch_gbe_down(adapter);
1844 if (!adapter->wake_up_evt)
1845 pch_gbe_hal_power_down_phy(hw);
1846 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1847 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1848 return 0;
1849}
1850
1851/**
1852 * pch_gbe_xmit_frame - Packet transmitting start
1853 * @skb: Socket buffer structure
1854 * @netdev: Network interface device structure
1855 * Returns
1856 * - NETDEV_TX_OK: Normal end
1857 * - NETDEV_TX_BUSY: Error end
1858 */
1859static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1860{
1861 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1862 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1863 unsigned long flags;
1864
1865 if (unlikely(skb->len > (adapter->hw.mac.max_frame_size - 4))) {
77555ee7
MO		 1866 pr_err("Transfer length Error: skb len: %d > max: %d\n",
1867 skb->len, adapter->hw.mac.max_frame_size);
419c2046 1868 dev_kfree_skb_any(skb);
77555ee7
MO		 1869 adapter->stats.tx_length_errors++;
1870 return NETDEV_TX_OK;
1871 }
1872 if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags)) {
1873 /* Collision - tell upper layer to requeue */
1874 return NETDEV_TX_LOCKED;
1875 }
1876 if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
1877 netif_stop_queue(netdev);
1878 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1879 pr_debug("Return : BUSY next_to use : 0x%08x next_to clean : 0x%08x\n",
1880 tx_ring->next_to_use, tx_ring->next_to_clean);
1881 return NETDEV_TX_BUSY;
1882 }
1883 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1884
1885 /* CRC,ITAG no support */
1886 pch_gbe_tx_queue(adapter, tx_ring, skb);
1887 return NETDEV_TX_OK;
1888}
1889
1890/**
1891 * pch_gbe_get_stats - Get System Network Statistics
1892 * @netdev: Network interface device structure
1893 * Returns: The current stats
1894 */
1895static struct net_device_stats *pch_gbe_get_stats(struct net_device *netdev)
1896{
1897 /* only return the current stats */
1898 return &netdev->stats;
1899}
1900
1901/**
1902 * pch_gbe_set_multi - Multicast and Promiscuous mode set
1903 * @netdev: Network interface device structure
1904 */
1905static void pch_gbe_set_multi(struct net_device *netdev)
1906{
1907 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1908 struct pch_gbe_hw *hw = &adapter->hw;
1909 struct netdev_hw_addr *ha;
1910 u8 *mta_list;
1911 u32 rctl;
1912 int i;
1913 int mc_count;
1914
1915 pr_debug("netdev->flags : 0x%08x\n", netdev->flags);
1916
1917 /* Check for Promiscuous and All Multicast modes */
1918 rctl = ioread32(&hw->reg->RX_MODE);
1919 mc_count = netdev_mc_count(netdev);
1920 if ((netdev->flags & IFF_PROMISC)) {
1921 rctl &= ~PCH_GBE_ADD_FIL_EN;
1922 rctl &= ~PCH_GBE_MLT_FIL_EN;
1923 } else if ((netdev->flags & IFF_ALLMULTI)) {
1924 /* all the multicasting receive permissions */
1925 rctl |= PCH_GBE_ADD_FIL_EN;
1926 rctl &= ~PCH_GBE_MLT_FIL_EN;
1927 } else {
1928 if (mc_count >= PCH_GBE_MAR_ENTRIES) {
1929 /* all the multicasting receive permissions */
1930 rctl |= PCH_GBE_ADD_FIL_EN;
1931 rctl &= ~PCH_GBE_MLT_FIL_EN;
1932 } else {
1933 rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
1934 }
1935 }
1936 iowrite32(rctl, &hw->reg->RX_MODE);
1937
1938 if (mc_count >= PCH_GBE_MAR_ENTRIES)
1939 return;
1940 mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC);
1941 if (!mta_list)
1942 return;
1943
1944 /* The shared function expects a packed array of only addresses. */
1945 i = 0;
1946 netdev_for_each_mc_addr(ha, netdev) {
1947 if (i == mc_count)
1948 break;
1949 memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
1950 }
1951 pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
1952 PCH_GBE_MAR_ENTRIES);
1953 kfree(mta_list);
1954
1955 pr_debug("RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x netdev->mc_count : 0x%08x\n",
1956 ioread32(&hw->reg->RX_MODE), mc_count);
1957}
1958
1959/**
1960 * pch_gbe_set_mac - Change the Ethernet Address of the NIC
1961 * @netdev: Network interface device structure
1962 * @addr: Pointer to an address structure
1963 * Returns
1964 * 0: Successfully
1965 * -EADDRNOTAVAIL: Failed
1966 */
1967static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
1968{
1969 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1970 struct sockaddr *skaddr = addr;
1971 int ret_val;
1972
1973 if (!is_valid_ether_addr(skaddr->sa_data)) {
1974 ret_val = -EADDRNOTAVAIL;
1975 } else {
1976 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
1977 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
1978 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1979 ret_val = 0;
1980 }
1981 pr_debug("ret_val : 0x%08x\n", ret_val);
1982 pr_debug("dev_addr : %pM\n", netdev->dev_addr);
1983 pr_debug("mac_addr : %pM\n", adapter->hw.mac.addr);
1984 pr_debug("MAC_ADR1AB reg : 0x%08x 0x%08x\n",
1985 ioread32(&adapter->hw.reg->mac_adr[0].high),
1986 ioread32(&adapter->hw.reg->mac_adr[0].low));
1987 return ret_val;
1988}
1989
1990/**
1991 * pch_gbe_change_mtu - Change the Maximum Transfer Unit
1992 * @netdev: Network interface device structure
1993 * @new_mtu: New value for maximum frame size
1994 * Returns
1995 * 0: Successfully
1996 * -EINVAL: Failed
1997 */
1998static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
1999{
2000 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2001 int max_frame;
2002
2003 max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2004 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2005 (max_frame > PCH_GBE_MAX_JUMBO_FRAME_SIZE)) {
2006 pr_err("Invalid MTU setting\n");
2007 return -EINVAL;
2008 }
2009 if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2010 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2011 else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2012 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2013 else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2014 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2015 else
2016 adapter->rx_buffer_len = PCH_GBE_MAX_JUMBO_FRAME_SIZE;
2017 netdev->mtu = new_mtu;
2018 adapter->hw.mac.max_frame_size = max_frame;
2019
2020 if (netif_running(netdev))
2021 pch_gbe_reinit_locked(adapter);
2022 else
2023 pch_gbe_reset(adapter);
2024
2025 pr_debug("max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n",
2026 max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2027 adapter->hw.mac.max_frame_size);
2028 return 0;
2029}
2030
2031/**
2032 * pch_gbe_ioctl - Controls register through a MII interface
2033 * @netdev: Network interface device structure
2034 * @ifr: Pointer to ifr structure
2035 * @cmd: Control command
2036 * Returns
2037 * 0: Successfully
2038 * Negative value: Failed
2039 */
2040static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2041{
2042 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2043
2044 pr_debug("cmd : 0x%04x\n", cmd);
2045
2046 return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2047}
2048
2049/**
2050 * pch_gbe_tx_timeout - Respond to a Tx Hang
2051 * @netdev: Network interface device structure
2052 */
2053static void pch_gbe_tx_timeout(struct net_device *netdev)
2054{
2055 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2056
2057 /* Do the reset outside of interrupt context */
2058 adapter->stats.tx_timeout_count++;
2059 schedule_work(&adapter->reset_task);
2060}
2061
2062/**
2063 * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2064 * @napi: Pointer of polling device struct
2065 * @budget: The maximum number of a packet
2066 * Returns
2067 * false: Exit the polling mode
2068 * true: Continue the polling mode
2069 */
2070static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2071{
2072 struct pch_gbe_adapter *adapter =
2073 container_of(napi, struct pch_gbe_adapter, napi);
2074 struct net_device *netdev = adapter->netdev;
2075 int work_done = 0;
2076 bool poll_end_flag = false;
2077 bool cleaned = false;
2078
2079 pr_debug("budget : %d\n", budget);
2080
2081 /* Keep link state information with original netdev */
2082 if (!netif_carrier_ok(netdev)) {
2083 poll_end_flag = true;
2084 } else {
2085 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2086 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2087
2088 if (cleaned)
2089 work_done = budget;
2090 /* If no Tx and not enough Rx work done,
2091 * exit the polling mode
2092 */
2093 if ((work_done < budget) || !netif_running(netdev))
2094 poll_end_flag = true;
2095 }
2096
2097 if (poll_end_flag) {
2098 napi_complete(napi);
2099 pch_gbe_irq_enable(adapter);
2100 }
2101
2102 pr_debug("poll_end_flag : %d work_done : %d budget : %d\n",
2103 poll_end_flag, work_done, budget);
2104
2105 return work_done;
2106}
2107
2108#ifdef CONFIG_NET_POLL_CONTROLLER
2109/**
2110 * pch_gbe_netpoll - Used by things like netconsole to send skbs
2111 * @netdev: Network interface device structure
2112 */
2113static void pch_gbe_netpoll(struct net_device *netdev)
2114{
2115 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2116
2117 disable_irq(adapter->pdev->irq);
2118 pch_gbe_intr(adapter->pdev->irq, netdev);
2119 enable_irq(adapter->pdev->irq);
2120}
2121#endif
2122
2123static const struct net_device_ops pch_gbe_netdev_ops = {
2124 .ndo_open = pch_gbe_open,
2125 .ndo_stop = pch_gbe_stop,
2126 .ndo_start_xmit = pch_gbe_xmit_frame,
2127 .ndo_get_stats = pch_gbe_get_stats,
2128 .ndo_set_mac_address = pch_gbe_set_mac,
2129 .ndo_tx_timeout = pch_gbe_tx_timeout,
2130 .ndo_change_mtu = pch_gbe_change_mtu,
2131 .ndo_do_ioctl = pch_gbe_ioctl,
2132 .ndo_set_multicast_list = &pch_gbe_set_multi,
2133#ifdef CONFIG_NET_POLL_CONTROLLER
2134 .ndo_poll_controller = pch_gbe_netpoll,
2135#endif
2136};
2137
2138static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2139 pci_channel_state_t state)
2140{
2141 struct net_device *netdev = pci_get_drvdata(pdev);
2142 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2143
2144 netif_device_detach(netdev);
2145 if (netif_running(netdev))
2146 pch_gbe_down(adapter);
2147 pci_disable_device(pdev);
2148 /* Request a slot slot reset. */
2149 return PCI_ERS_RESULT_NEED_RESET;
2150}
2151
2152static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2153{
2154 struct net_device *netdev = pci_get_drvdata(pdev);
2155 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2156 struct pch_gbe_hw *hw = &adapter->hw;
2157
2158 if (pci_enable_device(pdev)) {
2159 pr_err("Cannot re-enable PCI device after reset\n");
2160 return PCI_ERS_RESULT_DISCONNECT;
2161 }
2162 pci_set_master(pdev);
2163 pci_enable_wake(pdev, PCI_D0, 0);
2164 pch_gbe_hal_power_up_phy(hw);
2165 pch_gbe_reset(adapter);
2166 /* Clear wake up status */
2167 pch_gbe_mac_set_wol_event(hw, 0);
2168
2169 return PCI_ERS_RESULT_RECOVERED;
2170}
2171
2172static void pch_gbe_io_resume(struct pci_dev *pdev)
2173{
2174 struct net_device *netdev = pci_get_drvdata(pdev);
2175 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2176
2177 if (netif_running(netdev)) {
2178 if (pch_gbe_up(adapter)) {
2179 pr_debug("can't bring device back up after reset\n");
2180 return;
2181 }
2182 }
2183 netif_device_attach(netdev);
2184}
2185
2186static int __pch_gbe_suspend(struct pci_dev *pdev)
2187{
2188 struct net_device *netdev = pci_get_drvdata(pdev);
2189 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2190 struct pch_gbe_hw *hw = &adapter->hw;
2191 u32 wufc = adapter->wake_up_evt;
2192 int retval = 0;
2193
2194 netif_device_detach(netdev);
2195 if (netif_running(netdev))
2196 pch_gbe_down(adapter);
2197 if (wufc) {
2198 pch_gbe_set_multi(netdev);
2199 pch_gbe_setup_rctl(adapter);
2200 pch_gbe_configure_rx(adapter);
2201 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2202 hw->mac.link_duplex);
2203 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2204 hw->mac.link_duplex);
2205 pch_gbe_mac_set_wol_event(hw, wufc);
2206 pci_disable_device(pdev);
2207 } else {
2208 pch_gbe_hal_power_down_phy(hw);
2209 pch_gbe_mac_set_wol_event(hw, wufc);
2210 pci_disable_device(pdev);
2211 }
2212 return retval;
2213}
2214
2215#ifdef CONFIG_PM
2216static int pch_gbe_suspend(struct device *device)
2217{
2218 struct pci_dev *pdev = to_pci_dev(device);
2219
2220 return __pch_gbe_suspend(pdev);
2221}
2222
2223static int pch_gbe_resume(struct device *device)
2224{
2225 struct pci_dev *pdev = to_pci_dev(device);
2226 struct net_device *netdev = pci_get_drvdata(pdev);
2227 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2228 struct pch_gbe_hw *hw = &adapter->hw;
2229 u32 err;
2230
2231 err = pci_enable_device(pdev);
2232 if (err) {
2233 pr_err("Cannot enable PCI device from suspend\n");
2234 return err;
2235 }
2236 pci_set_master(pdev);
2237 pch_gbe_hal_power_up_phy(hw);
2238 pch_gbe_reset(adapter);
2239 /* Clear wake on lan control and status */
2240 pch_gbe_mac_set_wol_event(hw, 0);
2241
2242 if (netif_running(netdev))
2243 pch_gbe_up(adapter);
2244 netif_device_attach(netdev);
2245
2246 return 0;
2247}
2248#endif /* CONFIG_PM */
2249
2250static void pch_gbe_shutdown(struct pci_dev *pdev)
2251{
2252 __pch_gbe_suspend(pdev);
2253 if (system_state == SYSTEM_POWER_OFF) {
2254 pci_wake_from_d3(pdev, true);
2255 pci_set_power_state(pdev, PCI_D3hot);
2256 }
2257}
2258
2259static void pch_gbe_remove(struct pci_dev *pdev)
2260{
2261 struct net_device *netdev = pci_get_drvdata(pdev);
2262 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2263
2321f3b4 2264 cancel_work_sync(&adapter->reset_task);
77555ee7
MO		 2265 unregister_netdev(netdev);
2266
2267 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2268
2269 kfree(adapter->tx_ring);
2270 kfree(adapter->rx_ring);
2271
2272 iounmap(adapter->hw.reg);
2273 pci_release_regions(pdev);
2274 free_netdev(netdev);
2275 pci_disable_device(pdev);
2276}
2277
2278static int pch_gbe_probe(struct pci_dev *pdev,
2279 const struct pci_device_id *pci_id)
2280{
2281 struct net_device *netdev;
2282 struct pch_gbe_adapter *adapter;
2283 int ret;
2284
2285 ret = pci_enable_device(pdev);
2286 if (ret)
2287 return ret;
2288
2289 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2290 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2291 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2292 if (ret) {
2293 ret = pci_set_consistent_dma_mask(pdev,
2294 DMA_BIT_MASK(32));
2295 if (ret) {
2296 dev_err(&pdev->dev, "ERR: No usable DMA "
2297 "configuration, aborting\n");
2298 goto err_disable_device;
2299 }
2300 }
2301 }
2302
2303 ret = pci_request_regions(pdev, KBUILD_MODNAME);
2304 if (ret) {
2305 dev_err(&pdev->dev,
2306 "ERR: Can't reserve PCI I/O and memory resources\n");
2307 goto err_disable_device;
2308 }
2309 pci_set_master(pdev);
2310
2311 netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2312 if (!netdev) {
2313 ret = -ENOMEM;
2314 dev_err(&pdev->dev,
2315 "ERR: Can't allocate and set up an Ethernet device\n");
2316 goto err_release_pci;
2317 }
2318 SET_NETDEV_DEV(netdev, &pdev->dev);
2319
2320 pci_set_drvdata(pdev, netdev);
2321 adapter = netdev_priv(netdev);
2322 adapter->netdev = netdev;
2323 adapter->pdev = pdev;
2324 adapter->hw.back = adapter;
2325 adapter->hw.reg = pci_iomap(pdev, PCH_GBE_PCI_BAR, 0);
2326 if (!adapter->hw.reg) {
2327 ret = -EIO;
2328 dev_err(&pdev->dev, "Can't ioremap\n");
2329 goto err_free_netdev;
2330 }
2331
2332 netdev->netdev_ops = &pch_gbe_netdev_ops;
2333 netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2334 netif_napi_add(netdev, &adapter->napi,
2335 pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
79032644 2336 netdev->features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_GRO;
77555ee7
MO		 2337 pch_gbe_set_ethtool_ops(netdev);
2338
98200ec2 2339 pch_gbe_mac_load_mac_addr(&adapter->hw);
77555ee7
MO		 2340 pch_gbe_mac_reset_hw(&adapter->hw);
2341
2342 /* setup the private structure */
2343 ret = pch_gbe_sw_init(adapter);
2344 if (ret)
2345 goto err_iounmap;
2346
2347 /* Initialize PHY */
2348 ret = pch_gbe_init_phy(adapter);
2349 if (ret) {
2350 dev_err(&pdev->dev, "PHY initialize error\n");
2351 goto err_free_adapter;
2352 }
2353 pch_gbe_hal_get_bus_info(&adapter->hw);
2354
2355 /* Read the MAC address. and store to the private data */
2356 ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2357 if (ret) {
2358 dev_err(&pdev->dev, "MAC address Read Error\n");
2359 goto err_free_adapter;
2360 }
2361
2362 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2363 if (!is_valid_ether_addr(netdev->dev_addr)) {
2364 dev_err(&pdev->dev, "Invalid MAC Address\n");
2365 ret = -EIO;
2366 goto err_free_adapter;
2367 }
2368 setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog,
2369 (unsigned long)adapter);
2370
2371 INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2372
2373 pch_gbe_check_options(adapter);
2374
2375 if (adapter->tx_csum)
79032644 2376 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
77555ee7 2377 else
79032644 2378 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
77555ee7
MO		 2379
2380 /* initialize the wol settings based on the eeprom settings */
2381 adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2382 dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2383
2384 /* reset the hardware with the new settings */
2385 pch_gbe_reset(adapter);
2386
2387 ret = register_netdev(netdev);
2388 if (ret)
2389 goto err_free_adapter;
2390 /* tell the stack to leave us alone until pch_gbe_open() is called */
2391 netif_carrier_off(netdev);
2392 netif_stop_queue(netdev);
2393
2394 dev_dbg(&pdev->dev, "OKIsemi(R) PCH Network Connection\n");
2395
2396 device_set_wakeup_enable(&pdev->dev, 1);
2397 return 0;
2398
2399err_free_adapter:
2400 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2401 kfree(adapter->tx_ring);
2402 kfree(adapter->rx_ring);
2403err_iounmap:
2404 iounmap(adapter->hw.reg);
2405err_free_netdev:
2406 free_netdev(netdev);
2407err_release_pci:
2408 pci_release_regions(pdev);
2409err_disable_device:
2410 pci_disable_device(pdev);
2411 return ret;
2412}
2413
7fc44633 2414static DEFINE_PCI_DEVICE_TABLE(pch_gbe_pcidev_id) = {
77555ee7
MO		 2415 {.vendor = PCI_VENDOR_ID_INTEL,
2416 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2417 .subvendor = PCI_ANY_ID,
2418 .subdevice = PCI_ANY_ID,
2419 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2420 .class_mask = (0xFFFF00)
2421 },
2422 /* required last entry */
2423 {0}
2424};
2425
2426#ifdef CONFIG_PM
2427static const struct dev_pm_ops pch_gbe_pm_ops = {
2428 .suspend = pch_gbe_suspend,
2429 .resume = pch_gbe_resume,
2430 .freeze = pch_gbe_suspend,
2431 .thaw = pch_gbe_resume,
2432 .poweroff = pch_gbe_suspend,
2433 .restore = pch_gbe_resume,
2434};
2435#endif
2436
2437static struct pci_error_handlers pch_gbe_err_handler = {
2438 .error_detected = pch_gbe_io_error_detected,
2439 .slot_reset = pch_gbe_io_slot_reset,
2440 .resume = pch_gbe_io_resume
2441};
2442
f7594d42 2443static struct pci_driver pch_gbe_driver = {
77555ee7
MO		 2444 .name = KBUILD_MODNAME,
2445 .id_table = pch_gbe_pcidev_id,
2446 .probe = pch_gbe_probe,
2447 .remove = pch_gbe_remove,
aa338601 2448#ifdef CONFIG_PM
77555ee7
MO		 2449 .driver.pm = &pch_gbe_pm_ops,
2450#endif
2451 .shutdown = pch_gbe_shutdown,
2452 .err_handler = &pch_gbe_err_handler
2453};
2454
2455
2456static int __init pch_gbe_init_module(void)
2457{
2458 int ret;
2459
f7594d42 2460 ret = pci_register_driver(&pch_gbe_driver);
77555ee7
MO		 2461 if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
2462 if (copybreak == 0) {
2463 pr_info("copybreak disabled\n");
2464 } else {
2465 pr_info("copybreak enabled for packets <= %u bytes\n",
2466 copybreak);
2467 }
2468 }
2469 return ret;
2470}
2471
2472static void __exit pch_gbe_exit_module(void)
2473{
f7594d42 2474 pci_unregister_driver(&pch_gbe_driver);
77555ee7
MO		 2475}
2476
2477module_init(pch_gbe_init_module);
2478module_exit(pch_gbe_exit_module);
2479
a1dcfcb7
TO		 2480MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2481MODULE_AUTHOR("OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com>");
77555ee7
MO		 2482MODULE_LICENSE("GPL");
2483MODULE_VERSION(DRV_VERSION);
2484MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2485
2486module_param(copybreak, uint, 0644);
2487MODULE_PARM_DESC(copybreak,
2488 "Maximum size of packet that is copied to a new buffer on receive");
2489
2490/* pch_gbe_main.c */
Linux kernel - Deliverables
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