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[PATCH] pcnet32: Suspend the chip rather than restart when changing multicast/promisc
[deliverable/linux.git] / drivers / net / pcnet32.c
CommitLineData
1da177e4
LT		 1/* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2/*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15/**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24#define DRV_NAME "pcnet32"
ac62ef04
DF		 25#define DRV_VERSION "1.32"
26#define DRV_RELDATE "18.Mar.2006"
1da177e4
LT		 27#define PFX DRV_NAME ": "
28
4a5e8e29
JG		 29static const char *const version =
30 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
1da177e4
LT		 31
32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/string.h>
35#include <linux/errno.h>
36#include <linux/ioport.h>
37#include <linux/slab.h>
38#include <linux/interrupt.h>
39#include <linux/pci.h>
40#include <linux/delay.h>
41#include <linux/init.h>
42#include <linux/ethtool.h>
43#include <linux/mii.h>
44#include <linux/crc32.h>
45#include <linux/netdevice.h>
46#include <linux/etherdevice.h>
47#include <linux/skbuff.h>
48#include <linux/spinlock.h>
49#include <linux/moduleparam.h>
50#include <linux/bitops.h>
51
52#include <asm/dma.h>
53#include <asm/io.h>
54#include <asm/uaccess.h>
55#include <asm/irq.h>
56
57/*
58 * PCI device identifiers for "new style" Linux PCI Device Drivers
59 */
60static struct pci_device_id pcnet32_pci_tbl[] = {
f2622a2b
DF		 61 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
4a5e8e29
JG		 63
64 /*
65 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
66 * the incorrect vendor id.
67 */
f2622a2b
DF		 68 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
69 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
4a5e8e29
JG		 70
71 { } /* terminate list */
1da177e4
LT		 72};
73
4a5e8e29 74MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
1da177e4
LT		 75
76static int cards_found;
77
78/*
79 * VLB I/O addresses
80 */
81static unsigned int pcnet32_portlist[] __initdata =
4a5e8e29 82 { 0x300, 0x320, 0x340, 0x360, 0 };
1da177e4
LT		 83
84static int pcnet32_debug = 0;
4a5e8e29
JG		 85static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
86static int pcnet32vlb; /* check for VLB cards ? */
1da177e4
LT		 87
88static struct net_device *pcnet32_dev;
89
90static int max_interrupt_work = 2;
91static int rx_copybreak = 200;
92
93#define PCNET32_PORT_AUI 0x00
94#define PCNET32_PORT_10BT 0x01
95#define PCNET32_PORT_GPSI 0x02
96#define PCNET32_PORT_MII 0x03
97
98#define PCNET32_PORT_PORTSEL 0x03
99#define PCNET32_PORT_ASEL 0x04
100#define PCNET32_PORT_100 0x40
101#define PCNET32_PORT_FD 0x80
102
103#define PCNET32_DMA_MASK 0xffffffff
104
105#define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
106#define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
107
108/*
109 * table to translate option values from tulip
110 * to internal options
111 */
f71e1309 112static const unsigned char options_mapping[] = {
4a5e8e29
JG		 113 PCNET32_PORT_ASEL, /* 0 Auto-select */
114 PCNET32_PORT_AUI, /* 1 BNC/AUI */
115 PCNET32_PORT_AUI, /* 2 AUI/BNC */
116 PCNET32_PORT_ASEL, /* 3 not supported */
117 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
118 PCNET32_PORT_ASEL, /* 5 not supported */
119 PCNET32_PORT_ASEL, /* 6 not supported */
120 PCNET32_PORT_ASEL, /* 7 not supported */
121 PCNET32_PORT_ASEL, /* 8 not supported */
122 PCNET32_PORT_MII, /* 9 MII 10baseT */
123 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
124 PCNET32_PORT_MII, /* 11 MII (autosel) */
125 PCNET32_PORT_10BT, /* 12 10BaseT */
126 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
127 /* 14 MII 100BaseTx-FD */
128 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
129 PCNET32_PORT_ASEL /* 15 not supported */
1da177e4
LT		 130};
131
132static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
4a5e8e29 133 "Loopback test (offline)"
1da177e4 134};
4a5e8e29 135
1da177e4
LT		 136#define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
137
ac62ef04 138#define PCNET32_NUM_REGS 136
1da177e4 139
4a5e8e29 140#define MAX_UNITS 8 /* More are supported, limit only on options */
1da177e4
LT		 141static int options[MAX_UNITS];
142static int full_duplex[MAX_UNITS];
143static int homepna[MAX_UNITS];
144
145/*
146 * Theory of Operation
147 *
148 * This driver uses the same software structure as the normal lance
149 * driver. So look for a verbose description in lance.c. The differences
150 * to the normal lance driver is the use of the 32bit mode of PCnet32
151 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
152 * 16MB limitation and we don't need bounce buffers.
153 */
154
1da177e4
LT		 155/*
156 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
157 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
158 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
159 */
160#ifndef PCNET32_LOG_TX_BUFFERS
eabf0415
HWL		 161#define PCNET32_LOG_TX_BUFFERS 4
162#define PCNET32_LOG_RX_BUFFERS 5
163#define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
164#define PCNET32_LOG_MAX_RX_BUFFERS 9
1da177e4
LT		 165#endif
166
167#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
eabf0415 168#define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
1da177e4
LT		 169
170#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
eabf0415 171#define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
1da177e4
LT		 172
173#define PKT_BUF_SZ 1544
174
175/* Offsets from base I/O address. */
176#define PCNET32_WIO_RDP 0x10
177#define PCNET32_WIO_RAP 0x12
178#define PCNET32_WIO_RESET 0x14
179#define PCNET32_WIO_BDP 0x16
180
181#define PCNET32_DWIO_RDP 0x10
182#define PCNET32_DWIO_RAP 0x14
183#define PCNET32_DWIO_RESET 0x18
184#define PCNET32_DWIO_BDP 0x1C
185
186#define PCNET32_TOTAL_SIZE 0x20
187
06c87850
DF		 188#define CSR0 0
189#define CSR0_INIT 0x1
190#define CSR0_START 0x2
191#define CSR0_STOP 0x4
192#define CSR0_TXPOLL 0x8
193#define CSR0_INTEN 0x40
194#define CSR0_IDON 0x0100
195#define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
196#define PCNET32_INIT_LOW 1
197#define PCNET32_INIT_HIGH 2
198#define CSR3 3
199#define CSR4 4
200#define CSR5 5
201#define CSR5_SUSPEND 0x0001
202#define CSR15 15
203#define PCNET32_MC_FILTER 8
204
1da177e4
LT		 205/* The PCNET32 Rx and Tx ring descriptors. */
206struct pcnet32_rx_head {
0b5bf225
JG		 207 u32 base;
208 s16 buf_length;
209 s16 status;
210 u32 msg_length;
211 u32 reserved;
1da177e4
LT		 212};
213
214struct pcnet32_tx_head {
0b5bf225
JG		 215 u32 base;
216 s16 length;
217 s16 status;
218 u32 misc;
219 u32 reserved;
1da177e4
LT		 220};
221
222/* The PCNET32 32-Bit initialization block, described in databook. */
223struct pcnet32_init_block {
0b5bf225
JG		 224 u16 mode;
225 u16 tlen_rlen;
226 u8 phys_addr[6];
227 u16 reserved;
228 u32 filter[2];
4a5e8e29 229 /* Receive and transmit ring base, along with extra bits. */
0b5bf225
JG		 230 u32 rx_ring;
231 u32 tx_ring;
1da177e4
LT		 232};
233
234/* PCnet32 access functions */
235struct pcnet32_access {
4a5e8e29
JG		 236 u16 (*read_csr) (unsigned long, int);
237 void (*write_csr) (unsigned long, int, u16);
238 u16 (*read_bcr) (unsigned long, int);
239 void (*write_bcr) (unsigned long, int, u16);
240 u16 (*read_rap) (unsigned long);
241 void (*write_rap) (unsigned long, u16);
242 void (*reset) (unsigned long);
1da177e4
LT		 243};
244
245/*
76209926
HWL		 246 * The first field of pcnet32_private is read by the ethernet device
247 * so the structure should be allocated using pci_alloc_consistent().
1da177e4
LT		 248 */
249struct pcnet32_private {
4a5e8e29
JG		 250 struct pcnet32_init_block init_block;
251 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
0b5bf225
JG		 252 struct pcnet32_rx_head *rx_ring;
253 struct pcnet32_tx_head *tx_ring;
254 dma_addr_t dma_addr;/* DMA address of beginning of this
255 object, returned by pci_alloc_consistent */
256 struct pci_dev *pci_dev;
257 const char *name;
4a5e8e29 258 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
0b5bf225
JG		 259 struct sk_buff **tx_skbuff;
260 struct sk_buff **rx_skbuff;
261 dma_addr_t *tx_dma_addr;
262 dma_addr_t *rx_dma_addr;
263 struct pcnet32_access a;
264 spinlock_t lock; /* Guard lock */
265 unsigned int cur_rx, cur_tx; /* The next free ring entry */
266 unsigned int rx_ring_size; /* current rx ring size */
267 unsigned int tx_ring_size; /* current tx ring size */
268 unsigned int rx_mod_mask; /* rx ring modular mask */
269 unsigned int tx_mod_mask; /* tx ring modular mask */
270 unsigned short rx_len_bits;
271 unsigned short tx_len_bits;
272 dma_addr_t rx_ring_dma_addr;
273 dma_addr_t tx_ring_dma_addr;
274 unsigned int dirty_rx, /* ring entries to be freed. */
275 dirty_tx;
276
277 struct net_device_stats stats;
278 char tx_full;
279 char phycount; /* number of phys found */
280 int options;
281 unsigned int shared_irq:1, /* shared irq possible */
282 dxsuflo:1, /* disable transmit stop on uflo */
283 mii:1; /* mii port available */
284 struct net_device *next;
285 struct mii_if_info mii_if;
286 struct timer_list watchdog_timer;
287 struct timer_list blink_timer;
288 u32 msg_enable; /* debug message level */
4a5e8e29
JG		 289
290 /* each bit indicates an available PHY */
0b5bf225 291 u32 phymask;
1da177e4
LT		 292};
293
4a5e8e29
JG		 294static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
295static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
296static int pcnet32_open(struct net_device *);
297static int pcnet32_init_ring(struct net_device *);
298static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
299static int pcnet32_rx(struct net_device *);
300static void pcnet32_tx_timeout(struct net_device *dev);
1da177e4 301static irqreturn_t pcnet32_interrupt(int, void *, struct pt_regs *);
4a5e8e29 302static int pcnet32_close(struct net_device *);
1da177e4
LT		 303static struct net_device_stats *pcnet32_get_stats(struct net_device *);
304static void pcnet32_load_multicast(struct net_device *dev);
305static void pcnet32_set_multicast_list(struct net_device *);
4a5e8e29 306static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
1da177e4
LT		 307static void pcnet32_watchdog(struct net_device *);
308static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
4a5e8e29
JG		 309static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
310 int val);
1da177e4
LT		 311static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
312static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29
JG		 313 struct ethtool_test *eth_test, u64 * data);
314static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
1da177e4
LT		 315static int pcnet32_phys_id(struct net_device *dev, u32 data);
316static void pcnet32_led_blink_callback(struct net_device *dev);
317static int pcnet32_get_regs_len(struct net_device *dev);
318static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 319 void *ptr);
1bcd3153 320static void pcnet32_purge_tx_ring(struct net_device *dev);
a88c844c 321static int pcnet32_alloc_ring(struct net_device *dev, char *name);
eabf0415 322static void pcnet32_free_ring(struct net_device *dev);
ac62ef04 323static void pcnet32_check_media(struct net_device *dev, int verbose);
eabf0415 324
4a5e8e29 325static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
1da177e4 326{
4a5e8e29
JG		 327 outw(index, addr + PCNET32_WIO_RAP);
328 return inw(addr + PCNET32_WIO_RDP);
1da177e4
LT		 329}
330
4a5e8e29 331static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 332{
4a5e8e29
JG		 333 outw(index, addr + PCNET32_WIO_RAP);
334 outw(val, addr + PCNET32_WIO_RDP);
1da177e4
LT		 335}
336
4a5e8e29 337static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
1da177e4 338{
4a5e8e29
JG		 339 outw(index, addr + PCNET32_WIO_RAP);
340 return inw(addr + PCNET32_WIO_BDP);
1da177e4
LT		 341}
342
4a5e8e29 343static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 344{
4a5e8e29
JG		 345 outw(index, addr + PCNET32_WIO_RAP);
346 outw(val, addr + PCNET32_WIO_BDP);
1da177e4
LT		 347}
348
4a5e8e29 349static u16 pcnet32_wio_read_rap(unsigned long addr)
1da177e4 350{
4a5e8e29 351 return inw(addr + PCNET32_WIO_RAP);
1da177e4
LT		 352}
353
4a5e8e29 354static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
1da177e4 355{
4a5e8e29 356 outw(val, addr + PCNET32_WIO_RAP);
1da177e4
LT		 357}
358
4a5e8e29 359static void pcnet32_wio_reset(unsigned long addr)
1da177e4 360{
4a5e8e29 361 inw(addr + PCNET32_WIO_RESET);
1da177e4
LT		 362}
363
4a5e8e29 364static int pcnet32_wio_check(unsigned long addr)
1da177e4 365{
4a5e8e29
JG		 366 outw(88, addr + PCNET32_WIO_RAP);
367 return (inw(addr + PCNET32_WIO_RAP) == 88);
1da177e4
LT		 368}
369
370static struct pcnet32_access pcnet32_wio = {
4a5e8e29
JG		 371 .read_csr = pcnet32_wio_read_csr,
372 .write_csr = pcnet32_wio_write_csr,
373 .read_bcr = pcnet32_wio_read_bcr,
374 .write_bcr = pcnet32_wio_write_bcr,
375 .read_rap = pcnet32_wio_read_rap,
376 .write_rap = pcnet32_wio_write_rap,
377 .reset = pcnet32_wio_reset
1da177e4
LT		 378};
379
4a5e8e29 380static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
1da177e4 381{
4a5e8e29
JG		 382 outl(index, addr + PCNET32_DWIO_RAP);
383 return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
1da177e4
LT		 384}
385
4a5e8e29 386static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 387{
4a5e8e29
JG		 388 outl(index, addr + PCNET32_DWIO_RAP);
389 outl(val, addr + PCNET32_DWIO_RDP);
1da177e4
LT		 390}
391
4a5e8e29 392static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
1da177e4 393{
4a5e8e29
JG		 394 outl(index, addr + PCNET32_DWIO_RAP);
395 return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
1da177e4
LT		 396}
397
4a5e8e29 398static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 399{
4a5e8e29
JG		 400 outl(index, addr + PCNET32_DWIO_RAP);
401 outl(val, addr + PCNET32_DWIO_BDP);
1da177e4
LT		 402}
403
4a5e8e29 404static u16 pcnet32_dwio_read_rap(unsigned long addr)
1da177e4 405{
4a5e8e29 406 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
1da177e4
LT		 407}
408
4a5e8e29 409static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
1da177e4 410{
4a5e8e29 411 outl(val, addr + PCNET32_DWIO_RAP);
1da177e4
LT		 412}
413
4a5e8e29 414static void pcnet32_dwio_reset(unsigned long addr)
1da177e4 415{
4a5e8e29 416 inl(addr + PCNET32_DWIO_RESET);
1da177e4
LT		 417}
418
4a5e8e29 419static int pcnet32_dwio_check(unsigned long addr)
1da177e4 420{
4a5e8e29
JG		 421 outl(88, addr + PCNET32_DWIO_RAP);
422 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
1da177e4
LT		 423}
424
425static struct pcnet32_access pcnet32_dwio = {
4a5e8e29
JG		 426 .read_csr = pcnet32_dwio_read_csr,
427 .write_csr = pcnet32_dwio_write_csr,
428 .read_bcr = pcnet32_dwio_read_bcr,
429 .write_bcr = pcnet32_dwio_write_bcr,
430 .read_rap = pcnet32_dwio_read_rap,
431 .write_rap = pcnet32_dwio_write_rap,
432 .reset = pcnet32_dwio_reset
1da177e4
LT		 433};
434
06c87850
DF		 435static void pcnet32_netif_stop(struct net_device *dev)
436{
437 dev->trans_start = jiffies;
438 netif_poll_disable(dev);
439 netif_tx_disable(dev);
440}
441
442static void pcnet32_netif_start(struct net_device *dev)
443{
444 netif_wake_queue(dev);
445 netif_poll_enable(dev);
446}
447
448/*
449 * Allocate space for the new sized tx ring.
450 * Free old resources
451 * Save new resources.
452 * Any failure keeps old resources.
453 * Must be called with lp->lock held.
454 */
455static void pcnet32_realloc_tx_ring(struct net_device *dev,
456 struct pcnet32_private *lp,
457 unsigned int size)
458{
459 dma_addr_t new_ring_dma_addr;
460 dma_addr_t *new_dma_addr_list;
461 struct pcnet32_tx_head *new_tx_ring;
462 struct sk_buff **new_skb_list;
463
464 pcnet32_purge_tx_ring(dev);
465
466 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
467 sizeof(struct pcnet32_tx_head) *
468 (1 << size),
469 &new_ring_dma_addr);
470 if (new_tx_ring == NULL) {
471 if (netif_msg_drv(lp))
472 printk("\n" KERN_ERR
473 "%s: Consistent memory allocation failed.\n",
474 dev->name);
475 return;
476 }
477 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
478
479 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
480 GFP_ATOMIC);
481 if (!new_dma_addr_list) {
482 if (netif_msg_drv(lp))
483 printk("\n" KERN_ERR
484 "%s: Memory allocation failed.\n", dev->name);
485 goto free_new_tx_ring;
486 }
487
488 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
489 GFP_ATOMIC);
490 if (!new_skb_list) {
491 if (netif_msg_drv(lp))
492 printk("\n" KERN_ERR
493 "%s: Memory allocation failed.\n", dev->name);
494 goto free_new_lists;
495 }
496
497 kfree(lp->tx_skbuff);
498 kfree(lp->tx_dma_addr);
499 pci_free_consistent(lp->pci_dev,
500 sizeof(struct pcnet32_tx_head) *
501 lp->tx_ring_size, lp->tx_ring,
502 lp->tx_ring_dma_addr);
503
504 lp->tx_ring_size = (1 << size);
505 lp->tx_mod_mask = lp->tx_ring_size - 1;
506 lp->tx_len_bits = (size << 12);
507 lp->tx_ring = new_tx_ring;
508 lp->tx_ring_dma_addr = new_ring_dma_addr;
509 lp->tx_dma_addr = new_dma_addr_list;
510 lp->tx_skbuff = new_skb_list;
511 return;
512
513 free_new_lists:
514 kfree(new_dma_addr_list);
515 free_new_tx_ring:
516 pci_free_consistent(lp->pci_dev,
517 sizeof(struct pcnet32_tx_head) *
518 (1 << size),
519 new_tx_ring,
520 new_ring_dma_addr);
521 return;
522}
523
524/*
525 * Allocate space for the new sized rx ring.
526 * Re-use old receive buffers.
527 * alloc extra buffers
528 * free unneeded buffers
529 * free unneeded buffers
530 * Save new resources.
531 * Any failure keeps old resources.
532 * Must be called with lp->lock held.
533 */
534static void pcnet32_realloc_rx_ring(struct net_device *dev,
535 struct pcnet32_private *lp,
536 unsigned int size)
537{
538 dma_addr_t new_ring_dma_addr;
539 dma_addr_t *new_dma_addr_list;
540 struct pcnet32_rx_head *new_rx_ring;
541 struct sk_buff **new_skb_list;
542 int new, overlap;
543
544 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
545 sizeof(struct pcnet32_rx_head) *
546 (1 << size),
547 &new_ring_dma_addr);
548 if (new_rx_ring == NULL) {
549 if (netif_msg_drv(lp))
550 printk("\n" KERN_ERR
551 "%s: Consistent memory allocation failed.\n",
552 dev->name);
553 return;
554 }
555 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
556
557 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
558 GFP_ATOMIC);
559 if (!new_dma_addr_list) {
560 if (netif_msg_drv(lp))
561 printk("\n" KERN_ERR
562 "%s: Memory allocation failed.\n", dev->name);
563 goto free_new_rx_ring;
564 }
565
566 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
567 GFP_ATOMIC);
568 if (!new_skb_list) {
569 if (netif_msg_drv(lp))
570 printk("\n" KERN_ERR
571 "%s: Memory allocation failed.\n", dev->name);
572 goto free_new_lists;
573 }
574
575 /* first copy the current receive buffers */
576 overlap = min(size, lp->rx_ring_size);
577 for (new = 0; new < overlap; new++) {
578 new_rx_ring[new] = lp->rx_ring[new];
579 new_dma_addr_list[new] = lp->rx_dma_addr[new];
580 new_skb_list[new] = lp->rx_skbuff[new];
581 }
582 /* now allocate any new buffers needed */
583 for (; new < size; new++ ) {
584 struct sk_buff *rx_skbuff;
585 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SZ);
586 if (!(rx_skbuff = new_skb_list[new])) {
587 /* keep the original lists and buffers */
588 if (netif_msg_drv(lp))
589 printk(KERN_ERR
590 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
591 dev->name);
592 goto free_all_new;
593 }
594 skb_reserve(rx_skbuff, 2);
595
596 new_dma_addr_list[new] =
597 pci_map_single(lp->pci_dev, rx_skbuff->data,
598 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
599 new_rx_ring[new].base = (u32) le32_to_cpu(new_dma_addr_list[new]);
600 new_rx_ring[new].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
601 new_rx_ring[new].status = le16_to_cpu(0x8000);
602 }
603 /* and free any unneeded buffers */
604 for (; new < lp->rx_ring_size; new++) {
605 if (lp->rx_skbuff[new]) {
606 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
607 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
608 dev_kfree_skb(lp->rx_skbuff[new]);
609 }
610 }
611
612 kfree(lp->rx_skbuff);
613 kfree(lp->rx_dma_addr);
614 pci_free_consistent(lp->pci_dev,
615 sizeof(struct pcnet32_rx_head) *
616 lp->rx_ring_size, lp->rx_ring,
617 lp->rx_ring_dma_addr);
618
619 lp->rx_ring_size = (1 << size);
620 lp->rx_mod_mask = lp->rx_ring_size - 1;
621 lp->rx_len_bits = (size << 4);
622 lp->rx_ring = new_rx_ring;
623 lp->rx_ring_dma_addr = new_ring_dma_addr;
624 lp->rx_dma_addr = new_dma_addr_list;
625 lp->rx_skbuff = new_skb_list;
626 return;
627
628 free_all_new:
629 for (; --new >= lp->rx_ring_size; ) {
630 if (new_skb_list[new]) {
631 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
632 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
633 dev_kfree_skb(new_skb_list[new]);
634 }
635 }
636 kfree(new_skb_list);
637 free_new_lists:
638 kfree(new_dma_addr_list);
639 free_new_rx_ring:
640 pci_free_consistent(lp->pci_dev,
641 sizeof(struct pcnet32_rx_head) *
642 (1 << size),
643 new_rx_ring,
644 new_ring_dma_addr);
645 return;
646}
647
1da177e4
LT		 648#ifdef CONFIG_NET_POLL_CONTROLLER
649static void pcnet32_poll_controller(struct net_device *dev)
650{
4a5e8e29
JG		 651 disable_irq(dev->irq);
652 pcnet32_interrupt(0, dev, NULL);
653 enable_irq(dev->irq);
1da177e4
LT		 654}
655#endif
656
1da177e4
LT		 657static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
658{
4a5e8e29
JG		 659 struct pcnet32_private *lp = dev->priv;
660 unsigned long flags;
661 int r = -EOPNOTSUPP;
1da177e4 662
4a5e8e29
JG		 663 if (lp->mii) {
664 spin_lock_irqsave(&lp->lock, flags);
665 mii_ethtool_gset(&lp->mii_if, cmd);
666 spin_unlock_irqrestore(&lp->lock, flags);
667 r = 0;
668 }
669 return r;
1da177e4
LT		 670}
671
672static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
673{
4a5e8e29
JG		 674 struct pcnet32_private *lp = dev->priv;
675 unsigned long flags;
676 int r = -EOPNOTSUPP;
1da177e4 677
4a5e8e29
JG		 678 if (lp->mii) {
679 spin_lock_irqsave(&lp->lock, flags);
680 r = mii_ethtool_sset(&lp->mii_if, cmd);
681 spin_unlock_irqrestore(&lp->lock, flags);
682 }
683 return r;
1da177e4
LT		 684}
685
4a5e8e29
JG		 686static void pcnet32_get_drvinfo(struct net_device *dev,
687 struct ethtool_drvinfo *info)
1da177e4 688{
4a5e8e29
JG		 689 struct pcnet32_private *lp = dev->priv;
690
691 strcpy(info->driver, DRV_NAME);
692 strcpy(info->version, DRV_VERSION);
693 if (lp->pci_dev)
694 strcpy(info->bus_info, pci_name(lp->pci_dev));
695 else
696 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
1da177e4
LT		 697}
698
699static u32 pcnet32_get_link(struct net_device *dev)
700{
4a5e8e29
JG		 701 struct pcnet32_private *lp = dev->priv;
702 unsigned long flags;
703 int r;
1da177e4 704
4a5e8e29
JG		 705 spin_lock_irqsave(&lp->lock, flags);
706 if (lp->mii) {
707 r = mii_link_ok(&lp->mii_if);
708 } else {
709 ulong ioaddr = dev->base_addr; /* card base I/O address */
710 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
711 }
712 spin_unlock_irqrestore(&lp->lock, flags);
713
714 return r;
1da177e4
LT		 715}
716
717static u32 pcnet32_get_msglevel(struct net_device *dev)
718{
4a5e8e29
JG		 719 struct pcnet32_private *lp = dev->priv;
720 return lp->msg_enable;
1da177e4
LT		 721}
722
723static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
724{
4a5e8e29
JG		 725 struct pcnet32_private *lp = dev->priv;
726 lp->msg_enable = value;
1da177e4
LT		 727}
728
729static int pcnet32_nway_reset(struct net_device *dev)
730{
4a5e8e29
JG		 731 struct pcnet32_private *lp = dev->priv;
732 unsigned long flags;
733 int r = -EOPNOTSUPP;
1da177e4 734
4a5e8e29
JG		 735 if (lp->mii) {
736 spin_lock_irqsave(&lp->lock, flags);
737 r = mii_nway_restart(&lp->mii_if);
738 spin_unlock_irqrestore(&lp->lock, flags);
739 }
740 return r;
1da177e4
LT		 741}
742
4a5e8e29
JG		 743static void pcnet32_get_ringparam(struct net_device *dev,
744 struct ethtool_ringparam *ering)
1da177e4 745{
4a5e8e29 746 struct pcnet32_private *lp = dev->priv;
1da177e4 747
6dcd60c2
DF		 748 ering->tx_max_pending = TX_MAX_RING_SIZE;
749 ering->tx_pending = lp->tx_ring_size;
750 ering->rx_max_pending = RX_MAX_RING_SIZE;
751 ering->rx_pending = lp->rx_ring_size;
eabf0415
HWL		 752}
753
4a5e8e29
JG		 754static int pcnet32_set_ringparam(struct net_device *dev,
755 struct ethtool_ringparam *ering)
eabf0415 756{
4a5e8e29
JG		 757 struct pcnet32_private *lp = dev->priv;
758 unsigned long flags;
06c87850
DF		 759 unsigned int size;
760 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 761 int i;
762
763 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
764 return -EINVAL;
765
766 if (netif_running(dev))
06c87850 767 pcnet32_netif_stop(dev);
4a5e8e29
JG		 768
769 spin_lock_irqsave(&lp->lock, flags);
06c87850
DF		 770 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
771
772 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
4a5e8e29
JG		 773
774 /* set the minimum ring size to 4, to allow the loopback test to work
775 * unchanged.
776 */
777 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
06c87850 778 if (size <= (1 << i))
4a5e8e29
JG		 779 break;
780 }
06c87850
DF		 781 if ((1 << i) != lp->tx_ring_size)
782 pcnet32_realloc_tx_ring(dev, lp, i);
783
784 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
4a5e8e29 785 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
06c87850 786 if (size <= (1 << i))
4a5e8e29
JG		 787 break;
788 }
06c87850
DF		 789 if ((1 << i) != lp->rx_ring_size)
790 pcnet32_realloc_rx_ring(dev, lp, i);
791
792 dev->weight = lp->rx_ring_size / 2;
793
794 if (netif_running(dev)) {
795 pcnet32_netif_start(dev);
796 pcnet32_restart(dev, CSR0_NORMAL);
4a5e8e29 797 }
eabf0415 798
4a5e8e29 799 spin_unlock_irqrestore(&lp->lock, flags);
eabf0415 800
06c87850
DF		 801 if (netif_msg_drv(lp))
802 printk(KERN_INFO
4a5e8e29
JG		 803 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
804 lp->rx_ring_size, lp->tx_ring_size);
eabf0415 805
4a5e8e29 806 return 0;
1da177e4
LT		 807}
808
4a5e8e29
JG		 809static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
810 u8 * data)
1da177e4 811{
4a5e8e29 812 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
1da177e4
LT		 813}
814
815static int pcnet32_self_test_count(struct net_device *dev)
816{
4a5e8e29 817 return PCNET32_TEST_LEN;
1da177e4
LT		 818}
819
820static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29 821 struct ethtool_test *test, u64 * data)
1da177e4 822{
4a5e8e29
JG		 823 struct pcnet32_private *lp = dev->priv;
824 int rc;
825
826 if (test->flags == ETH_TEST_FL_OFFLINE) {
827 rc = pcnet32_loopback_test(dev, data);
828 if (rc) {
829 if (netif_msg_hw(lp))
830 printk(KERN_DEBUG "%s: Loopback test failed.\n",
831 dev->name);
832 test->flags |= ETH_TEST_FL_FAILED;
833 } else if (netif_msg_hw(lp))
834 printk(KERN_DEBUG "%s: Loopback test passed.\n",
835 dev->name);
1da177e4 836 } else if (netif_msg_hw(lp))
4a5e8e29
JG		 837 printk(KERN_DEBUG
838 "%s: No tests to run (specify 'Offline' on ethtool).",
839 dev->name);
840} /* end pcnet32_ethtool_test */
1da177e4 841
4a5e8e29 842static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
1da177e4 843{
4a5e8e29
JG		 844 struct pcnet32_private *lp = dev->priv;
845 struct pcnet32_access *a = &lp->a; /* access to registers */
846 ulong ioaddr = dev->base_addr; /* card base I/O address */
847 struct sk_buff *skb; /* sk buff */
848 int x, i; /* counters */
849 int numbuffs = 4; /* number of TX/RX buffers and descs */
850 u16 status = 0x8300; /* TX ring status */
851 u16 teststatus; /* test of ring status */
852 int rc; /* return code */
853 int size; /* size of packets */
854 unsigned char *packet; /* source packet data */
855 static const int data_len = 60; /* length of source packets */
856 unsigned long flags;
857 unsigned long ticks;
858
859 *data1 = 1; /* status of test, default to fail */
860 rc = 1; /* default to fail */
861
862 if (netif_running(dev))
863 pcnet32_close(dev);
864
865 spin_lock_irqsave(&lp->lock, flags);
866
867 /* Reset the PCNET32 */
868 lp->a.reset(ioaddr);
869
870 /* switch pcnet32 to 32bit mode */
871 lp->a.write_bcr(ioaddr, 20, 2);
872
873 lp->init_block.mode =
874 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
875 lp->init_block.filter[0] = 0;
876 lp->init_block.filter[1] = 0;
877
878 /* purge & init rings but don't actually restart */
879 pcnet32_restart(dev, 0x0000);
880
881 lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */
882
883 /* Initialize Transmit buffers. */
884 size = data_len + 15;
885 for (x = 0; x < numbuffs; x++) {
886 if (!(skb = dev_alloc_skb(size))) {
887 if (netif_msg_hw(lp))
888 printk(KERN_DEBUG
889 "%s: Cannot allocate skb at line: %d!\n",
890 dev->name, __LINE__);
891 goto clean_up;
892 } else {
893 packet = skb->data;
894 skb_put(skb, size); /* create space for data */
895 lp->tx_skbuff[x] = skb;
896 lp->tx_ring[x].length = le16_to_cpu(-skb->len);
897 lp->tx_ring[x].misc = 0;
898
899 /* put DA and SA into the skb */
900 for (i = 0; i < 6; i++)
901 *packet++ = dev->dev_addr[i];
902 for (i = 0; i < 6; i++)
903 *packet++ = dev->dev_addr[i];
904 /* type */
905 *packet++ = 0x08;
906 *packet++ = 0x06;
907 /* packet number */
908 *packet++ = x;
909 /* fill packet with data */
910 for (i = 0; i < data_len; i++)
911 *packet++ = i;
912
913 lp->tx_dma_addr[x] =
914 pci_map_single(lp->pci_dev, skb->data, skb->len,
915 PCI_DMA_TODEVICE);
916 lp->tx_ring[x].base =
917 (u32) le32_to_cpu(lp->tx_dma_addr[x]);
918 wmb(); /* Make sure owner changes after all others are visible */
919 lp->tx_ring[x].status = le16_to_cpu(status);
920 }
1da177e4 921 }
1da177e4 922
4a5e8e29
JG		 923 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BSR32 */
924 x = x | 0x0002;
925 a->write_bcr(ioaddr, 32, x);
926
927 lp->a.write_csr(ioaddr, 15, 0x0044); /* set int loopback in CSR15 */
928
929 teststatus = le16_to_cpu(0x8000);
930 lp->a.write_csr(ioaddr, 0, 0x0002); /* Set STRT bit */
931
932 /* Check status of descriptors */
933 for (x = 0; x < numbuffs; x++) {
934 ticks = 0;
935 rmb();
936 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
937 spin_unlock_irqrestore(&lp->lock, flags);
938 mdelay(1);
939 spin_lock_irqsave(&lp->lock, flags);
940 rmb();
941 ticks++;
942 }
943 if (ticks == 200) {
944 if (netif_msg_hw(lp))
945 printk("%s: Desc %d failed to reset!\n",
946 dev->name, x);
947 break;
948 }
949 }
950
951 lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */
952 wmb();
953 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
954 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
955
956 for (x = 0; x < numbuffs; x++) {
957 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
958 skb = lp->rx_skbuff[x];
959 for (i = 0; i < size; i++) {
960 printk("%02x ", *(skb->data + i));
961 }
962 printk("\n");
963 }
964 }
1da177e4 965
4a5e8e29
JG		 966 x = 0;
967 rc = 0;
968 while (x < numbuffs && !rc) {
969 skb = lp->rx_skbuff[x];
970 packet = lp->tx_skbuff[x]->data;
971 for (i = 0; i < size; i++) {
972 if (*(skb->data + i) != packet[i]) {
973 if (netif_msg_hw(lp))
974 printk(KERN_DEBUG
975 "%s: Error in compare! %2x - %02x %02x\n",
976 dev->name, i, *(skb->data + i),
977 packet[i]);
978 rc = 1;
979 break;
980 }
981 }
982 x++;
983 }
984 if (!rc) {
985 *data1 = 0;
986 }
1da177e4 987
4a5e8e29
JG		 988 clean_up:
989 pcnet32_purge_tx_ring(dev);
990 x = a->read_csr(ioaddr, 15) & 0xFFFF;
991 a->write_csr(ioaddr, 15, (x & ~0x0044)); /* reset bits 6 and 2 */
1da177e4 992
4a5e8e29
JG		 993 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
994 x = x & ~0x0002;
995 a->write_bcr(ioaddr, 32, x);
1da177e4 996
4a5e8e29
JG		 997 spin_unlock_irqrestore(&lp->lock, flags);
998
999 if (netif_running(dev)) {
1000 pcnet32_open(dev);
1001 } else {
1002 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1003 }
1004
1005 return (rc);
1006} /* end pcnet32_loopback_test */
1da177e4
LT		 1007
1008static void pcnet32_led_blink_callback(struct net_device *dev)
1009{
4a5e8e29
JG		 1010 struct pcnet32_private *lp = dev->priv;
1011 struct pcnet32_access *a = &lp->a;
1012 ulong ioaddr = dev->base_addr;
1013 unsigned long flags;
1014 int i;
1015
1016 spin_lock_irqsave(&lp->lock, flags);
1017 for (i = 4; i < 8; i++) {
1018 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1019 }
1020 spin_unlock_irqrestore(&lp->lock, flags);
1021
1022 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1da177e4
LT		 1023}
1024
1025static int pcnet32_phys_id(struct net_device *dev, u32 data)
1026{
4a5e8e29
JG		 1027 struct pcnet32_private *lp = dev->priv;
1028 struct pcnet32_access *a = &lp->a;
1029 ulong ioaddr = dev->base_addr;
1030 unsigned long flags;
1031 int i, regs[4];
1032
1033 if (!lp->blink_timer.function) {
1034 init_timer(&lp->blink_timer);
1035 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1036 lp->blink_timer.data = (unsigned long)dev;
1037 }
1038
1039 /* Save the current value of the bcrs */
1040 spin_lock_irqsave(&lp->lock, flags);
1041 for (i = 4; i < 8; i++) {
1042 regs[i - 4] = a->read_bcr(ioaddr, i);
1043 }
1044 spin_unlock_irqrestore(&lp->lock, flags);
1045
1046 mod_timer(&lp->blink_timer, jiffies);
1047 set_current_state(TASK_INTERRUPTIBLE);
1048
1049 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1050 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1051
1052 msleep_interruptible(data * 1000);
1053 del_timer_sync(&lp->blink_timer);
1054
1055 /* Restore the original value of the bcrs */
1056 spin_lock_irqsave(&lp->lock, flags);
1057 for (i = 4; i < 8; i++) {
1058 a->write_bcr(ioaddr, i, regs[i - 4]);
1059 }
1060 spin_unlock_irqrestore(&lp->lock, flags);
1061
1062 return 0;
1da177e4
LT		 1063}
1064
df27f4a6
DF		 1065/*
1066 * lp->lock must be held.
1067 */
1068static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1069 int can_sleep)
1070{
1071 int csr5;
1072 struct pcnet32_private *lp = dev->priv;
1073 struct pcnet32_access *a = &lp->a;
1074 ulong ioaddr = dev->base_addr;
1075 int ticks;
1076
1077 /* set SUSPEND (SPND) - CSR5 bit 0 */
1078 csr5 = a->read_csr(ioaddr, CSR5);
1079 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1080
1081 /* poll waiting for bit to be set */
1082 ticks = 0;
1083 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1084 spin_unlock_irqrestore(&lp->lock, *flags);
1085 if (can_sleep)
1086 msleep(1);
1087 else
1088 mdelay(1);
1089 spin_lock_irqsave(&lp->lock, *flags);
1090 ticks++;
1091 if (ticks > 200) {
1092 if (netif_msg_hw(lp))
1093 printk(KERN_DEBUG
1094 "%s: Error getting into suspend!\n",
1095 dev->name);
1096 return 0;
1097 }
1098 }
1099 return 1;
1100}
1101
ac62ef04
DF		 1102#define PCNET32_REGS_PER_PHY 32
1103#define PCNET32_MAX_PHYS 32
1da177e4
LT		 1104static int pcnet32_get_regs_len(struct net_device *dev)
1105{
4a5e8e29
JG		 1106 struct pcnet32_private *lp = dev->priv;
1107 int j = lp->phycount * PCNET32_REGS_PER_PHY;
ac62ef04 1108
4a5e8e29 1109 return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1da177e4
LT		 1110}
1111
1112static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 1113 void *ptr)
1da177e4 1114{
4a5e8e29
JG		 1115 int i, csr0;
1116 u16 *buff = ptr;
1117 struct pcnet32_private *lp = dev->priv;
1118 struct pcnet32_access *a = &lp->a;
1119 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 1120 unsigned long flags;
1121
1122 spin_lock_irqsave(&lp->lock, flags);
1123
df27f4a6
DF		 1124 csr0 = a->read_csr(ioaddr, CSR0);
1125 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1126 pcnet32_suspend(dev, &flags, 1);
1da177e4 1127
4a5e8e29
JG		 1128 /* read address PROM */
1129 for (i = 0; i < 16; i += 2)
1130 *buff++ = inw(ioaddr + i);
1131
1132 /* read control and status registers */
1133 for (i = 0; i < 90; i++) {
1134 *buff++ = a->read_csr(ioaddr, i);
1135 }
1136
1137 *buff++ = a->read_csr(ioaddr, 112);
1138 *buff++ = a->read_csr(ioaddr, 114);
1da177e4 1139
4a5e8e29
JG		 1140 /* read bus configuration registers */
1141 for (i = 0; i < 30; i++) {
1142 *buff++ = a->read_bcr(ioaddr, i);
1143 }
1144 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1145 for (i = 31; i < 36; i++) {
1146 *buff++ = a->read_bcr(ioaddr, i);
1147 }
1148
1149 /* read mii phy registers */
1150 if (lp->mii) {
1151 int j;
1152 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1153 if (lp->phymask & (1 << j)) {
1154 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1155 lp->a.write_bcr(ioaddr, 33,
1156 (j << 5) | i);
1157 *buff++ = lp->a.read_bcr(ioaddr, 34);
1158 }
1159 }
1160 }
1161 }
1162
df27f4a6
DF		 1163 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1164 int csr5;
1165
4a5e8e29 1166 /* clear SUSPEND (SPND) - CSR5 bit 0 */
df27f4a6
DF		 1167 csr5 = a->read_csr(ioaddr, CSR5);
1168 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
4a5e8e29
JG		 1169 }
1170
1171 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 1172}
1173
1174static struct ethtool_ops pcnet32_ethtool_ops = {
4a5e8e29
JG		 1175 .get_settings = pcnet32_get_settings,
1176 .set_settings = pcnet32_set_settings,
1177 .get_drvinfo = pcnet32_get_drvinfo,
1178 .get_msglevel = pcnet32_get_msglevel,
1179 .set_msglevel = pcnet32_set_msglevel,
1180 .nway_reset = pcnet32_nway_reset,
1181 .get_link = pcnet32_get_link,
1182 .get_ringparam = pcnet32_get_ringparam,
1183 .set_ringparam = pcnet32_set_ringparam,
1184 .get_tx_csum = ethtool_op_get_tx_csum,
1185 .get_sg = ethtool_op_get_sg,
1186 .get_tso = ethtool_op_get_tso,
1187 .get_strings = pcnet32_get_strings,
1188 .self_test_count = pcnet32_self_test_count,
1189 .self_test = pcnet32_ethtool_test,
1190 .phys_id = pcnet32_phys_id,
1191 .get_regs_len = pcnet32_get_regs_len,
1192 .get_regs = pcnet32_get_regs,
1193 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1194};
1195
1196/* only probes for non-PCI devices, the rest are handled by
1197 * pci_register_driver via pcnet32_probe_pci */
1198
dcaf9769 1199static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1da177e4 1200{
4a5e8e29
JG		 1201 unsigned int *port, ioaddr;
1202
1203 /* search for PCnet32 VLB cards at known addresses */
1204 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1205 if (request_region
1206 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1207 /* check if there is really a pcnet chip on that ioaddr */
1208 if ((inb(ioaddr + 14) == 0x57)
1209 && (inb(ioaddr + 15) == 0x57)) {
1210 pcnet32_probe1(ioaddr, 0, NULL);
1211 } else {
1212 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1213 }
1214 }
1215 }
1da177e4
LT		 1216}
1217
1da177e4
LT		 1218static int __devinit
1219pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1220{
4a5e8e29
JG		 1221 unsigned long ioaddr;
1222 int err;
1223
1224 err = pci_enable_device(pdev);
1225 if (err < 0) {
1226 if (pcnet32_debug & NETIF_MSG_PROBE)
1227 printk(KERN_ERR PFX
1228 "failed to enable device -- err=%d\n", err);
1229 return err;
1230 }
1231 pci_set_master(pdev);
1232
1233 ioaddr = pci_resource_start(pdev, 0);
1234 if (!ioaddr) {
1235 if (pcnet32_debug & NETIF_MSG_PROBE)
1236 printk(KERN_ERR PFX
1237 "card has no PCI IO resources, aborting\n");
1238 return -ENODEV;
1239 }
1da177e4 1240
4a5e8e29
JG		 1241 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1242 if (pcnet32_debug & NETIF_MSG_PROBE)
1243 printk(KERN_ERR PFX
1244 "architecture does not support 32bit PCI busmaster DMA\n");
1245 return -ENODEV;
1246 }
1247 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1248 NULL) {
1249 if (pcnet32_debug & NETIF_MSG_PROBE)
1250 printk(KERN_ERR PFX
1251 "io address range already allocated\n");
1252 return -EBUSY;
1253 }
1da177e4 1254
4a5e8e29
JG		 1255 err = pcnet32_probe1(ioaddr, 1, pdev);
1256 if (err < 0) {
1257 pci_disable_device(pdev);
1258 }
1259 return err;
1da177e4
LT		 1260}
1261
1da177e4
LT		 1262/* pcnet32_probe1
1263 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1264 * pdev will be NULL when called from pcnet32_probe_vlbus.
1265 */
1266static int __devinit
1267pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1268{
4a5e8e29
JG		 1269 struct pcnet32_private *lp;
1270 dma_addr_t lp_dma_addr;
1271 int i, media;
1272 int fdx, mii, fset, dxsuflo;
1273 int chip_version;
1274 char *chipname;
1275 struct net_device *dev;
1276 struct pcnet32_access *a = NULL;
1277 u8 promaddr[6];
1278 int ret = -ENODEV;
1279
1280 /* reset the chip */
1281 pcnet32_wio_reset(ioaddr);
1282
1283 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1284 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1285 a = &pcnet32_wio;
1286 } else {
1287 pcnet32_dwio_reset(ioaddr);
1288 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1289 && pcnet32_dwio_check(ioaddr)) {
1290 a = &pcnet32_dwio;
1291 } else
1292 goto err_release_region;
1293 }
1294
1295 chip_version =
1296 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1297 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1298 printk(KERN_INFO " PCnet chip version is %#x.\n",
1299 chip_version);
1300 if ((chip_version & 0xfff) != 0x003) {
1301 if (pcnet32_debug & NETIF_MSG_PROBE)
1302 printk(KERN_INFO PFX "Unsupported chip version.\n");
1303 goto err_release_region;
1304 }
1305
1306 /* initialize variables */
1307 fdx = mii = fset = dxsuflo = 0;
1308 chip_version = (chip_version >> 12) & 0xffff;
1309
1310 switch (chip_version) {
1311 case 0x2420:
1312 chipname = "PCnet/PCI 79C970"; /* PCI */
1313 break;
1314 case 0x2430:
1315 if (shared)
1316 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1317 else
1318 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1319 break;
1320 case 0x2621:
1321 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1322 fdx = 1;
1323 break;
1324 case 0x2623:
1325 chipname = "PCnet/FAST 79C971"; /* PCI */
1326 fdx = 1;
1327 mii = 1;
1328 fset = 1;
1329 break;
1330 case 0x2624:
1331 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1332 fdx = 1;
1333 mii = 1;
1334 fset = 1;
1335 break;
1336 case 0x2625:
1337 chipname = "PCnet/FAST III 79C973"; /* PCI */
1338 fdx = 1;
1339 mii = 1;
1340 break;
1341 case 0x2626:
1342 chipname = "PCnet/Home 79C978"; /* PCI */
1343 fdx = 1;
1344 /*
1345 * This is based on specs published at www.amd.com. This section
1346 * assumes that a card with a 79C978 wants to go into standard
1347 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1348 * and the module option homepna=1 can select this instead.
1349 */
1350 media = a->read_bcr(ioaddr, 49);
1351 media &= ~3; /* default to 10Mb ethernet */
1352 if (cards_found < MAX_UNITS && homepna[cards_found])
1353 media |= 1; /* switch to home wiring mode */
1354 if (pcnet32_debug & NETIF_MSG_PROBE)
1355 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1356 (media & 1) ? "1" : "10");
1357 a->write_bcr(ioaddr, 49, media);
1358 break;
1359 case 0x2627:
1360 chipname = "PCnet/FAST III 79C975"; /* PCI */
1361 fdx = 1;
1362 mii = 1;
1363 break;
1364 case 0x2628:
1365 chipname = "PCnet/PRO 79C976";
1366 fdx = 1;
1367 mii = 1;
1368 break;
1369 default:
1370 if (pcnet32_debug & NETIF_MSG_PROBE)
1371 printk(KERN_INFO PFX
1372 "PCnet version %#x, no PCnet32 chip.\n",
1373 chip_version);
1374 goto err_release_region;
1375 }
1376
1da177e4 1377 /*
4a5e8e29
JG		 1378 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1379 * starting until the packet is loaded. Strike one for reliability, lose
1380 * one for latency - although on PCI this isnt a big loss. Older chips
1381 * have FIFO's smaller than a packet, so you can't do this.
1382 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1da177e4 1383 */
4a5e8e29
JG		 1384
1385 if (fset) {
1386 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1387 a->write_csr(ioaddr, 80,
1388 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1389 dxsuflo = 1;
1390 }
1391
1392 dev = alloc_etherdev(0);
1393 if (!dev) {
1394 if (pcnet32_debug & NETIF_MSG_PROBE)
1395 printk(KERN_ERR PFX "Memory allocation failed.\n");
1396 ret = -ENOMEM;
1397 goto err_release_region;
1398 }
1399 SET_NETDEV_DEV(dev, &pdev->dev);
1400
1da177e4 1401 if (pcnet32_debug & NETIF_MSG_PROBE)
4a5e8e29
JG		 1402 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1403
1404 /* In most chips, after a chip reset, the ethernet address is read from the
1405 * station address PROM at the base address and programmed into the
1406 * "Physical Address Registers" CSR12-14.
1407 * As a precautionary measure, we read the PROM values and complain if
bc0e1fc9
LV		 1408 * they disagree with the CSRs. If they miscompare, and the PROM addr
1409 * is valid, then the PROM addr is used.
4a5e8e29
JG		 1410 */
1411 for (i = 0; i < 3; i++) {
1412 unsigned int val;
1413 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1414 /* There may be endianness issues here. */
1415 dev->dev_addr[2 * i] = val & 0x0ff;
1416 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1417 }
1418
1419 /* read PROM address and compare with CSR address */
1da177e4 1420 for (i = 0; i < 6; i++)
4a5e8e29
JG		 1421 promaddr[i] = inb(ioaddr + i);
1422
1423 if (memcmp(promaddr, dev->dev_addr, 6)
1424 || !is_valid_ether_addr(dev->dev_addr)) {
1425 if (is_valid_ether_addr(promaddr)) {
1426 if (pcnet32_debug & NETIF_MSG_PROBE) {
1427 printk(" warning: CSR address invalid,\n");
1428 printk(KERN_INFO
1429 " using instead PROM address of");
1430 }
1431 memcpy(dev->dev_addr, promaddr, 6);
1432 }
1433 }
1434 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1435
1436 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1437 if (!is_valid_ether_addr(dev->perm_addr))
1438 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1439
1440 if (pcnet32_debug & NETIF_MSG_PROBE) {
1441 for (i = 0; i < 6; i++)
1442 printk(" %2.2x", dev->dev_addr[i]);
1443
1444 /* Version 0x2623 and 0x2624 */
1445 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1446 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1447 printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i);
1448 switch (i >> 10) {
1449 case 0:
1450 printk(" 20 bytes,");
1451 break;
1452 case 1:
1453 printk(" 64 bytes,");
1454 break;
1455 case 2:
1456 printk(" 128 bytes,");
1457 break;
1458 case 3:
1459 printk("~220 bytes,");
1460 break;
1461 }
1462 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1463 printk(" BCR18(%x):", i & 0xffff);
1464 if (i & (1 << 5))
1465 printk("BurstWrEn ");
1466 if (i & (1 << 6))
1467 printk("BurstRdEn ");
1468 if (i & (1 << 7))
1469 printk("DWordIO ");
1470 if (i & (1 << 11))
1471 printk("NoUFlow ");
1472 i = a->read_bcr(ioaddr, 25);
1473 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
1474 i = a->read_bcr(ioaddr, 26);
1475 printk(" SRAM_BND=0x%04x,", i << 8);
1476 i = a->read_bcr(ioaddr, 27);
1477 if (i & (1 << 14))
1478 printk("LowLatRx");
1479 }
1480 }
1481
1482 dev->base_addr = ioaddr;
1483 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1484 if ((lp =
1485 pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) {
1486 if (pcnet32_debug & NETIF_MSG_PROBE)
1487 printk(KERN_ERR PFX
1488 "Consistent memory allocation failed.\n");
1489 ret = -ENOMEM;
1490 goto err_free_netdev;
1491 }
1492
1493 memset(lp, 0, sizeof(*lp));
1494 lp->dma_addr = lp_dma_addr;
1495 lp->pci_dev = pdev;
1496
1497 spin_lock_init(&lp->lock);
1498
1499 SET_MODULE_OWNER(dev);
1500 SET_NETDEV_DEV(dev, &pdev->dev);
1501 dev->priv = lp;
1502 lp->name = chipname;
1503 lp->shared_irq = shared;
1504 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1505 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1506 lp->tx_mod_mask = lp->tx_ring_size - 1;
1507 lp->rx_mod_mask = lp->rx_ring_size - 1;
1508 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1509 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1510 lp->mii_if.full_duplex = fdx;
1511 lp->mii_if.phy_id_mask = 0x1f;
1512 lp->mii_if.reg_num_mask = 0x1f;
1513 lp->dxsuflo = dxsuflo;
1514 lp->mii = mii;
1515 lp->msg_enable = pcnet32_debug;
1516 if ((cards_found >= MAX_UNITS)
1517 || (options[cards_found] > sizeof(options_mapping)))
1518 lp->options = PCNET32_PORT_ASEL;
1519 else
1520 lp->options = options_mapping[options[cards_found]];
1521 lp->mii_if.dev = dev;
1522 lp->mii_if.mdio_read = mdio_read;
1523 lp->mii_if.mdio_write = mdio_write;
1524
1525 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1526 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1527 lp->options |= PCNET32_PORT_FD;
1528
1529 if (!a) {
1530 if (pcnet32_debug & NETIF_MSG_PROBE)
1531 printk(KERN_ERR PFX "No access methods\n");
1532 ret = -ENODEV;
1533 goto err_free_consistent;
1534 }
1535 lp->a = *a;
1536
1537 /* prior to register_netdev, dev->name is not yet correct */
1538 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1539 ret = -ENOMEM;
1540 goto err_free_ring;
1541 }
1542 /* detect special T1/E1 WAN card by checking for MAC address */
1543 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1da177e4 1544 && dev->dev_addr[2] == 0x75)
4a5e8e29 1545 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1da177e4 1546
4a5e8e29
JG		 1547 lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1548 lp->init_block.tlen_rlen =
1549 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
1550 for (i = 0; i < 6; i++)
1551 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1552 lp->init_block.filter[0] = 0x00000000;
1553 lp->init_block.filter[1] = 0x00000000;
1554 lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
1555 lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
1556
1557 /* switch pcnet32 to 32bit mode */
1558 a->write_bcr(ioaddr, 20, 2);
1559
1560 a->write_csr(ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private,
1561 init_block)) & 0xffff);
1562 a->write_csr(ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private,
1563 init_block)) >> 16);
1564
1565 if (pdev) { /* use the IRQ provided by PCI */
1566 dev->irq = pdev->irq;
1567 if (pcnet32_debug & NETIF_MSG_PROBE)
1568 printk(" assigned IRQ %d.\n", dev->irq);
1569 } else {
1570 unsigned long irq_mask = probe_irq_on();
1571
1572 /*
1573 * To auto-IRQ we enable the initialization-done and DMA error
1574 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1575 * boards will work.
1576 */
1577 /* Trigger an initialization just for the interrupt. */
1578 a->write_csr(ioaddr, 0, 0x41);
1579 mdelay(1);
1580
1581 dev->irq = probe_irq_off(irq_mask);
1582 if (!dev->irq) {
1583 if (pcnet32_debug & NETIF_MSG_PROBE)
1584 printk(", failed to detect IRQ line.\n");
1585 ret = -ENODEV;
1586 goto err_free_ring;
1587 }
1588 if (pcnet32_debug & NETIF_MSG_PROBE)
1589 printk(", probed IRQ %d.\n", dev->irq);
1590 }
1da177e4 1591
4a5e8e29
JG		 1592 /* Set the mii phy_id so that we can query the link state */
1593 if (lp->mii) {
1594 /* lp->phycount and lp->phymask are set to 0 by memset above */
1595
1596 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1597 /* scan for PHYs */
1598 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1599 unsigned short id1, id2;
1600
1601 id1 = mdio_read(dev, i, MII_PHYSID1);
1602 if (id1 == 0xffff)
1603 continue;
1604 id2 = mdio_read(dev, i, MII_PHYSID2);
1605 if (id2 == 0xffff)
1606 continue;
1607 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1608 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1609 lp->phycount++;
1610 lp->phymask |= (1 << i);
1611 lp->mii_if.phy_id = i;
1612 if (pcnet32_debug & NETIF_MSG_PROBE)
1613 printk(KERN_INFO PFX
1614 "Found PHY %04x:%04x at address %d.\n",
1615 id1, id2, i);
1616 }
1617 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1618 if (lp->phycount > 1) {
1619 lp->options |= PCNET32_PORT_MII;
1620 }
1da177e4 1621 }
4a5e8e29
JG		 1622
1623 init_timer(&lp->watchdog_timer);
1624 lp->watchdog_timer.data = (unsigned long)dev;
1625 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1626
1627 /* The PCNET32-specific entries in the device structure. */
1628 dev->open = &pcnet32_open;
1629 dev->hard_start_xmit = &pcnet32_start_xmit;
1630 dev->stop = &pcnet32_close;
1631 dev->get_stats = &pcnet32_get_stats;
1632 dev->set_multicast_list = &pcnet32_set_multicast_list;
1633 dev->do_ioctl = &pcnet32_ioctl;
1634 dev->ethtool_ops = &pcnet32_ethtool_ops;
1635 dev->tx_timeout = pcnet32_tx_timeout;
1636 dev->watchdog_timeo = (5 * HZ);
1da177e4
LT		 1637
1638#ifdef CONFIG_NET_POLL_CONTROLLER
4a5e8e29 1639 dev->poll_controller = pcnet32_poll_controller;
1da177e4
LT		 1640#endif
1641
4a5e8e29
JG		 1642 /* Fill in the generic fields of the device structure. */
1643 if (register_netdev(dev))
1644 goto err_free_ring;
1645
1646 if (pdev) {
1647 pci_set_drvdata(pdev, dev);
1648 } else {
1649 lp->next = pcnet32_dev;
1650 pcnet32_dev = dev;
1651 }
1652
1653 if (pcnet32_debug & NETIF_MSG_PROBE)
1654 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1655 cards_found++;
1656
1657 /* enable LED writes */
1658 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1da177e4 1659
4a5e8e29
JG		 1660 return 0;
1661
1662 err_free_ring:
1663 pcnet32_free_ring(dev);
1664 err_free_consistent:
1665 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
1666 err_free_netdev:
1667 free_netdev(dev);
1668 err_release_region:
1669 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1670 return ret;
1671}
1da177e4 1672
a88c844c
DF		 1673/* if any allocation fails, caller must also call pcnet32_free_ring */
1674static int pcnet32_alloc_ring(struct net_device *dev, char *name)
eabf0415 1675{
4a5e8e29 1676 struct pcnet32_private *lp = dev->priv;
eabf0415 1677
4a5e8e29
JG		 1678 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1679 sizeof(struct pcnet32_tx_head) *
1680 lp->tx_ring_size,
1681 &lp->tx_ring_dma_addr);
1682 if (lp->tx_ring == NULL) {
12fa30f3 1683 if (netif_msg_drv(lp))
4a5e8e29
JG		 1684 printk("\n" KERN_ERR PFX
1685 "%s: Consistent memory allocation failed.\n",
1686 name);
1687 return -ENOMEM;
1688 }
eabf0415 1689
4a5e8e29
JG		 1690 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
1691 sizeof(struct pcnet32_rx_head) *
1692 lp->rx_ring_size,
1693 &lp->rx_ring_dma_addr);
1694 if (lp->rx_ring == NULL) {
12fa30f3 1695 if (netif_msg_drv(lp))
4a5e8e29
JG		 1696 printk("\n" KERN_ERR PFX
1697 "%s: Consistent memory allocation failed.\n",
1698 name);
1699 return -ENOMEM;
1700 }
eabf0415 1701
12fa30f3 1702 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 1703 GFP_ATOMIC);
1704 if (!lp->tx_dma_addr) {
12fa30f3 1705 if (netif_msg_drv(lp))
4a5e8e29
JG		 1706 printk("\n" KERN_ERR PFX
1707 "%s: Memory allocation failed.\n", name);
1708 return -ENOMEM;
1709 }
4a5e8e29 1710
12fa30f3 1711 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 1712 GFP_ATOMIC);
1713 if (!lp->rx_dma_addr) {
12fa30f3 1714 if (netif_msg_drv(lp))
4a5e8e29
JG		 1715 printk("\n" KERN_ERR PFX
1716 "%s: Memory allocation failed.\n", name);
1717 return -ENOMEM;
1718 }
4a5e8e29 1719
12fa30f3 1720 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 1721 GFP_ATOMIC);
1722 if (!lp->tx_skbuff) {
12fa30f3 1723 if (netif_msg_drv(lp))
4a5e8e29
JG		 1724 printk("\n" KERN_ERR PFX
1725 "%s: Memory allocation failed.\n", name);
1726 return -ENOMEM;
1727 }
4a5e8e29 1728
12fa30f3 1729 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 1730 GFP_ATOMIC);
1731 if (!lp->rx_skbuff) {
12fa30f3 1732 if (netif_msg_drv(lp))
4a5e8e29
JG		 1733 printk("\n" KERN_ERR PFX
1734 "%s: Memory allocation failed.\n", name);
1735 return -ENOMEM;
1736 }
4a5e8e29
JG		 1737
1738 return 0;
1739}
eabf0415
HWL		 1740
1741static void pcnet32_free_ring(struct net_device *dev)
1742{
4a5e8e29 1743 struct pcnet32_private *lp = dev->priv;
eabf0415 1744
4a5e8e29
JG		 1745 kfree(lp->tx_skbuff);
1746 lp->tx_skbuff = NULL;
eabf0415 1747
4a5e8e29
JG		 1748 kfree(lp->rx_skbuff);
1749 lp->rx_skbuff = NULL;
eabf0415 1750
4a5e8e29
JG		 1751 kfree(lp->tx_dma_addr);
1752 lp->tx_dma_addr = NULL;
eabf0415 1753
4a5e8e29
JG		 1754 kfree(lp->rx_dma_addr);
1755 lp->rx_dma_addr = NULL;
eabf0415 1756
4a5e8e29
JG		 1757 if (lp->tx_ring) {
1758 pci_free_consistent(lp->pci_dev,
1759 sizeof(struct pcnet32_tx_head) *
1760 lp->tx_ring_size, lp->tx_ring,
1761 lp->tx_ring_dma_addr);
1762 lp->tx_ring = NULL;
1763 }
eabf0415 1764
4a5e8e29
JG		 1765 if (lp->rx_ring) {
1766 pci_free_consistent(lp->pci_dev,
1767 sizeof(struct pcnet32_rx_head) *
1768 lp->rx_ring_size, lp->rx_ring,
1769 lp->rx_ring_dma_addr);
1770 lp->rx_ring = NULL;
1771 }
eabf0415
HWL		 1772}
1773
4a5e8e29 1774static int pcnet32_open(struct net_device *dev)
1da177e4 1775{
4a5e8e29
JG		 1776 struct pcnet32_private *lp = dev->priv;
1777 unsigned long ioaddr = dev->base_addr;
1778 u16 val;
1779 int i;
1780 int rc;
1781 unsigned long flags;
1782
1783 if (request_irq(dev->irq, &pcnet32_interrupt,
1fb9df5d 1784 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
4a5e8e29
JG		 1785 (void *)dev)) {
1786 return -EAGAIN;
1787 }
1788
1789 spin_lock_irqsave(&lp->lock, flags);
1790 /* Check for a valid station address */
1791 if (!is_valid_ether_addr(dev->dev_addr)) {
1792 rc = -EINVAL;
1793 goto err_free_irq;
1794 }
1795
1796 /* Reset the PCNET32 */
1797 lp->a.reset(ioaddr);
1798
1799 /* switch pcnet32 to 32bit mode */
1800 lp->a.write_bcr(ioaddr, 20, 2);
1801
1802 if (netif_msg_ifup(lp))
1803 printk(KERN_DEBUG
1804 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
1805 dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
1806 (u32) (lp->rx_ring_dma_addr),
1807 (u32) (lp->dma_addr +
1808 offsetof(struct pcnet32_private, init_block)));
1809
1810 /* set/reset autoselect bit */
1811 val = lp->a.read_bcr(ioaddr, 2) & ~2;
1812 if (lp->options & PCNET32_PORT_ASEL)
1da177e4 1813 val |= 2;
4a5e8e29
JG		 1814 lp->a.write_bcr(ioaddr, 2, val);
1815
1816 /* handle full duplex setting */
1817 if (lp->mii_if.full_duplex) {
1818 val = lp->a.read_bcr(ioaddr, 9) & ~3;
1819 if (lp->options & PCNET32_PORT_FD) {
1820 val |= 1;
1821 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
1822 val |= 2;
1823 } else if (lp->options & PCNET32_PORT_ASEL) {
1824 /* workaround of xSeries250, turn on for 79C975 only */
1825 i = ((lp->a.read_csr(ioaddr, 88) |
1826 (lp->a.
1827 read_csr(ioaddr, 89) << 16)) >> 12) & 0xffff;
1828 if (i == 0x2627)
1829 val |= 3;
1830 }
1831 lp->a.write_bcr(ioaddr, 9, val);
1832 }
1833
1834 /* set/reset GPSI bit in test register */
1835 val = lp->a.read_csr(ioaddr, 124) & ~0x10;
1836 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
1837 val |= 0x10;
1838 lp->a.write_csr(ioaddr, 124, val);
1839
1840 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
1841 if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2964bbd7
DF		 1842 (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
1843 lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
ac62ef04 1844 if (lp->options & PCNET32_PORT_ASEL) {
4a5e8e29
JG		 1845 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
1846 if (netif_msg_link(lp))
1847 printk(KERN_DEBUG
1848 "%s: Setting 100Mb-Full Duplex.\n",
1849 dev->name);
1850 }
1851 }
1852 if (lp->phycount < 2) {
1853 /*
1854 * 24 Jun 2004 according AMD, in order to change the PHY,
1855 * DANAS (or DISPM for 79C976) must be set; then select the speed,
1856 * duplex, and/or enable auto negotiation, and clear DANAS
1857 */
1858 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
1859 lp->a.write_bcr(ioaddr, 32,
1860 lp->a.read_bcr(ioaddr, 32) | 0x0080);
1861 /* disable Auto Negotiation, set 10Mpbs, HD */
1862 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
1863 if (lp->options & PCNET32_PORT_FD)
1864 val |= 0x10;
1865 if (lp->options & PCNET32_PORT_100)
1866 val |= 0x08;
1867 lp->a.write_bcr(ioaddr, 32, val);
1868 } else {
1869 if (lp->options & PCNET32_PORT_ASEL) {
1870 lp->a.write_bcr(ioaddr, 32,
1871 lp->a.read_bcr(ioaddr,
1872 32) | 0x0080);
1873 /* enable auto negotiate, setup, disable fd */
1874 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
1875 val |= 0x20;
1876 lp->a.write_bcr(ioaddr, 32, val);
1877 }
1878 }
1879 } else {
1880 int first_phy = -1;
1881 u16 bmcr;
1882 u32 bcr9;
1883 struct ethtool_cmd ecmd;
1884
1885 /*
1886 * There is really no good other way to handle multiple PHYs
1887 * other than turning off all automatics
1888 */
1889 val = lp->a.read_bcr(ioaddr, 2);
1890 lp->a.write_bcr(ioaddr, 2, val & ~2);
1891 val = lp->a.read_bcr(ioaddr, 32);
1892 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
1893
1894 if (!(lp->options & PCNET32_PORT_ASEL)) {
1895 /* setup ecmd */
1896 ecmd.port = PORT_MII;
1897 ecmd.transceiver = XCVR_INTERNAL;
1898 ecmd.autoneg = AUTONEG_DISABLE;
1899 ecmd.speed =
1900 lp->
1901 options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
1902 bcr9 = lp->a.read_bcr(ioaddr, 9);
1903
1904 if (lp->options & PCNET32_PORT_FD) {
1905 ecmd.duplex = DUPLEX_FULL;
1906 bcr9 |= (1 << 0);
1907 } else {
1908 ecmd.duplex = DUPLEX_HALF;
1909 bcr9 |= ~(1 << 0);
1910 }
1911 lp->a.write_bcr(ioaddr, 9, bcr9);
ac62ef04 1912 }
4a5e8e29
JG		 1913
1914 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1915 if (lp->phymask & (1 << i)) {
1916 /* isolate all but the first PHY */
1917 bmcr = mdio_read(dev, i, MII_BMCR);
1918 if (first_phy == -1) {
1919 first_phy = i;
1920 mdio_write(dev, i, MII_BMCR,
1921 bmcr & ~BMCR_ISOLATE);
1922 } else {
1923 mdio_write(dev, i, MII_BMCR,
1924 bmcr | BMCR_ISOLATE);
1925 }
1926 /* use mii_ethtool_sset to setup PHY */
1927 lp->mii_if.phy_id = i;
1928 ecmd.phy_address = i;
1929 if (lp->options & PCNET32_PORT_ASEL) {
1930 mii_ethtool_gset(&lp->mii_if, &ecmd);
1931 ecmd.autoneg = AUTONEG_ENABLE;
1932 }
1933 mii_ethtool_sset(&lp->mii_if, &ecmd);
1934 }
1935 }
1936 lp->mii_if.phy_id = first_phy;
1937 if (netif_msg_link(lp))
1938 printk(KERN_INFO "%s: Using PHY number %d.\n",
1939 dev->name, first_phy);
1940 }
1da177e4
LT		 1941
1942#ifdef DO_DXSUFLO
4a5e8e29
JG		 1943 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
1944 val = lp->a.read_csr(ioaddr, 3);
1945 val |= 0x40;
1946 lp->a.write_csr(ioaddr, 3, val);
1947 }
1da177e4
LT		 1948#endif
1949
4a5e8e29
JG		 1950 lp->init_block.mode =
1951 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
1952 pcnet32_load_multicast(dev);
1953
1954 if (pcnet32_init_ring(dev)) {
1955 rc = -ENOMEM;
1956 goto err_free_ring;
1957 }
1958
1959 /* Re-initialize the PCNET32, and start it when done. */
1960 lp->a.write_csr(ioaddr, 1, (lp->dma_addr +
1961 offsetof(struct pcnet32_private,
1962 init_block)) & 0xffff);
1963 lp->a.write_csr(ioaddr, 2,
1964 (lp->dma_addr +
1965 offsetof(struct pcnet32_private, init_block)) >> 16);
1966
1967 lp->a.write_csr(ioaddr, 4, 0x0915);
1968 lp->a.write_csr(ioaddr, 0, 0x0001);
1969
1970 netif_start_queue(dev);
1971
1972 /* Print the link status and start the watchdog */
1973 pcnet32_check_media(dev, 1);
1974 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
1975
1976 i = 0;
1977 while (i++ < 100)
1978 if (lp->a.read_csr(ioaddr, 0) & 0x0100)
1979 break;
1980 /*
1981 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
1982 * reports that doing so triggers a bug in the '974.
1983 */
1984 lp->a.write_csr(ioaddr, 0, 0x0042);
1985
1986 if (netif_msg_ifup(lp))
1987 printk(KERN_DEBUG
1988 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
1989 dev->name, i,
1990 (u32) (lp->dma_addr +
1991 offsetof(struct pcnet32_private, init_block)),
1992 lp->a.read_csr(ioaddr, 0));
1993
1994 spin_unlock_irqrestore(&lp->lock, flags);
1995
1996 return 0; /* Always succeed */
1997
1998 err_free_ring:
1999 /* free any allocated skbuffs */
2000 for (i = 0; i < lp->rx_ring_size; i++) {
2001 lp->rx_ring[i].status = 0;
2002 if (lp->rx_skbuff[i]) {
2003 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
2004 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
2005 dev_kfree_skb(lp->rx_skbuff[i]);
2006 }
2007 lp->rx_skbuff[i] = NULL;
2008 lp->rx_dma_addr[i] = 0;
2009 }
2010
4a5e8e29
JG		 2011 /*
2012 * Switch back to 16bit mode to avoid problems with dumb
2013 * DOS packet driver after a warm reboot
2014 */
2015 lp->a.write_bcr(ioaddr, 20, 4);
2016
2017 err_free_irq:
2018 spin_unlock_irqrestore(&lp->lock, flags);
2019 free_irq(dev->irq, dev);
2020 return rc;
1da177e4
LT		 2021}
2022
2023/*
2024 * The LANCE has been halted for one reason or another (busmaster memory
2025 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2026 * etc.). Modern LANCE variants always reload their ring-buffer
2027 * configuration when restarted, so we must reinitialize our ring
2028 * context before restarting. As part of this reinitialization,
2029 * find all packets still on the Tx ring and pretend that they had been
2030 * sent (in effect, drop the packets on the floor) - the higher-level
2031 * protocols will time out and retransmit. It'd be better to shuffle
2032 * these skbs to a temp list and then actually re-Tx them after
2033 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2034 */
2035
4a5e8e29 2036static void pcnet32_purge_tx_ring(struct net_device *dev)
1da177e4 2037{
4a5e8e29
JG		 2038 struct pcnet32_private *lp = dev->priv;
2039 int i;
1da177e4 2040
4a5e8e29
JG		 2041 for (i = 0; i < lp->tx_ring_size; i++) {
2042 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2043 wmb(); /* Make sure adapter sees owner change */
2044 if (lp->tx_skbuff[i]) {
2045 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2046 lp->tx_skbuff[i]->len,
2047 PCI_DMA_TODEVICE);
2048 dev_kfree_skb_any(lp->tx_skbuff[i]);
2049 }
2050 lp->tx_skbuff[i] = NULL;
2051 lp->tx_dma_addr[i] = 0;
2052 }
2053}
1da177e4
LT		 2054
2055/* Initialize the PCNET32 Rx and Tx rings. */
4a5e8e29 2056static int pcnet32_init_ring(struct net_device *dev)
1da177e4 2057{
4a5e8e29
JG		 2058 struct pcnet32_private *lp = dev->priv;
2059 int i;
2060
2061 lp->tx_full = 0;
2062 lp->cur_rx = lp->cur_tx = 0;
2063 lp->dirty_rx = lp->dirty_tx = 0;
2064
2065 for (i = 0; i < lp->rx_ring_size; i++) {
2066 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2067 if (rx_skbuff == NULL) {
2068 if (!
2069 (rx_skbuff = lp->rx_skbuff[i] =
2070 dev_alloc_skb(PKT_BUF_SZ))) {
2071 /* there is not much, we can do at this point */
2072 if (pcnet32_debug & NETIF_MSG_DRV)
2073 printk(KERN_ERR
2074 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2075 dev->name);
2076 return -1;
2077 }
2078 skb_reserve(rx_skbuff, 2);
2079 }
2080
2081 rmb();
2082 if (lp->rx_dma_addr[i] == 0)
2083 lp->rx_dma_addr[i] =
2084 pci_map_single(lp->pci_dev, rx_skbuff->data,
2085 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
2086 lp->rx_ring[i].base = (u32) le32_to_cpu(lp->rx_dma_addr[i]);
2087 lp->rx_ring[i].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
2088 wmb(); /* Make sure owner changes after all others are visible */
2089 lp->rx_ring[i].status = le16_to_cpu(0x8000);
2090 }
2091 /* The Tx buffer address is filled in as needed, but we do need to clear
2092 * the upper ownership bit. */
2093 for (i = 0; i < lp->tx_ring_size; i++) {
2094 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2095 wmb(); /* Make sure adapter sees owner change */
2096 lp->tx_ring[i].base = 0;
2097 lp->tx_dma_addr[i] = 0;
2098 }
2099
2100 lp->init_block.tlen_rlen =
2101 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
2102 for (i = 0; i < 6; i++)
2103 lp->init_block.phys_addr[i] = dev->dev_addr[i];
2104 lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
2105 lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
2106 wmb(); /* Make sure all changes are visible */
2107 return 0;
1da177e4
LT		 2108}
2109
2110/* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2111 * then flush the pending transmit operations, re-initialize the ring,
2112 * and tell the chip to initialize.
2113 */
4a5e8e29 2114static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1da177e4 2115{
4a5e8e29
JG		 2116 struct pcnet32_private *lp = dev->priv;
2117 unsigned long ioaddr = dev->base_addr;
2118 int i;
1da177e4 2119
4a5e8e29
JG		 2120 /* wait for stop */
2121 for (i = 0; i < 100; i++)
2122 if (lp->a.read_csr(ioaddr, 0) & 0x0004)
2123 break;
1da177e4 2124
4a5e8e29
JG		 2125 if (i >= 100 && netif_msg_drv(lp))
2126 printk(KERN_ERR
2127 "%s: pcnet32_restart timed out waiting for stop.\n",
2128 dev->name);
1da177e4 2129
4a5e8e29
JG		 2130 pcnet32_purge_tx_ring(dev);
2131 if (pcnet32_init_ring(dev))
2132 return;
1da177e4 2133
4a5e8e29
JG		 2134 /* ReInit Ring */
2135 lp->a.write_csr(ioaddr, 0, 1);
2136 i = 0;
2137 while (i++ < 1000)
2138 if (lp->a.read_csr(ioaddr, 0) & 0x0100)
2139 break;
1da177e4 2140
4a5e8e29 2141 lp->a.write_csr(ioaddr, 0, csr0_bits);
1da177e4
LT		 2142}
2143
4a5e8e29 2144static void pcnet32_tx_timeout(struct net_device *dev)
1da177e4 2145{
4a5e8e29
JG		 2146 struct pcnet32_private *lp = dev->priv;
2147 unsigned long ioaddr = dev->base_addr, flags;
2148
2149 spin_lock_irqsave(&lp->lock, flags);
2150 /* Transmitter timeout, serious problems. */
2151 if (pcnet32_debug & NETIF_MSG_DRV)
2152 printk(KERN_ERR
2153 "%s: transmit timed out, status %4.4x, resetting.\n",
2154 dev->name, lp->a.read_csr(ioaddr, 0));
2155 lp->a.write_csr(ioaddr, 0, 0x0004);
2156 lp->stats.tx_errors++;
2157 if (netif_msg_tx_err(lp)) {
2158 int i;
2159 printk(KERN_DEBUG
2160 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2161 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2162 lp->cur_rx);
2163 for (i = 0; i < lp->rx_ring_size; i++)
2164 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2165 le32_to_cpu(lp->rx_ring[i].base),
2166 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2167 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2168 le16_to_cpu(lp->rx_ring[i].status));
2169 for (i = 0; i < lp->tx_ring_size; i++)
2170 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2171 le32_to_cpu(lp->tx_ring[i].base),
2172 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2173 le32_to_cpu(lp->tx_ring[i].misc),
2174 le16_to_cpu(lp->tx_ring[i].status));
2175 printk("\n");
2176 }
2177 pcnet32_restart(dev, 0x0042);
1da177e4 2178
4a5e8e29
JG		 2179 dev->trans_start = jiffies;
2180 netif_wake_queue(dev);
1da177e4 2181
4a5e8e29
JG		 2182 spin_unlock_irqrestore(&lp->lock, flags);
2183}
2184
2185static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 2186{
4a5e8e29
JG		 2187 struct pcnet32_private *lp = dev->priv;
2188 unsigned long ioaddr = dev->base_addr;
2189 u16 status;
2190 int entry;
2191 unsigned long flags;
1da177e4 2192
4a5e8e29 2193 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2194
4a5e8e29
JG		 2195 if (netif_msg_tx_queued(lp)) {
2196 printk(KERN_DEBUG
2197 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
2198 dev->name, lp->a.read_csr(ioaddr, 0));
2199 }
1da177e4 2200
4a5e8e29
JG		 2201 /* Default status -- will not enable Successful-TxDone
2202 * interrupt when that option is available to us.
2203 */
2204 status = 0x8300;
1da177e4 2205
4a5e8e29 2206 /* Fill in a Tx ring entry */
1da177e4 2207
4a5e8e29
JG		 2208 /* Mask to ring buffer boundary. */
2209 entry = lp->cur_tx & lp->tx_mod_mask;
1da177e4 2210
4a5e8e29
JG		 2211 /* Caution: the write order is important here, set the status
2212 * with the "ownership" bits last. */
1da177e4 2213
4a5e8e29 2214 lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
1da177e4 2215
4a5e8e29 2216 lp->tx_ring[entry].misc = 0x00000000;
1da177e4 2217
4a5e8e29
JG		 2218 lp->tx_skbuff[entry] = skb;
2219 lp->tx_dma_addr[entry] =
2220 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2221 lp->tx_ring[entry].base = (u32) le32_to_cpu(lp->tx_dma_addr[entry]);
2222 wmb(); /* Make sure owner changes after all others are visible */
2223 lp->tx_ring[entry].status = le16_to_cpu(status);
1da177e4 2224
4a5e8e29
JG		 2225 lp->cur_tx++;
2226 lp->stats.tx_bytes += skb->len;
1da177e4 2227
4a5e8e29
JG		 2228 /* Trigger an immediate send poll. */
2229 lp->a.write_csr(ioaddr, 0, 0x0048);
1da177e4 2230
4a5e8e29 2231 dev->trans_start = jiffies;
1da177e4 2232
4a5e8e29
JG		 2233 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2234 lp->tx_full = 1;
2235 netif_stop_queue(dev);
2236 }
2237 spin_unlock_irqrestore(&lp->lock, flags);
2238 return 0;
1da177e4
LT		 2239}
2240
2241/* The PCNET32 interrupt handler. */
2242static irqreturn_t
4a5e8e29 2243pcnet32_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1da177e4 2244{
4a5e8e29
JG		 2245 struct net_device *dev = dev_id;
2246 struct pcnet32_private *lp;
2247 unsigned long ioaddr;
2248 u16 csr0, rap;
2249 int boguscnt = max_interrupt_work;
2250 int must_restart;
2251
2252 if (!dev) {
2253 if (pcnet32_debug & NETIF_MSG_INTR)
2254 printk(KERN_DEBUG "%s(): irq %d for unknown device\n",
2255 __FUNCTION__, irq);
2256 return IRQ_NONE;
1da177e4 2257 }
1da177e4 2258
4a5e8e29
JG		 2259 ioaddr = dev->base_addr;
2260 lp = dev->priv;
1da177e4 2261
4a5e8e29
JG		 2262 spin_lock(&lp->lock);
2263
2264 rap = lp->a.read_rap(ioaddr);
2265 while ((csr0 = lp->a.read_csr(ioaddr, 0)) & 0x8f00 && --boguscnt >= 0) {
2266 if (csr0 == 0xffff) {
2267 break; /* PCMCIA remove happened */
2268 }
2269 /* Acknowledge all of the current interrupt sources ASAP. */
2270 lp->a.write_csr(ioaddr, 0, csr0 & ~0x004f);
2271
2272 must_restart = 0;
2273
2274 if (netif_msg_intr(lp))
2275 printk(KERN_DEBUG
2276 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
2277 dev->name, csr0, lp->a.read_csr(ioaddr, 0));
2278
2279 if (csr0 & 0x0400) /* Rx interrupt */
2280 pcnet32_rx(dev);
2281
2282 if (csr0 & 0x0200) { /* Tx-done interrupt */
2283 unsigned int dirty_tx = lp->dirty_tx;
2284 int delta;
2285
2286 while (dirty_tx != lp->cur_tx) {
2287 int entry = dirty_tx & lp->tx_mod_mask;
2288 int status =
2289 (short)le16_to_cpu(lp->tx_ring[entry].
2290 status);
2291
2292 if (status < 0)
2293 break; /* It still hasn't been Txed */
2294
2295 lp->tx_ring[entry].base = 0;
2296
2297 if (status & 0x4000) {
2298 /* There was an major error, log it. */
2299 int err_status =
2300 le32_to_cpu(lp->tx_ring[entry].
2301 misc);
2302 lp->stats.tx_errors++;
2303 if (netif_msg_tx_err(lp))
2304 printk(KERN_ERR
2305 "%s: Tx error status=%04x err_status=%08x\n",
2306 dev->name, status,
2307 err_status);
2308 if (err_status & 0x04000000)
2309 lp->stats.tx_aborted_errors++;
2310 if (err_status & 0x08000000)
2311 lp->stats.tx_carrier_errors++;
2312 if (err_status & 0x10000000)
2313 lp->stats.tx_window_errors++;
1da177e4 2314#ifndef DO_DXSUFLO
4a5e8e29
JG		 2315 if (err_status & 0x40000000) {
2316 lp->stats.tx_fifo_errors++;
2317 /* Ackk! On FIFO errors the Tx unit is turned off! */
2318 /* Remove this verbosity later! */
2319 if (netif_msg_tx_err(lp))
2320 printk(KERN_ERR
2321 "%s: Tx FIFO error! CSR0=%4.4x\n",
2322 dev->name, csr0);
2323 must_restart = 1;
2324 }
1da177e4 2325#else
4a5e8e29
JG		 2326 if (err_status & 0x40000000) {
2327 lp->stats.tx_fifo_errors++;
2328 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
2329 /* Ackk! On FIFO errors the Tx unit is turned off! */
2330 /* Remove this verbosity later! */
2331 if (netif_msg_tx_err
2332 (lp))
2333 printk(KERN_ERR
2334 "%s: Tx FIFO error! CSR0=%4.4x\n",
2335 dev->
2336 name,
2337 csr0);
2338 must_restart = 1;
2339 }
2340 }
1da177e4 2341#endif
4a5e8e29
JG		 2342 } else {
2343 if (status & 0x1800)
2344 lp->stats.collisions++;
2345 lp->stats.tx_packets++;
2346 }
2347
2348 /* We must free the original skb */
2349 if (lp->tx_skbuff[entry]) {
2350 pci_unmap_single(lp->pci_dev,
2351 lp->tx_dma_addr[entry],
2352 lp->tx_skbuff[entry]->
2353 len, PCI_DMA_TODEVICE);
2354 dev_kfree_skb_irq(lp->tx_skbuff[entry]);
2355 lp->tx_skbuff[entry] = NULL;
2356 lp->tx_dma_addr[entry] = 0;
2357 }
2358 dirty_tx++;
2359 }
2360
2361 delta =
2362 (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask +
2363 lp->tx_ring_size);
2364 if (delta > lp->tx_ring_size) {
2365 if (netif_msg_drv(lp))
2366 printk(KERN_ERR
2367 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
2368 dev->name, dirty_tx, lp->cur_tx,
2369 lp->tx_full);
2370 dirty_tx += lp->tx_ring_size;
2371 delta -= lp->tx_ring_size;
2372 }
2373
2374 if (lp->tx_full &&
2375 netif_queue_stopped(dev) &&
2376 delta < lp->tx_ring_size - 2) {
2377 /* The ring is no longer full, clear tbusy. */
2378 lp->tx_full = 0;
2379 netif_wake_queue(dev);
2380 }
2381 lp->dirty_tx = dirty_tx;
2382 }
2383
2384 /* Log misc errors. */
2385 if (csr0 & 0x4000)
2386 lp->stats.tx_errors++; /* Tx babble. */
2387 if (csr0 & 0x1000) {
2388 /*
2389 * this happens when our receive ring is full. This shouldn't
2390 * be a problem as we will see normal rx interrupts for the frames
2391 * in the receive ring. But there are some PCI chipsets (I can
2392 * reproduce this on SP3G with Intel saturn chipset) which have
2393 * sometimes problems and will fill up the receive ring with
2394 * error descriptors. In this situation we don't get a rx
2395 * interrupt, but a missed frame interrupt sooner or later.
2396 * So we try to clean up our receive ring here.
2397 */
2398 pcnet32_rx(dev);
2399 lp->stats.rx_errors++; /* Missed a Rx frame. */
2400 }
2401 if (csr0 & 0x0800) {
2402 if (netif_msg_drv(lp))
2403 printk(KERN_ERR
2404 "%s: Bus master arbitration failure, status %4.4x.\n",
2405 dev->name, csr0);
2406 /* unlike for the lance, there is no restart needed */
1da177e4
LT		 2407 }
2408
4a5e8e29
JG		 2409 if (must_restart) {
2410 /* reset the chip to clear the error condition, then restart */
2411 lp->a.reset(ioaddr);
2412 lp->a.write_csr(ioaddr, 4, 0x0915);
2413 pcnet32_restart(dev, 0x0002);
2414 netif_wake_queue(dev);
1da177e4 2415 }
4a5e8e29
JG		 2416 }
2417
2418 /* Set interrupt enable. */
2419 lp->a.write_csr(ioaddr, 0, 0x0040);
2420 lp->a.write_rap(ioaddr, rap);
2421
2422 if (netif_msg_intr(lp))
2423 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
2424 dev->name, lp->a.read_csr(ioaddr, 0));
2425
2426 spin_unlock(&lp->lock);
2427
2428 return IRQ_HANDLED;
1da177e4
LT		 2429}
2430
4a5e8e29 2431static int pcnet32_rx(struct net_device *dev)
1da177e4 2432{
4a5e8e29
JG		 2433 struct pcnet32_private *lp = dev->priv;
2434 int entry = lp->cur_rx & lp->rx_mod_mask;
2435 int boguscnt = lp->rx_ring_size / 2;
2436
2437 /* If we own the next entry, it's a new packet. Send it up. */
2438 while ((short)le16_to_cpu(lp->rx_ring[entry].status) >= 0) {
2439 int status = (short)le16_to_cpu(lp->rx_ring[entry].status) >> 8;
2440
2441 if (status != 0x03) { /* There was an error. */
2442 /*
2443 * There is a tricky error noted by John Murphy,
2444 * <murf@perftech.com> to Russ Nelson: Even with full-sized
2445 * buffers it's possible for a jabber packet to use two
2446 * buffers, with only the last correctly noting the error.
2447 */
2448 if (status & 0x01) /* Only count a general error at the */
2449 lp->stats.rx_errors++; /* end of a packet. */
2450 if (status & 0x20)
2451 lp->stats.rx_frame_errors++;
2452 if (status & 0x10)
2453 lp->stats.rx_over_errors++;
2454 if (status & 0x08)
2455 lp->stats.rx_crc_errors++;
2456 if (status & 0x04)
2457 lp->stats.rx_fifo_errors++;
2458 lp->rx_ring[entry].status &= le16_to_cpu(0x03ff);
1da177e4 2459 } else {
4a5e8e29
JG		 2460 /* Malloc up new buffer, compatible with net-2e. */
2461 short pkt_len =
2462 (le32_to_cpu(lp->rx_ring[entry].msg_length) & 0xfff)
2463 - 4;
2464 struct sk_buff *skb;
2465
2466 /* Discard oversize frames. */
2467 if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
2468 if (netif_msg_drv(lp))
2469 printk(KERN_ERR
2470 "%s: Impossible packet size %d!\n",
2471 dev->name, pkt_len);
2472 lp->stats.rx_errors++;
2473 } else if (pkt_len < 60) {
2474 if (netif_msg_rx_err(lp))
2475 printk(KERN_ERR "%s: Runt packet!\n",
2476 dev->name);
2477 lp->stats.rx_errors++;
2478 } else {
2479 int rx_in_place = 0;
2480
2481 if (pkt_len > rx_copybreak) {
2482 struct sk_buff *newskb;
2483
2484 if ((newskb =
2485 dev_alloc_skb(PKT_BUF_SZ))) {
2486 skb_reserve(newskb, 2);
2487 skb = lp->rx_skbuff[entry];
2488 pci_unmap_single(lp->pci_dev,
2489 lp->
2490 rx_dma_addr
2491 [entry],
2492 PKT_BUF_SZ - 2,
2493 PCI_DMA_FROMDEVICE);
2494 skb_put(skb, pkt_len);
2495 lp->rx_skbuff[entry] = newskb;
2496 newskb->dev = dev;
2497 lp->rx_dma_addr[entry] =
2498 pci_map_single(lp->pci_dev,
2499 newskb->data,
2500 PKT_BUF_SZ -
2501 2,
2502 PCI_DMA_FROMDEVICE);
2503 lp->rx_ring[entry].base =
2504 le32_to_cpu(lp->
2505 rx_dma_addr
2506 [entry]);
2507 rx_in_place = 1;
2508 } else
2509 skb = NULL;
2510 } else {
2511 skb = dev_alloc_skb(pkt_len + 2);
2512 }
2513
2514 if (skb == NULL) {
2515 int i;
2516 if (netif_msg_drv(lp))
2517 printk(KERN_ERR
2518 "%s: Memory squeeze, deferring packet.\n",
2519 dev->name);
2520 for (i = 0; i < lp->rx_ring_size; i++)
2521 if ((short)
2522 le16_to_cpu(lp->
2523 rx_ring[(entry +
2524 i)
2525 & lp->
2526 rx_mod_mask].
2527 status) < 0)
2528 break;
2529
2530 if (i > lp->rx_ring_size - 2) {
2531 lp->stats.rx_dropped++;
2532 lp->rx_ring[entry].status |=
2533 le16_to_cpu(0x8000);
2534 wmb(); /* Make sure adapter sees owner change */
2535 lp->cur_rx++;
2536 }
2537 break;
2538 }
2539 skb->dev = dev;
2540 if (!rx_in_place) {
2541 skb_reserve(skb, 2); /* 16 byte align */
2542 skb_put(skb, pkt_len); /* Make room */
2543 pci_dma_sync_single_for_cpu(lp->pci_dev,
2544 lp->
2545 rx_dma_addr
2546 [entry],
2547 PKT_BUF_SZ -
2548 2,
2549 PCI_DMA_FROMDEVICE);
2550 eth_copy_and_sum(skb,
2551 (unsigned char *)(lp->
2552 rx_skbuff
2553 [entry]->
2554 data),
2555 pkt_len, 0);
2556 pci_dma_sync_single_for_device(lp->
2557 pci_dev,
2558 lp->
2559 rx_dma_addr
2560 [entry],
2561 PKT_BUF_SZ
2562 - 2,
2563 PCI_DMA_FROMDEVICE);
2564 }
2565 lp->stats.rx_bytes += skb->len;
2566 skb->protocol = eth_type_trans(skb, dev);
2567 netif_rx(skb);
2568 dev->last_rx = jiffies;
2569 lp->stats.rx_packets++;
2570 }
1da177e4 2571 }
4a5e8e29
JG		 2572 /*
2573 * The docs say that the buffer length isn't touched, but Andrew Boyd
2574 * of QNX reports that some revs of the 79C965 clear it.
2575 */
2576 lp->rx_ring[entry].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
2577 wmb(); /* Make sure owner changes after all others are visible */
2578 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
2579 entry = (++lp->cur_rx) & lp->rx_mod_mask;
2580 if (--boguscnt <= 0)
2581 break; /* don't stay in loop forever */
1da177e4 2582 }
4a5e8e29
JG		 2583
2584 return 0;
1da177e4
LT		 2585}
2586
4a5e8e29 2587static int pcnet32_close(struct net_device *dev)
1da177e4 2588{
4a5e8e29
JG		 2589 unsigned long ioaddr = dev->base_addr;
2590 struct pcnet32_private *lp = dev->priv;
2591 int i;
2592 unsigned long flags;
1da177e4 2593
4a5e8e29 2594 del_timer_sync(&lp->watchdog_timer);
1da177e4 2595
4a5e8e29 2596 netif_stop_queue(dev);
1da177e4 2597
4a5e8e29 2598 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2599
4a5e8e29 2600 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
1da177e4 2601
4a5e8e29
JG		 2602 if (netif_msg_ifdown(lp))
2603 printk(KERN_DEBUG
2604 "%s: Shutting down ethercard, status was %2.2x.\n",
2605 dev->name, lp->a.read_csr(ioaddr, 0));
1da177e4 2606
4a5e8e29
JG		 2607 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2608 lp->a.write_csr(ioaddr, 0, 0x0004);
1da177e4 2609
4a5e8e29
JG		 2610 /*
2611 * Switch back to 16bit mode to avoid problems with dumb
2612 * DOS packet driver after a warm reboot
2613 */
2614 lp->a.write_bcr(ioaddr, 20, 4);
1da177e4 2615
4a5e8e29 2616 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2617
4a5e8e29 2618 free_irq(dev->irq, dev);
1da177e4 2619
4a5e8e29 2620 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2621
4a5e8e29
JG		 2622 /* free all allocated skbuffs */
2623 for (i = 0; i < lp->rx_ring_size; i++) {
2624 lp->rx_ring[i].status = 0;
2625 wmb(); /* Make sure adapter sees owner change */
2626 if (lp->rx_skbuff[i]) {
2627 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
2628 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
2629 dev_kfree_skb(lp->rx_skbuff[i]);
2630 }
2631 lp->rx_skbuff[i] = NULL;
2632 lp->rx_dma_addr[i] = 0;
1da177e4 2633 }
1da177e4 2634
4a5e8e29
JG		 2635 for (i = 0; i < lp->tx_ring_size; i++) {
2636 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2637 wmb(); /* Make sure adapter sees owner change */
2638 if (lp->tx_skbuff[i]) {
2639 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2640 lp->tx_skbuff[i]->len,
2641 PCI_DMA_TODEVICE);
2642 dev_kfree_skb(lp->tx_skbuff[i]);
2643 }
2644 lp->tx_skbuff[i] = NULL;
2645 lp->tx_dma_addr[i] = 0;
1da177e4 2646 }
1da177e4 2647
4a5e8e29 2648 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2649
4a5e8e29 2650 return 0;
1da177e4
LT		 2651}
2652
4a5e8e29 2653static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
1da177e4 2654{
4a5e8e29
JG		 2655 struct pcnet32_private *lp = dev->priv;
2656 unsigned long ioaddr = dev->base_addr;
2657 u16 saved_addr;
2658 unsigned long flags;
2659
2660 spin_lock_irqsave(&lp->lock, flags);
2661 saved_addr = lp->a.read_rap(ioaddr);
2662 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2663 lp->a.write_rap(ioaddr, saved_addr);
2664 spin_unlock_irqrestore(&lp->lock, flags);
2665
2666 return &lp->stats;
1da177e4
LT		 2667}
2668
2669/* taken from the sunlance driver, which it took from the depca driver */
4a5e8e29 2670static void pcnet32_load_multicast(struct net_device *dev)
1da177e4 2671{
4a5e8e29
JG		 2672 struct pcnet32_private *lp = dev->priv;
2673 volatile struct pcnet32_init_block *ib = &lp->init_block;
2674 volatile u16 *mcast_table = (u16 *) & ib->filter;
2675 struct dev_mc_list *dmi = dev->mc_list;
df27f4a6 2676 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2677 char *addrs;
2678 int i;
2679 u32 crc;
2680
2681 /* set all multicast bits */
2682 if (dev->flags & IFF_ALLMULTI) {
2683 ib->filter[0] = 0xffffffff;
2684 ib->filter[1] = 0xffffffff;
df27f4a6
DF		 2685 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2686 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2687 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2688 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
4a5e8e29
JG		 2689 return;
2690 }
2691 /* clear the multicast filter */
2692 ib->filter[0] = 0;
2693 ib->filter[1] = 0;
2694
2695 /* Add addresses */
2696 for (i = 0; i < dev->mc_count; i++) {
2697 addrs = dmi->dmi_addr;
2698 dmi = dmi->next;
2699
2700 /* multicast address? */
2701 if (!(*addrs & 1))
2702 continue;
2703
2704 crc = ether_crc_le(6, addrs);
2705 crc = crc >> 26;
2706 mcast_table[crc >> 4] =
2707 le16_to_cpu(le16_to_cpu(mcast_table[crc >> 4]) |
2708 (1 << (crc & 0xf)));
2709 }
df27f4a6
DF		 2710 for (i = 0; i < 4; i++)
2711 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2712 le16_to_cpu(mcast_table[i]));
1da177e4 2713 return;
1da177e4
LT		 2714}
2715
1da177e4
LT		 2716/*
2717 * Set or clear the multicast filter for this adaptor.
2718 */
2719static void pcnet32_set_multicast_list(struct net_device *dev)
2720{
4a5e8e29
JG		 2721 unsigned long ioaddr = dev->base_addr, flags;
2722 struct pcnet32_private *lp = dev->priv;
df27f4a6 2723 int csr15, suspended;
4a5e8e29
JG		 2724
2725 spin_lock_irqsave(&lp->lock, flags);
df27f4a6
DF		 2726 suspended = pcnet32_suspend(dev, &flags, 0);
2727 csr15 = lp->a.read_csr(ioaddr, CSR15);
4a5e8e29
JG		 2728 if (dev->flags & IFF_PROMISC) {
2729 /* Log any net taps. */
2730 if (netif_msg_hw(lp))
2731 printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2732 dev->name);
2733 lp->init_block.mode =
2734 le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2735 7);
df27f4a6 2736 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
4a5e8e29
JG		 2737 } else {
2738 lp->init_block.mode =
2739 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
df27f4a6 2740 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
4a5e8e29
JG		 2741 pcnet32_load_multicast(dev);
2742 }
2743
df27f4a6
DF		 2744 if (suspended) {
2745 int csr5;
2746 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2747 csr5 = lp->a.read_csr(ioaddr, CSR5);
2748 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
2749 } else {
2750 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2751 pcnet32_restart(dev, CSR0_NORMAL);
2752 netif_wake_queue(dev);
2753 }
4a5e8e29
JG		 2754
2755 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 2756}
2757
2758/* This routine assumes that the lp->lock is held */
2759static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2760{
4a5e8e29
JG		 2761 struct pcnet32_private *lp = dev->priv;
2762 unsigned long ioaddr = dev->base_addr;
2763 u16 val_out;
1da177e4 2764
4a5e8e29
JG		 2765 if (!lp->mii)
2766 return 0;
1da177e4 2767
4a5e8e29
JG		 2768 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2769 val_out = lp->a.read_bcr(ioaddr, 34);
1da177e4 2770
4a5e8e29 2771 return val_out;
1da177e4
LT		 2772}
2773
2774/* This routine assumes that the lp->lock is held */
2775static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2776{
4a5e8e29
JG		 2777 struct pcnet32_private *lp = dev->priv;
2778 unsigned long ioaddr = dev->base_addr;
1da177e4 2779
4a5e8e29
JG		 2780 if (!lp->mii)
2781 return;
1da177e4 2782
4a5e8e29
JG		 2783 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2784 lp->a.write_bcr(ioaddr, 34, val);
1da177e4
LT		 2785}
2786
2787static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2788{
4a5e8e29
JG		 2789 struct pcnet32_private *lp = dev->priv;
2790 int rc;
2791 unsigned long flags;
1da177e4 2792
4a5e8e29
JG		 2793 /* SIOC[GS]MIIxxx ioctls */
2794 if (lp->mii) {
2795 spin_lock_irqsave(&lp->lock, flags);
2796 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2797 spin_unlock_irqrestore(&lp->lock, flags);
2798 } else {
2799 rc = -EOPNOTSUPP;
2800 }
1da177e4 2801
4a5e8e29 2802 return rc;
1da177e4
LT		 2803}
2804
ac62ef04
DF		 2805static int pcnet32_check_otherphy(struct net_device *dev)
2806{
4a5e8e29
JG		 2807 struct pcnet32_private *lp = dev->priv;
2808 struct mii_if_info mii = lp->mii_if;
2809 u16 bmcr;
2810 int i;
ac62ef04 2811
4a5e8e29
JG		 2812 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2813 if (i == lp->mii_if.phy_id)
2814 continue; /* skip active phy */
2815 if (lp->phymask & (1 << i)) {
2816 mii.phy_id = i;
2817 if (mii_link_ok(&mii)) {
2818 /* found PHY with active link */
2819 if (netif_msg_link(lp))
2820 printk(KERN_INFO
2821 "%s: Using PHY number %d.\n",
2822 dev->name, i);
2823
2824 /* isolate inactive phy */
2825 bmcr =
2826 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2827 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2828 bmcr | BMCR_ISOLATE);
2829
2830 /* de-isolate new phy */
2831 bmcr = mdio_read(dev, i, MII_BMCR);
2832 mdio_write(dev, i, MII_BMCR,
2833 bmcr & ~BMCR_ISOLATE);
2834
2835 /* set new phy address */
2836 lp->mii_if.phy_id = i;
2837 return 1;
2838 }
2839 }
ac62ef04 2840 }
4a5e8e29 2841 return 0;
ac62ef04
DF		 2842}
2843
2844/*
2845 * Show the status of the media. Similar to mii_check_media however it
2846 * correctly shows the link speed for all (tested) pcnet32 variants.
2847 * Devices with no mii just report link state without speed.
2848 *
2849 * Caller is assumed to hold and release the lp->lock.
2850 */
2851
2852static void pcnet32_check_media(struct net_device *dev, int verbose)
2853{
4a5e8e29
JG		 2854 struct pcnet32_private *lp = dev->priv;
2855 int curr_link;
2856 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2857 u32 bcr9;
2858
ac62ef04 2859 if (lp->mii) {
4a5e8e29 2860 curr_link = mii_link_ok(&lp->mii_if);
ac62ef04 2861 } else {
4a5e8e29
JG		 2862 ulong ioaddr = dev->base_addr; /* card base I/O address */
2863 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2864 }
2865 if (!curr_link) {
2866 if (prev_link || verbose) {
2867 netif_carrier_off(dev);
2868 if (netif_msg_link(lp))
2869 printk(KERN_INFO "%s: link down\n", dev->name);
2870 }
2871 if (lp->phycount > 1) {
2872 curr_link = pcnet32_check_otherphy(dev);
2873 prev_link = 0;
2874 }
2875 } else if (verbose || !prev_link) {
2876 netif_carrier_on(dev);
2877 if (lp->mii) {
2878 if (netif_msg_link(lp)) {
2879 struct ethtool_cmd ecmd;
2880 mii_ethtool_gset(&lp->mii_if, &ecmd);
2881 printk(KERN_INFO
2882 "%s: link up, %sMbps, %s-duplex\n",
2883 dev->name,
2884 (ecmd.speed == SPEED_100) ? "100" : "10",
2885 (ecmd.duplex ==
2886 DUPLEX_FULL) ? "full" : "half");
2887 }
2888 bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2889 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2890 if (lp->mii_if.full_duplex)
2891 bcr9 |= (1 << 0);
2892 else
2893 bcr9 &= ~(1 << 0);
2894 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2895 }
2896 } else {
2897 if (netif_msg_link(lp))
2898 printk(KERN_INFO "%s: link up\n", dev->name);
2899 }
ac62ef04 2900 }
ac62ef04
DF		 2901}
2902
2903/*
2904 * Check for loss of link and link establishment.
2905 * Can not use mii_check_media because it does nothing if mode is forced.
2906 */
2907
1da177e4
LT		 2908static void pcnet32_watchdog(struct net_device *dev)
2909{
4a5e8e29
JG		 2910 struct pcnet32_private *lp = dev->priv;
2911 unsigned long flags;
1da177e4 2912
4a5e8e29
JG		 2913 /* Print the link status if it has changed */
2914 spin_lock_irqsave(&lp->lock, flags);
2915 pcnet32_check_media(dev, 0);
2916 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2917
4a5e8e29 2918 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
1da177e4
LT		 2919}
2920
2921static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2922{
4a5e8e29
JG		 2923 struct net_device *dev = pci_get_drvdata(pdev);
2924
2925 if (dev) {
2926 struct pcnet32_private *lp = dev->priv;
2927
2928 unregister_netdev(dev);
2929 pcnet32_free_ring(dev);
2930 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2931 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2932 free_netdev(dev);
2933 pci_disable_device(pdev);
2934 pci_set_drvdata(pdev, NULL);
2935 }
1da177e4
LT		 2936}
2937
2938static struct pci_driver pcnet32_driver = {
4a5e8e29
JG		 2939 .name = DRV_NAME,
2940 .probe = pcnet32_probe_pci,
2941 .remove = __devexit_p(pcnet32_remove_one),
2942 .id_table = pcnet32_pci_tbl,
1da177e4
LT		 2943};
2944
2945/* An additional parameter that may be passed in... */
2946static int debug = -1;
2947static int tx_start_pt = -1;
2948static int pcnet32_have_pci;
2949
2950module_param(debug, int, 0);
2951MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2952module_param(max_interrupt_work, int, 0);
4a5e8e29
JG		 2953MODULE_PARM_DESC(max_interrupt_work,
2954 DRV_NAME " maximum events handled per interrupt");
1da177e4 2955module_param(rx_copybreak, int, 0);
4a5e8e29
JG		 2956MODULE_PARM_DESC(rx_copybreak,
2957 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 2958module_param(tx_start_pt, int, 0);
2959MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2960module_param(pcnet32vlb, int, 0);
2961MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2962module_param_array(options, int, NULL, 0);
2963MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2964module_param_array(full_duplex, int, NULL, 0);
2965MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2966/* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2967module_param_array(homepna, int, NULL, 0);
4a5e8e29
JG		 2968MODULE_PARM_DESC(homepna,
2969 DRV_NAME
2970 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
1da177e4
LT		 2971
2972MODULE_AUTHOR("Thomas Bogendoerfer");
2973MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2974MODULE_LICENSE("GPL");
2975
2976#define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2977
2978static int __init pcnet32_init_module(void)
2979{
4a5e8e29 2980 printk(KERN_INFO "%s", version);
1da177e4 2981
4a5e8e29 2982 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
1da177e4 2983
4a5e8e29
JG		 2984 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2985 tx_start = tx_start_pt;
1da177e4 2986
4a5e8e29
JG		 2987 /* find the PCI devices */
2988 if (!pci_module_init(&pcnet32_driver))
2989 pcnet32_have_pci = 1;
1da177e4 2990
4a5e8e29
JG		 2991 /* should we find any remaining VLbus devices ? */
2992 if (pcnet32vlb)
dcaf9769 2993 pcnet32_probe_vlbus(pcnet32_portlist);
1da177e4 2994
4a5e8e29
JG		 2995 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
2996 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
1da177e4 2997
4a5e8e29 2998 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
1da177e4
LT		 2999}
3000
3001static void __exit pcnet32_cleanup_module(void)
3002{
4a5e8e29
JG		 3003 struct net_device *next_dev;
3004
3005 while (pcnet32_dev) {
3006 struct pcnet32_private *lp = pcnet32_dev->priv;
3007 next_dev = lp->next;
3008 unregister_netdev(pcnet32_dev);
3009 pcnet32_free_ring(pcnet32_dev);
3010 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
3011 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
3012 free_netdev(pcnet32_dev);
3013 pcnet32_dev = next_dev;
3014 }
1da177e4 3015
4a5e8e29
JG		 3016 if (pcnet32_have_pci)
3017 pci_unregister_driver(&pcnet32_driver);
1da177e4
LT		 3018}
3019
3020module_init(pcnet32_init_module);
3021module_exit(pcnet32_cleanup_module);
3022
3023/*
3024 * Local variables:
3025 * c-indent-level: 4
3026 * tab-width: 8
3027 * End:
3028 */
Linux kernel - Deliverables
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