[deliverable/linux.git] / drivers / net / phy / at803x.c

/*
 * drivers/net/phy/at803x.c
 *
 * Driver for Atheros 803x PHY
 *
 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/phy.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>

#define AT803X_INTR_ENABLE			0x12
#define AT803X_INTR_STATUS			0x13
#define AT803X_WOL_ENABLE			0x01
#define AT803X_DEVICE_ADDR			0x03
#define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
#define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
#define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
#define AT803X_MMD_ACCESS_CONTROL		0x0D
#define AT803X_MMD_ACCESS_CONTROL_DATA		0x0E
#define AT803X_FUNC_DATA			0x4003
#define AT803X_INER				0x0012
#define AT803X_INER_INIT			0xec00
#define AT803X_INSR				0x0013
#define AT803X_DEBUG_ADDR			0x1D
#define AT803X_DEBUG_DATA			0x1E
#define AT803X_DEBUG_SYSTEM_MODE_CTRL		0x05
#define AT803X_DEBUG_RGMII_TX_CLK_DLY		BIT(8)

MODULE_DESCRIPTION("Atheros 803x PHY driver");
MODULE_AUTHOR("Matus Ujhelyi");
MODULE_LICENSE("GPL");

static int at803x_set_wol(struct phy_device *phydev,
			  struct ethtool_wolinfo *wol)
{
	struct net_device *ndev = phydev->attached_dev;
	const u8 *mac;
	int ret;
	u32 value;
	unsigned int i, offsets[] = {
		AT803X_LOC_MAC_ADDR_32_47_OFFSET,
		AT803X_LOC_MAC_ADDR_16_31_OFFSET,
		AT803X_LOC_MAC_ADDR_0_15_OFFSET,
	};

	if (!ndev)
		return -ENODEV;

	if (wol->wolopts & WAKE_MAGIC) {
		mac = (const u8 *) ndev->dev_addr;

		if (!is_valid_ether_addr(mac))
			return -EFAULT;

		for (i = 0; i < 3; i++) {
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
				  AT803X_DEVICE_ADDR);
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
				  offsets[i]);
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
				  AT803X_FUNC_DATA);
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
				  mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
		}

		value = phy_read(phydev, AT803X_INTR_ENABLE);
		value |= AT803X_WOL_ENABLE;
		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
		if (ret)
			return ret;
		value = phy_read(phydev, AT803X_INTR_STATUS);
	} else {
		value = phy_read(phydev, AT803X_INTR_ENABLE);
		value &= (~AT803X_WOL_ENABLE);
		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
		if (ret)
			return ret;
		value = phy_read(phydev, AT803X_INTR_STATUS);
	}

	return ret;
}

static void at803x_get_wol(struct phy_device *phydev,
			   struct ethtool_wolinfo *wol)
{
	u32 value;

	wol->supported = WAKE_MAGIC;
	wol->wolopts = 0;

	value = phy_read(phydev, AT803X_INTR_ENABLE);
	if (value & AT803X_WOL_ENABLE)
		wol->wolopts |= WAKE_MAGIC;
}

static int at803x_suspend(struct phy_device *phydev)
{
	int value;
	int wol_enabled;

	mutex_lock(&phydev->lock);

	value = phy_read(phydev, AT803X_INTR_ENABLE);
	wol_enabled = value & AT803X_WOL_ENABLE;

	value = phy_read(phydev, MII_BMCR);

	if (wol_enabled)
		value |= BMCR_ISOLATE;
	else
		value |= BMCR_PDOWN;

	phy_write(phydev, MII_BMCR, value);

	mutex_unlock(&phydev->lock);

	return 0;
}

static int at803x_resume(struct phy_device *phydev)
{
	int value;

	mutex_lock(&phydev->lock);

	value = phy_read(phydev, MII_BMCR);
	value &= ~(BMCR_PDOWN | BMCR_ISOLATE);
	phy_write(phydev, MII_BMCR, value);

	mutex_unlock(&phydev->lock);

	return 0;
}

static int at803x_config_init(struct phy_device *phydev)
{
	int ret;

	ret = genphy_config_init(phydev);
	if (ret < 0)
		return ret;

	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
		ret = phy_write(phydev, AT803X_DEBUG_ADDR,
				AT803X_DEBUG_SYSTEM_MODE_CTRL);
		if (ret)
			return ret;
		ret = phy_write(phydev, AT803X_DEBUG_DATA,
				AT803X_DEBUG_RGMII_TX_CLK_DLY);
		if (ret)
			return ret;
	}

	return 0;
}

static int at803x_ack_interrupt(struct phy_device *phydev)
{
	int err;

	err = phy_read(phydev, AT803X_INSR);

	return (err < 0) ? err : 0;
}

static int at803x_config_intr(struct phy_device *phydev)
{
	int err;
	int value;

	value = phy_read(phydev, AT803X_INER);

	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
		err = phy_write(phydev, AT803X_INER,
				value | AT803X_INER_INIT);
	else
		err = phy_write(phydev, AT803X_INER, 0);

	return err;
}

static struct phy_driver at803x_driver[] = {
{
	/* ATHEROS 8035 */
	.phy_id		= 0x004dd072,
	.name		= "Atheros 8035 ethernet",
	.phy_id_mask	= 0xffffffef,
	.config_init	= at803x_config_init,
	.set_wol	= at803x_set_wol,
	.get_wol	= at803x_get_wol,
	.suspend	= at803x_suspend,
	.resume		= at803x_resume,
	.features	= PHY_GBIT_FEATURES,
	.flags		= PHY_HAS_INTERRUPT,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.driver		= {
		.owner = THIS_MODULE,
	},
}, {
	/* ATHEROS 8030 */
	.phy_id		= 0x004dd076,
	.name		= "Atheros 8030 ethernet",
	.phy_id_mask	= 0xffffffef,
	.config_init	= at803x_config_init,
	.set_wol	= at803x_set_wol,
	.get_wol	= at803x_get_wol,
	.suspend	= at803x_suspend,
	.resume		= at803x_resume,
	.features	= PHY_GBIT_FEATURES,
	.flags		= PHY_HAS_INTERRUPT,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.driver		= {
		.owner = THIS_MODULE,
	},
}, {
	/* ATHEROS 8031 */
	.phy_id		= 0x004dd074,
	.name		= "Atheros 8031 ethernet",
	.phy_id_mask	= 0xffffffef,
	.config_init	= at803x_config_init,
	.set_wol	= at803x_set_wol,
	.get_wol	= at803x_get_wol,
	.suspend	= at803x_suspend,
	.resume		= at803x_resume,
	.features	= PHY_GBIT_FEATURES,
	.flags		= PHY_HAS_INTERRUPT,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt  = &at803x_ack_interrupt,
	.config_intr    = &at803x_config_intr,
	.driver		= {
		.owner = THIS_MODULE,
	},
} };

static int __init atheros_init(void)
{
	return phy_drivers_register(at803x_driver,
				    ARRAY_SIZE(at803x_driver));
}

static void __exit atheros_exit(void)
{
	phy_drivers_unregister(at803x_driver, ARRAY_SIZE(at803x_driver));
}

module_init(atheros_init);
module_exit(atheros_exit);

static struct mdio_device_id __maybe_unused atheros_tbl[] = {
	{ 0x004dd076, 0xffffffef },
	{ 0x004dd074, 0xffffffef },
	{ 0x004dd072, 0xffffffef },
	{ }
};

MODULE_DEVICE_TABLE(mdio, atheros_tbl);
Commit	Line	Data
0ca7111a MU	1	/*
	2	* drivers/net/phy/at803x.c
	3	*
	4	* Driver for Atheros 803x PHY
	5	*
	6	* Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
	14	#include <linux/phy.h>
	15	#include <linux/module.h>
	16	#include <linux/string.h>
	17	#include <linux/netdevice.h>
	18	#include <linux/etherdevice.h>
	19
	20	#define AT803X_INTR_ENABLE 0x12
	21	#define AT803X_INTR_STATUS 0x13
	22	#define AT803X_WOL_ENABLE 0x01
	23	#define AT803X_DEVICE_ADDR 0x03
	24	#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
	25	#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
	26	#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
	27	#define AT803X_MMD_ACCESS_CONTROL 0x0D
	28	#define AT803X_MMD_ACCESS_CONTROL_DATA 0x0E
	29	#define AT803X_FUNC_DATA 0x4003
77a99394 ZQ	30	#define AT803X_INER 0x0012
	31	#define AT803X_INER_INIT 0xec00
	32	#define AT803X_INSR 0x0013
1ca6d1b1 M	33	#define AT803X_DEBUG_ADDR 0x1D
	34	#define AT803X_DEBUG_DATA 0x1E
	35	#define AT803X_DEBUG_SYSTEM_MODE_CTRL 0x05
	36	#define AT803X_DEBUG_RGMII_TX_CLK_DLY BIT(8)
0ca7111a MU	37
	38	MODULE_DESCRIPTION("Atheros 803x PHY driver");
	39	MODULE_AUTHOR("Matus Ujhelyi");
	40	MODULE_LICENSE("GPL");
	41
ea13c9ee M	42	static int at803x_set_wol(struct phy_device *phydev,
ea13c9ee M	43	struct ethtool_wolinfo *wol)
0ca7111a MU	44	{
	45	struct net_device *ndev = phydev->attached_dev;
	46	const u8 *mac;
ea13c9ee M	47	int ret;
ea13c9ee M	48	u32 value;
0ca7111a MU	49	unsigned int i, offsets[] = {
	50	AT803X_LOC_MAC_ADDR_32_47_OFFSET,
	51	AT803X_LOC_MAC_ADDR_16_31_OFFSET,
	52	AT803X_LOC_MAC_ADDR_0_15_OFFSET,
	53	};
	54
	55	if (!ndev)
ea13c9ee	56	return -ENODEV;
0ca7111a	57
ea13c9ee M	58	if (wol->wolopts & WAKE_MAGIC) {
ea13c9ee M	59	mac = (const u8 *) ndev->dev_addr;
0ca7111a	60
ea13c9ee M	61	if (!is_valid_ether_addr(mac))
ea13c9ee M	62	return -EFAULT;
0ca7111a	63
ea13c9ee M	64	for (i = 0; i < 3; i++) {
ea13c9ee M	65	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
0ca7111a	66	AT803X_DEVICE_ADDR);
ea13c9ee	67	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
0ca7111a	68	offsets[i]);
ea13c9ee	69	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
0ca7111a	70	AT803X_FUNC_DATA);
ea13c9ee	71	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
0ca7111a	72	mac[(i * 2) + 1] \| (mac[(i * 2)] << 8));
ea13c9ee M	73	}
	74
	75	value = phy_read(phydev, AT803X_INTR_ENABLE);
	76	value \|= AT803X_WOL_ENABLE;
	77	ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
	78	if (ret)
	79	return ret;
	80	value = phy_read(phydev, AT803X_INTR_STATUS);
	81	} else {
	82	value = phy_read(phydev, AT803X_INTR_ENABLE);
	83	value &= (~AT803X_WOL_ENABLE);
	84	ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
	85	if (ret)
	86	return ret;
	87	value = phy_read(phydev, AT803X_INTR_STATUS);
0ca7111a	88	}
ea13c9ee M	89
	90	return ret;
	91	}
	92
	93	static void at803x_get_wol(struct phy_device *phydev,
	94	struct ethtool_wolinfo *wol)
	95	{
	96	u32 value;
	97
	98	wol->supported = WAKE_MAGIC;
	99	wol->wolopts = 0;
	100
	101	value = phy_read(phydev, AT803X_INTR_ENABLE);
	102	if (value & AT803X_WOL_ENABLE)
	103	wol->wolopts \|= WAKE_MAGIC;
0ca7111a MU	104	}
0ca7111a MU	105
6229ed1f DM	106	static int at803x_suspend(struct phy_device *phydev)
	107	{
	108	int value;
	109	int wol_enabled;
	110
	111	mutex_lock(&phydev->lock);
	112
	113	value = phy_read(phydev, AT803X_INTR_ENABLE);
	114	wol_enabled = value & AT803X_WOL_ENABLE;
	115
	116	value = phy_read(phydev, MII_BMCR);
	117
	118	if (wol_enabled)
	119	value \|= BMCR_ISOLATE;
	120	else
	121	value \|= BMCR_PDOWN;
	122
	123	phy_write(phydev, MII_BMCR, value);
	124
	125	mutex_unlock(&phydev->lock);
	126
	127	return 0;
	128	}
	129
	130	static int at803x_resume(struct phy_device *phydev)
	131	{
	132	int value;
	133
	134	mutex_lock(&phydev->lock);
	135
	136	value = phy_read(phydev, MII_BMCR);
	137	value &= ~(BMCR_PDOWN \| BMCR_ISOLATE);
	138	phy_write(phydev, MII_BMCR, value);
	139
	140	mutex_unlock(&phydev->lock);
	141
	142	return 0;
	143	}
	144
0ca7111a MU	145	static int at803x_config_init(struct phy_device *phydev)
0ca7111a MU	146	{
1ca6d1b1	147	int ret;
0ca7111a	148
6ff01dbb DM	149	ret = genphy_config_init(phydev);
	150	if (ret < 0)
	151	return ret;
0ca7111a	152
1ca6d1b1 M	153	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
	154	ret = phy_write(phydev, AT803X_DEBUG_ADDR,
	155	AT803X_DEBUG_SYSTEM_MODE_CTRL);
	156	if (ret)
	157	return ret;
	158	ret = phy_write(phydev, AT803X_DEBUG_DATA,
	159	AT803X_DEBUG_RGMII_TX_CLK_DLY);
	160	if (ret)
	161	return ret;
	162	}
	163
0ca7111a MU	164	return 0;
	165	}
	166
77a99394 ZQ	167	static int at803x_ack_interrupt(struct phy_device *phydev)
	168	{
	169	int err;
	170
	171	err = phy_read(phydev, AT803X_INSR);
	172
	173	return (err < 0) ? err : 0;
	174	}
	175
	176	static int at803x_config_intr(struct phy_device *phydev)
	177	{
	178	int err;
	179	int value;
	180
	181	value = phy_read(phydev, AT803X_INER);
	182
	183	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
	184	err = phy_write(phydev, AT803X_INER,
	185	value \| AT803X_INER_INIT);
	186	else
	187	err = phy_write(phydev, AT803X_INER, 0);
	188
	189	return err;
	190	}
	191
317420ab M	192	static struct phy_driver at803x_driver[] = {
	193	{
	194	/* ATHEROS 8035 */
0ca7111a MU	195	.phy_id = 0x004dd072,
	196	.name = "Atheros 8035 ethernet",
	197	.phy_id_mask = 0xffffffef,
	198	.config_init = at803x_config_init,
ea13c9ee M	199	.set_wol = at803x_set_wol,
ea13c9ee M	200	.get_wol = at803x_get_wol,
6229ed1f DM	201	.suspend = at803x_suspend,
6229ed1f DM	202	.resume = at803x_resume,
0ca7111a MU	203	.features = PHY_GBIT_FEATURES,
0ca7111a MU	204	.flags = PHY_HAS_INTERRUPT,
0197ffed DM	205	.config_aneg = genphy_config_aneg,
0197ffed DM	206	.read_status = genphy_read_status,
0ca7111a MU	207	.driver = {
	208	.owner = THIS_MODULE,
	209	},
317420ab M	210	}, {
317420ab M	211	/* ATHEROS 8030 */
0ca7111a MU	212	.phy_id = 0x004dd076,
	213	.name = "Atheros 8030 ethernet",
	214	.phy_id_mask = 0xffffffef,
	215	.config_init = at803x_config_init,
ea13c9ee M	216	.set_wol = at803x_set_wol,
ea13c9ee M	217	.get_wol = at803x_get_wol,
6229ed1f DM	218	.suspend = at803x_suspend,
6229ed1f DM	219	.resume = at803x_resume,
0ca7111a MU	220	.features = PHY_GBIT_FEATURES,
0ca7111a MU	221	.flags = PHY_HAS_INTERRUPT,
0197ffed DM	222	.config_aneg = genphy_config_aneg,
0197ffed DM	223	.read_status = genphy_read_status,
0ca7111a MU	224	.driver = {
	225	.owner = THIS_MODULE,
	226	},
05d7cce8 M	227	}, {
	228	/* ATHEROS 8031 */
	229	.phy_id = 0x004dd074,
	230	.name = "Atheros 8031 ethernet",
	231	.phy_id_mask = 0xffffffef,
	232	.config_init = at803x_config_init,
	233	.set_wol = at803x_set_wol,
	234	.get_wol = at803x_get_wol,
6229ed1f DM	235	.suspend = at803x_suspend,
6229ed1f DM	236	.resume = at803x_resume,
05d7cce8 M	237	.features = PHY_GBIT_FEATURES,
05d7cce8 M	238	.flags = PHY_HAS_INTERRUPT,
0197ffed DM	239	.config_aneg = genphy_config_aneg,
0197ffed DM	240	.read_status = genphy_read_status,
77a99394 ZQ	241	.ack_interrupt = &at803x_ack_interrupt,
77a99394 ZQ	242	.config_intr = &at803x_config_intr,
05d7cce8 M	243	.driver = {
	244	.owner = THIS_MODULE,
	245	},
317420ab	246	} };
0ca7111a MU	247
	248	static int __init atheros_init(void)
	249	{
317420ab M	250	return phy_drivers_register(at803x_driver,
317420ab M	251	ARRAY_SIZE(at803x_driver));
0ca7111a MU	252	}
	253
	254	static void __exit atheros_exit(void)
	255	{
2ebb1582	256	phy_drivers_unregister(at803x_driver, ARRAY_SIZE(at803x_driver));
0ca7111a MU	257	}
	258
	259	module_init(atheros_init);
	260	module_exit(atheros_exit);
	261
	262	static struct mdio_device_id __maybe_unused atheros_tbl[] = {
	263	{ 0x004dd076, 0xffffffef },
ce9a1bf8	264	{ 0x004dd074, 0xffffffef },
0ca7111a MU	265	{ 0x004dd072, 0xffffffef },
	266	{ }
	267	};
	268
	269	MODULE_DEVICE_TABLE(mdio, atheros_tbl);