[deliverable/linux.git] / drivers / net / phy / at803x.c

/*
 * drivers/net/phy/at803x.c
 *
 * Driver for Atheros 803x PHY
 *
 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/phy.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>

#define AT803X_INTR_ENABLE			0x12
#define AT803X_INTR_STATUS			0x13
#define AT803X_WOL_ENABLE			0x01
#define AT803X_DEVICE_ADDR			0x03
#define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
#define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
#define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
#define AT803X_MMD_ACCESS_CONTROL		0x0D
#define AT803X_MMD_ACCESS_CONTROL_DATA		0x0E
#define AT803X_FUNC_DATA			0x4003
#define AT803X_INER				0x0012
#define AT803X_INER_INIT			0xec00
#define AT803X_INSR				0x0013
#define AT803X_DEBUG_ADDR			0x1D
#define AT803X_DEBUG_DATA			0x1E
#define AT803X_DEBUG_SYSTEM_MODE_CTRL		0x05
#define AT803X_DEBUG_RGMII_TX_CLK_DLY		BIT(8)

#define ATH8030_PHY_ID 0x004dd076
#define ATH8031_PHY_ID 0x004dd074
#define ATH8035_PHY_ID 0x004dd072

MODULE_DESCRIPTION("Atheros 803x PHY driver");
MODULE_AUTHOR("Matus Ujhelyi");
MODULE_LICENSE("GPL");

static int at803x_set_wol(struct phy_device *phydev,
			  struct ethtool_wolinfo *wol)
{
	struct net_device *ndev = phydev->attached_dev;
	const u8 *mac;
	int ret;
	u32 value;
	unsigned int i, offsets[] = {
		AT803X_LOC_MAC_ADDR_32_47_OFFSET,
		AT803X_LOC_MAC_ADDR_16_31_OFFSET,
		AT803X_LOC_MAC_ADDR_0_15_OFFSET,
	};

	if (!ndev)
		return -ENODEV;

	if (wol->wolopts & WAKE_MAGIC) {
		mac = (const u8 *) ndev->dev_addr;

		if (!is_valid_ether_addr(mac))
			return -EFAULT;

		for (i = 0; i < 3; i++) {
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
				  AT803X_DEVICE_ADDR);
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
				  offsets[i]);
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
				  AT803X_FUNC_DATA);
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
				  mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
		}

		value = phy_read(phydev, AT803X_INTR_ENABLE);
		value |= AT803X_WOL_ENABLE;
		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
		if (ret)
			return ret;
		value = phy_read(phydev, AT803X_INTR_STATUS);
	} else {
		value = phy_read(phydev, AT803X_INTR_ENABLE);
		value &= (~AT803X_WOL_ENABLE);
		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
		if (ret)
			return ret;
		value = phy_read(phydev, AT803X_INTR_STATUS);
	}

	return ret;
}

static void at803x_get_wol(struct phy_device *phydev,
			   struct ethtool_wolinfo *wol)
{
	u32 value;

	wol->supported = WAKE_MAGIC;
	wol->wolopts = 0;

	value = phy_read(phydev, AT803X_INTR_ENABLE);
	if (value & AT803X_WOL_ENABLE)
		wol->wolopts |= WAKE_MAGIC;
}

static int at803x_suspend(struct phy_device *phydev)
{
	int value;
	int wol_enabled;

	mutex_lock(&phydev->lock);

	value = phy_read(phydev, AT803X_INTR_ENABLE);
	wol_enabled = value & AT803X_WOL_ENABLE;

	value = phy_read(phydev, MII_BMCR);

	if (wol_enabled)
		value |= BMCR_ISOLATE;
	else
		value |= BMCR_PDOWN;

	phy_write(phydev, MII_BMCR, value);

	mutex_unlock(&phydev->lock);

	return 0;
}

static int at803x_resume(struct phy_device *phydev)
{
	int value;

	mutex_lock(&phydev->lock);

	value = phy_read(phydev, MII_BMCR);
	value &= ~(BMCR_PDOWN | BMCR_ISOLATE);
	phy_write(phydev, MII_BMCR, value);

	mutex_unlock(&phydev->lock);

	return 0;
}

static int at803x_config_init(struct phy_device *phydev)
{
	int ret;

	ret = genphy_config_init(phydev);
	if (ret < 0)
		return ret;

	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
		ret = phy_write(phydev, AT803X_DEBUG_ADDR,
				AT803X_DEBUG_SYSTEM_MODE_CTRL);
		if (ret)
			return ret;
		ret = phy_write(phydev, AT803X_DEBUG_DATA,
				AT803X_DEBUG_RGMII_TX_CLK_DLY);
		if (ret)
			return ret;
	}

	return 0;
}

static int at803x_ack_interrupt(struct phy_device *phydev)
{
	int err;

	err = phy_read(phydev, AT803X_INSR);

	return (err < 0) ? err : 0;
}

static int at803x_config_intr(struct phy_device *phydev)
{
	int err;
	int value;

	value = phy_read(phydev, AT803X_INER);

	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
		err = phy_write(phydev, AT803X_INER,
				value | AT803X_INER_INIT);
	else
		err = phy_write(phydev, AT803X_INER, 0);

	return err;
}

static struct phy_driver at803x_driver[] = {
{
	/* ATHEROS 8035 */
	.phy_id		= ATH8035_PHY_ID,
	.name		= "Atheros 8035 ethernet",
	.phy_id_mask	= 0xffffffef,
	.config_init	= at803x_config_init,
	.set_wol	= at803x_set_wol,
	.get_wol	= at803x_get_wol,
	.suspend	= at803x_suspend,
	.resume		= at803x_resume,
	.features	= PHY_GBIT_FEATURES,
	.flags		= PHY_HAS_INTERRUPT,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.driver		= {
		.owner = THIS_MODULE,
	},
}, {
	/* ATHEROS 8030 */
	.phy_id		= ATH8030_PHY_ID,
	.name		= "Atheros 8030 ethernet",
	.phy_id_mask	= 0xffffffef,
	.config_init	= at803x_config_init,
	.set_wol	= at803x_set_wol,
	.get_wol	= at803x_get_wol,
	.suspend	= at803x_suspend,
	.resume		= at803x_resume,
	.features	= PHY_GBIT_FEATURES,
	.flags		= PHY_HAS_INTERRUPT,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.driver		= {
		.owner = THIS_MODULE,
	},
}, {
	/* ATHEROS 8031 */
	.phy_id		= ATH8031_PHY_ID,
	.name		= "Atheros 8031 ethernet",
	.phy_id_mask	= 0xffffffef,
	.config_init	= at803x_config_init,
	.set_wol	= at803x_set_wol,
	.get_wol	= at803x_get_wol,
	.suspend	= at803x_suspend,
	.resume		= at803x_resume,
	.features	= PHY_GBIT_FEATURES,
	.flags		= PHY_HAS_INTERRUPT,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt  = &at803x_ack_interrupt,
	.config_intr    = &at803x_config_intr,
	.driver		= {
		.owner = THIS_MODULE,
	},
} };

static int __init atheros_init(void)
{
	return phy_drivers_register(at803x_driver,
				    ARRAY_SIZE(at803x_driver));
}

static void __exit atheros_exit(void)
{
	phy_drivers_unregister(at803x_driver, ARRAY_SIZE(at803x_driver));
}

module_init(atheros_init);
module_exit(atheros_exit);

static struct mdio_device_id __maybe_unused atheros_tbl[] = {
	{ ATH8030_PHY_ID, 0xffffffef },
	{ ATH8031_PHY_ID, 0xffffffef },
	{ ATH8035_PHY_ID, 0xffffffef },
	{ }
};

MODULE_DEVICE_TABLE(mdio, atheros_tbl);
Commit	Line	Data
0ca7111a MU	1	/*
	2	* drivers/net/phy/at803x.c
	3	*
	4	* Driver for Atheros 803x PHY
	5	*
	6	* Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
	14	#include <linux/phy.h>
	15	#include <linux/module.h>
	16	#include <linux/string.h>
	17	#include <linux/netdevice.h>
	18	#include <linux/etherdevice.h>
	19
	20	#define AT803X_INTR_ENABLE 0x12
	21	#define AT803X_INTR_STATUS 0x13
	22	#define AT803X_WOL_ENABLE 0x01
	23	#define AT803X_DEVICE_ADDR 0x03
	24	#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
	25	#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
	26	#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
	27	#define AT803X_MMD_ACCESS_CONTROL 0x0D
	28	#define AT803X_MMD_ACCESS_CONTROL_DATA 0x0E
	29	#define AT803X_FUNC_DATA 0x4003
77a99394 ZQ	30	#define AT803X_INER 0x0012
	31	#define AT803X_INER_INIT 0xec00
	32	#define AT803X_INSR 0x0013
1ca6d1b1 M	33	#define AT803X_DEBUG_ADDR 0x1D
	34	#define AT803X_DEBUG_DATA 0x1E
	35	#define AT803X_DEBUG_SYSTEM_MODE_CTRL 0x05
	36	#define AT803X_DEBUG_RGMII_TX_CLK_DLY BIT(8)
0ca7111a	37
bd8ca17f DM	38	#define ATH8030_PHY_ID 0x004dd076
	39	#define ATH8031_PHY_ID 0x004dd074
	40	#define ATH8035_PHY_ID 0x004dd072
	41
0ca7111a MU	42	MODULE_DESCRIPTION("Atheros 803x PHY driver");
	43	MODULE_AUTHOR("Matus Ujhelyi");
	44	MODULE_LICENSE("GPL");
	45
ea13c9ee M	46	static int at803x_set_wol(struct phy_device *phydev,
ea13c9ee M	47	struct ethtool_wolinfo *wol)
0ca7111a MU	48	{
	49	struct net_device *ndev = phydev->attached_dev;
	50	const u8 *mac;
ea13c9ee M	51	int ret;
ea13c9ee M	52	u32 value;
0ca7111a MU	53	unsigned int i, offsets[] = {
	54	AT803X_LOC_MAC_ADDR_32_47_OFFSET,
	55	AT803X_LOC_MAC_ADDR_16_31_OFFSET,
	56	AT803X_LOC_MAC_ADDR_0_15_OFFSET,
	57	};
	58
	59	if (!ndev)
ea13c9ee	60	return -ENODEV;
0ca7111a	61
ea13c9ee M	62	if (wol->wolopts & WAKE_MAGIC) {
ea13c9ee M	63	mac = (const u8 *) ndev->dev_addr;
0ca7111a	64
ea13c9ee M	65	if (!is_valid_ether_addr(mac))
ea13c9ee M	66	return -EFAULT;
0ca7111a	67
ea13c9ee M	68	for (i = 0; i < 3; i++) {
ea13c9ee M	69	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
0ca7111a	70	AT803X_DEVICE_ADDR);
ea13c9ee	71	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
0ca7111a	72	offsets[i]);
ea13c9ee	73	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
0ca7111a	74	AT803X_FUNC_DATA);
ea13c9ee	75	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
0ca7111a	76	mac[(i * 2) + 1] \| (mac[(i * 2)] << 8));
ea13c9ee M	77	}
	78
	79	value = phy_read(phydev, AT803X_INTR_ENABLE);
	80	value \|= AT803X_WOL_ENABLE;
	81	ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
	82	if (ret)
	83	return ret;
	84	value = phy_read(phydev, AT803X_INTR_STATUS);
	85	} else {
	86	value = phy_read(phydev, AT803X_INTR_ENABLE);
	87	value &= (~AT803X_WOL_ENABLE);
	88	ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
	89	if (ret)
	90	return ret;
	91	value = phy_read(phydev, AT803X_INTR_STATUS);
0ca7111a	92	}
ea13c9ee M	93
	94	return ret;
	95	}
	96
	97	static void at803x_get_wol(struct phy_device *phydev,
	98	struct ethtool_wolinfo *wol)
	99	{
	100	u32 value;
	101
	102	wol->supported = WAKE_MAGIC;
	103	wol->wolopts = 0;
	104
	105	value = phy_read(phydev, AT803X_INTR_ENABLE);
	106	if (value & AT803X_WOL_ENABLE)
	107	wol->wolopts \|= WAKE_MAGIC;
0ca7111a MU	108	}
0ca7111a MU	109
6229ed1f DM	110	static int at803x_suspend(struct phy_device *phydev)
	111	{
	112	int value;
	113	int wol_enabled;
	114
	115	mutex_lock(&phydev->lock);
	116
	117	value = phy_read(phydev, AT803X_INTR_ENABLE);
	118	wol_enabled = value & AT803X_WOL_ENABLE;
	119
	120	value = phy_read(phydev, MII_BMCR);
	121
	122	if (wol_enabled)
	123	value \|= BMCR_ISOLATE;
	124	else
	125	value \|= BMCR_PDOWN;
	126
	127	phy_write(phydev, MII_BMCR, value);
	128
	129	mutex_unlock(&phydev->lock);
	130
	131	return 0;
	132	}
	133
	134	static int at803x_resume(struct phy_device *phydev)
	135	{
	136	int value;
	137
	138	mutex_lock(&phydev->lock);
	139
	140	value = phy_read(phydev, MII_BMCR);
	141	value &= ~(BMCR_PDOWN \| BMCR_ISOLATE);
	142	phy_write(phydev, MII_BMCR, value);
	143
	144	mutex_unlock(&phydev->lock);
	145
	146	return 0;
	147	}
	148
0ca7111a MU	149	static int at803x_config_init(struct phy_device *phydev)
0ca7111a MU	150	{
1ca6d1b1	151	int ret;
0ca7111a	152
6ff01dbb DM	153	ret = genphy_config_init(phydev);
	154	if (ret < 0)
	155	return ret;
0ca7111a	156
1ca6d1b1 M	157	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
	158	ret = phy_write(phydev, AT803X_DEBUG_ADDR,
	159	AT803X_DEBUG_SYSTEM_MODE_CTRL);
	160	if (ret)
	161	return ret;
	162	ret = phy_write(phydev, AT803X_DEBUG_DATA,
	163	AT803X_DEBUG_RGMII_TX_CLK_DLY);
	164	if (ret)
	165	return ret;
	166	}
	167
0ca7111a MU	168	return 0;
	169	}
	170
77a99394 ZQ	171	static int at803x_ack_interrupt(struct phy_device *phydev)
	172	{
	173	int err;
	174
	175	err = phy_read(phydev, AT803X_INSR);
	176
	177	return (err < 0) ? err : 0;
	178	}
	179
	180	static int at803x_config_intr(struct phy_device *phydev)
	181	{
	182	int err;
	183	int value;
	184
	185	value = phy_read(phydev, AT803X_INER);
	186
	187	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
	188	err = phy_write(phydev, AT803X_INER,
	189	value \| AT803X_INER_INIT);
	190	else
	191	err = phy_write(phydev, AT803X_INER, 0);
	192
	193	return err;
	194	}
	195
317420ab M	196	static struct phy_driver at803x_driver[] = {
	197	{
	198	/* ATHEROS 8035 */
bd8ca17f	199	.phy_id = ATH8035_PHY_ID,
0ca7111a MU	200	.name = "Atheros 8035 ethernet",
	201	.phy_id_mask = 0xffffffef,
	202	.config_init = at803x_config_init,
ea13c9ee M	203	.set_wol = at803x_set_wol,
ea13c9ee M	204	.get_wol = at803x_get_wol,
6229ed1f DM	205	.suspend = at803x_suspend,
6229ed1f DM	206	.resume = at803x_resume,
0ca7111a MU	207	.features = PHY_GBIT_FEATURES,
0ca7111a MU	208	.flags = PHY_HAS_INTERRUPT,
0197ffed DM	209	.config_aneg = genphy_config_aneg,
0197ffed DM	210	.read_status = genphy_read_status,
0ca7111a MU	211	.driver = {
	212	.owner = THIS_MODULE,
	213	},
317420ab M	214	}, {
317420ab M	215	/* ATHEROS 8030 */
bd8ca17f	216	.phy_id = ATH8030_PHY_ID,
0ca7111a MU	217	.name = "Atheros 8030 ethernet",
	218	.phy_id_mask = 0xffffffef,
	219	.config_init = at803x_config_init,
ea13c9ee M	220	.set_wol = at803x_set_wol,
ea13c9ee M	221	.get_wol = at803x_get_wol,
6229ed1f DM	222	.suspend = at803x_suspend,
6229ed1f DM	223	.resume = at803x_resume,
0ca7111a MU	224	.features = PHY_GBIT_FEATURES,
0ca7111a MU	225	.flags = PHY_HAS_INTERRUPT,
0197ffed DM	226	.config_aneg = genphy_config_aneg,
0197ffed DM	227	.read_status = genphy_read_status,
0ca7111a MU	228	.driver = {
	229	.owner = THIS_MODULE,
	230	},
05d7cce8 M	231	}, {
05d7cce8 M	232	/* ATHEROS 8031 */
bd8ca17f	233	.phy_id = ATH8031_PHY_ID,
05d7cce8 M	234	.name = "Atheros 8031 ethernet",
	235	.phy_id_mask = 0xffffffef,
	236	.config_init = at803x_config_init,
	237	.set_wol = at803x_set_wol,
	238	.get_wol = at803x_get_wol,
6229ed1f DM	239	.suspend = at803x_suspend,
6229ed1f DM	240	.resume = at803x_resume,
05d7cce8 M	241	.features = PHY_GBIT_FEATURES,
05d7cce8 M	242	.flags = PHY_HAS_INTERRUPT,
0197ffed DM	243	.config_aneg = genphy_config_aneg,
0197ffed DM	244	.read_status = genphy_read_status,
77a99394 ZQ	245	.ack_interrupt = &at803x_ack_interrupt,
77a99394 ZQ	246	.config_intr = &at803x_config_intr,
05d7cce8 M	247	.driver = {
	248	.owner = THIS_MODULE,
	249	},
317420ab	250	} };
0ca7111a MU	251
	252	static int __init atheros_init(void)
	253	{
317420ab M	254	return phy_drivers_register(at803x_driver,
317420ab M	255	ARRAY_SIZE(at803x_driver));
0ca7111a MU	256	}
	257
	258	static void __exit atheros_exit(void)
	259	{
2ebb1582	260	phy_drivers_unregister(at803x_driver, ARRAY_SIZE(at803x_driver));
0ca7111a MU	261	}
	262
	263	module_init(atheros_init);
	264	module_exit(atheros_exit);
	265
	266	static struct mdio_device_id __maybe_unused atheros_tbl[] = {
bd8ca17f DM	267	{ ATH8030_PHY_ID, 0xffffffef },
	268	{ ATH8031_PHY_ID, 0xffffffef },
	269	{ ATH8035_PHY_ID, 0xffffffef },
0ca7111a MU	270	{ }
	271	};
	272
	273	MODULE_DEVICE_TABLE(mdio, atheros_tbl);