[deliverable/linux.git] / drivers / net / phy / bcm7xxx.c

/*
 * Broadcom BCM7xxx internal transceivers support.
 *
 * Copyright (C) 2014, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/phy.h>
#include <linux/delay.h>
#include <linux/bitops.h>
#include <linux/brcmphy.h>
#include <linux/mdio.h>

/* Broadcom BCM7xxx internal PHY registers */
#define MII_BCM7XXX_CHANNEL_WIDTH	0x2000

/* 40nm only register definitions */
#define MII_BCM7XXX_100TX_AUX_CTL	0x10
#define MII_BCM7XXX_100TX_FALSE_CAR	0x13
#define MII_BCM7XXX_100TX_DISC		0x14
#define MII_BCM7XXX_AUX_MODE		0x1d
#define  MII_BCM7XX_64CLK_MDIO		BIT(12)
#define MII_BCM7XXX_CORE_BASE1E		0x1e
#define MII_BCM7XXX_TEST		0x1f
#define  MII_BCM7XXX_SHD_MODE_2		BIT(2)

/* 28nm only register definitions */
#define MISC_ADDR(base, channel)	base, channel

#define DSP_TAP10			MISC_ADDR(0x0a, 0)
#define PLL_PLLCTRL_1			MISC_ADDR(0x32, 1)
#define PLL_PLLCTRL_2			MISC_ADDR(0x32, 2)
#define PLL_PLLCTRL_4			MISC_ADDR(0x33, 0)

#define AFE_RXCONFIG_0			MISC_ADDR(0x38, 0)
#define AFE_RXCONFIG_1			MISC_ADDR(0x38, 1)
#define AFE_RX_LP_COUNTER		MISC_ADDR(0x38, 3)
#define AFE_TX_CONFIG			MISC_ADDR(0x39, 0)
#define AFE_HPF_TRIM_OTHERS		MISC_ADDR(0x3a, 0)

#define CORE_EXPB0			0xb0

static int bcm7445_config_init(struct phy_device *phydev)
{
	int ret;
	const struct bcm7445_regs {
		int reg;
		u16 value;
	} bcm7445_regs_cfg[] = {
		/* increases ADC latency by 24ns */
		{ MII_BCM54XX_EXP_SEL, 0x0038 },
		{ MII_BCM54XX_EXP_DATA, 0xAB95 },
		/* increases internal 1V LDO voltage by 5% */
		{ MII_BCM54XX_EXP_SEL, 0x2038 },
		{ MII_BCM54XX_EXP_DATA, 0xBB22 },
		/* reduce RX low pass filter corner frequency */
		{ MII_BCM54XX_EXP_SEL, 0x6038 },
		{ MII_BCM54XX_EXP_DATA, 0xFFC5 },
		/* reduce RX high pass filter corner frequency */
		{ MII_BCM54XX_EXP_SEL, 0x003a },
		{ MII_BCM54XX_EXP_DATA, 0x2002 },
	};
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(bcm7445_regs_cfg); i++) {
		ret = phy_write(phydev,
				bcm7445_regs_cfg[i].reg,
				bcm7445_regs_cfg[i].value);
		if (ret)
			return ret;
	}

	return 0;
}

static void phy_write_exp(struct phy_device *phydev,
					u16 reg, u16 value)
{
	phy_write(phydev, MII_BCM54XX_EXP_SEL, MII_BCM54XX_EXP_SEL_ER | reg);
	phy_write(phydev, MII_BCM54XX_EXP_DATA, value);
}

static void phy_write_misc(struct phy_device *phydev,
					u16 reg, u16 chl, u16 value)
{
	int tmp;

	phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);

	tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
	tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
	phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);

	tmp = (chl * MII_BCM7XXX_CHANNEL_WIDTH) | reg;
	phy_write(phydev, MII_BCM54XX_EXP_SEL, tmp);

	phy_write(phydev, MII_BCM54XX_EXP_DATA, value);
}

static int bcm7xxx_28nm_afe_config_init(struct phy_device *phydev)
{
	/* Increase VCO range to prevent unlocking problem of PLL at low
	 * temp
	 */
	phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);

	/* Change Ki to 011 */
	phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);

	/* Disable loading of TVCO buffer to bandgap, set bandgap trim
	 * to 111
	 */
	phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);

	/* Adjust bias current trim by -3 */
	phy_write_misc(phydev, DSP_TAP10, 0x690b);

	/* Switch to CORE_BASE1E */
	phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0xd);

	/* Reset R_CAL/RC_CAL Engine */
	phy_write_exp(phydev, CORE_EXPB0, 0x0010);

	/* Disable Reset R_CAL/RC_CAL Engine */
	phy_write_exp(phydev, CORE_EXPB0, 0x0000);

	/* write AFE_RXCONFIG_0 */
	phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);

	/* write AFE_RXCONFIG_1 */
	phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);

	/* write AFE_RX_LP_COUNTER */
	phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);

	/* write AFE_HPF_TRIM_OTHERS */
	phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);

	/* write AFTE_TX_CONFIG */
	phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);

	return 0;
}

static int bcm7xxx_apd_enable(struct phy_device *phydev)
{
	int val;

	/* Enable powering down of the DLL during auto-power down */
	val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_SCR3);
	if (val < 0)
		return val;

	val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
	bcm54xx_shadow_write(phydev, BCM54XX_SHD_SCR3, val);

	/* Enable auto-power down */
	val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_APD);
	if (val < 0)
		return val;

	val |= BCM54XX_SHD_APD_EN;
	return bcm54xx_shadow_write(phydev, BCM54XX_SHD_APD, val);
}

static int bcm7xxx_eee_enable(struct phy_device *phydev)
{
	int val;

	val = phy_read_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
				    MDIO_MMD_AN, phydev->addr);
	if (val < 0)
		return val;

	/* Enable general EEE feature at the PHY level */
	val |= LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X;

	phy_write_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
			       MDIO_MMD_AN, phydev->addr, val);

	/* Advertise supported modes */
	val = phy_read_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
				    MDIO_MMD_AN, phydev->addr);

	val |= (MDIO_AN_EEE_ADV_100TX | MDIO_AN_EEE_ADV_1000T);
	phy_write_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
			       MDIO_MMD_AN, phydev->addr, val);

	return 0;
}

static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
{
	u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
	u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
	int ret = 0;

	pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
		     dev_name(&phydev->dev), phydev->drv->name, rev, patch);

	switch (rev) {
	case 0xa0:
	case 0xb0:
		ret = bcm7445_config_init(phydev);
		break;
	default:
		ret = bcm7xxx_28nm_afe_config_init(phydev);
		break;
	}

	if (ret)
		return ret;

	ret = bcm7xxx_eee_enable(phydev);
	if (ret)
		return ret;

	return bcm7xxx_apd_enable(phydev);
}

static int bcm7xxx_28nm_resume(struct phy_device *phydev)
{
	int ret;

	/* Re-apply workarounds coming out suspend/resume */
	ret = bcm7xxx_28nm_config_init(phydev);
	if (ret)
		return ret;

	/* 28nm Gigabit PHYs come out of reset without any half-duplex
	 * or "hub" compliant advertised mode, fix that. This does not
	 * cause any problems with the PHY library since genphy_config_aneg()
	 * gracefully handles auto-negotiated and forced modes.
	 */
	return genphy_config_aneg(phydev);
}

static int phy_set_clr_bits(struct phy_device *dev, int location,
					int set_mask, int clr_mask)
{
	int v, ret;

	v = phy_read(dev, location);
	if (v < 0)
		return v;

	v &= ~clr_mask;
	v |= set_mask;

	ret = phy_write(dev, location, v);
	if (ret < 0)
		return ret;

	return v;
}

static int bcm7xxx_config_init(struct phy_device *phydev)
{
	int ret;

	/* Enable 64 clock MDIO */
	phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XX_64CLK_MDIO);
	phy_read(phydev, MII_BCM7XXX_AUX_MODE);

	/* Workaround only required for 100Mbits/sec capable PHYs */
	if (phydev->supported & PHY_GBIT_FEATURES)
		return 0;

	/* set shadow mode 2 */
	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
			MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
	if (ret < 0)
		return ret;

	/* set iddq_clkbias */
	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
	udelay(10);

	/* reset iddq_clkbias */
	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);

	phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);

	/* reset shadow mode 2 */
	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, MII_BCM7XXX_SHD_MODE_2, 0);
	if (ret < 0)
		return ret;

	return 0;
}

/* Workaround for putting the PHY in IDDQ mode, required
 * for all BCM7XXX 40nm and 65nm PHYs
 */
static int bcm7xxx_suspend(struct phy_device *phydev)
{
	int ret;
	const struct bcm7xxx_regs {
		int reg;
		u16 value;
	} bcm7xxx_suspend_cfg[] = {
		{ MII_BCM7XXX_TEST, 0x008b },
		{ MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
		{ MII_BCM7XXX_100TX_DISC, 0x7000 },
		{ MII_BCM7XXX_TEST, 0x000f },
		{ MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
		{ MII_BCM7XXX_TEST, 0x000b },
	};
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
		ret = phy_write(phydev,
				bcm7xxx_suspend_cfg[i].reg,
				bcm7xxx_suspend_cfg[i].value);
		if (ret)
			return ret;
	}

	return 0;
}

static int bcm7xxx_dummy_config_init(struct phy_device *phydev)
{
	return 0;
}

#define BCM7XXX_28NM_GPHY(_oui, _name)					\
{									\
	.phy_id		= (_oui),					\
	.phy_id_mask	= 0xfffffff0,					\
	.name		= _name,					\
	.features	= PHY_GBIT_FEATURES |				\
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,	\
	.flags		= PHY_IS_INTERNAL,				\
	.config_init	= bcm7xxx_28nm_afe_config_init,			\
	.config_aneg	= genphy_config_aneg,				\
	.read_status	= genphy_read_status,				\
	.resume		= bcm7xxx_28nm_resume,				\
	.driver		= { .owner = THIS_MODULE },			\
}

static struct phy_driver bcm7xxx_driver[] = {
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
{
	.phy_id         = PHY_ID_BCM7425,
	.phy_id_mask    = 0xfffffff0,
	.name           = "Broadcom BCM7425",
	.features       = PHY_GBIT_FEATURES |
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
	.flags          = 0,
	.config_init    = bcm7xxx_config_init,
	.config_aneg    = genphy_config_aneg,
	.read_status    = genphy_read_status,
	.suspend        = bcm7xxx_suspend,
	.resume         = bcm7xxx_config_init,
	.driver         = { .owner = THIS_MODULE },
}, {
	.phy_id         = PHY_ID_BCM7429,
	.phy_id_mask    = 0xfffffff0,
	.name           = "Broadcom BCM7429",
	.features       = PHY_GBIT_FEATURES |
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
	.flags          = PHY_IS_INTERNAL,
	.config_init    = bcm7xxx_config_init,
	.config_aneg    = genphy_config_aneg,
	.read_status    = genphy_read_status,
	.suspend        = bcm7xxx_suspend,
	.resume         = bcm7xxx_config_init,
	.driver         = { .owner = THIS_MODULE },
}, {
	.phy_id		= PHY_BCM_OUI_4,
	.phy_id_mask	= 0xffff0000,
	.name		= "Broadcom BCM7XXX 40nm",
	.features	= PHY_GBIT_FEATURES |
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
	.flags		= PHY_IS_INTERNAL,
	.config_init	= bcm7xxx_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.suspend	= bcm7xxx_suspend,
	.resume		= bcm7xxx_config_init,
	.driver		= { .owner = THIS_MODULE },
}, {
	.phy_id		= PHY_BCM_OUI_5,
	.phy_id_mask	= 0xffffff00,
	.name		= "Broadcom BCM7XXX 65nm",
	.features	= PHY_BASIC_FEATURES |
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
	.flags		= PHY_IS_INTERNAL,
	.config_init	= bcm7xxx_dummy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.suspend	= bcm7xxx_suspend,
	.resume		= bcm7xxx_config_init,
	.driver		= { .owner = THIS_MODULE },
} };

static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
	{ PHY_ID_BCM7250, 0xfffffff0, },
	{ PHY_ID_BCM7364, 0xfffffff0, },
	{ PHY_ID_BCM7366, 0xfffffff0, },
	{ PHY_ID_BCM7425, 0xfffffff0, },
	{ PHY_ID_BCM7429, 0xfffffff0, },
	{ PHY_ID_BCM7439, 0xfffffff0, },
	{ PHY_ID_BCM7445, 0xfffffff0, },
	{ PHY_BCM_OUI_4, 0xffff0000 },
	{ PHY_BCM_OUI_5, 0xffffff00 },
	{ }
};

module_phy_driver(bcm7xxx_driver);

MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);

MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Broadcom Corporation");
Commit	Line	Data
b560a58c FF	1	/*
	2	* Broadcom BCM7xxx internal transceivers support.
	3	*
	4	* Copyright (C) 2014, Broadcom Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/phy.h>
	14	#include <linux/delay.h>
	15	#include <linux/bitops.h>
	16	#include <linux/brcmphy.h>
b8f9a029	17	#include <linux/mdio.h>
b560a58c FF	18
	19	/* Broadcom BCM7xxx internal PHY registers */
	20	#define MII_BCM7XXX_CHANNEL_WIDTH 0x2000
	21
	22	/* 40nm only register definitions */
	23	#define MII_BCM7XXX_100TX_AUX_CTL 0x10
	24	#define MII_BCM7XXX_100TX_FALSE_CAR 0x13
	25	#define MII_BCM7XXX_100TX_DISC 0x14
	26	#define MII_BCM7XXX_AUX_MODE 0x1d
	27	#define MII_BCM7XX_64CLK_MDIO BIT(12)
	28	#define MII_BCM7XXX_CORE_BASE1E 0x1e
	29	#define MII_BCM7XXX_TEST 0x1f
	30	#define MII_BCM7XXX_SHD_MODE_2 BIT(2)
	31
a3622f2c FF	32	/* 28nm only register definitions */
	33	#define MISC_ADDR(base, channel) base, channel
	34
	35	#define DSP_TAP10 MISC_ADDR(0x0a, 0)
	36	#define PLL_PLLCTRL_1 MISC_ADDR(0x32, 1)
	37	#define PLL_PLLCTRL_2 MISC_ADDR(0x32, 2)
	38	#define PLL_PLLCTRL_4 MISC_ADDR(0x33, 0)
	39
	40	#define AFE_RXCONFIG_0 MISC_ADDR(0x38, 0)
	41	#define AFE_RXCONFIG_1 MISC_ADDR(0x38, 1)
	42	#define AFE_RX_LP_COUNTER MISC_ADDR(0x38, 3)
	43	#define AFE_TX_CONFIG MISC_ADDR(0x39, 0)
	44	#define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0)
	45
	46	#define CORE_EXPB0 0xb0
	47
b560a58c FF	48	static int bcm7445_config_init(struct phy_device *phydev)
	49	{
	50	int ret;
	51	const struct bcm7445_regs {
	52	int reg;
	53	u16 value;
	54	} bcm7445_regs_cfg[] = {
	55	/* increases ADC latency by 24ns */
	56	{ MII_BCM54XX_EXP_SEL, 0x0038 },
	57	{ MII_BCM54XX_EXP_DATA, 0xAB95 },
	58	/* increases internal 1V LDO voltage by 5% */
	59	{ MII_BCM54XX_EXP_SEL, 0x2038 },
	60	{ MII_BCM54XX_EXP_DATA, 0xBB22 },
	61	/* reduce RX low pass filter corner frequency */
	62	{ MII_BCM54XX_EXP_SEL, 0x6038 },
	63	{ MII_BCM54XX_EXP_DATA, 0xFFC5 },
	64	/* reduce RX high pass filter corner frequency */
	65	{ MII_BCM54XX_EXP_SEL, 0x003a },
	66	{ MII_BCM54XX_EXP_DATA, 0x2002 },
	67	};
	68	unsigned int i;
	69
	70	for (i = 0; i < ARRAY_SIZE(bcm7445_regs_cfg); i++) {
	71	ret = phy_write(phydev,
	72	bcm7445_regs_cfg[i].reg,
	73	bcm7445_regs_cfg[i].value);
	74	if (ret)
	75	return ret;
	76	}
	77
	78	return 0;
	79	}
	80
	81	static void phy_write_exp(struct phy_device *phydev,
	82	u16 reg, u16 value)
	83	{
	84	phy_write(phydev, MII_BCM54XX_EXP_SEL, MII_BCM54XX_EXP_SEL_ER \| reg);
	85	phy_write(phydev, MII_BCM54XX_EXP_DATA, value);
	86	}
	87
	88	static void phy_write_misc(struct phy_device *phydev,
	89	u16 reg, u16 chl, u16 value)
	90	{
	91	int tmp;
	92
	93	phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
	94
	95	tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
	96	tmp \|= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
	97	phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
	98
	99	tmp = (chl * MII_BCM7XXX_CHANNEL_WIDTH) \| reg;
	100	phy_write(phydev, MII_BCM54XX_EXP_SEL, tmp);
	101
	102	phy_write(phydev, MII_BCM54XX_EXP_DATA, value);
	103	}
	104
	105	static int bcm7xxx_28nm_afe_config_init(struct phy_device *phydev)
	106	{
b560a58c FF	107	/* Increase VCO range to prevent unlocking problem of PLL at low
	108	* temp
	109	*/
a3622f2c	110	phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);
b560a58c FF	111
b560a58c FF	112	/* Change Ki to 011 */
a3622f2c	113	phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);
b560a58c FF	114
	115	/* Disable loading of TVCO buffer to bandgap, set bandgap trim
	116	* to 111
	117	*/
a3622f2c	118	phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);
b560a58c FF	119
b560a58c FF	120	/* Adjust bias current trim by -3 */
a3622f2c	121	phy_write_misc(phydev, DSP_TAP10, 0x690b);
b560a58c FF	122
	123	/* Switch to CORE_BASE1E */
	124	phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0xd);
	125
	126	/* Reset R_CAL/RC_CAL Engine */
a3622f2c	127	phy_write_exp(phydev, CORE_EXPB0, 0x0010);
b560a58c FF	128
b560a58c FF	129	/* Disable Reset R_CAL/RC_CAL Engine */
a3622f2c	130	phy_write_exp(phydev, CORE_EXPB0, 0x0000);
b560a58c	131
9918542e FF	132	/* write AFE_RXCONFIG_0 */
	133	phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
	134
	135	/* write AFE_RXCONFIG_1 */
	136	phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);
	137
	138	/* write AFE_RX_LP_COUNTER */
a62ea5a7	139	phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
9918542e FF	140
	141	/* write AFE_HPF_TRIM_OTHERS */
	142	phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);
	143
	144	/* write AFTE_TX_CONFIG */
	145	phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);
	146
b560a58c FF	147	return 0;
	148	}
	149
9df54dda FF	150	static int bcm7xxx_apd_enable(struct phy_device *phydev)
	151	{
	152	int val;
	153
	154	/* Enable powering down of the DLL during auto-power down */
	155	val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_SCR3);
	156	if (val < 0)
	157	return val;
	158
	159	val \|= BCM54XX_SHD_SCR3_DLLAPD_DIS;
	160	bcm54xx_shadow_write(phydev, BCM54XX_SHD_SCR3, val);
	161
	162	/* Enable auto-power down */
	163	val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_APD);
	164	if (val < 0)
	165	return val;
	166
	167	val \|= BCM54XX_SHD_APD_EN;
	168	return bcm54xx_shadow_write(phydev, BCM54XX_SHD_APD, val);
	169	}
	170
b8f9a029 FF	171	static int bcm7xxx_eee_enable(struct phy_device *phydev)
	172	{
	173	int val;
	174
	175	val = phy_read_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
	176	MDIO_MMD_AN, phydev->addr);
	177	if (val < 0)
	178	return val;
	179
	180	/* Enable general EEE feature at the PHY level */
	181	val \|= LPI_FEATURE_EN \| LPI_FEATURE_EN_DIG1000X;
	182
	183	phy_write_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
	184	MDIO_MMD_AN, phydev->addr, val);
	185
	186	/* Advertise supported modes */
	187	val = phy_read_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
	188	MDIO_MMD_AN, phydev->addr);
	189
	190	val \|= (MDIO_AN_EEE_ADV_100TX \| MDIO_AN_EEE_ADV_1000T);
	191	phy_write_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
	192	MDIO_MMD_AN, phydev->addr, val);
	193
	194	return 0;
	195	}
	196
b560a58c FF	197	static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
b560a58c FF	198	{
d8ebfed3 FF	199	u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
	200	u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
	201	int ret = 0;
	202
6ec259c1 FF	203	pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
6ec259c1 FF	204	dev_name(&phydev->dev), phydev->drv->name, rev, patch);
d8ebfed3 FF	205
	206	switch (rev) {
	207	case 0xa0:
	208	case 0xb0:
	209	ret = bcm7445_config_init(phydev);
	210	break;
	211	default:
	212	ret = bcm7xxx_28nm_afe_config_init(phydev);
	213	break;
	214	}
b560a58c	215
9df54dda FF	216	if (ret)
	217	return ret;
	218
b8f9a029 FF	219	ret = bcm7xxx_eee_enable(phydev);
	220	if (ret)
	221	return ret;
	222
9df54dda	223	return bcm7xxx_apd_enable(phydev);
b560a58c FF	224	}
b560a58c FF	225
4fd14e0b FF	226	static int bcm7xxx_28nm_resume(struct phy_device *phydev)
	227	{
	228	int ret;
	229
	230	/* Re-apply workarounds coming out suspend/resume */
	231	ret = bcm7xxx_28nm_config_init(phydev);
	232	if (ret)
	233	return ret;
	234
	235	/* 28nm Gigabit PHYs come out of reset without any half-duplex
	236	* or "hub" compliant advertised mode, fix that. This does not
	237	* cause any problems with the PHY library since genphy_config_aneg()
	238	* gracefully handles auto-negotiated and forced modes.
	239	*/
	240	return genphy_config_aneg(phydev);
	241	}
	242
b560a58c FF	243	static int phy_set_clr_bits(struct phy_device *dev, int location,
	244	int set_mask, int clr_mask)
	245	{
	246	int v, ret;
	247
	248	v = phy_read(dev, location);
	249	if (v < 0)
	250	return v;
	251
	252	v &= ~clr_mask;
	253	v \|= set_mask;
	254
	255	ret = phy_write(dev, location, v);
	256	if (ret < 0)
	257	return ret;
	258
	259	return v;
	260	}
	261
	262	static int bcm7xxx_config_init(struct phy_device *phydev)
	263	{
	264	int ret;
	265
	266	/* Enable 64 clock MDIO */
	267	phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XX_64CLK_MDIO);
	268	phy_read(phydev, MII_BCM7XXX_AUX_MODE);
	269
e18556ee FF	270	/* Workaround only required for 100Mbits/sec capable PHYs */
e18556ee FF	271	if (phydev->supported & PHY_GBIT_FEATURES)
b560a58c FF	272	return 0;
	273
	274	/* set shadow mode 2 */
	275	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
	276	MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
	277	if (ret < 0)
	278	return ret;
	279
	280	/* set iddq_clkbias */
	281	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
	282	udelay(10);
	283
	284	/* reset iddq_clkbias */
	285	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);
	286
	287	phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);
	288
	289	/* reset shadow mode 2 */
	290	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, MII_BCM7XXX_SHD_MODE_2, 0);
	291	if (ret < 0)
	292	return ret;
	293
	294	return 0;
	295	}
	296
	297	/* Workaround for putting the PHY in IDDQ mode, required
82c084f5	298	* for all BCM7XXX 40nm and 65nm PHYs
b560a58c FF	299	*/
	300	static int bcm7xxx_suspend(struct phy_device *phydev)
	301	{
	302	int ret;
	303	const struct bcm7xxx_regs {
	304	int reg;
	305	u16 value;
	306	} bcm7xxx_suspend_cfg[] = {
	307	{ MII_BCM7XXX_TEST, 0x008b },
	308	{ MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
	309	{ MII_BCM7XXX_100TX_DISC, 0x7000 },
	310	{ MII_BCM7XXX_TEST, 0x000f },
	311	{ MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
	312	{ MII_BCM7XXX_TEST, 0x000b },
	313	};
	314	unsigned int i;
	315
	316	for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
	317	ret = phy_write(phydev,
	318	bcm7xxx_suspend_cfg[i].reg,
	319	bcm7xxx_suspend_cfg[i].value);
	320	if (ret)
	321	return ret;
	322	}
	323
	324	return 0;
	325	}
	326
	327	static int bcm7xxx_dummy_config_init(struct phy_device *phydev)
	328	{
	329	return 0;
	330	}
	331
153df3c7 FF	332	#define BCM7XXX_28NM_GPHY(_oui, _name) \
	333	{ \
	334	.phy_id = (_oui), \
	335	.phy_id_mask = 0xfffffff0, \
	336	.name = _name, \
	337	.features = PHY_GBIT_FEATURES \| \
	338	SUPPORTED_Pause \| SUPPORTED_Asym_Pause, \
	339	.flags = PHY_IS_INTERNAL, \
	340	.config_init = bcm7xxx_28nm_afe_config_init, \
	341	.config_aneg = genphy_config_aneg, \
	342	.read_status = genphy_read_status, \
	343	.resume = bcm7xxx_28nm_resume, \
	344	.driver = { .owner = THIS_MODULE }, \
	345	}
	346
b560a58c	347	static struct phy_driver bcm7xxx_driver[] = {
430ad68f FF	348	BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
430ad68f FF	349	BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
153df3c7 FF	350	BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
	351	BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
	352	BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
b560a58c	353	{
d068b02c PG	354	.phy_id = PHY_ID_BCM7425,
	355	.phy_id_mask = 0xfffffff0,
	356	.name = "Broadcom BCM7425",
	357	.features = PHY_GBIT_FEATURES \|
	358	SUPPORTED_Pause \| SUPPORTED_Asym_Pause,
	359	.flags = 0,
	360	.config_init = bcm7xxx_config_init,
	361	.config_aneg = genphy_config_aneg,
	362	.read_status = genphy_read_status,
	363	.suspend = bcm7xxx_suspend,
	364	.resume = bcm7xxx_config_init,
	365	.driver = { .owner = THIS_MODULE },
	366	}, {
	367	.phy_id = PHY_ID_BCM7429,
	368	.phy_id_mask = 0xfffffff0,
	369	.name = "Broadcom BCM7429",
	370	.features = PHY_GBIT_FEATURES \|
	371	SUPPORTED_Pause \| SUPPORTED_Asym_Pause,
	372	.flags = PHY_IS_INTERNAL,
	373	.config_init = bcm7xxx_config_init,
	374	.config_aneg = genphy_config_aneg,
	375	.read_status = genphy_read_status,
	376	.suspend = bcm7xxx_suspend,
	377	.resume = bcm7xxx_config_init,
	378	.driver = { .owner = THIS_MODULE },
	379	}, {
b560a58c FF	380	.phy_id = PHY_BCM_OUI_4,
	381	.phy_id_mask = 0xffff0000,
	382	.name = "Broadcom BCM7XXX 40nm",
	383	.features = PHY_GBIT_FEATURES \|
	384	SUPPORTED_Pause \| SUPPORTED_Asym_Pause,
	385	.flags = PHY_IS_INTERNAL,
	386	.config_init = bcm7xxx_config_init,
	387	.config_aneg = genphy_config_aneg,
	388	.read_status = genphy_read_status,
	389	.suspend = bcm7xxx_suspend,
	390	.resume = bcm7xxx_config_init,
	391	.driver = { .owner = THIS_MODULE },
	392	}, {
	393	.phy_id = PHY_BCM_OUI_5,
	394	.phy_id_mask = 0xffffff00,
	395	.name = "Broadcom BCM7XXX 65nm",
	396	.features = PHY_BASIC_FEATURES \|
	397	SUPPORTED_Pause \| SUPPORTED_Asym_Pause,
	398	.flags = PHY_IS_INTERNAL,
	399	.config_init = bcm7xxx_dummy_config_init,
	400	.config_aneg = genphy_config_aneg,
	401	.read_status = genphy_read_status,
	402	.suspend = bcm7xxx_suspend,
	403	.resume = bcm7xxx_config_init,
	404	.driver = { .owner = THIS_MODULE },
	405	} };
	406
	407	static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
430ad68f FF	408	{ PHY_ID_BCM7250, 0xfffffff0, },
430ad68f FF	409	{ PHY_ID_BCM7364, 0xfffffff0, },
b560a58c	410	{ PHY_ID_BCM7366, 0xfffffff0, },
d068b02c PG	411	{ PHY_ID_BCM7425, 0xfffffff0, },
d068b02c PG	412	{ PHY_ID_BCM7429, 0xfffffff0, },
b560a58c FF	413	{ PHY_ID_BCM7439, 0xfffffff0, },
b560a58c FF	414	{ PHY_ID_BCM7445, 0xfffffff0, },
b560a58c FF	415	{ PHY_BCM_OUI_4, 0xffff0000 },
	416	{ PHY_BCM_OUI_5, 0xffffff00 },
	417	{ }
	418	};
	419
50fd7150	420	module_phy_driver(bcm7xxx_driver);
b560a58c FF	421
	422	MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);
	423
	424	MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
	425	MODULE_LICENSE("GPL");
	426	MODULE_AUTHOR("Broadcom Corporation");