[deliverable/linux.git] / drivers / net / phy / bcm7xxx.c

/*
 * Broadcom BCM7xxx internal transceivers support.
 *
 * Copyright (C) 2014, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/phy.h>
#include <linux/delay.h>
#include "bcm-phy-lib.h"
#include <linux/bitops.h>
#include <linux/brcmphy.h>
#include <linux/mdio.h>

/* Broadcom BCM7xxx internal PHY registers */

/* 40nm only register definitions */
#define MII_BCM7XXX_100TX_AUX_CTL	0x10
#define MII_BCM7XXX_100TX_FALSE_CAR	0x13
#define MII_BCM7XXX_100TX_DISC		0x14
#define MII_BCM7XXX_AUX_MODE		0x1d
#define  MII_BCM7XX_64CLK_MDIO		BIT(12)
#define MII_BCM7XXX_TEST		0x1f
#define  MII_BCM7XXX_SHD_MODE_2		BIT(2)

/* 28nm only register definitions */
#define MISC_ADDR(base, channel)	base, channel

#define DSP_TAP10			MISC_ADDR(0x0a, 0)
#define PLL_PLLCTRL_1			MISC_ADDR(0x32, 1)
#define PLL_PLLCTRL_2			MISC_ADDR(0x32, 2)
#define PLL_PLLCTRL_4			MISC_ADDR(0x33, 0)

#define AFE_RXCONFIG_0			MISC_ADDR(0x38, 0)
#define AFE_RXCONFIG_1			MISC_ADDR(0x38, 1)
#define AFE_RXCONFIG_2			MISC_ADDR(0x38, 2)
#define AFE_RX_LP_COUNTER		MISC_ADDR(0x38, 3)
#define AFE_TX_CONFIG			MISC_ADDR(0x39, 0)
#define AFE_VDCA_ICTRL_0		MISC_ADDR(0x39, 1)
#define AFE_VDAC_OTHERS_0		MISC_ADDR(0x39, 3)
#define AFE_HPF_TRIM_OTHERS		MISC_ADDR(0x3a, 0)

static void r_rc_cal_reset(struct phy_device *phydev)
{
	/* Reset R_CAL/RC_CAL Engine */
	bcm_phy_write_exp(phydev, 0x00b0, 0x0010);

	/* Disable Reset R_AL/RC_CAL Engine */
	bcm_phy_write_exp(phydev, 0x00b0, 0x0000);
}

static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)
{
	/* Increase VCO range to prevent unlocking problem of PLL at low
	 * temp
	 */
	bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);

	/* Change Ki to 011 */
	bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);

	/* Disable loading of TVCO buffer to bandgap, set bandgap trim
	 * to 111
	 */
	bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);

	/* Adjust bias current trim by -3 */
	bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b);

	/* Switch to CORE_BASE1E */
	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd);

	r_rc_cal_reset(phydev);

	/* write AFE_RXCONFIG_0 */
	bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);

	/* write AFE_RXCONFIG_1 */
	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);

	/* write AFE_RX_LP_COUNTER */
	bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);

	/* write AFE_HPF_TRIM_OTHERS */
	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);

	/* write AFTE_TX_CONFIG */
	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);

	return 0;
}

static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
{
	/* AFE_RXCONFIG_0 */
	bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);

	/* AFE_RXCONFIG_1 */
	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);

	/* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */
	bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);

	/* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */
	bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);

	/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);

	/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
	bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);

	/* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */
	bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);

	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
	 * offset for HT=0 code
	 */
	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);

	/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);

	/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
	bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);

	/* Reset R_CAL/RC_CAL engine */
	r_rc_cal_reset(phydev);

	return 0;
}

static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
{
	/* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement */
	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);

	/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);

	/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
	bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);

	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
	 * offset for HT=0 code
	 */
	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);

	/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);

	/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
	bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);

	/* Reset R_CAL/RC_CAL engine */
	r_rc_cal_reset(phydev);

	return 0;
}

static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
{
	u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
	u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
	int ret = 0;

	pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
		     dev_name(&phydev->dev), phydev->drv->name, rev, patch);

	/* Dummy read to a register to workaround an issue upon reset where the
	 * internal inverter may not allow the first MDIO transaction to pass
	 * the MDIO management controller and make us return 0xffff for such
	 * reads.
	 */
	phy_read(phydev, MII_BMSR);

	switch (rev) {
	case 0xb0:
		ret = bcm7xxx_28nm_b0_afe_config_init(phydev);
		break;
	case 0xd0:
		ret = bcm7xxx_28nm_d0_afe_config_init(phydev);
		break;
	case 0xe0:
	case 0xf0:
	/* Rev G0 introduces a roll over */
	case 0x10:
		ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
		break;
	default:
		break;
	}

	if (ret)
		return ret;

	ret = bcm_phy_enable_eee(phydev);
	if (ret)
		return ret;

	return bcm_phy_enable_apd(phydev, true);
}

static int bcm7xxx_28nm_resume(struct phy_device *phydev)
{
	int ret;

	/* Re-apply workarounds coming out suspend/resume */
	ret = bcm7xxx_28nm_config_init(phydev);
	if (ret)
		return ret;

	/* 28nm Gigabit PHYs come out of reset without any half-duplex
	 * or "hub" compliant advertised mode, fix that. This does not
	 * cause any problems with the PHY library since genphy_config_aneg()
	 * gracefully handles auto-negotiated and forced modes.
	 */
	return genphy_config_aneg(phydev);
}

static int phy_set_clr_bits(struct phy_device *dev, int location,
					int set_mask, int clr_mask)
{
	int v, ret;

	v = phy_read(dev, location);
	if (v < 0)
		return v;

	v &= ~clr_mask;
	v |= set_mask;

	ret = phy_write(dev, location, v);
	if (ret < 0)
		return ret;

	return v;
}

static int bcm7xxx_config_init(struct phy_device *phydev)
{
	int ret;

	/* Enable 64 clock MDIO */
	phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XX_64CLK_MDIO);
	phy_read(phydev, MII_BCM7XXX_AUX_MODE);

	/* Workaround only required for 100Mbits/sec capable PHYs */
	if (phydev->supported & PHY_GBIT_FEATURES)
		return 0;

	/* set shadow mode 2 */
	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
			MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
	if (ret < 0)
		return ret;

	/* set iddq_clkbias */
	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
	udelay(10);

	/* reset iddq_clkbias */
	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);

	phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);

	/* reset shadow mode 2 */
	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, MII_BCM7XXX_SHD_MODE_2, 0);
	if (ret < 0)
		return ret;

	return 0;
}

/* Workaround for putting the PHY in IDDQ mode, required
 * for all BCM7XXX 40nm and 65nm PHYs
 */
static int bcm7xxx_suspend(struct phy_device *phydev)
{
	int ret;
	const struct bcm7xxx_regs {
		int reg;
		u16 value;
	} bcm7xxx_suspend_cfg[] = {
		{ MII_BCM7XXX_TEST, 0x008b },
		{ MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
		{ MII_BCM7XXX_100TX_DISC, 0x7000 },
		{ MII_BCM7XXX_TEST, 0x000f },
		{ MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
		{ MII_BCM7XXX_TEST, 0x000b },
	};
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
		ret = phy_write(phydev,
				bcm7xxx_suspend_cfg[i].reg,
				bcm7xxx_suspend_cfg[i].value);
		if (ret)
			return ret;
	}

	return 0;
}

static int bcm7xxx_dummy_config_init(struct phy_device *phydev)
{
	return 0;
}

#define BCM7XXX_28NM_GPHY(_oui, _name)					\
{									\
	.phy_id		= (_oui),					\
	.phy_id_mask	= 0xfffffff0,					\
	.name		= _name,					\
	.features	= PHY_GBIT_FEATURES |				\
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,	\
	.flags		= PHY_IS_INTERNAL,				\
	.config_init	= bcm7xxx_28nm_config_init,			\
	.config_aneg	= genphy_config_aneg,				\
	.read_status	= genphy_read_status,				\
	.resume		= bcm7xxx_28nm_resume,				\
	.driver		= { .owner = THIS_MODULE },			\
}

static struct phy_driver bcm7xxx_driver[] = {
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
{
	.phy_id         = PHY_ID_BCM7425,
	.phy_id_mask    = 0xfffffff0,
	.name           = "Broadcom BCM7425",
	.features       = PHY_GBIT_FEATURES |
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
	.flags          = PHY_IS_INTERNAL,
	.config_init    = bcm7xxx_config_init,
	.config_aneg    = genphy_config_aneg,
	.read_status    = genphy_read_status,
	.suspend        = bcm7xxx_suspend,
	.resume         = bcm7xxx_config_init,
	.driver         = { .owner = THIS_MODULE },
}, {
	.phy_id         = PHY_ID_BCM7429,
	.phy_id_mask    = 0xfffffff0,
	.name           = "Broadcom BCM7429",
	.features       = PHY_GBIT_FEATURES |
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
	.flags          = PHY_IS_INTERNAL,
	.config_init    = bcm7xxx_config_init,
	.config_aneg    = genphy_config_aneg,
	.read_status    = genphy_read_status,
	.suspend        = bcm7xxx_suspend,
	.resume         = bcm7xxx_config_init,
	.driver         = { .owner = THIS_MODULE },
}, {
	.phy_id         = PHY_ID_BCM7435,
	.phy_id_mask    = 0xfffffff0,
	.name           = "Broadcom BCM7435",
	.features       = PHY_GBIT_FEATURES |
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
	.flags          = PHY_IS_INTERNAL,
	.config_init    = bcm7xxx_config_init,
	.config_aneg    = genphy_config_aneg,
	.read_status    = genphy_read_status,
	.suspend        = bcm7xxx_suspend,
	.resume         = bcm7xxx_config_init,
	.driver         = { .owner = THIS_MODULE },
}, {
	.phy_id		= PHY_BCM_OUI_4,
	.phy_id_mask	= 0xffff0000,
	.name		= "Broadcom BCM7XXX 40nm",
	.features	= PHY_GBIT_FEATURES |
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
	.flags		= PHY_IS_INTERNAL,
	.config_init	= bcm7xxx_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.suspend	= bcm7xxx_suspend,
	.resume		= bcm7xxx_config_init,
	.driver		= { .owner = THIS_MODULE },
}, {
	.phy_id		= PHY_BCM_OUI_5,
	.phy_id_mask	= 0xffffff00,
	.name		= "Broadcom BCM7XXX 65nm",
	.features	= PHY_BASIC_FEATURES |
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
	.flags		= PHY_IS_INTERNAL,
	.config_init	= bcm7xxx_dummy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.suspend	= bcm7xxx_suspend,
	.resume		= bcm7xxx_config_init,
	.driver		= { .owner = THIS_MODULE },
} };

static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
	{ PHY_ID_BCM7250, 0xfffffff0, },
	{ PHY_ID_BCM7364, 0xfffffff0, },
	{ PHY_ID_BCM7366, 0xfffffff0, },
	{ PHY_ID_BCM7425, 0xfffffff0, },
	{ PHY_ID_BCM7429, 0xfffffff0, },
	{ PHY_ID_BCM7439, 0xfffffff0, },
	{ PHY_ID_BCM7435, 0xfffffff0, },
	{ PHY_ID_BCM7445, 0xfffffff0, },
	{ PHY_BCM_OUI_4, 0xffff0000 },
	{ PHY_BCM_OUI_5, 0xffffff00 },
	{ }
};

module_phy_driver(bcm7xxx_driver);

MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);

MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Broadcom Corporation");
Commit	Line	Data
b560a58c FF	1	/*
	2	* Broadcom BCM7xxx internal transceivers support.
	3	*
	4	* Copyright (C) 2014, Broadcom Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/phy.h>
	14	#include <linux/delay.h>
a1cba561	15	#include "bcm-phy-lib.h"
b560a58c FF	16	#include <linux/bitops.h>
b560a58c FF	17	#include <linux/brcmphy.h>
b8f9a029	18	#include <linux/mdio.h>
b560a58c FF	19
b560a58c FF	20	/* Broadcom BCM7xxx internal PHY registers */
b560a58c FF	21
	22	/* 40nm only register definitions */
	23	#define MII_BCM7XXX_100TX_AUX_CTL 0x10
	24	#define MII_BCM7XXX_100TX_FALSE_CAR 0x13
	25	#define MII_BCM7XXX_100TX_DISC 0x14
	26	#define MII_BCM7XXX_AUX_MODE 0x1d
	27	#define MII_BCM7XX_64CLK_MDIO BIT(12)
b560a58c FF	28	#define MII_BCM7XXX_TEST 0x1f
	29	#define MII_BCM7XXX_SHD_MODE_2 BIT(2)
	30
a3622f2c FF	31	/* 28nm only register definitions */
	32	#define MISC_ADDR(base, channel) base, channel
	33
	34	#define DSP_TAP10 MISC_ADDR(0x0a, 0)
	35	#define PLL_PLLCTRL_1 MISC_ADDR(0x32, 1)
	36	#define PLL_PLLCTRL_2 MISC_ADDR(0x32, 2)
	37	#define PLL_PLLCTRL_4 MISC_ADDR(0x33, 0)
	38
	39	#define AFE_RXCONFIG_0 MISC_ADDR(0x38, 0)
	40	#define AFE_RXCONFIG_1 MISC_ADDR(0x38, 1)
a490631f	41	#define AFE_RXCONFIG_2 MISC_ADDR(0x38, 2)
a3622f2c FF	42	#define AFE_RX_LP_COUNTER MISC_ADDR(0x38, 3)
a3622f2c FF	43	#define AFE_TX_CONFIG MISC_ADDR(0x39, 0)
a490631f FF	44	#define AFE_VDCA_ICTRL_0 MISC_ADDR(0x39, 1)
a490631f FF	45	#define AFE_VDAC_OTHERS_0 MISC_ADDR(0x39, 3)
a3622f2c FF	46	#define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0)
a3622f2c FF	47
9c41f2ba FF	48	static void r_rc_cal_reset(struct phy_device *phydev)
	49	{
	50	/* Reset R_CAL/RC_CAL Engine */
a1cba561	51	bcm_phy_write_exp(phydev, 0x00b0, 0x0010);
9c41f2ba FF	52
9c41f2ba FF	53	/* Disable Reset R_AL/RC_CAL Engine */
a1cba561	54	bcm_phy_write_exp(phydev, 0x00b0, 0x0000);
9c41f2ba FF	55	}
9c41f2ba FF	56
2a9df742	57	static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)
b560a58c	58	{
b560a58c FF	59	/* Increase VCO range to prevent unlocking problem of PLL at low
	60	* temp
	61	*/
a1cba561	62	bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);
b560a58c FF	63
b560a58c FF	64	/* Change Ki to 011 */
a1cba561	65	bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);
b560a58c FF	66
	67	/* Disable loading of TVCO buffer to bandgap, set bandgap trim
	68	* to 111
	69	*/
a1cba561	70	bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);
b560a58c FF	71
b560a58c FF	72	/* Adjust bias current trim by -3 */
a1cba561	73	bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b);
b560a58c FF	74
b560a58c FF	75	/* Switch to CORE_BASE1E */
9200c27a	76	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd);
b560a58c	77
9c41f2ba	78	r_rc_cal_reset(phydev);
b560a58c	79
9918542e	80	/* write AFE_RXCONFIG_0 */
a1cba561	81	bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
9918542e FF	82
9918542e FF	83	/* write AFE_RXCONFIG_1 */
a1cba561	84	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);
9918542e FF	85
9918542e FF	86	/* write AFE_RX_LP_COUNTER */
a1cba561	87	bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
9918542e FF	88
9918542e FF	89	/* write AFE_HPF_TRIM_OTHERS */
a1cba561	90	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);
9918542e FF	91
9918542e FF	92	/* write AFTE_TX_CONFIG */
a1cba561	93	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);
9918542e	94
b560a58c FF	95	return 0;
	96	}
	97
a490631f FF	98	static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
	99	{
	100	/* AFE_RXCONFIG_0 */
a1cba561	101	bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);
a490631f FF	102
a490631f FF	103	/* AFE_RXCONFIG_1 */
a1cba561	104	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
a490631f FF	105
a490631f FF	106	/* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */
a1cba561	107	bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);
a490631f FF	108
a490631f FF	109	/* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */
a1cba561	110	bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
a490631f	111
6da8253b	112	/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
a1cba561	113	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
a490631f FF	114
a490631f FF	115	/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
a1cba561	116	bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
a490631f FF	117
a490631f FF	118	/* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */
a1cba561	119	bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);
a490631f FF	120
	121	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
	122	* offset for HT=0 code
	123	*/
a1cba561	124	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
a490631f FF	125
a490631f FF	126	/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
9200c27a	127	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
a490631f FF	128
a490631f FF	129	/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
a1cba561	130	bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
a490631f FF	131
	132	/* Reset R_CAL/RC_CAL engine */
	133	r_rc_cal_reset(phydev);
	134
	135	return 0;
	136	}
	137
0c2fdc25 FF	138	static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
	139	{
	140	/* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement */
a1cba561	141	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
0c2fdc25	142
6da8253b	143	/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
a1cba561	144	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
6da8253b	145
0c2fdc25	146	/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
a1cba561	147	bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
0c2fdc25 FF	148
	149	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
	150	* offset for HT=0 code
	151	*/
a1cba561	152	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
0c2fdc25 FF	153
0c2fdc25 FF	154	/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
9200c27a	155	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
0c2fdc25 FF	156
0c2fdc25 FF	157	/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
a1cba561	158	bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
0c2fdc25 FF	159
	160	/* Reset R_CAL/RC_CAL engine */
	161	r_rc_cal_reset(phydev);
	162
	163	return 0;
	164	}
	165
b560a58c FF	166	static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
b560a58c FF	167	{
d8ebfed3 FF	168	u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
	169	u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
	170	int ret = 0;
	171
6ec259c1 FF	172	pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
6ec259c1 FF	173	dev_name(&phydev->dev), phydev->drv->name, rev, patch);
d8ebfed3	174
8e346e15 FF	175	/* Dummy read to a register to workaround an issue upon reset where the
	176	* internal inverter may not allow the first MDIO transaction to pass
	177	* the MDIO management controller and make us return 0xffff for such
	178	* reads.
	179	*/
	180	phy_read(phydev, MII_BMSR);
	181
d8ebfed3	182	switch (rev) {
d8ebfed3	183	case 0xb0:
2a9df742	184	ret = bcm7xxx_28nm_b0_afe_config_init(phydev);
d8ebfed3	185	break;
a490631f FF	186	case 0xd0:
	187	ret = bcm7xxx_28nm_d0_afe_config_init(phydev);
	188	break;
0c2fdc25 FF	189	case 0xe0:
0c2fdc25 FF	190	case 0xf0:
60efff0c FF	191	/* Rev G0 introduces a roll over */
60efff0c FF	192	case 0x10:
0c2fdc25 FF	193	ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
0c2fdc25 FF	194	break;
d8ebfed3	195	default:
d8ebfed3 FF	196	break;
d8ebfed3 FF	197	}
b560a58c	198
9df54dda FF	199	if (ret)
	200	return ret;
	201
a1cba561	202	ret = bcm_phy_enable_eee(phydev);
b8f9a029 FF	203	if (ret)
	204	return ret;
	205
a1cba561	206	return bcm_phy_enable_apd(phydev, true);
b560a58c FF	207	}
b560a58c FF	208
4fd14e0b FF	209	static int bcm7xxx_28nm_resume(struct phy_device *phydev)
	210	{
	211	int ret;
	212
	213	/* Re-apply workarounds coming out suspend/resume */
	214	ret = bcm7xxx_28nm_config_init(phydev);
	215	if (ret)
	216	return ret;
	217
	218	/* 28nm Gigabit PHYs come out of reset without any half-duplex
	219	* or "hub" compliant advertised mode, fix that. This does not
	220	* cause any problems with the PHY library since genphy_config_aneg()
	221	* gracefully handles auto-negotiated and forced modes.
	222	*/
	223	return genphy_config_aneg(phydev);
	224	}
	225
b560a58c FF	226	static int phy_set_clr_bits(struct phy_device *dev, int location,
	227	int set_mask, int clr_mask)
	228	{
	229	int v, ret;
	230
	231	v = phy_read(dev, location);
	232	if (v < 0)
	233	return v;
	234
	235	v &= ~clr_mask;
	236	v \|= set_mask;
	237
	238	ret = phy_write(dev, location, v);
	239	if (ret < 0)
	240	return ret;
	241
	242	return v;
	243	}
	244
	245	static int bcm7xxx_config_init(struct phy_device *phydev)
	246	{
	247	int ret;
	248
	249	/* Enable 64 clock MDIO */
	250	phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XX_64CLK_MDIO);
	251	phy_read(phydev, MII_BCM7XXX_AUX_MODE);
	252
e18556ee FF	253	/* Workaround only required for 100Mbits/sec capable PHYs */
e18556ee FF	254	if (phydev->supported & PHY_GBIT_FEATURES)
b560a58c FF	255	return 0;
	256
	257	/* set shadow mode 2 */
	258	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
	259	MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
	260	if (ret < 0)
	261	return ret;
	262
	263	/* set iddq_clkbias */
	264	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
	265	udelay(10);
	266
	267	/* reset iddq_clkbias */
	268	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);
	269
	270	phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);
	271
	272	/* reset shadow mode 2 */
	273	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, MII_BCM7XXX_SHD_MODE_2, 0);
	274	if (ret < 0)
	275	return ret;
	276
	277	return 0;
	278	}
	279
	280	/* Workaround for putting the PHY in IDDQ mode, required
82c084f5	281	* for all BCM7XXX 40nm and 65nm PHYs
b560a58c FF	282	*/
	283	static int bcm7xxx_suspend(struct phy_device *phydev)
	284	{
	285	int ret;
	286	const struct bcm7xxx_regs {
	287	int reg;
	288	u16 value;
	289	} bcm7xxx_suspend_cfg[] = {
	290	{ MII_BCM7XXX_TEST, 0x008b },
	291	{ MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
	292	{ MII_BCM7XXX_100TX_DISC, 0x7000 },
	293	{ MII_BCM7XXX_TEST, 0x000f },
	294	{ MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
	295	{ MII_BCM7XXX_TEST, 0x000b },
	296	};
	297	unsigned int i;
	298
	299	for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
	300	ret = phy_write(phydev,
	301	bcm7xxx_suspend_cfg[i].reg,
	302	bcm7xxx_suspend_cfg[i].value);
	303	if (ret)
	304	return ret;
	305	}
	306
	307	return 0;
	308	}
	309
	310	static int bcm7xxx_dummy_config_init(struct phy_device *phydev)
	311	{
	312	return 0;
	313	}
	314
153df3c7 FF	315	#define BCM7XXX_28NM_GPHY(_oui, _name) \
	316	{ \
	317	.phy_id = (_oui), \
	318	.phy_id_mask = 0xfffffff0, \
	319	.name = _name, \
	320	.features = PHY_GBIT_FEATURES \| \
	321	SUPPORTED_Pause \| SUPPORTED_Asym_Pause, \
	322	.flags = PHY_IS_INTERNAL, \
2a9df742	323	.config_init = bcm7xxx_28nm_config_init, \
153df3c7 FF	324	.config_aneg = genphy_config_aneg, \
	325	.read_status = genphy_read_status, \
	326	.resume = bcm7xxx_28nm_resume, \
	327	.driver = { .owner = THIS_MODULE }, \
	328	}
	329
b560a58c	330	static struct phy_driver bcm7xxx_driver[] = {
430ad68f FF	331	BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
430ad68f FF	332	BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
153df3c7 FF	333	BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
153df3c7 FF	334	BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
59e33c2b	335	BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"),
153df3c7	336	BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
b560a58c	337	{
d068b02c PG	338	.phy_id = PHY_ID_BCM7425,
	339	.phy_id_mask = 0xfffffff0,
	340	.name = "Broadcom BCM7425",
	341	.features = PHY_GBIT_FEATURES \|
	342	SUPPORTED_Pause \| SUPPORTED_Asym_Pause,
cc4a84c3	343	.flags = PHY_IS_INTERNAL,
d068b02c PG	344	.config_init = bcm7xxx_config_init,
	345	.config_aneg = genphy_config_aneg,
	346	.read_status = genphy_read_status,
	347	.suspend = bcm7xxx_suspend,
	348	.resume = bcm7xxx_config_init,
	349	.driver = { .owner = THIS_MODULE },
	350	}, {
	351	.phy_id = PHY_ID_BCM7429,
	352	.phy_id_mask = 0xfffffff0,
	353	.name = "Broadcom BCM7429",
	354	.features = PHY_GBIT_FEATURES \|
	355	SUPPORTED_Pause \| SUPPORTED_Asym_Pause,
	356	.flags = PHY_IS_INTERNAL,
	357	.config_init = bcm7xxx_config_init,
	358	.config_aneg = genphy_config_aneg,
	359	.read_status = genphy_read_status,
	360	.suspend = bcm7xxx_suspend,
	361	.resume = bcm7xxx_config_init,
	362	.driver = { .owner = THIS_MODULE },
9458ceab FF	363	}, {
	364	.phy_id = PHY_ID_BCM7435,
	365	.phy_id_mask = 0xfffffff0,
	366	.name = "Broadcom BCM7435",
	367	.features = PHY_GBIT_FEATURES \|
	368	SUPPORTED_Pause \| SUPPORTED_Asym_Pause,
	369	.flags = PHY_IS_INTERNAL,
	370	.config_init = bcm7xxx_config_init,
	371	.config_aneg = genphy_config_aneg,
	372	.read_status = genphy_read_status,
	373	.suspend = bcm7xxx_suspend,
	374	.resume = bcm7xxx_config_init,
	375	.driver = { .owner = THIS_MODULE },
d068b02c	376	}, {
b560a58c FF	377	.phy_id = PHY_BCM_OUI_4,
	378	.phy_id_mask = 0xffff0000,
	379	.name = "Broadcom BCM7XXX 40nm",
	380	.features = PHY_GBIT_FEATURES \|
	381	SUPPORTED_Pause \| SUPPORTED_Asym_Pause,
	382	.flags = PHY_IS_INTERNAL,
	383	.config_init = bcm7xxx_config_init,
	384	.config_aneg = genphy_config_aneg,
	385	.read_status = genphy_read_status,
	386	.suspend = bcm7xxx_suspend,
	387	.resume = bcm7xxx_config_init,
	388	.driver = { .owner = THIS_MODULE },
	389	}, {
	390	.phy_id = PHY_BCM_OUI_5,
	391	.phy_id_mask = 0xffffff00,
	392	.name = "Broadcom BCM7XXX 65nm",
	393	.features = PHY_BASIC_FEATURES \|
	394	SUPPORTED_Pause \| SUPPORTED_Asym_Pause,
	395	.flags = PHY_IS_INTERNAL,
	396	.config_init = bcm7xxx_dummy_config_init,
	397	.config_aneg = genphy_config_aneg,
	398	.read_status = genphy_read_status,
	399	.suspend = bcm7xxx_suspend,
	400	.resume = bcm7xxx_config_init,
	401	.driver = { .owner = THIS_MODULE },
	402	} };
	403
	404	static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
430ad68f FF	405	{ PHY_ID_BCM7250, 0xfffffff0, },
430ad68f FF	406	{ PHY_ID_BCM7364, 0xfffffff0, },
b560a58c	407	{ PHY_ID_BCM7366, 0xfffffff0, },
d068b02c PG	408	{ PHY_ID_BCM7425, 0xfffffff0, },
d068b02c PG	409	{ PHY_ID_BCM7429, 0xfffffff0, },
b560a58c	410	{ PHY_ID_BCM7439, 0xfffffff0, },
9458ceab	411	{ PHY_ID_BCM7435, 0xfffffff0, },
b560a58c	412	{ PHY_ID_BCM7445, 0xfffffff0, },
b560a58c FF	413	{ PHY_BCM_OUI_4, 0xffff0000 },
	414	{ PHY_BCM_OUI_5, 0xffffff00 },
	415	{ }
	416	};
	417
50fd7150	418	module_phy_driver(bcm7xxx_driver);
b560a58c FF	419
	420	MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);
	421
	422	MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
	423	MODULE_LICENSE("GPL");
	424	MODULE_AUTHOR("Broadcom Corporation");