[deliverable/linux.git] / drivers / net / phy / bcm7xxx.c

/*
 * Broadcom BCM7xxx internal transceivers support.
 *
 * Copyright (C) 2014, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/phy.h>
#include <linux/delay.h>
#include <linux/bitops.h>
#include <linux/brcmphy.h>
#include <linux/mdio.h>

/* Broadcom BCM7xxx internal PHY registers */
#define MII_BCM7XXX_CHANNEL_WIDTH	0x2000

/* 40nm only register definitions */
#define MII_BCM7XXX_100TX_AUX_CTL	0x10
#define MII_BCM7XXX_100TX_FALSE_CAR	0x13
#define MII_BCM7XXX_100TX_DISC		0x14
#define MII_BCM7XXX_AUX_MODE		0x1d
#define  MII_BCM7XX_64CLK_MDIO		BIT(12)
#define MII_BCM7XXX_CORE_BASE1E		0x1e
#define MII_BCM7XXX_TEST		0x1f
#define  MII_BCM7XXX_SHD_MODE_2		BIT(2)

/* 28nm only register definitions */
#define MISC_ADDR(base, channel)	base, channel

#define DSP_TAP10			MISC_ADDR(0x0a, 0)
#define PLL_PLLCTRL_1			MISC_ADDR(0x32, 1)
#define PLL_PLLCTRL_2			MISC_ADDR(0x32, 2)
#define PLL_PLLCTRL_4			MISC_ADDR(0x33, 0)

#define AFE_RXCONFIG_0			MISC_ADDR(0x38, 0)
#define AFE_RXCONFIG_1			MISC_ADDR(0x38, 1)
#define AFE_RXCONFIG_2			MISC_ADDR(0x38, 2)
#define AFE_RX_LP_COUNTER		MISC_ADDR(0x38, 3)
#define AFE_TX_CONFIG			MISC_ADDR(0x39, 0)
#define AFE_VDCA_ICTRL_0		MISC_ADDR(0x39, 1)
#define AFE_VDAC_OTHERS_0		MISC_ADDR(0x39, 3)
#define AFE_HPF_TRIM_OTHERS		MISC_ADDR(0x3a, 0)

#define CORE_EXPB0			0xb0

static void phy_write_exp(struct phy_device *phydev,
					u16 reg, u16 value)
{
	phy_write(phydev, MII_BCM54XX_EXP_SEL, MII_BCM54XX_EXP_SEL_ER | reg);
	phy_write(phydev, MII_BCM54XX_EXP_DATA, value);
}

static void phy_write_misc(struct phy_device *phydev,
					u16 reg, u16 chl, u16 value)
{
	int tmp;

	phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);

	tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
	tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
	phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);

	tmp = (chl * MII_BCM7XXX_CHANNEL_WIDTH) | reg;
	phy_write(phydev, MII_BCM54XX_EXP_SEL, tmp);

	phy_write(phydev, MII_BCM54XX_EXP_DATA, value);
}

static void r_rc_cal_reset(struct phy_device *phydev)
{
	/* Reset R_CAL/RC_CAL Engine */
	phy_write_exp(phydev, 0x00b0, 0x0010);

	/* Disable Reset R_AL/RC_CAL Engine */
	phy_write_exp(phydev, 0x00b0, 0x0000);
}

static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)
{
	/* Increase VCO range to prevent unlocking problem of PLL at low
	 * temp
	 */
	phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);

	/* Change Ki to 011 */
	phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);

	/* Disable loading of TVCO buffer to bandgap, set bandgap trim
	 * to 111
	 */
	phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);

	/* Adjust bias current trim by -3 */
	phy_write_misc(phydev, DSP_TAP10, 0x690b);

	/* Switch to CORE_BASE1E */
	phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0xd);

	r_rc_cal_reset(phydev);

	/* write AFE_RXCONFIG_0 */
	phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);

	/* write AFE_RXCONFIG_1 */
	phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);

	/* write AFE_RX_LP_COUNTER */
	phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);

	/* write AFE_HPF_TRIM_OTHERS */
	phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);

	/* write AFTE_TX_CONFIG */
	phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);

	return 0;
}

static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
{
	/* AFE_RXCONFIG_0 */
	phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);

	/* AFE_RXCONFIG_1 */
	phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);

	/* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */
	phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);

	/* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */
	phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);

	/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
	phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);

	/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
	phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);

	/* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */
	phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);

	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
	 * offset for HT=0 code
	 */
	phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);

	/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
	phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0x0010);

	/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
	phy_write_misc(phydev, DSP_TAP10, 0x011b);

	/* Reset R_CAL/RC_CAL engine */
	r_rc_cal_reset(phydev);

	return 0;
}

static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
{
	/* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement */
	phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);

	/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
	phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);

	/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
	phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);

	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
	 * offset for HT=0 code
	 */
	phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);

	/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
	phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0x0010);

	/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
	phy_write_misc(phydev, DSP_TAP10, 0x011b);

	/* Reset R_CAL/RC_CAL engine */
	r_rc_cal_reset(phydev);

	return 0;
}

static int bcm7xxx_apd_enable(struct phy_device *phydev)
{
	int val;

	/* Enable powering down of the DLL during auto-power down */
	val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_SCR3);
	if (val < 0)
		return val;

	val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
	bcm54xx_shadow_write(phydev, BCM54XX_SHD_SCR3, val);

	/* Enable auto-power down */
	val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_APD);
	if (val < 0)
		return val;

	val |= BCM54XX_SHD_APD_EN;
	return bcm54xx_shadow_write(phydev, BCM54XX_SHD_APD, val);
}

static int bcm7xxx_eee_enable(struct phy_device *phydev)
{
	int val;

	val = phy_read_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
				    MDIO_MMD_AN, phydev->addr);
	if (val < 0)
		return val;

	/* Enable general EEE feature at the PHY level */
	val |= LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X;

	phy_write_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
			       MDIO_MMD_AN, phydev->addr, val);

	/* Advertise supported modes */
	val = phy_read_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
				    MDIO_MMD_AN, phydev->addr);

	val |= (MDIO_AN_EEE_ADV_100TX | MDIO_AN_EEE_ADV_1000T);
	phy_write_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
			       MDIO_MMD_AN, phydev->addr, val);

	return 0;
}

static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
{
	u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
	u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
	int ret = 0;

	pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
		     dev_name(&phydev->dev), phydev->drv->name, rev, patch);

	switch (rev) {
	case 0xb0:
		ret = bcm7xxx_28nm_b0_afe_config_init(phydev);
		break;
	case 0xd0:
		ret = bcm7xxx_28nm_d0_afe_config_init(phydev);
		break;
	case 0xe0:
	case 0xf0:
	/* Rev G0 introduces a roll over */
	case 0x10:
		ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
		break;
	default:
		break;
	}

	if (ret)
		return ret;

	ret = bcm7xxx_eee_enable(phydev);
	if (ret)
		return ret;

	return bcm7xxx_apd_enable(phydev);
}

static int bcm7xxx_28nm_resume(struct phy_device *phydev)
{
	int ret;

	/* Re-apply workarounds coming out suspend/resume */
	ret = bcm7xxx_28nm_config_init(phydev);
	if (ret)
		return ret;

	/* 28nm Gigabit PHYs come out of reset without any half-duplex
	 * or "hub" compliant advertised mode, fix that. This does not
	 * cause any problems with the PHY library since genphy_config_aneg()
	 * gracefully handles auto-negotiated and forced modes.
	 */
	return genphy_config_aneg(phydev);
}

static int phy_set_clr_bits(struct phy_device *dev, int location,
					int set_mask, int clr_mask)
{
	int v, ret;

	v = phy_read(dev, location);
	if (v < 0)
		return v;

	v &= ~clr_mask;
	v |= set_mask;

	ret = phy_write(dev, location, v);
	if (ret < 0)
		return ret;

	return v;
}

static int bcm7xxx_config_init(struct phy_device *phydev)
{
	int ret;

	/* Enable 64 clock MDIO */
	phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XX_64CLK_MDIO);
	phy_read(phydev, MII_BCM7XXX_AUX_MODE);

	/* Workaround only required for 100Mbits/sec capable PHYs */
	if (phydev->supported & PHY_GBIT_FEATURES)
		return 0;

	/* set shadow mode 2 */
	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
			MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
	if (ret < 0)
		return ret;

	/* set iddq_clkbias */
	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
	udelay(10);

	/* reset iddq_clkbias */
	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);

	phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);

	/* reset shadow mode 2 */
	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, MII_BCM7XXX_SHD_MODE_2, 0);
	if (ret < 0)
		return ret;

	return 0;
}

/* Workaround for putting the PHY in IDDQ mode, required
 * for all BCM7XXX 40nm and 65nm PHYs
 */
static int bcm7xxx_suspend(struct phy_device *phydev)
{
	int ret;
	const struct bcm7xxx_regs {
		int reg;
		u16 value;
	} bcm7xxx_suspend_cfg[] = {
		{ MII_BCM7XXX_TEST, 0x008b },
		{ MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
		{ MII_BCM7XXX_100TX_DISC, 0x7000 },
		{ MII_BCM7XXX_TEST, 0x000f },
		{ MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
		{ MII_BCM7XXX_TEST, 0x000b },
	};
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
		ret = phy_write(phydev,
				bcm7xxx_suspend_cfg[i].reg,
				bcm7xxx_suspend_cfg[i].value);
		if (ret)
			return ret;
	}

	return 0;
}

static int bcm7xxx_dummy_config_init(struct phy_device *phydev)
{
	return 0;
}

#define BCM7XXX_28NM_GPHY(_oui, _name)					\
{									\
	.phy_id		= (_oui),					\
	.phy_id_mask	= 0xfffffff0,					\
	.name		= _name,					\
	.features	= PHY_GBIT_FEATURES |				\
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,	\
	.flags		= PHY_IS_INTERNAL,				\
	.config_init	= bcm7xxx_28nm_config_init,			\
	.config_aneg	= genphy_config_aneg,				\
	.read_status	= genphy_read_status,				\
	.resume		= bcm7xxx_28nm_resume,				\
	.driver		= { .owner = THIS_MODULE },			\
}

static struct phy_driver bcm7xxx_driver[] = {
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
{
	.phy_id         = PHY_ID_BCM7425,
	.phy_id_mask    = 0xfffffff0,
	.name           = "Broadcom BCM7425",
	.features       = PHY_GBIT_FEATURES |
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
	.flags          = PHY_IS_INTERNAL,
	.config_init    = bcm7xxx_config_init,
	.config_aneg    = genphy_config_aneg,
	.read_status    = genphy_read_status,
	.suspend        = bcm7xxx_suspend,
	.resume         = bcm7xxx_config_init,
	.driver         = { .owner = THIS_MODULE },
}, {
	.phy_id         = PHY_ID_BCM7429,
	.phy_id_mask    = 0xfffffff0,
	.name           = "Broadcom BCM7429",
	.features       = PHY_GBIT_FEATURES |
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
	.flags          = PHY_IS_INTERNAL,
	.config_init    = bcm7xxx_config_init,
	.config_aneg    = genphy_config_aneg,
	.read_status    = genphy_read_status,
	.suspend        = bcm7xxx_suspend,
	.resume         = bcm7xxx_config_init,
	.driver         = { .owner = THIS_MODULE },
}, {
	.phy_id		= PHY_BCM_OUI_4,
	.phy_id_mask	= 0xffff0000,
	.name		= "Broadcom BCM7XXX 40nm",
	.features	= PHY_GBIT_FEATURES |
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
	.flags		= PHY_IS_INTERNAL,
	.config_init	= bcm7xxx_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.suspend	= bcm7xxx_suspend,
	.resume		= bcm7xxx_config_init,
	.driver		= { .owner = THIS_MODULE },
}, {
	.phy_id		= PHY_BCM_OUI_5,
	.phy_id_mask	= 0xffffff00,
	.name		= "Broadcom BCM7XXX 65nm",
	.features	= PHY_BASIC_FEATURES |
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
	.flags		= PHY_IS_INTERNAL,
	.config_init	= bcm7xxx_dummy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.suspend	= bcm7xxx_suspend,
	.resume		= bcm7xxx_config_init,
	.driver		= { .owner = THIS_MODULE },
} };

static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
	{ PHY_ID_BCM7250, 0xfffffff0, },
	{ PHY_ID_BCM7364, 0xfffffff0, },
	{ PHY_ID_BCM7366, 0xfffffff0, },
	{ PHY_ID_BCM7425, 0xfffffff0, },
	{ PHY_ID_BCM7429, 0xfffffff0, },
	{ PHY_ID_BCM7439, 0xfffffff0, },
	{ PHY_ID_BCM7445, 0xfffffff0, },
	{ PHY_BCM_OUI_4, 0xffff0000 },
	{ PHY_BCM_OUI_5, 0xffffff00 },
	{ }
};

module_phy_driver(bcm7xxx_driver);

MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);

MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Broadcom Corporation");
Commit	Line	Data
b560a58c FF	1	/*
	2	* Broadcom BCM7xxx internal transceivers support.
	3	*
	4	* Copyright (C) 2014, Broadcom Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/phy.h>
	14	#include <linux/delay.h>
	15	#include <linux/bitops.h>
	16	#include <linux/brcmphy.h>
b8f9a029	17	#include <linux/mdio.h>
b560a58c FF	18
	19	/* Broadcom BCM7xxx internal PHY registers */
	20	#define MII_BCM7XXX_CHANNEL_WIDTH 0x2000
	21
	22	/* 40nm only register definitions */
	23	#define MII_BCM7XXX_100TX_AUX_CTL 0x10
	24	#define MII_BCM7XXX_100TX_FALSE_CAR 0x13
	25	#define MII_BCM7XXX_100TX_DISC 0x14
	26	#define MII_BCM7XXX_AUX_MODE 0x1d
	27	#define MII_BCM7XX_64CLK_MDIO BIT(12)
	28	#define MII_BCM7XXX_CORE_BASE1E 0x1e
	29	#define MII_BCM7XXX_TEST 0x1f
	30	#define MII_BCM7XXX_SHD_MODE_2 BIT(2)
	31
a3622f2c FF	32	/* 28nm only register definitions */
	33	#define MISC_ADDR(base, channel) base, channel
	34
	35	#define DSP_TAP10 MISC_ADDR(0x0a, 0)
	36	#define PLL_PLLCTRL_1 MISC_ADDR(0x32, 1)
	37	#define PLL_PLLCTRL_2 MISC_ADDR(0x32, 2)
	38	#define PLL_PLLCTRL_4 MISC_ADDR(0x33, 0)
	39
	40	#define AFE_RXCONFIG_0 MISC_ADDR(0x38, 0)
	41	#define AFE_RXCONFIG_1 MISC_ADDR(0x38, 1)
a490631f	42	#define AFE_RXCONFIG_2 MISC_ADDR(0x38, 2)
a3622f2c FF	43	#define AFE_RX_LP_COUNTER MISC_ADDR(0x38, 3)
a3622f2c FF	44	#define AFE_TX_CONFIG MISC_ADDR(0x39, 0)
a490631f FF	45	#define AFE_VDCA_ICTRL_0 MISC_ADDR(0x39, 1)
a490631f FF	46	#define AFE_VDAC_OTHERS_0 MISC_ADDR(0x39, 3)
a3622f2c FF	47	#define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0)
	48
	49	#define CORE_EXPB0 0xb0
	50
b560a58c FF	51	static void phy_write_exp(struct phy_device *phydev,
	52	u16 reg, u16 value)
	53	{
	54	phy_write(phydev, MII_BCM54XX_EXP_SEL, MII_BCM54XX_EXP_SEL_ER \| reg);
	55	phy_write(phydev, MII_BCM54XX_EXP_DATA, value);
	56	}
	57
	58	static void phy_write_misc(struct phy_device *phydev,
	59	u16 reg, u16 chl, u16 value)
	60	{
	61	int tmp;
	62
	63	phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
	64
	65	tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
	66	tmp \|= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
	67	phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
	68
	69	tmp = (chl * MII_BCM7XXX_CHANNEL_WIDTH) \| reg;
	70	phy_write(phydev, MII_BCM54XX_EXP_SEL, tmp);
	71
	72	phy_write(phydev, MII_BCM54XX_EXP_DATA, value);
	73	}
	74
9c41f2ba FF	75	static void r_rc_cal_reset(struct phy_device *phydev)
	76	{
	77	/* Reset R_CAL/RC_CAL Engine */
	78	phy_write_exp(phydev, 0x00b0, 0x0010);
	79
	80	/* Disable Reset R_AL/RC_CAL Engine */
	81	phy_write_exp(phydev, 0x00b0, 0x0000);
	82	}
	83
2a9df742	84	static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)
b560a58c	85	{
b560a58c FF	86	/* Increase VCO range to prevent unlocking problem of PLL at low
	87	* temp
	88	*/
a3622f2c	89	phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);
b560a58c FF	90
b560a58c FF	91	/* Change Ki to 011 */
a3622f2c	92	phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);
b560a58c FF	93
	94	/* Disable loading of TVCO buffer to bandgap, set bandgap trim
	95	* to 111
	96	*/
a3622f2c	97	phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);
b560a58c FF	98
b560a58c FF	99	/* Adjust bias current trim by -3 */
a3622f2c	100	phy_write_misc(phydev, DSP_TAP10, 0x690b);
b560a58c FF	101
	102	/* Switch to CORE_BASE1E */
	103	phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0xd);
	104
9c41f2ba	105	r_rc_cal_reset(phydev);
b560a58c	106
9918542e FF	107	/* write AFE_RXCONFIG_0 */
	108	phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
	109
	110	/* write AFE_RXCONFIG_1 */
	111	phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);
	112
	113	/* write AFE_RX_LP_COUNTER */
a62ea5a7	114	phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
9918542e FF	115
	116	/* write AFE_HPF_TRIM_OTHERS */
	117	phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);
	118
	119	/* write AFTE_TX_CONFIG */
	120	phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);
	121
b560a58c FF	122	return 0;
	123	}
	124
a490631f FF	125	static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
	126	{
	127	/* AFE_RXCONFIG_0 */
	128	phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);
	129
	130	/* AFE_RXCONFIG_1 */
	131	phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
	132
	133	/* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */
	134	phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);
	135
	136	/* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */
	137	phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
	138
6da8253b FF	139	/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
6da8253b FF	140	phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
a490631f FF	141
	142	/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
	143	phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
	144
	145	/* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */
	146	phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);
	147
	148	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
	149	* offset for HT=0 code
	150	*/
	151	phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
	152
	153	/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
	154	phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0x0010);
	155
	156	/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
	157	phy_write_misc(phydev, DSP_TAP10, 0x011b);
	158
	159	/* Reset R_CAL/RC_CAL engine */
	160	r_rc_cal_reset(phydev);
	161
	162	return 0;
	163	}
	164
0c2fdc25 FF	165	static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
	166	{
	167	/* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement */
	168	phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
	169
6da8253b FF	170	/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
	171	phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
	172
0c2fdc25 FF	173	/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
	174	phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
	175
	176	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
	177	* offset for HT=0 code
	178	*/
	179	phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
	180
	181	/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
	182	phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0x0010);
	183
	184	/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
	185	phy_write_misc(phydev, DSP_TAP10, 0x011b);
	186
	187	/* Reset R_CAL/RC_CAL engine */
	188	r_rc_cal_reset(phydev);
	189
	190	return 0;
	191	}
	192
9df54dda FF	193	static int bcm7xxx_apd_enable(struct phy_device *phydev)
	194	{
	195	int val;
	196
	197	/* Enable powering down of the DLL during auto-power down */
	198	val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_SCR3);
	199	if (val < 0)
	200	return val;
	201
	202	val \|= BCM54XX_SHD_SCR3_DLLAPD_DIS;
	203	bcm54xx_shadow_write(phydev, BCM54XX_SHD_SCR3, val);
	204
	205	/* Enable auto-power down */
	206	val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_APD);
	207	if (val < 0)
	208	return val;
	209
	210	val \|= BCM54XX_SHD_APD_EN;
	211	return bcm54xx_shadow_write(phydev, BCM54XX_SHD_APD, val);
	212	}
	213
b8f9a029 FF	214	static int bcm7xxx_eee_enable(struct phy_device *phydev)
	215	{
	216	int val;
	217
	218	val = phy_read_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
	219	MDIO_MMD_AN, phydev->addr);
	220	if (val < 0)
	221	return val;
	222
	223	/* Enable general EEE feature at the PHY level */
	224	val \|= LPI_FEATURE_EN \| LPI_FEATURE_EN_DIG1000X;
	225
	226	phy_write_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
	227	MDIO_MMD_AN, phydev->addr, val);
	228
	229	/* Advertise supported modes */
	230	val = phy_read_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
	231	MDIO_MMD_AN, phydev->addr);
	232
	233	val \|= (MDIO_AN_EEE_ADV_100TX \| MDIO_AN_EEE_ADV_1000T);
	234	phy_write_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
	235	MDIO_MMD_AN, phydev->addr, val);
	236
	237	return 0;
	238	}
	239
b560a58c FF	240	static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
b560a58c FF	241	{
d8ebfed3 FF	242	u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
	243	u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
	244	int ret = 0;
	245
6ec259c1 FF	246	pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
6ec259c1 FF	247	dev_name(&phydev->dev), phydev->drv->name, rev, patch);
d8ebfed3 FF	248
d8ebfed3 FF	249	switch (rev) {
d8ebfed3	250	case 0xb0:
2a9df742	251	ret = bcm7xxx_28nm_b0_afe_config_init(phydev);
d8ebfed3	252	break;
a490631f FF	253	case 0xd0:
	254	ret = bcm7xxx_28nm_d0_afe_config_init(phydev);
	255	break;
0c2fdc25 FF	256	case 0xe0:
0c2fdc25 FF	257	case 0xf0:
60efff0c FF	258	/* Rev G0 introduces a roll over */
60efff0c FF	259	case 0x10:
0c2fdc25 FF	260	ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
0c2fdc25 FF	261	break;
d8ebfed3	262	default:
d8ebfed3 FF	263	break;
d8ebfed3 FF	264	}
b560a58c	265
9df54dda FF	266	if (ret)
	267	return ret;
	268
b8f9a029 FF	269	ret = bcm7xxx_eee_enable(phydev);
	270	if (ret)
	271	return ret;
	272
9df54dda	273	return bcm7xxx_apd_enable(phydev);
b560a58c FF	274	}
b560a58c FF	275
4fd14e0b FF	276	static int bcm7xxx_28nm_resume(struct phy_device *phydev)
	277	{
	278	int ret;
	279
	280	/* Re-apply workarounds coming out suspend/resume */
	281	ret = bcm7xxx_28nm_config_init(phydev);
	282	if (ret)
	283	return ret;
	284
	285	/* 28nm Gigabit PHYs come out of reset without any half-duplex
	286	* or "hub" compliant advertised mode, fix that. This does not
	287	* cause any problems with the PHY library since genphy_config_aneg()
	288	* gracefully handles auto-negotiated and forced modes.
	289	*/
	290	return genphy_config_aneg(phydev);
	291	}
	292
b560a58c FF	293	static int phy_set_clr_bits(struct phy_device *dev, int location,
	294	int set_mask, int clr_mask)
	295	{
	296	int v, ret;
	297
	298	v = phy_read(dev, location);
	299	if (v < 0)
	300	return v;
	301
	302	v &= ~clr_mask;
	303	v \|= set_mask;
	304
	305	ret = phy_write(dev, location, v);
	306	if (ret < 0)
	307	return ret;
	308
	309	return v;
	310	}
	311
	312	static int bcm7xxx_config_init(struct phy_device *phydev)
	313	{
	314	int ret;
	315
	316	/* Enable 64 clock MDIO */
	317	phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XX_64CLK_MDIO);
	318	phy_read(phydev, MII_BCM7XXX_AUX_MODE);
	319
e18556ee FF	320	/* Workaround only required for 100Mbits/sec capable PHYs */
e18556ee FF	321	if (phydev->supported & PHY_GBIT_FEATURES)
b560a58c FF	322	return 0;
	323
	324	/* set shadow mode 2 */
	325	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
	326	MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
	327	if (ret < 0)
	328	return ret;
	329
	330	/* set iddq_clkbias */
	331	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
	332	udelay(10);
	333
	334	/* reset iddq_clkbias */
	335	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);
	336
	337	phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);
	338
	339	/* reset shadow mode 2 */
	340	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, MII_BCM7XXX_SHD_MODE_2, 0);
	341	if (ret < 0)
	342	return ret;
	343
	344	return 0;
	345	}
	346
	347	/* Workaround for putting the PHY in IDDQ mode, required
82c084f5	348	* for all BCM7XXX 40nm and 65nm PHYs
b560a58c FF	349	*/
	350	static int bcm7xxx_suspend(struct phy_device *phydev)
	351	{
	352	int ret;
	353	const struct bcm7xxx_regs {
	354	int reg;
	355	u16 value;
	356	} bcm7xxx_suspend_cfg[] = {
	357	{ MII_BCM7XXX_TEST, 0x008b },
	358	{ MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
	359	{ MII_BCM7XXX_100TX_DISC, 0x7000 },
	360	{ MII_BCM7XXX_TEST, 0x000f },
	361	{ MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
	362	{ MII_BCM7XXX_TEST, 0x000b },
	363	};
	364	unsigned int i;
	365
	366	for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
	367	ret = phy_write(phydev,
	368	bcm7xxx_suspend_cfg[i].reg,
	369	bcm7xxx_suspend_cfg[i].value);
	370	if (ret)
	371	return ret;
	372	}
	373
	374	return 0;
	375	}
	376
	377	static int bcm7xxx_dummy_config_init(struct phy_device *phydev)
	378	{
	379	return 0;
	380	}
	381
153df3c7 FF	382	#define BCM7XXX_28NM_GPHY(_oui, _name) \
	383	{ \
	384	.phy_id = (_oui), \
	385	.phy_id_mask = 0xfffffff0, \
	386	.name = _name, \
	387	.features = PHY_GBIT_FEATURES \| \
	388	SUPPORTED_Pause \| SUPPORTED_Asym_Pause, \
	389	.flags = PHY_IS_INTERNAL, \
2a9df742	390	.config_init = bcm7xxx_28nm_config_init, \
153df3c7 FF	391	.config_aneg = genphy_config_aneg, \
	392	.read_status = genphy_read_status, \
	393	.resume = bcm7xxx_28nm_resume, \
	394	.driver = { .owner = THIS_MODULE }, \
	395	}
	396
b560a58c	397	static struct phy_driver bcm7xxx_driver[] = {
430ad68f FF	398	BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
430ad68f FF	399	BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
153df3c7 FF	400	BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
153df3c7 FF	401	BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
59e33c2b	402	BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"),
153df3c7	403	BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
b560a58c	404	{
d068b02c PG	405	.phy_id = PHY_ID_BCM7425,
	406	.phy_id_mask = 0xfffffff0,
	407	.name = "Broadcom BCM7425",
	408	.features = PHY_GBIT_FEATURES \|
	409	SUPPORTED_Pause \| SUPPORTED_Asym_Pause,
cc4a84c3	410	.flags = PHY_IS_INTERNAL,
d068b02c PG	411	.config_init = bcm7xxx_config_init,
	412	.config_aneg = genphy_config_aneg,
	413	.read_status = genphy_read_status,
	414	.suspend = bcm7xxx_suspend,
	415	.resume = bcm7xxx_config_init,
	416	.driver = { .owner = THIS_MODULE },
	417	}, {
	418	.phy_id = PHY_ID_BCM7429,
	419	.phy_id_mask = 0xfffffff0,
	420	.name = "Broadcom BCM7429",
	421	.features = PHY_GBIT_FEATURES \|
	422	SUPPORTED_Pause \| SUPPORTED_Asym_Pause,
	423	.flags = PHY_IS_INTERNAL,
	424	.config_init = bcm7xxx_config_init,
	425	.config_aneg = genphy_config_aneg,
	426	.read_status = genphy_read_status,
	427	.suspend = bcm7xxx_suspend,
	428	.resume = bcm7xxx_config_init,
	429	.driver = { .owner = THIS_MODULE },
	430	}, {
b560a58c FF	431	.phy_id = PHY_BCM_OUI_4,
	432	.phy_id_mask = 0xffff0000,
	433	.name = "Broadcom BCM7XXX 40nm",
	434	.features = PHY_GBIT_FEATURES \|
	435	SUPPORTED_Pause \| SUPPORTED_Asym_Pause,
	436	.flags = PHY_IS_INTERNAL,
	437	.config_init = bcm7xxx_config_init,
	438	.config_aneg = genphy_config_aneg,
	439	.read_status = genphy_read_status,
	440	.suspend = bcm7xxx_suspend,
	441	.resume = bcm7xxx_config_init,
	442	.driver = { .owner = THIS_MODULE },
	443	}, {
	444	.phy_id = PHY_BCM_OUI_5,
	445	.phy_id_mask = 0xffffff00,
	446	.name = "Broadcom BCM7XXX 65nm",
	447	.features = PHY_BASIC_FEATURES \|
	448	SUPPORTED_Pause \| SUPPORTED_Asym_Pause,
	449	.flags = PHY_IS_INTERNAL,
	450	.config_init = bcm7xxx_dummy_config_init,
	451	.config_aneg = genphy_config_aneg,
	452	.read_status = genphy_read_status,
	453	.suspend = bcm7xxx_suspend,
	454	.resume = bcm7xxx_config_init,
	455	.driver = { .owner = THIS_MODULE },
	456	} };
	457
	458	static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
430ad68f FF	459	{ PHY_ID_BCM7250, 0xfffffff0, },
430ad68f FF	460	{ PHY_ID_BCM7364, 0xfffffff0, },
b560a58c	461	{ PHY_ID_BCM7366, 0xfffffff0, },
d068b02c PG	462	{ PHY_ID_BCM7425, 0xfffffff0, },
d068b02c PG	463	{ PHY_ID_BCM7429, 0xfffffff0, },
b560a58c FF	464	{ PHY_ID_BCM7439, 0xfffffff0, },
b560a58c FF	465	{ PHY_ID_BCM7445, 0xfffffff0, },
b560a58c FF	466	{ PHY_BCM_OUI_4, 0xffff0000 },
	467	{ PHY_BCM_OUI_5, 0xffffff00 },
	468	{ }
	469	};
	470
50fd7150	471	module_phy_driver(bcm7xxx_driver);
b560a58c FF	472
	473	MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);
	474
	475	MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
	476	MODULE_LICENSE("GPL");
	477	MODULE_AUTHOR("Broadcom Corporation");