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Merge branch 'mvebu'
[deliverable/linux.git] / drivers / net / phy / dp83640.c
CommitLineData
cb646e2b
RC		 1/*
2 * Driver for the National Semiconductor DP83640 PHYTER
3 *
4 * Copyright (C) 2010 OMICRON electronics GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
8d242488
JP		 20
21#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22
cb646e2b
RC		 23#include <linux/ethtool.h>
24#include <linux/kernel.h>
25#include <linux/list.h>
26#include <linux/mii.h>
27#include <linux/module.h>
28#include <linux/net_tstamp.h>
29#include <linux/netdevice.h>
408eccce 30#include <linux/if_vlan.h>
cb646e2b
RC		 31#include <linux/phy.h>
32#include <linux/ptp_classify.h>
33#include <linux/ptp_clock_kernel.h>
34
35#include "dp83640_reg.h"
36
37#define DP83640_PHY_ID 0x20005ce1
38#define PAGESEL 0x13
39#define LAYER4 0x02
40#define LAYER2 0x01
8028837d 41#define MAX_RXTS 64
49b3fd4a 42#define N_EXT_TS 6
ad01577a 43#define N_PER_OUT 7
cb646e2b
RC		 44#define PSF_PTPVER 2
45#define PSF_EVNT 0x4000
46#define PSF_RX 0x2000
47#define PSF_TX 0x1000
48#define EXT_EVENT 1
49b3fd4a
RC		 49#define CAL_EVENT 7
50#define CAL_TRIGGER 7
86dd3612 51#define DP83640_N_PINS 12
cb646e2b 52
1642182e
SG		 53#define MII_DP83640_MICR 0x11
54#define MII_DP83640_MISR 0x12
55
56#define MII_DP83640_MICR_OE 0x1
57#define MII_DP83640_MICR_IE 0x2
58
59#define MII_DP83640_MISR_RHF_INT_EN 0x01
60#define MII_DP83640_MISR_FHF_INT_EN 0x02
61#define MII_DP83640_MISR_ANC_INT_EN 0x04
62#define MII_DP83640_MISR_DUP_INT_EN 0x08
63#define MII_DP83640_MISR_SPD_INT_EN 0x10
64#define MII_DP83640_MISR_LINK_INT_EN 0x20
65#define MII_DP83640_MISR_ED_INT_EN 0x40
66#define MII_DP83640_MISR_LQ_INT_EN 0x80
67
cb646e2b
RC		 68/* phyter seems to miss the mark by 16 ns */
69#define ADJTIME_FIX 16
70
71#if defined(__BIG_ENDIAN)
72#define ENDIAN_FLAG 0
73#elif defined(__LITTLE_ENDIAN)
74#define ENDIAN_FLAG PSF_ENDIAN
75#endif
76
77#define SKB_PTP_TYPE(__skb) (*(unsigned int *)((__skb)->cb))
78
79struct phy_rxts {
80 u16 ns_lo; /* ns[15:0] */
81 u16 ns_hi; /* overflow[1:0], ns[29:16] */
82 u16 sec_lo; /* sec[15:0] */
83 u16 sec_hi; /* sec[31:16] */
84 u16 seqid; /* sequenceId[15:0] */
85 u16 msgtype; /* messageType[3:0], hash[11:0] */
86};
87
88struct phy_txts {
89 u16 ns_lo; /* ns[15:0] */
90 u16 ns_hi; /* overflow[1:0], ns[29:16] */
91 u16 sec_lo; /* sec[15:0] */
92 u16 sec_hi; /* sec[31:16] */
93};
94
95struct rxts {
96 struct list_head list;
97 unsigned long tmo;
98 u64 ns;
99 u16 seqid;
100 u8 msgtype;
101 u16 hash;
102};
103
104struct dp83640_clock;
105
106struct dp83640_private {
107 struct list_head list;
108 struct dp83640_clock *clock;
109 struct phy_device *phydev;
110 struct work_struct ts_work;
111 int hwts_tx_en;
112 int hwts_rx_en;
113 int layer;
114 int version;
115 /* remember state of cfg0 during calibration */
116 int cfg0;
117 /* remember the last event time stamp */
118 struct phy_txts edata;
119 /* list of rx timestamps */
120 struct list_head rxts;
121 struct list_head rxpool;
122 struct rxts rx_pool_data[MAX_RXTS];
123 /* protects above three fields from concurrent access */
124 spinlock_t rx_lock;
125 /* queues of incoming and outgoing packets */
126 struct sk_buff_head rx_queue;
127 struct sk_buff_head tx_queue;
128};
129
130struct dp83640_clock {
131 /* keeps the instance in the 'phyter_clocks' list */
132 struct list_head list;
133 /* we create one clock instance per MII bus */
134 struct mii_bus *bus;
135 /* protects extended registers from concurrent access */
136 struct mutex extreg_lock;
137 /* remembers which page was last selected */
138 int page;
139 /* our advertised capabilities */
140 struct ptp_clock_info caps;
141 /* protects the three fields below from concurrent access */
142 struct mutex clock_lock;
143 /* the one phyter from which we shall read */
144 struct dp83640_private *chosen;
145 /* list of the other attached phyters, not chosen */
146 struct list_head phylist;
147 /* reference to our PTP hardware clock */
148 struct ptp_clock *ptp_clock;
149};
150
151/* globals */
152
49b3fd4a
RC		 153enum {
154 CALIBRATE_GPIO,
155 PEROUT_GPIO,
156 EXTTS0_GPIO,
157 EXTTS1_GPIO,
158 EXTTS2_GPIO,
159 EXTTS3_GPIO,
160 EXTTS4_GPIO,
161 EXTTS5_GPIO,
162 GPIO_TABLE_SIZE
163};
164
cb646e2b 165static int chosen_phy = -1;
49b3fd4a
RC		 166static ushort gpio_tab[GPIO_TABLE_SIZE] = {
167 1, 2, 3, 4, 8, 9, 10, 11
168};
cb646e2b
RC		 169
170module_param(chosen_phy, int, 0444);
49b3fd4a 171module_param_array(gpio_tab, ushort, NULL, 0444);
cb646e2b
RC		 172
173MODULE_PARM_DESC(chosen_phy, \
174 "The address of the PHY to use for the ancillary clock features");
49b3fd4a
RC		 175MODULE_PARM_DESC(gpio_tab, \
176 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");
cb646e2b 177
86dd3612
RC		 178static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)
179{
180 int i, index;
181
182 for (i = 0; i < DP83640_N_PINS; i++) {
183 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i);
184 pd[i].index = i;
185 }
186
187 for (i = 0; i < GPIO_TABLE_SIZE; i++) {
188 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) {
189 pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]);
190 return;
191 }
192 }
193
194 index = gpio_tab[CALIBRATE_GPIO] - 1;
195 pd[index].func = PTP_PF_PHYSYNC;
196 pd[index].chan = 0;
197
198 index = gpio_tab[PEROUT_GPIO] - 1;
199 pd[index].func = PTP_PF_PEROUT;
200 pd[index].chan = 0;
201
202 for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) {
203 index = gpio_tab[i] - 1;
204 pd[index].func = PTP_PF_EXTTS;
205 pd[index].chan = i - EXTTS0_GPIO;
206 }
207}
208
cb646e2b
RC		 209/* a list of clocks and a mutex to protect it */
210static LIST_HEAD(phyter_clocks);
211static DEFINE_MUTEX(phyter_clocks_lock);
212
213static void rx_timestamp_work(struct work_struct *work);
214
215/* extended register access functions */
216
217#define BROADCAST_ADDR 31
218
219static inline int broadcast_write(struct mii_bus *bus, u32 regnum, u16 val)
220{
221 return mdiobus_write(bus, BROADCAST_ADDR, regnum, val);
222}
223
224/* Caller must hold extreg_lock. */
225static int ext_read(struct phy_device *phydev, int page, u32 regnum)
226{
227 struct dp83640_private *dp83640 = phydev->priv;
228 int val;
229
230 if (dp83640->clock->page != page) {
231 broadcast_write(phydev->bus, PAGESEL, page);
232 dp83640->clock->page = page;
233 }
234 val = phy_read(phydev, regnum);
235
236 return val;
237}
238
239/* Caller must hold extreg_lock. */
240static void ext_write(int broadcast, struct phy_device *phydev,
241 int page, u32 regnum, u16 val)
242{
243 struct dp83640_private *dp83640 = phydev->priv;
244
245 if (dp83640->clock->page != page) {
246 broadcast_write(phydev->bus, PAGESEL, page);
247 dp83640->clock->page = page;
248 }
249 if (broadcast)
250 broadcast_write(phydev->bus, regnum, val);
251 else
252 phy_write(phydev, regnum, val);
253}
254
255/* Caller must hold extreg_lock. */
256static int tdr_write(int bc, struct phy_device *dev,
257 const struct timespec *ts, u16 cmd)
258{
259 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */
260 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */
261 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
262 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/
263
264 ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
265
266 return 0;
267}
268
269/* convert phy timestamps into driver timestamps */
270
271static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
272{
273 u32 sec;
274
275 sec = p->sec_lo;
276 sec |= p->sec_hi << 16;
277
278 rxts->ns = p->ns_lo;
279 rxts->ns |= (p->ns_hi & 0x3fff) << 16;
280 rxts->ns += ((u64)sec) * 1000000000ULL;
281 rxts->seqid = p->seqid;
282 rxts->msgtype = (p->msgtype >> 12) & 0xf;
283 rxts->hash = p->msgtype & 0x0fff;
8028837d 284 rxts->tmo = jiffies + 2;
cb646e2b
RC		 285}
286
287static u64 phy2txts(struct phy_txts *p)
288{
289 u64 ns;
290 u32 sec;
291
292 sec = p->sec_lo;
293 sec |= p->sec_hi << 16;
294
295 ns = p->ns_lo;
296 ns |= (p->ns_hi & 0x3fff) << 16;
297 ns += ((u64)sec) * 1000000000ULL;
298
299 return ns;
300}
301
621bdecc 302static int periodic_output(struct dp83640_clock *clock,
ad01577a
SS		 303 struct ptp_clock_request *clkreq, bool on,
304 int trigger)
49b3fd4a
RC		 305{
306 struct dp83640_private *dp83640 = clock->chosen;
307 struct phy_device *phydev = dp83640->phydev;
564ca56e 308 u32 sec, nsec, pwidth;
ad01577a 309 u16 gpio, ptp_trig, val;
49b3fd4a 310
621bdecc 311 if (on) {
ad01577a
SS		 312 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
313 trigger);
621bdecc
RC		 314 if (gpio < 1)
315 return -EINVAL;
316 } else {
317 gpio = 0;
318 }
319
49b3fd4a
RC		 320 ptp_trig = TRIG_WR |
321 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
322 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
323 TRIG_PER |
324 TRIG_PULSE;
325
326 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
327
328 if (!on) {
329 val |= TRIG_DIS;
330 mutex_lock(&clock->extreg_lock);
331 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
332 ext_write(0, phydev, PAGE4, PTP_CTL, val);
333 mutex_unlock(&clock->extreg_lock);
621bdecc 334 return 0;
49b3fd4a
RC		 335 }
336
337 sec = clkreq->perout.start.sec;
338 nsec = clkreq->perout.start.nsec;
564ca56e
RC		 339 pwidth = clkreq->perout.period.sec * 1000000000UL;
340 pwidth += clkreq->perout.period.nsec;
341 pwidth /= 2;
49b3fd4a
RC		 342
343 mutex_lock(&clock->extreg_lock);
344
345 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
346
347 /*load trigger*/
348 val |= TRIG_LOAD;
349 ext_write(0, phydev, PAGE4, PTP_CTL, val);
350 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */
351 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */
352 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */
353 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */
564ca56e
RC		 354 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */
355 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */
35e872ae
SS		 356 /* Triggers 0 and 1 has programmable pulsewidth2 */
357 if (trigger < 2) {
358 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
359 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
360 }
49b3fd4a
RC		 361
362 /*enable trigger*/
363 val &= ~TRIG_LOAD;
364 val |= TRIG_EN;
365 ext_write(0, phydev, PAGE4, PTP_CTL, val);
366
367 mutex_unlock(&clock->extreg_lock);
621bdecc 368 return 0;
49b3fd4a
RC		 369}
370
cb646e2b
RC		 371/* ptp clock methods */
372
373static int ptp_dp83640_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
374{
375 struct dp83640_clock *clock =
376 container_of(ptp, struct dp83640_clock, caps);
377 struct phy_device *phydev = clock->chosen->phydev;
378 u64 rate;
379 int neg_adj = 0;
380 u16 hi, lo;
381
382 if (ppb < 0) {
383 neg_adj = 1;
384 ppb = -ppb;
385 }
386 rate = ppb;
387 rate <<= 26;
388 rate = div_u64(rate, 1953125);
389
390 hi = (rate >> 16) & PTP_RATE_HI_MASK;
391 if (neg_adj)
392 hi |= PTP_RATE_DIR;
393
394 lo = rate & 0xffff;
395
396 mutex_lock(&clock->extreg_lock);
397
398 ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
399 ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
400
401 mutex_unlock(&clock->extreg_lock);
402
403 return 0;
404}
405
406static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
407{
408 struct dp83640_clock *clock =
409 container_of(ptp, struct dp83640_clock, caps);
410 struct phy_device *phydev = clock->chosen->phydev;
411 struct timespec ts;
412 int err;
413
414 delta += ADJTIME_FIX;
415
416 ts = ns_to_timespec(delta);
417
418 mutex_lock(&clock->extreg_lock);
419
420 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
421
422 mutex_unlock(&clock->extreg_lock);
423
424 return err;
425}
426
427static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
428{
429 struct dp83640_clock *clock =
430 container_of(ptp, struct dp83640_clock, caps);
431 struct phy_device *phydev = clock->chosen->phydev;
432 unsigned int val[4];
433
434 mutex_lock(&clock->extreg_lock);
435
436 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
437
438 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
439 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
440 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
441 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
442
443 mutex_unlock(&clock->extreg_lock);
444
445 ts->tv_nsec = val[0] | (val[1] << 16);
446 ts->tv_sec = val[2] | (val[3] << 16);
447
448 return 0;
449}
450
451static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
452 const struct timespec *ts)
453{
454 struct dp83640_clock *clock =
455 container_of(ptp, struct dp83640_clock, caps);
456 struct phy_device *phydev = clock->chosen->phydev;
457 int err;
458
459 mutex_lock(&clock->extreg_lock);
460
461 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
462
463 mutex_unlock(&clock->extreg_lock);
464
465 return err;
466}
467
468static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
469 struct ptp_clock_request *rq, int on)
470{
471 struct dp83640_clock *clock =
472 container_of(ptp, struct dp83640_clock, caps);
473 struct phy_device *phydev = clock->chosen->phydev;
fbf4b934 474 unsigned int index;
49b3fd4a 475 u16 evnt, event_num, gpio_num;
cb646e2b
RC		 476
477 switch (rq->type) {
478 case PTP_CLK_REQ_EXTTS:
49b3fd4a 479 index = rq->extts.index;
fbf4b934 480 if (index >= N_EXT_TS)
cb646e2b 481 return -EINVAL;
49b3fd4a
RC		 482 event_num = EXT_EVENT + index;
483 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
cb646e2b 484 if (on) {
faa89716
RC		 485 gpio_num = 1 + ptp_find_pin(clock->ptp_clock,
486 PTP_PF_EXTTS, index);
487 if (gpio_num < 1)
488 return -EINVAL;
49b3fd4a 489 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
80671bd2
SS		 490 if (rq->extts.flags & PTP_FALLING_EDGE)
491 evnt |= EVNT_FALL;
492 else
493 evnt |= EVNT_RISE;
cb646e2b
RC		 494 }
495 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
496 return 0;
49b3fd4a
RC		 497
498 case PTP_CLK_REQ_PEROUT:
ad01577a 499 if (rq->perout.index >= N_PER_OUT)
49b3fd4a 500 return -EINVAL;
ad01577a 501 return periodic_output(clock, rq, on, rq->perout.index);
49b3fd4a 502
cb646e2b
RC		 503 default:
504 break;
505 }
506
507 return -EOPNOTSUPP;
508}
509
86dd3612
RC		 510static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin,
511 enum ptp_pin_function func, unsigned int chan)
512{
6f39eb87
SS		 513 struct dp83640_clock *clock =
514 container_of(ptp, struct dp83640_clock, caps);
515
516 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&
517 !list_empty(&clock->phylist))
518 return 1;
519
520 if (func == PTP_PF_PHYSYNC)
521 return 1;
522
86dd3612
RC		 523 return 0;
524}
525
cb646e2b
RC		 526static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
527static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
528
529static void enable_status_frames(struct phy_device *phydev, bool on)
530{
531 u16 cfg0 = 0, ver;
532
533 if (on)
534 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
535
536 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
537
538 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
539 ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
540
541 if (!phydev->attached_dev) {
8d242488 542 pr_warn("expected to find an attached netdevice\n");
cb646e2b
RC		 543 return;
544 }
545
546 if (on) {
547 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
8d242488 548 pr_warn("failed to add mc address\n");
cb646e2b
RC		 549 } else {
550 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
8d242488 551 pr_warn("failed to delete mc address\n");
cb646e2b
RC		 552 }
553}
554
555static bool is_status_frame(struct sk_buff *skb, int type)
556{
557 struct ethhdr *h = eth_hdr(skb);
558
559 if (PTP_CLASS_V2_L2 == type &&
560 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
561 return true;
562 else
563 return false;
564}
565
566static int expired(struct rxts *rxts)
567{
568 return time_after(jiffies, rxts->tmo);
569}
570
571/* Caller must hold rx_lock. */
572static void prune_rx_ts(struct dp83640_private *dp83640)
573{
574 struct list_head *this, *next;
575 struct rxts *rxts;
576
577 list_for_each_safe(this, next, &dp83640->rxts) {
578 rxts = list_entry(this, struct rxts, list);
579 if (expired(rxts)) {
580 list_del_init(&rxts->list);
581 list_add(&rxts->list, &dp83640->rxpool);
582 }
583 }
584}
585
586/* synchronize the phyters so they act as one clock */
587
588static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
589{
590 int val;
591 phy_write(phydev, PAGESEL, 0);
592 val = phy_read(phydev, PHYCR2);
593 if (on)
594 val |= BC_WRITE;
595 else
596 val &= ~BC_WRITE;
597 phy_write(phydev, PHYCR2, val);
598 phy_write(phydev, PAGESEL, init_page);
599}
600
601static void recalibrate(struct dp83640_clock *clock)
602{
603 s64 now, diff;
604 struct phy_txts event_ts;
605 struct timespec ts;
606 struct list_head *this;
607 struct dp83640_private *tmp;
608 struct phy_device *master = clock->chosen->phydev;
49b3fd4a 609 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;
cb646e2b
RC		 610
611 trigger = CAL_TRIGGER;
e0155950
SS		 612 cal_gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PHYSYNC, 0);
613 if (cal_gpio < 1) {
614 pr_err("PHY calibration pin not avaible - PHY is not calibrated.");
615 return;
616 }
cb646e2b
RC		 617
618 mutex_lock(&clock->extreg_lock);
619
620 /*
621 * enable broadcast, disable status frames, enable ptp clock
622 */
623 list_for_each(this, &clock->phylist) {
624 tmp = list_entry(this, struct dp83640_private, list);
625 enable_broadcast(tmp->phydev, clock->page, 1);
626 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
627 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
628 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
629 }
630 enable_broadcast(master, clock->page, 1);
631 cfg0 = ext_read(master, PAGE5, PSF_CFG0);
632 ext_write(0, master, PAGE5, PSF_CFG0, 0);
633 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
634
635 /*
636 * enable an event timestamp
637 */
638 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
639 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
640 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
641
642 list_for_each(this, &clock->phylist) {
643 tmp = list_entry(this, struct dp83640_private, list);
644 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
645 }
646 ext_write(0, master, PAGE5, PTP_EVNT, evnt);
647
648 /*
649 * configure a trigger
650 */
651 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
652 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
653 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
654 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
655
656 /* load trigger */
657 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
658 val |= TRIG_LOAD;
659 ext_write(0, master, PAGE4, PTP_CTL, val);
660
661 /* enable trigger */
662 val &= ~TRIG_LOAD;
663 val |= TRIG_EN;
664 ext_write(0, master, PAGE4, PTP_CTL, val);
665
666 /* disable trigger */
667 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
668 val |= TRIG_DIS;
669 ext_write(0, master, PAGE4, PTP_CTL, val);
670
671 /*
672 * read out and correct offsets
673 */
674 val = ext_read(master, PAGE4, PTP_STS);
8d242488 675 pr_info("master PTP_STS 0x%04hx\n", val);
cb646e2b 676 val = ext_read(master, PAGE4, PTP_ESTS);
8d242488 677 pr_info("master PTP_ESTS 0x%04hx\n", val);
cb646e2b
RC		 678 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA);
679 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA);
680 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
681 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
682 now = phy2txts(&event_ts);
683
684 list_for_each(this, &clock->phylist) {
685 tmp = list_entry(this, struct dp83640_private, list);
686 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
8d242488 687 pr_info("slave PTP_STS 0x%04hx\n", val);
cb646e2b 688 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
8d242488 689 pr_info("slave PTP_ESTS 0x%04hx\n", val);
cb646e2b
RC		 690 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
691 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
692 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
693 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
694 diff = now - (s64) phy2txts(&event_ts);
695 pr_info("slave offset %lld nanoseconds\n", diff);
696 diff += ADJTIME_FIX;
697 ts = ns_to_timespec(diff);
698 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
699 }
700
701 /*
702 * restore status frames
703 */
704 list_for_each(this, &clock->phylist) {
705 tmp = list_entry(this, struct dp83640_private, list);
706 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
707 }
708 ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
709
710 mutex_unlock(&clock->extreg_lock);
711}
712
713/* time stamping methods */
714
49b3fd4a
RC		 715static inline u16 exts_chan_to_edata(int ch)
716{
717 return 1 << ((ch + EXT_EVENT) * 2);
718}
719
2331038a
RC		 720static int decode_evnt(struct dp83640_private *dp83640,
721 void *data, u16 ests)
cb646e2b 722{
2331038a 723 struct phy_txts *phy_txts;
cb646e2b 724 struct ptp_clock_event event;
49b3fd4a 725 int i, parsed;
cb646e2b 726 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
2331038a
RC		 727 u16 ext_status = 0;
728
729 if (ests & MULT_EVNT) {
730 ext_status = *(u16 *) data;
731 data += sizeof(ext_status);
732 }
733
734 phy_txts = data;
cb646e2b
RC		 735
736 switch (words) { /* fall through in every case */
737 case 3:
738 dp83640->edata.sec_hi = phy_txts->sec_hi;
739 case 2:
740 dp83640->edata.sec_lo = phy_txts->sec_lo;
741 case 1:
742 dp83640->edata.ns_hi = phy_txts->ns_hi;
743 case 0:
744 dp83640->edata.ns_lo = phy_txts->ns_lo;
745 }
746
49b3fd4a
RC		 747 if (ext_status) {
748 parsed = words + 2;
749 } else {
750 parsed = words + 1;
751 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
752 ext_status = exts_chan_to_edata(i);
753 }
754
cb646e2b 755 event.type = PTP_CLOCK_EXTTS;
cb646e2b
RC		 756 event.timestamp = phy2txts(&dp83640->edata);
757
49b3fd4a
RC		 758 for (i = 0; i < N_EXT_TS; i++) {
759 if (ext_status & exts_chan_to_edata(i)) {
760 event.index = i;
761 ptp_clock_event(dp83640->clock->ptp_clock, &event);
762 }
763 }
2331038a 764
49b3fd4a 765 return parsed * sizeof(u16);
cb646e2b
RC		 766}
767
768static void decode_rxts(struct dp83640_private *dp83640,
769 struct phy_rxts *phy_rxts)
770{
771 struct rxts *rxts;
772 unsigned long flags;
773
774 spin_lock_irqsave(&dp83640->rx_lock, flags);
775
776 prune_rx_ts(dp83640);
777
778 if (list_empty(&dp83640->rxpool)) {
8d242488 779 pr_debug("rx timestamp pool is empty\n");
cb646e2b
RC		 780 goto out;
781 }
782 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
783 list_del_init(&rxts->list);
784 phy2rxts(phy_rxts, rxts);
785 list_add_tail(&rxts->list, &dp83640->rxts);
786out:
787 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
788}
789
790static void decode_txts(struct dp83640_private *dp83640,
791 struct phy_txts *phy_txts)
792{
793 struct skb_shared_hwtstamps shhwtstamps;
794 struct sk_buff *skb;
795 u64 ns;
796
797 /* We must already have the skb that triggered this. */
798
799 skb = skb_dequeue(&dp83640->tx_queue);
800
801 if (!skb) {
8d242488 802 pr_debug("have timestamp but tx_queue empty\n");
cb646e2b
RC		 803 return;
804 }
805 ns = phy2txts(phy_txts);
806 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
807 shhwtstamps.hwtstamp = ns_to_ktime(ns);
808 skb_complete_tx_timestamp(skb, &shhwtstamps);
809}
810
811static void decode_status_frame(struct dp83640_private *dp83640,
812 struct sk_buff *skb)
813{
814 struct phy_rxts *phy_rxts;
815 struct phy_txts *phy_txts;
816 u8 *ptr;
817 int len, size;
818 u16 ests, type;
819
820 ptr = skb->data + 2;
821
822 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
823
824 type = *(u16 *)ptr;
825 ests = type & 0x0fff;
826 type = type & 0xf000;
827 len -= sizeof(type);
828 ptr += sizeof(type);
829
830 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
831
832 phy_rxts = (struct phy_rxts *) ptr;
833 decode_rxts(dp83640, phy_rxts);
834 size = sizeof(*phy_rxts);
835
836 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
837
838 phy_txts = (struct phy_txts *) ptr;
839 decode_txts(dp83640, phy_txts);
840 size = sizeof(*phy_txts);
841
842 } else if (PSF_EVNT == type && len >= sizeof(*phy_txts)) {
843
2331038a 844 size = decode_evnt(dp83640, ptr, ests);
cb646e2b
RC		 845
846 } else {
847 size = 0;
848 break;
849 }
850 ptr += size;
851 }
852}
853
dccaa9e0
RC		 854static int is_sync(struct sk_buff *skb, int type)
855{
856 u8 *data = skb->data, *msgtype;
857 unsigned int offset = 0;
858
ae5c6c6d
SS		 859 if (type & PTP_CLASS_VLAN)
860 offset += VLAN_HLEN;
861
862 switch (type & PTP_CLASS_PMASK) {
863 case PTP_CLASS_IPV4:
864 offset += ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
dccaa9e0 865 break;
ae5c6c6d
SS		 866 case PTP_CLASS_IPV6:
867 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
dccaa9e0 868 break;
ae5c6c6d
SS		 869 case PTP_CLASS_L2:
870 offset += ETH_HLEN;
dccaa9e0
RC		 871 break;
872 default:
873 return 0;
874 }
875
876 if (type & PTP_CLASS_V1)
877 offset += OFF_PTP_CONTROL;
878
879 if (skb->len < offset + 1)
880 return 0;
881
882 msgtype = data + offset;
883
884 return (*msgtype & 0xf) == 0;
885}
886
cb646e2b
RC		 887static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
888{
889 u16 *seqid;
ae5c6c6d 890 unsigned int offset = 0;
cb646e2b
RC		 891 u8 *msgtype, *data = skb_mac_header(skb);
892
893 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
894
ae5c6c6d
SS		 895 if (type & PTP_CLASS_VLAN)
896 offset += VLAN_HLEN;
897
898 switch (type & PTP_CLASS_PMASK) {
899 case PTP_CLASS_IPV4:
900 offset += ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
cb646e2b 901 break;
ae5c6c6d
SS		 902 case PTP_CLASS_IPV6:
903 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
cb646e2b 904 break;
ae5c6c6d
SS		 905 case PTP_CLASS_L2:
906 offset += ETH_HLEN;
cb646e2b
RC		 907 break;
908 default:
909 return 0;
910 }
911
912 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
913 return 0;
914
915 if (unlikely(type & PTP_CLASS_V1))
916 msgtype = data + offset + OFF_PTP_CONTROL;
917 else
918 msgtype = data + offset;
919
920 seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
921
dd61d963
FF		 922 return rxts->msgtype == (*msgtype & 0xf) &&
923 rxts->seqid == ntohs(*seqid);
cb646e2b
RC		 924}
925
926static void dp83640_free_clocks(void)
927{
928 struct dp83640_clock *clock;
929 struct list_head *this, *next;
930
931 mutex_lock(&phyter_clocks_lock);
932
933 list_for_each_safe(this, next, &phyter_clocks) {
934 clock = list_entry(this, struct dp83640_clock, list);
935 if (!list_empty(&clock->phylist)) {
8d242488 936 pr_warn("phy list non-empty while unloading\n");
cb646e2b
RC		 937 BUG();
938 }
939 list_del(&clock->list);
940 mutex_destroy(&clock->extreg_lock);
941 mutex_destroy(&clock->clock_lock);
942 put_device(&clock->bus->dev);
86dd3612 943 kfree(clock->caps.pin_config);
cb646e2b
RC		 944 kfree(clock);
945 }
946
947 mutex_unlock(&phyter_clocks_lock);
948}
949
950static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
951{
952 INIT_LIST_HEAD(&clock->list);
953 clock->bus = bus;
954 mutex_init(&clock->extreg_lock);
955 mutex_init(&clock->clock_lock);
956 INIT_LIST_HEAD(&clock->phylist);
957 clock->caps.owner = THIS_MODULE;
958 sprintf(clock->caps.name, "dp83640 timer");
959 clock->caps.max_adj = 1953124;
960 clock->caps.n_alarm = 0;
961 clock->caps.n_ext_ts = N_EXT_TS;
ad01577a 962 clock->caps.n_per_out = N_PER_OUT;
86dd3612 963 clock->caps.n_pins = DP83640_N_PINS;
cb646e2b
RC		 964 clock->caps.pps = 0;
965 clock->caps.adjfreq = ptp_dp83640_adjfreq;
966 clock->caps.adjtime = ptp_dp83640_adjtime;
967 clock->caps.gettime = ptp_dp83640_gettime;
968 clock->caps.settime = ptp_dp83640_settime;
969 clock->caps.enable = ptp_dp83640_enable;
86dd3612
RC		 970 clock->caps.verify = ptp_dp83640_verify;
971 /*
972 * Convert the module param defaults into a dynamic pin configuration.
973 */
974 dp83640_gpio_defaults(clock->caps.pin_config);
cb646e2b
RC		 975 /*
976 * Get a reference to this bus instance.
977 */
978 get_device(&bus->dev);
979}
980
981static int choose_this_phy(struct dp83640_clock *clock,
982 struct phy_device *phydev)
983{
984 if (chosen_phy == -1 && !clock->chosen)
985 return 1;
986
987 if (chosen_phy == phydev->addr)
988 return 1;
989
990 return 0;
991}
992
993static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
994{
995 if (clock)
996 mutex_lock(&clock->clock_lock);
997 return clock;
998}
999
1000/*
1001 * Look up and lock a clock by bus instance.
1002 * If there is no clock for this bus, then create it first.
1003 */
1004static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
1005{
1006 struct dp83640_clock *clock = NULL, *tmp;
1007 struct list_head *this;
1008
1009 mutex_lock(&phyter_clocks_lock);
1010
1011 list_for_each(this, &phyter_clocks) {
1012 tmp = list_entry(this, struct dp83640_clock, list);
1013 if (tmp->bus == bus) {
1014 clock = tmp;
1015 break;
1016 }
1017 }
1018 if (clock)
1019 goto out;
1020
1021 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
1022 if (!clock)
1023 goto out;
1024
86dd3612
RC		 1025 clock->caps.pin_config = kzalloc(sizeof(struct ptp_pin_desc) *
1026 DP83640_N_PINS, GFP_KERNEL);
1027 if (!clock->caps.pin_config) {
1028 kfree(clock);
1029 clock = NULL;
1030 goto out;
1031 }
cb646e2b
RC		 1032 dp83640_clock_init(clock, bus);
1033 list_add_tail(&phyter_clocks, &clock->list);
1034out:
1035 mutex_unlock(&phyter_clocks_lock);
1036
1037 return dp83640_clock_get(clock);
1038}
1039
1040static void dp83640_clock_put(struct dp83640_clock *clock)
1041{
1042 mutex_unlock(&clock->clock_lock);
1043}
1044
1045static int dp83640_probe(struct phy_device *phydev)
1046{
1047 struct dp83640_clock *clock;
1048 struct dp83640_private *dp83640;
1049 int err = -ENOMEM, i;
1050
1051 if (phydev->addr == BROADCAST_ADDR)
1052 return 0;
1053
1054 clock = dp83640_clock_get_bus(phydev->bus);
1055 if (!clock)
1056 goto no_clock;
1057
1058 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
1059 if (!dp83640)
1060 goto no_memory;
1061
1062 dp83640->phydev = phydev;
1063 INIT_WORK(&dp83640->ts_work, rx_timestamp_work);
1064
1065 INIT_LIST_HEAD(&dp83640->rxts);
1066 INIT_LIST_HEAD(&dp83640->rxpool);
1067 for (i = 0; i < MAX_RXTS; i++)
1068 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
1069
1070 phydev->priv = dp83640;
1071
1072 spin_lock_init(&dp83640->rx_lock);
1073 skb_queue_head_init(&dp83640->rx_queue);
1074 skb_queue_head_init(&dp83640->tx_queue);
1075
1076 dp83640->clock = clock;
1077
1078 if (choose_this_phy(clock, phydev)) {
1079 clock->chosen = dp83640;
1ef76158 1080 clock->ptp_clock = ptp_clock_register(&clock->caps, &phydev->dev);
cb646e2b
RC		 1081 if (IS_ERR(clock->ptp_clock)) {
1082 err = PTR_ERR(clock->ptp_clock);
1083 goto no_register;
1084 }
1085 } else
1086 list_add_tail(&dp83640->list, &clock->phylist);
1087
cb646e2b
RC		 1088 dp83640_clock_put(clock);
1089 return 0;
1090
1091no_register:
1092 clock->chosen = NULL;
1093 kfree(dp83640);
1094no_memory:
1095 dp83640_clock_put(clock);
1096no_clock:
1097 return err;
1098}
1099
1100static void dp83640_remove(struct phy_device *phydev)
1101{
1102 struct dp83640_clock *clock;
1103 struct list_head *this, *next;
1104 struct dp83640_private *tmp, *dp83640 = phydev->priv;
8b3408f8 1105 struct sk_buff *skb;
cb646e2b
RC		 1106
1107 if (phydev->addr == BROADCAST_ADDR)
1108 return;
1109
1110 enable_status_frames(phydev, false);
1111 cancel_work_sync(&dp83640->ts_work);
1112
8b3408f8
RC		 1113 while ((skb = skb_dequeue(&dp83640->rx_queue)) != NULL)
1114 kfree_skb(skb);
1115
1116 while ((skb = skb_dequeue(&dp83640->tx_queue)) != NULL)
1117 skb_complete_tx_timestamp(skb, NULL);
1118
cb646e2b
RC		 1119 clock = dp83640_clock_get(dp83640->clock);
1120
1121 if (dp83640 == clock->chosen) {
1122 ptp_clock_unregister(clock->ptp_clock);
1123 clock->chosen = NULL;
1124 } else {
1125 list_for_each_safe(this, next, &clock->phylist) {
1126 tmp = list_entry(this, struct dp83640_private, list);
1127 if (tmp == dp83640) {
1128 list_del_init(&tmp->list);
1129 break;
1130 }
1131 }
1132 }
1133
1134 dp83640_clock_put(clock);
1135 kfree(dp83640);
1136}
1137
62ad9684
SS		 1138static int dp83640_config_init(struct phy_device *phydev)
1139{
602b1099
SS		 1140 struct dp83640_private *dp83640 = phydev->priv;
1141 struct dp83640_clock *clock = dp83640->clock;
1142
1143 if (clock->chosen && !list_empty(&clock->phylist))
1144 recalibrate(clock);
1145 else
1146 enable_broadcast(phydev, clock->page, 1);
1147
62ad9684
SS		 1148 enable_status_frames(phydev, true);
1149 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
1150 return 0;
1151}
1152
1642182e
SG		 1153static int dp83640_ack_interrupt(struct phy_device *phydev)
1154{
1155 int err = phy_read(phydev, MII_DP83640_MISR);
1156
1157 if (err < 0)
1158 return err;
1159
1160 return 0;
1161}
1162
1163static int dp83640_config_intr(struct phy_device *phydev)
1164{
1165 int micr;
1166 int misr;
1167 int err;
1168
1169 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1170 misr = phy_read(phydev, MII_DP83640_MISR);
1171 if (misr < 0)
1172 return misr;
1173 misr |=
1174 (MII_DP83640_MISR_ANC_INT_EN |
1175 MII_DP83640_MISR_DUP_INT_EN |
1176 MII_DP83640_MISR_SPD_INT_EN |
1177 MII_DP83640_MISR_LINK_INT_EN);
1178 err = phy_write(phydev, MII_DP83640_MISR, misr);
1179 if (err < 0)
1180 return err;
1181
1182 micr = phy_read(phydev, MII_DP83640_MICR);
1183 if (micr < 0)
1184 return micr;
1185 micr |=
1186 (MII_DP83640_MICR_OE |
1187 MII_DP83640_MICR_IE);
1188 return phy_write(phydev, MII_DP83640_MICR, micr);
1189 } else {
1190 micr = phy_read(phydev, MII_DP83640_MICR);
1191 if (micr < 0)
1192 return micr;
1193 micr &=
1194 ~(MII_DP83640_MICR_OE |
1195 MII_DP83640_MICR_IE);
1196 err = phy_write(phydev, MII_DP83640_MICR, micr);
1197 if (err < 0)
1198 return err;
1199
1200 misr = phy_read(phydev, MII_DP83640_MISR);
1201 if (misr < 0)
1202 return misr;
1203 misr &=
1204 ~(MII_DP83640_MISR_ANC_INT_EN |
1205 MII_DP83640_MISR_DUP_INT_EN |
1206 MII_DP83640_MISR_SPD_INT_EN |
1207 MII_DP83640_MISR_LINK_INT_EN);
1208 return phy_write(phydev, MII_DP83640_MISR, misr);
1209 }
1210}
1211
cb646e2b
RC		 1212static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
1213{
1214 struct dp83640_private *dp83640 = phydev->priv;
1215 struct hwtstamp_config cfg;
1216 u16 txcfg0, rxcfg0;
1217
1218 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1219 return -EFAULT;
1220
1221 if (cfg.flags) /* reserved for future extensions */
1222 return -EINVAL;
1223
dccaa9e0 1224 if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC)
cb646e2b 1225 return -ERANGE;
dccaa9e0
RC		 1226
1227 dp83640->hwts_tx_en = cfg.tx_type;
cb646e2b
RC		 1228
1229 switch (cfg.rx_filter) {
1230 case HWTSTAMP_FILTER_NONE:
1231 dp83640->hwts_rx_en = 0;
1232 dp83640->layer = 0;
1233 dp83640->version = 0;
1234 break;
1235 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1236 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1237 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1238 dp83640->hwts_rx_en = 1;
1239 dp83640->layer = LAYER4;
1240 dp83640->version = 1;
1241 break;
1242 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1243 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1244 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1245 dp83640->hwts_rx_en = 1;
1246 dp83640->layer = LAYER4;
1247 dp83640->version = 2;
1248 break;
1249 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1250 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1251 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1252 dp83640->hwts_rx_en = 1;
1253 dp83640->layer = LAYER2;
1254 dp83640->version = 2;
1255 break;
1256 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1257 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1258 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1259 dp83640->hwts_rx_en = 1;
1260 dp83640->layer = LAYER4|LAYER2;
1261 dp83640->version = 2;
1262 break;
1263 default:
1264 return -ERANGE;
1265 }
1266
1267 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1268 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1269
1270 if (dp83640->layer & LAYER2) {
1271 txcfg0 |= TX_L2_EN;
1272 rxcfg0 |= RX_L2_EN;
1273 }
1274 if (dp83640->layer & LAYER4) {
1275 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
1276 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
1277 }
1278
1279 if (dp83640->hwts_tx_en)
1280 txcfg0 |= TX_TS_EN;
1281
dccaa9e0
RC		 1282 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)
1283 txcfg0 |= SYNC_1STEP | CHK_1STEP;
1284
cb646e2b
RC		 1285 if (dp83640->hwts_rx_en)
1286 rxcfg0 |= RX_TS_EN;
1287
1288 mutex_lock(&dp83640->clock->extreg_lock);
1289
cb646e2b
RC		 1290 ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0);
1291 ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0);
1292
1293 mutex_unlock(&dp83640->clock->extreg_lock);
1294
1295 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1296}
1297
1298static void rx_timestamp_work(struct work_struct *work)
1299{
1300 struct dp83640_private *dp83640 =
1301 container_of(work, struct dp83640_private, ts_work);
1302 struct list_head *this, *next;
1303 struct rxts *rxts;
1304 struct skb_shared_hwtstamps *shhwtstamps;
1305 struct sk_buff *skb;
1306 unsigned int type;
1307 unsigned long flags;
1308
1309 /* Deliver each deferred packet, with or without a time stamp. */
1310
1311 while ((skb = skb_dequeue(&dp83640->rx_queue)) != NULL) {
1312 type = SKB_PTP_TYPE(skb);
1313 spin_lock_irqsave(&dp83640->rx_lock, flags);
1314 list_for_each_safe(this, next, &dp83640->rxts) {
1315 rxts = list_entry(this, struct rxts, list);
1316 if (match(skb, type, rxts)) {
1317 shhwtstamps = skb_hwtstamps(skb);
1318 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1319 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1320 list_del_init(&rxts->list);
1321 list_add(&rxts->list, &dp83640->rxpool);
1322 break;
1323 }
1324 }
1325 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
72092cc4 1326 netif_rx_ni(skb);
cb646e2b
RC		 1327 }
1328
1329 /* Clear out expired time stamps. */
1330
1331 spin_lock_irqsave(&dp83640->rx_lock, flags);
1332 prune_rx_ts(dp83640);
1333 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1334}
1335
1336static bool dp83640_rxtstamp(struct phy_device *phydev,
1337 struct sk_buff *skb, int type)
1338{
1339 struct dp83640_private *dp83640 = phydev->priv;
1340
1341 if (!dp83640->hwts_rx_en)
1342 return false;
1343
1344 if (is_status_frame(skb, type)) {
1345 decode_status_frame(dp83640, skb);
ae6e86b7
RC		 1346 kfree_skb(skb);
1347 return true;
cb646e2b
RC		 1348 }
1349
1350 SKB_PTP_TYPE(skb) = type;
1351 skb_queue_tail(&dp83640->rx_queue, skb);
1352 schedule_work(&dp83640->ts_work);
1353
1354 return true;
1355}
1356
1357static void dp83640_txtstamp(struct phy_device *phydev,
1358 struct sk_buff *skb, int type)
1359{
1360 struct dp83640_private *dp83640 = phydev->priv;
1361
dccaa9e0
RC		 1362 switch (dp83640->hwts_tx_en) {
1363
1364 case HWTSTAMP_TX_ONESTEP_SYNC:
1365 if (is_sync(skb, type)) {
f5ff7cd1 1366 skb_complete_tx_timestamp(skb, NULL);
dccaa9e0
RC		 1367 return;
1368 }
1369 /* fall through */
1370 case HWTSTAMP_TX_ON:
e2e2f51d 1371 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
dccaa9e0
RC		 1372 skb_queue_tail(&dp83640->tx_queue, skb);
1373 schedule_work(&dp83640->ts_work);
1374 break;
1375
1376 case HWTSTAMP_TX_OFF:
1377 default:
f5ff7cd1 1378 skb_complete_tx_timestamp(skb, NULL);
dccaa9e0 1379 break;
cb646e2b 1380 }
cb646e2b
RC		 1381}
1382
7dff3499
RC		 1383static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info)
1384{
1385 struct dp83640_private *dp83640 = dev->priv;
1386
1387 info->so_timestamping =
1388 SOF_TIMESTAMPING_TX_HARDWARE |
1389 SOF_TIMESTAMPING_RX_HARDWARE |
1390 SOF_TIMESTAMPING_RAW_HARDWARE;
1391 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
1392 info->tx_types =
1393 (1 << HWTSTAMP_TX_OFF) |
1394 (1 << HWTSTAMP_TX_ON) |
1395 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
1396 info->rx_filters =
1397 (1 << HWTSTAMP_FILTER_NONE) |
1398 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1399 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1400 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
1401 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1402 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
1403 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
1404 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1405 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
1406 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
1407 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
1408 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
1409 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ);
1410 return 0;
1411}
1412
cb646e2b
RC		 1413static struct phy_driver dp83640_driver = {
1414 .phy_id = DP83640_PHY_ID,
1415 .phy_id_mask = 0xfffffff0,
1416 .name = "NatSemi DP83640",
1417 .features = PHY_BASIC_FEATURES,
1642182e 1418 .flags = PHY_HAS_INTERRUPT,
cb646e2b
RC		 1419 .probe = dp83640_probe,
1420 .remove = dp83640_remove,
62ad9684 1421 .config_init = dp83640_config_init,
cb646e2b
RC		 1422 .config_aneg = genphy_config_aneg,
1423 .read_status = genphy_read_status,
1642182e
SG		 1424 .ack_interrupt = dp83640_ack_interrupt,
1425 .config_intr = dp83640_config_intr,
7dff3499 1426 .ts_info = dp83640_ts_info,
cb646e2b
RC		 1427 .hwtstamp = dp83640_hwtstamp,
1428 .rxtstamp = dp83640_rxtstamp,
1429 .txtstamp = dp83640_txtstamp,
1430 .driver = {.owner = THIS_MODULE,}
1431};
1432
1433static int __init dp83640_init(void)
1434{
1435 return phy_driver_register(&dp83640_driver);
1436}
1437
1438static void __exit dp83640_exit(void)
1439{
1440 dp83640_free_clocks();
1441 phy_driver_unregister(&dp83640_driver);
1442}
1443
1444MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
fbf4b934 1445MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
cb646e2b
RC		 1446MODULE_LICENSE("GPL");
1447
1448module_init(dp83640_init);
1449module_exit(dp83640_exit);
1450
86ff9baa 1451static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
cb646e2b
RC		 1452 { DP83640_PHY_ID, 0xfffffff0 },
1453 { }
1454};
1455
1456MODULE_DEVICE_TABLE(mdio, dp83640_tbl);
Linux kernel - Deliverables
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