[deliverable/linux.git] / drivers / net / phy / icplus.c

/*
 * Driver for ICPlus PHYs
 *
 * Copyright (c) 2007 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/unistd.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/phy.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>

MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IP101G/IC1001 PHY drivers");
MODULE_AUTHOR("Michael Barkowski");
MODULE_LICENSE("GPL");

/* IP101A/G - IP1001 */
#define IP10XX_SPEC_CTRL_STATUS		16	/* Spec. Control Register */
#define IP1001_SPEC_CTRL_STATUS_2	20	/* IP1001 Spec. Control Reg 2 */
#define IP1001_PHASE_SEL_MASK		3	/* IP1001 RX/TXPHASE_SEL */
#define IP1001_APS_ON			11	/* IP1001 APS Mode  bit */
#define IP101A_G_APS_ON			2	/* IP101A/G APS Mode bit */
#define IP101A_G_IRQ_CONF_STATUS	0x11	/* Conf Info IRQ & Status Reg */
#define	IP101A_G_IRQ_PIN_USED		(1<<15) /* INTR pin used */
#define	IP101A_G_IRQ_DEFAULT		IP101A_G_IRQ_PIN_USED

static int ip175c_config_init(struct phy_device *phydev)
{
	int err, i;
	static int full_reset_performed = 0;

	if (full_reset_performed == 0) {

		/* master reset */
		err = mdiobus_write(phydev->bus, 30, 0, 0x175c);
		if (err < 0)
			return err;

		/* ensure no bus delays overlap reset period */
		err = mdiobus_read(phydev->bus, 30, 0);

		/* data sheet specifies reset period is 2 msec */
		mdelay(2);

		/* enable IP175C mode */
		err = mdiobus_write(phydev->bus, 29, 31, 0x175c);
		if (err < 0)
			return err;

		/* Set MII0 speed and duplex (in PHY mode) */
		err = mdiobus_write(phydev->bus, 29, 22, 0x420);
		if (err < 0)
			return err;

		/* reset switch ports */
		for (i = 0; i < 5; i++) {
			err = mdiobus_write(phydev->bus, i,
					    MII_BMCR, BMCR_RESET);
			if (err < 0)
				return err;
		}

		for (i = 0; i < 5; i++)
			err = mdiobus_read(phydev->bus, i, MII_BMCR);

		mdelay(2);

		full_reset_performed = 1;
	}

	if (phydev->addr != 4) {
		phydev->state = PHY_RUNNING;
		phydev->speed = SPEED_100;
		phydev->duplex = DUPLEX_FULL;
		phydev->link = 1;
		netif_carrier_on(phydev->attached_dev);
	}

	return 0;
}

static int ip1xx_reset(struct phy_device *phydev)
{
	int bmcr;

	/* Software Reset PHY */
	bmcr = phy_read(phydev, MII_BMCR);
	if (bmcr < 0)
		return bmcr;
	bmcr |= BMCR_RESET;
	bmcr = phy_write(phydev, MII_BMCR, bmcr);
	if (bmcr < 0)
		return bmcr;

	do {
		bmcr = phy_read(phydev, MII_BMCR);
		if (bmcr < 0)
			return bmcr;
	} while (bmcr & BMCR_RESET);

	return 0;
}

static int ip1001_config_init(struct phy_device *phydev)
{
	int c;

	c = ip1xx_reset(phydev);
	if (c < 0)
		return c;

	/* Enable Auto Power Saving mode */
	c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
	if (c < 0)
		return c;
	c |= IP1001_APS_ON;
	c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
	if (c < 0)
		return c;

	/* INTR pin used: speed/link/duplex will cause an interrupt */
	c = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, IP101A_G_IRQ_DEFAULT);
	if (c < 0)
		return c;

	if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
		/* Additional delay (2ns) used to adjust RX clock phase
		 * at RGMII interface */
		c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
		if (c < 0)
			return c;

		c |= IP1001_PHASE_SEL_MASK;
		c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
		if (c < 0)
			return c;
	}

	return 0;
}

static int ip101a_g_config_init(struct phy_device *phydev)
{
	int c;

	c = ip1xx_reset(phydev);
	if (c < 0)
		return c;

	/* Enable Auto Power Saving mode */
	c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
	c |= IP101A_G_APS_ON;

	return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
}

static int ip175c_read_status(struct phy_device *phydev)
{
	if (phydev->addr == 4) /* WAN port */
		genphy_read_status(phydev);
	else
		/* Don't need to read status for switch ports */
		phydev->irq = PHY_IGNORE_INTERRUPT;

	return 0;
}

static int ip175c_config_aneg(struct phy_device *phydev)
{
	if (phydev->addr == 4) /* WAN port */
		genphy_config_aneg(phydev);

	return 0;
}

static int ip101a_g_ack_interrupt(struct phy_device *phydev)
{
	int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
	if (err < 0)
		return err;

	return 0;
}

static struct phy_driver icplus_driver[] = {
{
	.phy_id		= 0x02430d80,
	.name		= "ICPlus IP175C",
	.phy_id_mask	= 0x0ffffff0,
	.features	= PHY_BASIC_FEATURES,
	.config_init	= &ip175c_config_init,
	.config_aneg	= &ip175c_config_aneg,
	.read_status	= &ip175c_read_status,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= 0x02430d90,
	.name		= "ICPlus IP1001",
	.phy_id_mask	= 0x0ffffff0,
	.features	= PHY_GBIT_FEATURES | SUPPORTED_Pause |
			  SUPPORTED_Asym_Pause,
	.config_init	= &ip1001_config_init,
	.config_aneg	= &genphy_config_aneg,
	.read_status	= &genphy_read_status,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= 0x02430c54,
	.name		= "ICPlus IP101A/G",
	.phy_id_mask	= 0x0ffffff0,
	.features	= PHY_BASIC_FEATURES | SUPPORTED_Pause |
			  SUPPORTED_Asym_Pause,
	.flags		= PHY_HAS_INTERRUPT,
	.ack_interrupt	= ip101a_g_ack_interrupt,
	.config_init	= &ip101a_g_config_init,
	.config_aneg	= &genphy_config_aneg,
	.read_status	= &genphy_read_status,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
} };

static int __init icplus_init(void)
{
	return phy_drivers_register(icplus_driver,
		ARRAY_SIZE(icplus_driver));
}

static void __exit icplus_exit(void)
{
	phy_drivers_unregister(icplus_driver,
		ARRAY_SIZE(icplus_driver));
}

module_init(icplus_init);
module_exit(icplus_exit);

static struct mdio_device_id __maybe_unused icplus_tbl[] = {
	{ 0x02430d80, 0x0ffffff0 },
	{ 0x02430d90, 0x0ffffff0 },
	{ 0x02430c54, 0x0ffffff0 },
	{ }
};

MODULE_DEVICE_TABLE(mdio, icplus_tbl);
Commit	Line	Data
0cefeeba MB	1	/*
	2	* Driver for ICPlus PHYs
	3	*
	4	* Copyright (c) 2007 Freescale Semiconductor, Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	*/
	12	#include <linux/kernel.h>
	13	#include <linux/string.h>
	14	#include <linux/errno.h>
	15	#include <linux/unistd.h>
0cefeeba MB	16	#include <linux/interrupt.h>
	17	#include <linux/init.h>
	18	#include <linux/delay.h>
	19	#include <linux/netdevice.h>
	20	#include <linux/etherdevice.h>
	21	#include <linux/skbuff.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/mm.h>
	24	#include <linux/module.h>
	25	#include <linux/mii.h>
	26	#include <linux/ethtool.h>
	27	#include <linux/phy.h>
	28
	29	#include <asm/io.h>
	30	#include <asm/irq.h>
	31	#include <asm/uaccess.h>
	32
e3e09f26	33	MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IP101G/IC1001 PHY drivers");
0cefeeba MB	34	MODULE_AUTHOR("Michael Barkowski");
	35	MODULE_LICENSE("GPL");
	36
e3e09f26 GC	37	/* IP101A/G - IP1001 */
	38	#define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
	39	#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
	40	#define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */
	41	#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
	42	#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */
996f7393	43	#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
9ec0db71 GC	44	#define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */
9ec0db71 GC	45	#define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED
9c9b1f24	46
0cefeeba MB	47	static int ip175c_config_init(struct phy_device *phydev)
	48	{
	49	int err, i;
	50	static int full_reset_performed = 0;
	51
	52	if (full_reset_performed == 0) {
	53
	54	/* master reset */
76231e02	55	err = mdiobus_write(phydev->bus, 30, 0, 0x175c);
0cefeeba MB	56	if (err < 0)
	57	return err;
	58
	59	/* ensure no bus delays overlap reset period */
76231e02	60	err = mdiobus_read(phydev->bus, 30, 0);
0cefeeba MB	61
	62	/* data sheet specifies reset period is 2 msec */
	63	mdelay(2);
	64
	65	/* enable IP175C mode */
76231e02	66	err = mdiobus_write(phydev->bus, 29, 31, 0x175c);
0cefeeba MB	67	if (err < 0)
	68	return err;
	69
	70	/* Set MII0 speed and duplex (in PHY mode) */
76231e02	71	err = mdiobus_write(phydev->bus, 29, 22, 0x420);
0cefeeba MB	72	if (err < 0)
	73	return err;
	74
	75	/* reset switch ports */
	76	for (i = 0; i < 5; i++) {
76231e02 DD	77	err = mdiobus_write(phydev->bus, i,
76231e02 DD	78	MII_BMCR, BMCR_RESET);
0cefeeba MB	79	if (err < 0)
	80	return err;
	81	}
	82
	83	for (i = 0; i < 5; i++)
76231e02	84	err = mdiobus_read(phydev->bus, i, MII_BMCR);
0cefeeba MB	85
	86	mdelay(2);
	87
	88	full_reset_performed = 1;
	89	}
	90
	91	if (phydev->addr != 4) {
	92	phydev->state = PHY_RUNNING;
	93	phydev->speed = SPEED_100;
	94	phydev->duplex = DUPLEX_FULL;
	95	phydev->link = 1;
	96	netif_carrier_on(phydev->attached_dev);
	97	}
	98
	99	return 0;
	100	}
	101
9c9b1f24	102	static int ip1xx_reset(struct phy_device *phydev)
377ecca9	103	{
b8e3995a	104	int bmcr;
377ecca9 GC	105
377ecca9 GC	106	/* Software Reset PHY */
9c9b1f24	107	bmcr = phy_read(phydev, MII_BMCR);
b8e3995a DM	108	if (bmcr < 0)
b8e3995a DM	109	return bmcr;
9c9b1f24	110	bmcr \|= BMCR_RESET;
b8e3995a DM	111	bmcr = phy_write(phydev, MII_BMCR, bmcr);
	112	if (bmcr < 0)
	113	return bmcr;
377ecca9 GC	114
377ecca9 GC	115	do {
9c9b1f24	116	bmcr = phy_read(phydev, MII_BMCR);
b8e3995a DM	117	if (bmcr < 0)
b8e3995a DM	118	return bmcr;
9c9b1f24 GC	119	} while (bmcr & BMCR_RESET);
9c9b1f24 GC	120
b8e3995a	121	return 0;
9c9b1f24 GC	122	}
	123
	124	static int ip1001_config_init(struct phy_device *phydev)
	125	{
	126	int c;
	127
	128	c = ip1xx_reset(phydev);
	129	if (c < 0)
	130	return c;
	131
	132	/* Enable Auto Power Saving mode */
	133	c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
b8e3995a DM	134	if (c < 0)
b8e3995a DM	135	return c;
9c9b1f24	136	c \|= IP1001_APS_ON;
b8e3995a	137	c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
9c9b1f24 GC	138	if (c < 0)
9c9b1f24 GC	139	return c;
377ecca9	140
9ec0db71 GC	141	/* INTR pin used: speed/link/duplex will cause an interrupt */
	142	c = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, IP101A_G_IRQ_DEFAULT);
	143	if (c < 0)
	144	return c;
	145
a4886d52 GC	146	if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
	147	/* Additional delay (2ns) used to adjust RX clock phase
	148	* at RGMII interface */
	149	c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
b8e3995a DM	150	if (c < 0)
	151	return c;
	152
a4886d52 GC	153	c \|= IP1001_PHASE_SEL_MASK;
a4886d52 GC	154	c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
b8e3995a DM	155	if (c < 0)
b8e3995a DM	156	return c;
a4886d52	157	}
9c9b1f24	158
b8e3995a	159	return 0;
9c9b1f24 GC	160	}
9c9b1f24 GC	161
e3e09f26	162	static int ip101a_g_config_init(struct phy_device *phydev)
9c9b1f24 GC	163	{
9c9b1f24 GC	164	int c;
377ecca9	165
9c9b1f24 GC	166	c = ip1xx_reset(phydev);
	167	if (c < 0)
	168	return c;
	169
	170	/* Enable Auto Power Saving mode */
	171	c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
e3e09f26	172	c \|= IP101A_G_APS_ON;
b3300146 SK	173
b3300146 SK	174	return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
377ecca9 GC	175	}
377ecca9 GC	176
0cefeeba MB	177	static int ip175c_read_status(struct phy_device *phydev)
	178	{
	179	if (phydev->addr == 4) /* WAN port */
	180	genphy_read_status(phydev);
	181	else
	182	/* Don't need to read status for switch ports */
	183	phydev->irq = PHY_IGNORE_INTERRUPT;
	184
	185	return 0;
	186	}
	187
	188	static int ip175c_config_aneg(struct phy_device *phydev)
	189	{
	190	if (phydev->addr == 4) /* WAN port */
	191	genphy_config_aneg(phydev);
	192
	193	return 0;
	194	}
	195
996f7393 GC	196	static int ip101a_g_ack_interrupt(struct phy_device *phydev)
	197	{
	198	int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
	199	if (err < 0)
	200	return err;
	201
	202	return 0;
	203	}
	204
d5bf9071 CH	205	static struct phy_driver icplus_driver[] = {
d5bf9071 CH	206	{
0cefeeba MB	207	.phy_id = 0x02430d80,
	208	.name = "ICPlus IP175C",
	209	.phy_id_mask = 0x0ffffff0,
	210	.features = PHY_BASIC_FEATURES,
	211	.config_init = &ip175c_config_init,
	212	.config_aneg = &ip175c_config_aneg,
	213	.read_status = &ip175c_read_status,
dab10863 GC	214	.suspend = genphy_suspend,
dab10863 GC	215	.resume = genphy_resume,
0cefeeba	216	.driver = { .owner = THIS_MODULE,},
d5bf9071	217	}, {
377ecca9 GC	218	.phy_id = 0x02430d90,
	219	.name = "ICPlus IP1001",
	220	.phy_id_mask = 0x0ffffff0,
	221	.features = PHY_GBIT_FEATURES \| SUPPORTED_Pause \|
	222	SUPPORTED_Asym_Pause,
	223	.config_init = &ip1001_config_init,
	224	.config_aneg = &genphy_config_aneg,
	225	.read_status = &genphy_read_status,
	226	.suspend = genphy_suspend,
	227	.resume = genphy_resume,
	228	.driver = { .owner = THIS_MODULE,},
d5bf9071	229	}, {
9c9b1f24	230	.phy_id = 0x02430c54,
e3e09f26	231	.name = "ICPlus IP101A/G",
9c9b1f24 GC	232	.phy_id_mask = 0x0ffffff0,
	233	.features = PHY_BASIC_FEATURES \| SUPPORTED_Pause \|
	234	SUPPORTED_Asym_Pause,
e3e09f26	235	.flags = PHY_HAS_INTERRUPT,
996f7393	236	.ack_interrupt = ip101a_g_ack_interrupt,
e3e09f26	237	.config_init = &ip101a_g_config_init,
9c9b1f24 GC	238	.config_aneg = &genphy_config_aneg,
	239	.read_status = &genphy_read_status,
	240	.suspend = genphy_suspend,
	241	.resume = genphy_resume,
	242	.driver = { .owner = THIS_MODULE,},
d5bf9071	243	} };
9c9b1f24	244
377ecca9	245	static int __init icplus_init(void)
0cefeeba	246	{
d5bf9071 CH	247	return phy_drivers_register(icplus_driver,
d5bf9071 CH	248	ARRAY_SIZE(icplus_driver));
0cefeeba MB	249	}
0cefeeba MB	250
377ecca9	251	static void __exit icplus_exit(void)
0cefeeba	252	{
d5bf9071 CH	253	phy_drivers_unregister(icplus_driver,
d5bf9071 CH	254	ARRAY_SIZE(icplus_driver));
0cefeeba MB	255	}
0cefeeba MB	256
377ecca9 GC	257	module_init(icplus_init);
377ecca9 GC	258	module_exit(icplus_exit);
4e4f10f6	259
cf93c945	260	static struct mdio_device_id __maybe_unused icplus_tbl[] = {
4e4f10f6	261	{ 0x02430d80, 0x0ffffff0 },
377ecca9	262	{ 0x02430d90, 0x0ffffff0 },
e3e09f26	263	{ 0x02430c54, 0x0ffffff0 },
4e4f10f6 DW	264	{ }
	265	};
	266
	267	MODULE_DEVICE_TABLE(mdio, icplus_tbl);