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00db8189 AF |
1 | /* |
2 | * drivers/net/phy/lxt.c | |
3 | * | |
4 | * Driver for Intel LXT PHYs | |
5 | * | |
6 | * Author: Andy Fleming | |
7 | * | |
8 | * Copyright (c) 2004 Freescale Semiconductor, Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | * | |
15 | */ | |
00db8189 | 16 | #include <linux/kernel.h> |
00db8189 AF |
17 | #include <linux/string.h> |
18 | #include <linux/errno.h> | |
19 | #include <linux/unistd.h> | |
00db8189 AF |
20 | #include <linux/interrupt.h> |
21 | #include <linux/init.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/netdevice.h> | |
24 | #include <linux/etherdevice.h> | |
25 | #include <linux/skbuff.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/mm.h> | |
28 | #include <linux/module.h> | |
00db8189 AF |
29 | #include <linux/mii.h> |
30 | #include <linux/ethtool.h> | |
31 | #include <linux/phy.h> | |
32 | ||
33 | #include <asm/io.h> | |
34 | #include <asm/irq.h> | |
35 | #include <asm/uaccess.h> | |
36 | ||
37 | /* The Level one LXT970 is used by many boards */ | |
38 | ||
39 | #define MII_LXT970_IER 17 /* Interrupt Enable Register */ | |
40 | ||
41 | #define MII_LXT970_IER_IEN 0x0002 | |
42 | ||
43 | #define MII_LXT970_ISR 18 /* Interrupt Status Register */ | |
44 | ||
45 | #define MII_LXT970_CONFIG 19 /* Configuration Register */ | |
46 | ||
47 | /* ------------------------------------------------------------------------- */ | |
48 | /* The Level one LXT971 is used on some of my custom boards */ | |
49 | ||
50 | /* register definitions for the 971 */ | |
51 | #define MII_LXT971_IER 18 /* Interrupt Enable Register */ | |
52 | #define MII_LXT971_IER_IEN 0x00f2 | |
53 | ||
54 | #define MII_LXT971_ISR 19 /* Interrupt Status Register */ | |
55 | ||
e13647c1 RC |
56 | /* register definitions for the 973 */ |
57 | #define MII_LXT973_PCR 16 /* Port Configuration Register */ | |
58 | #define PCR_FIBER_SELECT 1 | |
00db8189 AF |
59 | |
60 | MODULE_DESCRIPTION("Intel LXT PHY driver"); | |
61 | MODULE_AUTHOR("Andy Fleming"); | |
62 | MODULE_LICENSE("GPL"); | |
63 | ||
64 | static int lxt970_ack_interrupt(struct phy_device *phydev) | |
65 | { | |
66 | int err; | |
67 | ||
68 | err = phy_read(phydev, MII_BMSR); | |
69 | ||
70 | if (err < 0) | |
71 | return err; | |
72 | ||
73 | err = phy_read(phydev, MII_LXT970_ISR); | |
74 | ||
75 | if (err < 0) | |
76 | return err; | |
77 | ||
78 | return 0; | |
79 | } | |
80 | ||
81 | static int lxt970_config_intr(struct phy_device *phydev) | |
82 | { | |
5df47d5e | 83 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) |
04e6233d | 84 | return phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN); |
00db8189 | 85 | else |
04e6233d | 86 | return phy_write(phydev, MII_LXT970_IER, 0); |
00db8189 AF |
87 | } |
88 | ||
89 | static int lxt970_config_init(struct phy_device *phydev) | |
90 | { | |
c8396d84 | 91 | return phy_write(phydev, MII_LXT970_CONFIG, 0); |
00db8189 AF |
92 | } |
93 | ||
94 | ||
95 | static int lxt971_ack_interrupt(struct phy_device *phydev) | |
96 | { | |
97 | int err = phy_read(phydev, MII_LXT971_ISR); | |
98 | ||
99 | if (err < 0) | |
100 | return err; | |
101 | ||
102 | return 0; | |
103 | } | |
104 | ||
105 | static int lxt971_config_intr(struct phy_device *phydev) | |
106 | { | |
5df47d5e | 107 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) |
04e6233d | 108 | return phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN); |
00db8189 | 109 | else |
04e6233d | 110 | return phy_write(phydev, MII_LXT971_IER, 0); |
00db8189 AF |
111 | } |
112 | ||
871d1d6b LC |
113 | /* |
114 | * A2 version of LXT973 chip has an ERRATA: it randomly return the contents | |
115 | * of the previous even register when you read a odd register regularly | |
116 | */ | |
117 | ||
118 | static int lxt973a2_update_link(struct phy_device *phydev) | |
119 | { | |
120 | int status; | |
121 | int control; | |
122 | int retry = 8; /* we try 8 times */ | |
123 | ||
124 | /* Do a fake read */ | |
125 | status = phy_read(phydev, MII_BMSR); | |
126 | ||
127 | if (status < 0) | |
128 | return status; | |
129 | ||
130 | control = phy_read(phydev, MII_BMCR); | |
131 | if (control < 0) | |
132 | return control; | |
133 | ||
134 | do { | |
135 | /* Read link and autonegotiation status */ | |
136 | status = phy_read(phydev, MII_BMSR); | |
137 | } while (status >= 0 && retry-- && status == control); | |
138 | ||
139 | if (status < 0) | |
140 | return status; | |
141 | ||
142 | if ((status & BMSR_LSTATUS) == 0) | |
143 | phydev->link = 0; | |
144 | else | |
145 | phydev->link = 1; | |
146 | ||
147 | return 0; | |
148 | } | |
149 | ||
19945333 | 150 | static int lxt973a2_read_status(struct phy_device *phydev) |
871d1d6b LC |
151 | { |
152 | int adv; | |
153 | int err; | |
154 | int lpa; | |
155 | int lpagb = 0; | |
156 | ||
157 | /* Update the link, but return if there was an error */ | |
158 | err = lxt973a2_update_link(phydev); | |
159 | if (err) | |
160 | return err; | |
161 | ||
162 | if (AUTONEG_ENABLE == phydev->autoneg) { | |
163 | int retry = 1; | |
164 | ||
165 | adv = phy_read(phydev, MII_ADVERTISE); | |
166 | ||
167 | if (adv < 0) | |
168 | return adv; | |
169 | ||
170 | do { | |
171 | lpa = phy_read(phydev, MII_LPA); | |
172 | ||
173 | if (lpa < 0) | |
174 | return lpa; | |
175 | ||
176 | /* If both registers are equal, it is suspect but not | |
177 | * impossible, hence a new try | |
178 | */ | |
179 | } while (lpa == adv && retry--); | |
180 | ||
181 | lpa &= adv; | |
182 | ||
183 | phydev->speed = SPEED_10; | |
184 | phydev->duplex = DUPLEX_HALF; | |
185 | phydev->pause = phydev->asym_pause = 0; | |
186 | ||
187 | if (lpagb & (LPA_1000FULL | LPA_1000HALF)) { | |
188 | phydev->speed = SPEED_1000; | |
189 | ||
190 | if (lpagb & LPA_1000FULL) | |
191 | phydev->duplex = DUPLEX_FULL; | |
192 | } else if (lpa & (LPA_100FULL | LPA_100HALF)) { | |
193 | phydev->speed = SPEED_100; | |
194 | ||
195 | if (lpa & LPA_100FULL) | |
196 | phydev->duplex = DUPLEX_FULL; | |
197 | } else { | |
198 | if (lpa & LPA_10FULL) | |
199 | phydev->duplex = DUPLEX_FULL; | |
200 | } | |
201 | ||
202 | if (phydev->duplex == DUPLEX_FULL) { | |
203 | phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0; | |
204 | phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0; | |
205 | } | |
206 | } else { | |
207 | int bmcr = phy_read(phydev, MII_BMCR); | |
208 | ||
209 | if (bmcr < 0) | |
210 | return bmcr; | |
211 | ||
212 | if (bmcr & BMCR_FULLDPLX) | |
213 | phydev->duplex = DUPLEX_FULL; | |
214 | else | |
215 | phydev->duplex = DUPLEX_HALF; | |
216 | ||
217 | if (bmcr & BMCR_SPEED1000) | |
218 | phydev->speed = SPEED_1000; | |
219 | else if (bmcr & BMCR_SPEED100) | |
220 | phydev->speed = SPEED_100; | |
221 | else | |
222 | phydev->speed = SPEED_10; | |
223 | ||
224 | phydev->pause = phydev->asym_pause = 0; | |
225 | } | |
226 | ||
227 | return 0; | |
228 | } | |
229 | ||
e13647c1 RC |
230 | static int lxt973_probe(struct phy_device *phydev) |
231 | { | |
232 | int val = phy_read(phydev, MII_LXT973_PCR); | |
233 | ||
234 | if (val & PCR_FIBER_SELECT) { | |
235 | /* | |
236 | * If fiber is selected, then the only correct setting | |
237 | * is 100Mbps, full duplex, and auto negotiation off. | |
238 | */ | |
239 | val = phy_read(phydev, MII_BMCR); | |
240 | val |= (BMCR_SPEED100 | BMCR_FULLDPLX); | |
241 | val &= ~BMCR_ANENABLE; | |
242 | phy_write(phydev, MII_BMCR, val); | |
243 | /* Remember that the port is in fiber mode. */ | |
244 | phydev->priv = lxt973_probe; | |
245 | } else { | |
246 | phydev->priv = NULL; | |
247 | } | |
248 | return 0; | |
249 | } | |
250 | ||
251 | static int lxt973_config_aneg(struct phy_device *phydev) | |
252 | { | |
253 | /* Do nothing if port is in fiber mode. */ | |
254 | return phydev->priv ? 0 : genphy_config_aneg(phydev); | |
255 | } | |
256 | ||
d5bf9071 CH |
257 | static struct phy_driver lxt97x_driver[] = { |
258 | { | |
600991b0 | 259 | .phy_id = 0x78100000, |
00db8189 | 260 | .name = "LXT970", |
600991b0 | 261 | .phy_id_mask = 0xfffffff0, |
00db8189 AF |
262 | .features = PHY_BASIC_FEATURES, |
263 | .flags = PHY_HAS_INTERRUPT, | |
264 | .config_init = lxt970_config_init, | |
265 | .config_aneg = genphy_config_aneg, | |
266 | .read_status = genphy_read_status, | |
267 | .ack_interrupt = lxt970_ack_interrupt, | |
268 | .config_intr = lxt970_config_intr, | |
d5bf9071 | 269 | }, { |
600991b0 | 270 | .phy_id = 0x001378e0, |
00db8189 | 271 | .name = "LXT971", |
600991b0 | 272 | .phy_id_mask = 0xfffffff0, |
00db8189 AF |
273 | .features = PHY_BASIC_FEATURES, |
274 | .flags = PHY_HAS_INTERRUPT, | |
275 | .config_aneg = genphy_config_aneg, | |
276 | .read_status = genphy_read_status, | |
277 | .ack_interrupt = lxt971_ack_interrupt, | |
278 | .config_intr = lxt971_config_intr, | |
871d1d6b LC |
279 | }, { |
280 | .phy_id = 0x00137a10, | |
281 | .name = "LXT973-A2", | |
282 | .phy_id_mask = 0xffffffff, | |
283 | .features = PHY_BASIC_FEATURES, | |
284 | .flags = 0, | |
285 | .probe = lxt973_probe, | |
286 | .config_aneg = lxt973_config_aneg, | |
287 | .read_status = lxt973a2_read_status, | |
d5bf9071 | 288 | }, { |
e13647c1 RC |
289 | .phy_id = 0x00137a10, |
290 | .name = "LXT973", | |
291 | .phy_id_mask = 0xfffffff0, | |
292 | .features = PHY_BASIC_FEATURES, | |
293 | .flags = 0, | |
294 | .probe = lxt973_probe, | |
295 | .config_aneg = lxt973_config_aneg, | |
296 | .read_status = genphy_read_status, | |
d5bf9071 | 297 | } }; |
e13647c1 | 298 | |
50fd7150 | 299 | module_phy_driver(lxt97x_driver); |
4e4f10f6 | 300 | |
cf93c945 | 301 | static struct mdio_device_id __maybe_unused lxt_tbl[] = { |
4e4f10f6 DW |
302 | { 0x78100000, 0xfffffff0 }, |
303 | { 0x001378e0, 0xfffffff0 }, | |
e2f5b045 | 304 | { 0x00137a10, 0xfffffff0 }, |
4e4f10f6 DW |
305 | { } |
306 | }; | |
307 | ||
308 | MODULE_DEVICE_TABLE(mdio, lxt_tbl); |