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phy: Add Marvell 88E1116R phy ID
[deliverable/linux.git] / drivers / net / phy / marvell.c
CommitLineData
00db8189
AF		 1/*
2 * drivers/net/phy/marvell.c
3 *
4 * Driver for Marvell PHYs
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 *
3871c387
MS		 10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
11 *
00db8189
AF		 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
00db8189 18#include <linux/kernel.h>
00db8189
AF		 19#include <linux/string.h>
20#include <linux/errno.h>
21#include <linux/unistd.h>
00db8189
AF		 22#include <linux/interrupt.h>
23#include <linux/init.h>
24#include <linux/delay.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/spinlock.h>
29#include <linux/mm.h>
30#include <linux/module.h>
00db8189
AF		 31#include <linux/mii.h>
32#include <linux/ethtool.h>
33#include <linux/phy.h>
2f495c39 34#include <linux/marvell_phy.h>
cf41a51d 35#include <linux/of.h>
00db8189
AF		 36
37#include <asm/io.h>
38#include <asm/irq.h>
39#include <asm/uaccess.h>
40
27d916d6
DD		 41#define MII_MARVELL_PHY_PAGE 22
42
00db8189
AF		 43#define MII_M1011_IEVENT 0x13
44#define MII_M1011_IEVENT_CLEAR 0x0000
45
46#define MII_M1011_IMASK 0x12
47#define MII_M1011_IMASK_INIT 0x6400
48#define MII_M1011_IMASK_CLEAR 0x0000
49
76884679
AF		 50#define MII_M1011_PHY_SCR 0x10
51#define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
52
53#define MII_M1145_PHY_EXT_CR 0x14
54#define MII_M1145_RGMII_RX_DELAY 0x0080
55#define MII_M1145_RGMII_TX_DELAY 0x0002
56
76884679
AF		 57#define MII_M1111_PHY_LED_CONTROL 0x18
58#define MII_M1111_PHY_LED_DIRECT 0x4100
59#define MII_M1111_PHY_LED_COMBINE 0x411c
895ee682
KP		 60#define MII_M1111_PHY_EXT_CR 0x14
61#define MII_M1111_RX_DELAY 0x80
62#define MII_M1111_TX_DELAY 0x2
63#define MII_M1111_PHY_EXT_SR 0x1b
be937f1f
AS		 64
65#define MII_M1111_HWCFG_MODE_MASK 0xf
66#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
67#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
4117b5be 68#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
5f8cbc13 69#define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
be937f1f
AS		 70#define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
71#define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
72
73#define MII_M1111_COPPER 0
74#define MII_M1111_FIBER 1
75
c477d044
CC		 76#define MII_88E1121_PHY_MSCR_PAGE 2
77#define MII_88E1121_PHY_MSCR_REG 21
78#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
79#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
80#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
81
337ac9d5
CC		 82#define MII_88E1318S_PHY_MSCR1_REG 16
83#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
3ff1c259 84
3871c387
MS		 85/* Copper Specific Interrupt Enable Register */
86#define MII_88E1318S_PHY_CSIER 0x12
87/* WOL Event Interrupt Enable */
88#define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
89
90/* LED Timer Control Register */
91#define MII_88E1318S_PHY_LED_PAGE 0x03
92#define MII_88E1318S_PHY_LED_TCR 0x12
93#define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
94#define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
95#define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
96
97/* Magic Packet MAC address registers */
98#define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
99#define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
100#define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
101
102#define MII_88E1318S_PHY_WOL_PAGE 0x11
103#define MII_88E1318S_PHY_WOL_CTRL 0x10
104#define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
105#define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
106
140bc929
SP		 107#define MII_88E1121_PHY_LED_CTRL 16
108#define MII_88E1121_PHY_LED_PAGE 3
109#define MII_88E1121_PHY_LED_DEF 0x0030
140bc929 110
be937f1f
AS		 111#define MII_M1011_PHY_STATUS 0x11
112#define MII_M1011_PHY_STATUS_1000 0x8000
113#define MII_M1011_PHY_STATUS_100 0x4000
114#define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
115#define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
116#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
117#define MII_M1011_PHY_STATUS_LINK 0x0400
118
3da09a51
MS		 119#define MII_M1116R_CONTROL_REG_MAC 21
120
76884679 121
00db8189
AF		 122MODULE_DESCRIPTION("Marvell PHY driver");
123MODULE_AUTHOR("Andy Fleming");
124MODULE_LICENSE("GPL");
125
126static int marvell_ack_interrupt(struct phy_device *phydev)
127{
128 int err;
129
130 /* Clear the interrupts by reading the reg */
131 err = phy_read(phydev, MII_M1011_IEVENT);
132
133 if (err < 0)
134 return err;
135
136 return 0;
137}
138
139static int marvell_config_intr(struct phy_device *phydev)
140{
141 int err;
142
76884679 143 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
00db8189
AF		 144 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
145 else
146 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
147
148 return err;
149}
150
151static int marvell_config_aneg(struct phy_device *phydev)
152{
153 int err;
154
155 /* The Marvell PHY has an errata which requires
156 * that certain registers get written in order
157 * to restart autonegotiation */
158 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
159
160 if (err < 0)
161 return err;
162
163 err = phy_write(phydev, 0x1d, 0x1f);
164 if (err < 0)
165 return err;
166
167 err = phy_write(phydev, 0x1e, 0x200c);
168 if (err < 0)
169 return err;
170
171 err = phy_write(phydev, 0x1d, 0x5);
172 if (err < 0)
173 return err;
174
175 err = phy_write(phydev, 0x1e, 0);
176 if (err < 0)
177 return err;
178
179 err = phy_write(phydev, 0x1e, 0x100);
180 if (err < 0)
181 return err;
182
76884679
AF		 183 err = phy_write(phydev, MII_M1011_PHY_SCR,
184 MII_M1011_PHY_SCR_AUTO_CROSS);
185 if (err < 0)
186 return err;
187
188 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
189 MII_M1111_PHY_LED_DIRECT);
190 if (err < 0)
191 return err;
00db8189
AF		 192
193 err = genphy_config_aneg(phydev);
8ff44985
AV		 194 if (err < 0)
195 return err;
00db8189 196
8ff44985
AV		 197 if (phydev->autoneg != AUTONEG_ENABLE) {
198 int bmcr;
199
200 /*
201 * A write to speed/duplex bits (that is performed by
202 * genphy_config_aneg() call above) must be followed by
203 * a software reset. Otherwise, the write has no effect.
204 */
205 bmcr = phy_read(phydev, MII_BMCR);
206 if (bmcr < 0)
207 return bmcr;
208
209 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
210 if (err < 0)
211 return err;
212 }
213
214 return 0;
00db8189
AF		 215}
216
cf41a51d
DD		 217#ifdef CONFIG_OF_MDIO
218/*
219 * Set and/or override some configuration registers based on the
220 * marvell,reg-init property stored in the of_node for the phydev.
221 *
222 * marvell,reg-init = <reg-page reg mask value>,...;
223 *
224 * There may be one or more sets of <reg-page reg mask value>:
225 *
226 * reg-page: which register bank to use.
227 * reg: the register.
228 * mask: if non-zero, ANDed with existing register value.
229 * value: ORed with the masked value and written to the regiser.
230 *
231 */
232static int marvell_of_reg_init(struct phy_device *phydev)
233{
234 const __be32 *paddr;
235 int len, i, saved_page, current_page, page_changed, ret;
236
237 if (!phydev->dev.of_node)
238 return 0;
239
240 paddr = of_get_property(phydev->dev.of_node, "marvell,reg-init", &len);
241 if (!paddr || len < (4 * sizeof(*paddr)))
242 return 0;
243
244 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
245 if (saved_page < 0)
246 return saved_page;
247 page_changed = 0;
248 current_page = saved_page;
249
250 ret = 0;
251 len /= sizeof(*paddr);
252 for (i = 0; i < len - 3; i += 4) {
253 u16 reg_page = be32_to_cpup(paddr + i);
254 u16 reg = be32_to_cpup(paddr + i + 1);
255 u16 mask = be32_to_cpup(paddr + i + 2);
256 u16 val_bits = be32_to_cpup(paddr + i + 3);
257 int val;
258
259 if (reg_page != current_page) {
260 current_page = reg_page;
261 page_changed = 1;
262 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
263 if (ret < 0)
264 goto err;
265 }
266
267 val = 0;
268 if (mask) {
269 val = phy_read(phydev, reg);
270 if (val < 0) {
271 ret = val;
272 goto err;
273 }
274 val &= mask;
275 }
276 val |= val_bits;
277
278 ret = phy_write(phydev, reg, val);
279 if (ret < 0)
280 goto err;
281
282 }
283err:
284 if (page_changed) {
285 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
286 if (ret == 0)
287 ret = i;
288 }
289 return ret;
290}
291#else
292static int marvell_of_reg_init(struct phy_device *phydev)
293{
294 return 0;
295}
296#endif /* CONFIG_OF_MDIO */
297
140bc929
SP		 298static int m88e1121_config_aneg(struct phy_device *phydev)
299{
c477d044
CC		 300 int err, oldpage, mscr;
301
27d916d6 302 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
c477d044 303
27d916d6 304 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
c477d044
CC		 305 MII_88E1121_PHY_MSCR_PAGE);
306 if (err < 0)
307 return err;
be8c6480
AP		 308
309 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
310 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
311 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
312 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
313
314 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
315 MII_88E1121_PHY_MSCR_DELAY_MASK;
316
317 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
318 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
319 MII_88E1121_PHY_MSCR_TX_DELAY);
320 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
321 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
322 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
323 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
324
325 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
326 if (err < 0)
327 return err;
328 }
c477d044 329
27d916d6 330 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
140bc929
SP		 331
332 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
333 if (err < 0)
334 return err;
335
336 err = phy_write(phydev, MII_M1011_PHY_SCR,
337 MII_M1011_PHY_SCR_AUTO_CROSS);
338 if (err < 0)
339 return err;
340
27d916d6 341 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
140bc929 342
27d916d6 343 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
140bc929 344 phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
27d916d6 345 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
140bc929
SP		 346
347 err = genphy_config_aneg(phydev);
348
349 return err;
350}
351
337ac9d5 352static int m88e1318_config_aneg(struct phy_device *phydev)
3ff1c259
CC		 353{
354 int err, oldpage, mscr;
355
27d916d6 356 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
3ff1c259 357
27d916d6 358 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
3ff1c259
CC		 359 MII_88E1121_PHY_MSCR_PAGE);
360 if (err < 0)
361 return err;
362
337ac9d5
CC		 363 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
364 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
3ff1c259 365
337ac9d5 366 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
3ff1c259
CC		 367 if (err < 0)
368 return err;
369
27d916d6 370 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
3ff1c259
CC		 371 if (err < 0)
372 return err;
373
374 return m88e1121_config_aneg(phydev);
375}
376
3da09a51
MS		 377static int m88e1116r_config_init(struct phy_device *phydev)
378{
379 int temp;
380 int err;
381
382 temp = phy_read(phydev, MII_BMCR);
383 temp |= BMCR_RESET;
384 err = phy_write(phydev, MII_BMCR, temp);
385 if (err < 0)
386 return err;
387
388 mdelay(500);
389
390 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
391 if (err < 0)
392 return err;
393
394 temp = phy_read(phydev, MII_M1011_PHY_SCR);
395 temp |= (7 << 12); /* max number of gigabit attempts */
396 temp |= (1 << 11); /* enable downshift */
397 temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
398 err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
399 if (err < 0)
400 return err;
401
402 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
403 if (err < 0)
404 return err;
405 temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
406 temp |= (1 << 5);
407 temp |= (1 << 4);
408 err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
409 if (err < 0)
410 return err;
411 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
412 if (err < 0)
413 return err;
414
415 temp = phy_read(phydev, MII_BMCR);
416 temp |= BMCR_RESET;
417 err = phy_write(phydev, MII_BMCR, temp);
418 if (err < 0)
419 return err;
420
421 mdelay(500);
422
423 return 0;
424}
425
895ee682
KP		 426static int m88e1111_config_init(struct phy_device *phydev)
427{
428 int err;
be937f1f 429 int temp;
be937f1f 430
895ee682 431 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
9daf5a76
KP		 432 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
433 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
434 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
895ee682 435
9daf5a76
KP		 436 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
437 if (temp < 0)
438 return temp;
895ee682 439
9daf5a76 440 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
895ee682 441 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
9daf5a76
KP		 442 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
443 temp &= ~MII_M1111_TX_DELAY;
444 temp |= MII_M1111_RX_DELAY;
445 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
446 temp &= ~MII_M1111_RX_DELAY;
447 temp |= MII_M1111_TX_DELAY;
895ee682
KP		 448 }
449
9daf5a76
KP		 450 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
451 if (err < 0)
452 return err;
453
895ee682
KP		 454 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
455 if (temp < 0)
456 return temp;
457
458 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
be937f1f 459
7239016d 460 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
be937f1f
AS		 461 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
462 else
463 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
895ee682
KP		 464
465 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
466 if (err < 0)
467 return err;
468 }
469
4117b5be 470 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
4117b5be
KJ		 471 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
472 if (temp < 0)
473 return temp;
474
475 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
476 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
32d0c1e1 477 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
4117b5be
KJ		 478
479 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
480 if (err < 0)
481 return err;
482 }
483
5f8cbc13
LYB		 484 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
485 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
486 if (temp < 0)
487 return temp;
488 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
489 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
490 if (err < 0)
491 return err;
492
493 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
494 if (temp < 0)
495 return temp;
496 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
497 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
498 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
499 if (err < 0)
500 return err;
501
502 /* soft reset */
503 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
504 if (err < 0)
505 return err;
506 do
507 temp = phy_read(phydev, MII_BMCR);
508 while (temp & BMCR_RESET);
509
510 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
511 if (temp < 0)
512 return temp;
513 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
514 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
515 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
516 if (err < 0)
517 return err;
518 }
519
cf41a51d
DD		 520 err = marvell_of_reg_init(phydev);
521 if (err < 0)
522 return err;
5f8cbc13 523
cc90cb3b 524 return phy_write(phydev, MII_BMCR, BMCR_RESET);
895ee682
KP		 525}
526
605f196e
RM		 527static int m88e1118_config_aneg(struct phy_device *phydev)
528{
529 int err;
530
531 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
532 if (err < 0)
533 return err;
534
535 err = phy_write(phydev, MII_M1011_PHY_SCR,
536 MII_M1011_PHY_SCR_AUTO_CROSS);
537 if (err < 0)
538 return err;
539
540 err = genphy_config_aneg(phydev);
541 return 0;
542}
543
544static int m88e1118_config_init(struct phy_device *phydev)
545{
546 int err;
547
548 /* Change address */
27d916d6 549 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
605f196e
RM		 550 if (err < 0)
551 return err;
552
553 /* Enable 1000 Mbit */
554 err = phy_write(phydev, 0x15, 0x1070);
555 if (err < 0)
556 return err;
557
558 /* Change address */
27d916d6 559 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
605f196e
RM		 560 if (err < 0)
561 return err;
562
563 /* Adjust LED Control */
2f495c39
BH		 564 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
565 err = phy_write(phydev, 0x10, 0x1100);
566 else
567 err = phy_write(phydev, 0x10, 0x021e);
605f196e
RM		 568 if (err < 0)
569 return err;
570
cf41a51d
DD		 571 err = marvell_of_reg_init(phydev);
572 if (err < 0)
573 return err;
574
605f196e 575 /* Reset address */
27d916d6 576 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
605f196e
RM		 577 if (err < 0)
578 return err;
579
cc90cb3b 580 return phy_write(phydev, MII_BMCR, BMCR_RESET);
605f196e
RM		 581}
582
90600732
DD		 583static int m88e1149_config_init(struct phy_device *phydev)
584{
585 int err;
586
587 /* Change address */
588 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
589 if (err < 0)
590 return err;
591
592 /* Enable 1000 Mbit */
593 err = phy_write(phydev, 0x15, 0x1048);
594 if (err < 0)
595 return err;
596
cf41a51d
DD		 597 err = marvell_of_reg_init(phydev);
598 if (err < 0)
599 return err;
600
90600732
DD		 601 /* Reset address */
602 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
603 if (err < 0)
604 return err;
605
cc90cb3b 606 return phy_write(phydev, MII_BMCR, BMCR_RESET);
90600732
DD		 607}
608
76884679
AF		 609static int m88e1145_config_init(struct phy_device *phydev)
610{
611 int err;
612
613 /* Take care of errata E0 & E1 */
614 err = phy_write(phydev, 0x1d, 0x001b);
615 if (err < 0)
616 return err;
617
618 err = phy_write(phydev, 0x1e, 0x418f);
619 if (err < 0)
620 return err;
621
622 err = phy_write(phydev, 0x1d, 0x0016);
623 if (err < 0)
624 return err;
625
626 err = phy_write(phydev, 0x1e, 0xa2da);
627 if (err < 0)
628 return err;
629
895ee682 630 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
76884679
AF		 631 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
632 if (temp < 0)
633 return temp;
634
635 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
636
637 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
638 if (err < 0)
639 return err;
640
2f495c39 641 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
76884679
AF		 642 err = phy_write(phydev, 0x1d, 0x0012);
643 if (err < 0)
644 return err;
645
646 temp = phy_read(phydev, 0x1e);
647 if (temp < 0)
648 return temp;
649
650 temp &= 0xf03f;
651 temp |= 2 << 9; /* 36 ohm */
652 temp |= 2 << 6; /* 39 ohm */
653
654 err = phy_write(phydev, 0x1e, temp);
655 if (err < 0)
656 return err;
657
658 err = phy_write(phydev, 0x1d, 0x3);
659 if (err < 0)
660 return err;
661
662 err = phy_write(phydev, 0x1e, 0x8000);
663 if (err < 0)
664 return err;
665 }
666 }
667
cf41a51d
DD		 668 err = marvell_of_reg_init(phydev);
669 if (err < 0)
670 return err;
671
76884679
AF		 672 return 0;
673}
00db8189 674
be937f1f
AS		 675/* marvell_read_status
676 *
677 * Generic status code does not detect Fiber correctly!
f0c88f9c 678 * Description:
be937f1f
AS		 679 * Check the link, then figure out the current state
680 * by comparing what we advertise with what the link partner
681 * advertises. Start by checking the gigabit possibilities,
682 * then move on to 10/100.
683 */
684static int marvell_read_status(struct phy_device *phydev)
685{
686 int adv;
687 int err;
688 int lpa;
689 int status = 0;
690
691 /* Update the link, but return if there
692 * was an error */
693 err = genphy_update_link(phydev);
694 if (err)
695 return err;
696
697 if (AUTONEG_ENABLE == phydev->autoneg) {
698 status = phy_read(phydev, MII_M1011_PHY_STATUS);
699 if (status < 0)
700 return status;
701
702 lpa = phy_read(phydev, MII_LPA);
703 if (lpa < 0)
704 return lpa;
705
706 adv = phy_read(phydev, MII_ADVERTISE);
707 if (adv < 0)
708 return adv;
709
710 lpa &= adv;
711
712 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
713 phydev->duplex = DUPLEX_FULL;
714 else
715 phydev->duplex = DUPLEX_HALF;
716
717 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
718 phydev->pause = phydev->asym_pause = 0;
719
720 switch (status) {
721 case MII_M1011_PHY_STATUS_1000:
722 phydev->speed = SPEED_1000;
723 break;
724
725 case MII_M1011_PHY_STATUS_100:
726 phydev->speed = SPEED_100;
727 break;
728
729 default:
730 phydev->speed = SPEED_10;
731 break;
732 }
733
734 if (phydev->duplex == DUPLEX_FULL) {
735 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
736 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
737 }
738 } else {
739 int bmcr = phy_read(phydev, MII_BMCR);
740
741 if (bmcr < 0)
742 return bmcr;
743
744 if (bmcr & BMCR_FULLDPLX)
745 phydev->duplex = DUPLEX_FULL;
746 else
747 phydev->duplex = DUPLEX_HALF;
748
749 if (bmcr & BMCR_SPEED1000)
750 phydev->speed = SPEED_1000;
751 else if (bmcr & BMCR_SPEED100)
752 phydev->speed = SPEED_100;
753 else
754 phydev->speed = SPEED_10;
755
756 phydev->pause = phydev->asym_pause = 0;
757 }
758
759 return 0;
760}
761
dcd07be3
AG		 762static int m88e1121_did_interrupt(struct phy_device *phydev)
763{
764 int imask;
765
766 imask = phy_read(phydev, MII_M1011_IEVENT);
767
768 if (imask & MII_M1011_IMASK_INIT)
769 return 1;
770
771 return 0;
772}
773
3871c387
MS		 774static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
775{
776 wol->supported = WAKE_MAGIC;
777 wol->wolopts = 0;
778
779 if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
780 MII_88E1318S_PHY_WOL_PAGE) < 0)
781 return;
782
783 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
784 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
785 wol->wolopts |= WAKE_MAGIC;
786
787 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
788 return;
789}
790
791static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
792{
793 int err, oldpage, temp;
794
795 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
796
797 if (wol->wolopts & WAKE_MAGIC) {
798 /* Explicitly switch to page 0x00, just to be sure */
799 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
800 if (err < 0)
801 return err;
802
803 /* Enable the WOL interrupt */
804 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
805 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
806 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
807 if (err < 0)
808 return err;
809
810 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
811 MII_88E1318S_PHY_LED_PAGE);
812 if (err < 0)
813 return err;
814
815 /* Setup LED[2] as interrupt pin (active low) */
816 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
817 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
818 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
819 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
820 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
821 if (err < 0)
822 return err;
823
824 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
825 MII_88E1318S_PHY_WOL_PAGE);
826 if (err < 0)
827 return err;
828
829 /* Store the device address for the magic packet */
830 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
831 ((phydev->attached_dev->dev_addr[5] << 8) |
832 phydev->attached_dev->dev_addr[4]));
833 if (err < 0)
834 return err;
835 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
836 ((phydev->attached_dev->dev_addr[3] << 8) |
837 phydev->attached_dev->dev_addr[2]));
838 if (err < 0)
839 return err;
840 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
841 ((phydev->attached_dev->dev_addr[1] << 8) |
842 phydev->attached_dev->dev_addr[0]));
843 if (err < 0)
844 return err;
845
846 /* Clear WOL status and enable magic packet matching */
847 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
848 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
849 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
850 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
851 if (err < 0)
852 return err;
853 } else {
854 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
855 MII_88E1318S_PHY_WOL_PAGE);
856 if (err < 0)
857 return err;
858
859 /* Clear WOL status and disable magic packet matching */
860 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
861 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
862 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
863 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
864 if (err < 0)
865 return err;
866 }
867
868 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
869 if (err < 0)
870 return err;
871
872 return 0;
873}
874
e5479239
OJ		 875static struct phy_driver marvell_drivers[] = {
876 {
2f495c39
BH		 877 .phy_id = MARVELL_PHY_ID_88E1101,
878 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 879 .name = "Marvell 88E1101",
880 .features = PHY_GBIT_FEATURES,
881 .flags = PHY_HAS_INTERRUPT,
882 .config_aneg = &marvell_config_aneg,
883 .read_status = &genphy_read_status,
884 .ack_interrupt = &marvell_ack_interrupt,
885 .config_intr = &marvell_config_intr,
ac8c635a 886 .driver = { .owner = THIS_MODULE },
e5479239 887 },
85cfb534 888 {
2f495c39
BH		 889 .phy_id = MARVELL_PHY_ID_88E1112,
890 .phy_id_mask = MARVELL_PHY_ID_MASK,
85cfb534
OJ		 891 .name = "Marvell 88E1112",
892 .features = PHY_GBIT_FEATURES,
893 .flags = PHY_HAS_INTERRUPT,
894 .config_init = &m88e1111_config_init,
895 .config_aneg = &marvell_config_aneg,
896 .read_status = &genphy_read_status,
897 .ack_interrupt = &marvell_ack_interrupt,
898 .config_intr = &marvell_config_intr,
ac8c635a 899 .driver = { .owner = THIS_MODULE },
85cfb534 900 },
e5479239 901 {
2f495c39
BH		 902 .phy_id = MARVELL_PHY_ID_88E1111,
903 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 904 .name = "Marvell 88E1111",
905 .features = PHY_GBIT_FEATURES,
906 .flags = PHY_HAS_INTERRUPT,
907 .config_init = &m88e1111_config_init,
908 .config_aneg = &marvell_config_aneg,
be937f1f 909 .read_status = &marvell_read_status,
e5479239
OJ		 910 .ack_interrupt = &marvell_ack_interrupt,
911 .config_intr = &marvell_config_intr,
ac8c635a 912 .driver = { .owner = THIS_MODULE },
e5479239 913 },
605f196e 914 {
2f495c39
BH		 915 .phy_id = MARVELL_PHY_ID_88E1118,
916 .phy_id_mask = MARVELL_PHY_ID_MASK,
605f196e
RM		 917 .name = "Marvell 88E1118",
918 .features = PHY_GBIT_FEATURES,
919 .flags = PHY_HAS_INTERRUPT,
920 .config_init = &m88e1118_config_init,
921 .config_aneg = &m88e1118_config_aneg,
922 .read_status = &genphy_read_status,
923 .ack_interrupt = &marvell_ack_interrupt,
924 .config_intr = &marvell_config_intr,
925 .driver = {.owner = THIS_MODULE,},
926 },
140bc929 927 {
2f495c39
BH		 928 .phy_id = MARVELL_PHY_ID_88E1121R,
929 .phy_id_mask = MARVELL_PHY_ID_MASK,
140bc929
SP		 930 .name = "Marvell 88E1121R",
931 .features = PHY_GBIT_FEATURES,
932 .flags = PHY_HAS_INTERRUPT,
933 .config_aneg = &m88e1121_config_aneg,
934 .read_status = &marvell_read_status,
935 .ack_interrupt = &marvell_ack_interrupt,
936 .config_intr = &marvell_config_intr,
dcd07be3 937 .did_interrupt = &m88e1121_did_interrupt,
140bc929
SP		 938 .driver = { .owner = THIS_MODULE },
939 },
3ff1c259 940 {
337ac9d5 941 .phy_id = MARVELL_PHY_ID_88E1318S,
6ba74014 942 .phy_id_mask = MARVELL_PHY_ID_MASK,
337ac9d5 943 .name = "Marvell 88E1318S",
3ff1c259
CC		 944 .features = PHY_GBIT_FEATURES,
945 .flags = PHY_HAS_INTERRUPT,
337ac9d5 946 .config_aneg = &m88e1318_config_aneg,
3ff1c259
CC		 947 .read_status = &marvell_read_status,
948 .ack_interrupt = &marvell_ack_interrupt,
949 .config_intr = &marvell_config_intr,
950 .did_interrupt = &m88e1121_did_interrupt,
3871c387
MS		 951 .get_wol = &m88e1318_get_wol,
952 .set_wol = &m88e1318_set_wol,
3ff1c259
CC		 953 .driver = { .owner = THIS_MODULE },
954 },
e5479239 955 {
2f495c39
BH		 956 .phy_id = MARVELL_PHY_ID_88E1145,
957 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 958 .name = "Marvell 88E1145",
959 .features = PHY_GBIT_FEATURES,
960 .flags = PHY_HAS_INTERRUPT,
961 .config_init = &m88e1145_config_init,
962 .config_aneg = &marvell_config_aneg,
963 .read_status = &genphy_read_status,
964 .ack_interrupt = &marvell_ack_interrupt,
965 .config_intr = &marvell_config_intr,
ac8c635a
OJ		 966 .driver = { .owner = THIS_MODULE },
967 },
90600732
DD		 968 {
969 .phy_id = MARVELL_PHY_ID_88E1149R,
970 .phy_id_mask = MARVELL_PHY_ID_MASK,
971 .name = "Marvell 88E1149R",
972 .features = PHY_GBIT_FEATURES,
973 .flags = PHY_HAS_INTERRUPT,
974 .config_init = &m88e1149_config_init,
975 .config_aneg = &m88e1118_config_aneg,
976 .read_status = &genphy_read_status,
977 .ack_interrupt = &marvell_ack_interrupt,
978 .config_intr = &marvell_config_intr,
979 .driver = { .owner = THIS_MODULE },
980 },
ac8c635a 981 {
2f495c39
BH		 982 .phy_id = MARVELL_PHY_ID_88E1240,
983 .phy_id_mask = MARVELL_PHY_ID_MASK,
ac8c635a
OJ		 984 .name = "Marvell 88E1240",
985 .features = PHY_GBIT_FEATURES,
986 .flags = PHY_HAS_INTERRUPT,
987 .config_init = &m88e1111_config_init,
988 .config_aneg = &marvell_config_aneg,
989 .read_status = &genphy_read_status,
990 .ack_interrupt = &marvell_ack_interrupt,
991 .config_intr = &marvell_config_intr,
992 .driver = { .owner = THIS_MODULE },
993 },
3da09a51
MS		 994 {
995 .phy_id = MARVELL_PHY_ID_88E1116R,
996 .phy_id_mask = MARVELL_PHY_ID_MASK,
997 .name = "Marvell 88E1116R",
998 .features = PHY_GBIT_FEATURES,
999 .flags = PHY_HAS_INTERRUPT,
1000 .config_init = &m88e1116r_config_init,
1001 .config_aneg = &genphy_config_aneg,
1002 .read_status = &genphy_read_status,
1003 .ack_interrupt = &marvell_ack_interrupt,
1004 .config_intr = &marvell_config_intr,
1005 .driver = { .owner = THIS_MODULE },
1006 },
00db8189
AF		 1007};
1008
1009static int __init marvell_init(void)
1010{
d5bf9071
CH		 1011 return phy_drivers_register(marvell_drivers,
1012 ARRAY_SIZE(marvell_drivers));
00db8189
AF		 1013}
1014
1015static void __exit marvell_exit(void)
1016{
d5bf9071
CH		 1017 phy_drivers_unregister(marvell_drivers,
1018 ARRAY_SIZE(marvell_drivers));
00db8189
AF		 1019}
1020
1021module_init(marvell_init);
1022module_exit(marvell_exit);
4e4f10f6 1023
cf93c945 1024static struct mdio_device_id __maybe_unused marvell_tbl[] = {
f5e1cabf
MS		 1025 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
1026 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
1027 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
1028 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
1029 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
1030 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
1031 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
1032 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
1033 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
3da09a51 1034 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
4e4f10f6
DW		 1035 { }
1036};
1037
1038MODULE_DEVICE_TABLE(mdio, marvell_tbl);
Linux kernel - Deliverables
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