Commit | Line | Data |
---|---|---|
00db8189 AF |
1 | /* |
2 | * drivers/net/phy/marvell.c | |
3 | * | |
4 | * Driver for Marvell PHYs | |
5 | * | |
6 | * Author: Andy Fleming | |
7 | * | |
8 | * Copyright (c) 2004 Freescale Semiconductor, Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | * | |
15 | */ | |
00db8189 | 16 | #include <linux/kernel.h> |
00db8189 AF |
17 | #include <linux/string.h> |
18 | #include <linux/errno.h> | |
19 | #include <linux/unistd.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/netdevice.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/skbuff.h> | |
27 | #include <linux/spinlock.h> | |
28 | #include <linux/mm.h> | |
29 | #include <linux/module.h> | |
00db8189 AF |
30 | #include <linux/mii.h> |
31 | #include <linux/ethtool.h> | |
32 | #include <linux/phy.h> | |
33 | ||
34 | #include <asm/io.h> | |
35 | #include <asm/irq.h> | |
36 | #include <asm/uaccess.h> | |
37 | ||
38 | #define MII_M1011_IEVENT 0x13 | |
39 | #define MII_M1011_IEVENT_CLEAR 0x0000 | |
40 | ||
41 | #define MII_M1011_IMASK 0x12 | |
42 | #define MII_M1011_IMASK_INIT 0x6400 | |
43 | #define MII_M1011_IMASK_CLEAR 0x0000 | |
44 | ||
76884679 AF |
45 | #define MII_M1011_PHY_SCR 0x10 |
46 | #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060 | |
47 | ||
48 | #define MII_M1145_PHY_EXT_CR 0x14 | |
49 | #define MII_M1145_RGMII_RX_DELAY 0x0080 | |
50 | #define MII_M1145_RGMII_TX_DELAY 0x0002 | |
51 | ||
52 | #define M1145_DEV_FLAGS_RESISTANCE 0x00000001 | |
53 | ||
54 | #define MII_M1111_PHY_LED_CONTROL 0x18 | |
55 | #define MII_M1111_PHY_LED_DIRECT 0x4100 | |
56 | #define MII_M1111_PHY_LED_COMBINE 0x411c | |
895ee682 KP |
57 | #define MII_M1111_PHY_EXT_CR 0x14 |
58 | #define MII_M1111_RX_DELAY 0x80 | |
59 | #define MII_M1111_TX_DELAY 0x2 | |
60 | #define MII_M1111_PHY_EXT_SR 0x1b | |
be937f1f AS |
61 | |
62 | #define MII_M1111_HWCFG_MODE_MASK 0xf | |
63 | #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb | |
64 | #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3 | |
4117b5be | 65 | #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4 |
be937f1f AS |
66 | #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000 |
67 | #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000 | |
68 | ||
69 | #define MII_M1111_COPPER 0 | |
70 | #define MII_M1111_FIBER 1 | |
71 | ||
72 | #define MII_M1011_PHY_STATUS 0x11 | |
73 | #define MII_M1011_PHY_STATUS_1000 0x8000 | |
74 | #define MII_M1011_PHY_STATUS_100 0x4000 | |
75 | #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000 | |
76 | #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000 | |
77 | #define MII_M1011_PHY_STATUS_RESOLVED 0x0800 | |
78 | #define MII_M1011_PHY_STATUS_LINK 0x0400 | |
79 | ||
76884679 | 80 | |
00db8189 AF |
81 | MODULE_DESCRIPTION("Marvell PHY driver"); |
82 | MODULE_AUTHOR("Andy Fleming"); | |
83 | MODULE_LICENSE("GPL"); | |
84 | ||
85 | static int marvell_ack_interrupt(struct phy_device *phydev) | |
86 | { | |
87 | int err; | |
88 | ||
89 | /* Clear the interrupts by reading the reg */ | |
90 | err = phy_read(phydev, MII_M1011_IEVENT); | |
91 | ||
92 | if (err < 0) | |
93 | return err; | |
94 | ||
95 | return 0; | |
96 | } | |
97 | ||
98 | static int marvell_config_intr(struct phy_device *phydev) | |
99 | { | |
100 | int err; | |
101 | ||
76884679 | 102 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) |
00db8189 AF |
103 | err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT); |
104 | else | |
105 | err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR); | |
106 | ||
107 | return err; | |
108 | } | |
109 | ||
110 | static int marvell_config_aneg(struct phy_device *phydev) | |
111 | { | |
112 | int err; | |
113 | ||
114 | /* The Marvell PHY has an errata which requires | |
115 | * that certain registers get written in order | |
116 | * to restart autonegotiation */ | |
117 | err = phy_write(phydev, MII_BMCR, BMCR_RESET); | |
118 | ||
119 | if (err < 0) | |
120 | return err; | |
121 | ||
122 | err = phy_write(phydev, 0x1d, 0x1f); | |
123 | if (err < 0) | |
124 | return err; | |
125 | ||
126 | err = phy_write(phydev, 0x1e, 0x200c); | |
127 | if (err < 0) | |
128 | return err; | |
129 | ||
130 | err = phy_write(phydev, 0x1d, 0x5); | |
131 | if (err < 0) | |
132 | return err; | |
133 | ||
134 | err = phy_write(phydev, 0x1e, 0); | |
135 | if (err < 0) | |
136 | return err; | |
137 | ||
138 | err = phy_write(phydev, 0x1e, 0x100); | |
139 | if (err < 0) | |
140 | return err; | |
141 | ||
76884679 AF |
142 | err = phy_write(phydev, MII_M1011_PHY_SCR, |
143 | MII_M1011_PHY_SCR_AUTO_CROSS); | |
144 | if (err < 0) | |
145 | return err; | |
146 | ||
147 | err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL, | |
148 | MII_M1111_PHY_LED_DIRECT); | |
149 | if (err < 0) | |
150 | return err; | |
00db8189 AF |
151 | |
152 | err = genphy_config_aneg(phydev); | |
153 | ||
154 | return err; | |
155 | } | |
156 | ||
895ee682 KP |
157 | static int m88e1111_config_init(struct phy_device *phydev) |
158 | { | |
159 | int err; | |
be937f1f AS |
160 | int temp; |
161 | int mode; | |
162 | ||
163 | /* Enable Fiber/Copper auto selection */ | |
164 | temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); | |
165 | temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO; | |
166 | phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); | |
167 | ||
168 | temp = phy_read(phydev, MII_BMCR); | |
169 | temp |= BMCR_RESET; | |
170 | phy_write(phydev, MII_BMCR, temp); | |
895ee682 KP |
171 | |
172 | if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || | |
9daf5a76 KP |
173 | (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || |
174 | (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) || | |
175 | (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { | |
895ee682 | 176 | |
9daf5a76 KP |
177 | temp = phy_read(phydev, MII_M1111_PHY_EXT_CR); |
178 | if (temp < 0) | |
179 | return temp; | |
895ee682 | 180 | |
9daf5a76 | 181 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { |
895ee682 | 182 | temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); |
9daf5a76 KP |
183 | } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { |
184 | temp &= ~MII_M1111_TX_DELAY; | |
185 | temp |= MII_M1111_RX_DELAY; | |
186 | } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { | |
187 | temp &= ~MII_M1111_RX_DELAY; | |
188 | temp |= MII_M1111_TX_DELAY; | |
895ee682 KP |
189 | } |
190 | ||
9daf5a76 KP |
191 | err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp); |
192 | if (err < 0) | |
193 | return err; | |
194 | ||
895ee682 KP |
195 | temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); |
196 | if (temp < 0) | |
197 | return temp; | |
198 | ||
199 | temp &= ~(MII_M1111_HWCFG_MODE_MASK); | |
be937f1f AS |
200 | |
201 | mode = phy_read(phydev, MII_M1111_PHY_EXT_CR); | |
202 | ||
203 | if (mode & MII_M1111_HWCFG_FIBER_COPPER_RES) | |
204 | temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII; | |
205 | else | |
206 | temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII; | |
895ee682 KP |
207 | |
208 | err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); | |
209 | if (err < 0) | |
210 | return err; | |
211 | } | |
212 | ||
4117b5be | 213 | if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { |
4117b5be KJ |
214 | temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); |
215 | if (temp < 0) | |
216 | return temp; | |
217 | ||
218 | temp &= ~(MII_M1111_HWCFG_MODE_MASK); | |
219 | temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK; | |
220 | ||
221 | err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); | |
222 | if (err < 0) | |
223 | return err; | |
224 | } | |
225 | ||
895ee682 KP |
226 | err = phy_write(phydev, MII_BMCR, BMCR_RESET); |
227 | if (err < 0) | |
228 | return err; | |
229 | ||
230 | return 0; | |
231 | } | |
232 | ||
76884679 AF |
233 | static int m88e1145_config_init(struct phy_device *phydev) |
234 | { | |
235 | int err; | |
236 | ||
237 | /* Take care of errata E0 & E1 */ | |
238 | err = phy_write(phydev, 0x1d, 0x001b); | |
239 | if (err < 0) | |
240 | return err; | |
241 | ||
242 | err = phy_write(phydev, 0x1e, 0x418f); | |
243 | if (err < 0) | |
244 | return err; | |
245 | ||
246 | err = phy_write(phydev, 0x1d, 0x0016); | |
247 | if (err < 0) | |
248 | return err; | |
249 | ||
250 | err = phy_write(phydev, 0x1e, 0xa2da); | |
251 | if (err < 0) | |
252 | return err; | |
253 | ||
895ee682 | 254 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { |
76884679 AF |
255 | int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR); |
256 | if (temp < 0) | |
257 | return temp; | |
258 | ||
259 | temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY); | |
260 | ||
261 | err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp); | |
262 | if (err < 0) | |
263 | return err; | |
264 | ||
265 | if (phydev->dev_flags & M1145_DEV_FLAGS_RESISTANCE) { | |
266 | err = phy_write(phydev, 0x1d, 0x0012); | |
267 | if (err < 0) | |
268 | return err; | |
269 | ||
270 | temp = phy_read(phydev, 0x1e); | |
271 | if (temp < 0) | |
272 | return temp; | |
273 | ||
274 | temp &= 0xf03f; | |
275 | temp |= 2 << 9; /* 36 ohm */ | |
276 | temp |= 2 << 6; /* 39 ohm */ | |
277 | ||
278 | err = phy_write(phydev, 0x1e, temp); | |
279 | if (err < 0) | |
280 | return err; | |
281 | ||
282 | err = phy_write(phydev, 0x1d, 0x3); | |
283 | if (err < 0) | |
284 | return err; | |
285 | ||
286 | err = phy_write(phydev, 0x1e, 0x8000); | |
287 | if (err < 0) | |
288 | return err; | |
289 | } | |
290 | } | |
291 | ||
292 | return 0; | |
293 | } | |
00db8189 | 294 | |
be937f1f AS |
295 | /* marvell_read_status |
296 | * | |
297 | * Generic status code does not detect Fiber correctly! | |
f0c88f9c | 298 | * Description: |
be937f1f AS |
299 | * Check the link, then figure out the current state |
300 | * by comparing what we advertise with what the link partner | |
301 | * advertises. Start by checking the gigabit possibilities, | |
302 | * then move on to 10/100. | |
303 | */ | |
304 | static int marvell_read_status(struct phy_device *phydev) | |
305 | { | |
306 | int adv; | |
307 | int err; | |
308 | int lpa; | |
309 | int status = 0; | |
310 | ||
311 | /* Update the link, but return if there | |
312 | * was an error */ | |
313 | err = genphy_update_link(phydev); | |
314 | if (err) | |
315 | return err; | |
316 | ||
317 | if (AUTONEG_ENABLE == phydev->autoneg) { | |
318 | status = phy_read(phydev, MII_M1011_PHY_STATUS); | |
319 | if (status < 0) | |
320 | return status; | |
321 | ||
322 | lpa = phy_read(phydev, MII_LPA); | |
323 | if (lpa < 0) | |
324 | return lpa; | |
325 | ||
326 | adv = phy_read(phydev, MII_ADVERTISE); | |
327 | if (adv < 0) | |
328 | return adv; | |
329 | ||
330 | lpa &= adv; | |
331 | ||
332 | if (status & MII_M1011_PHY_STATUS_FULLDUPLEX) | |
333 | phydev->duplex = DUPLEX_FULL; | |
334 | else | |
335 | phydev->duplex = DUPLEX_HALF; | |
336 | ||
337 | status = status & MII_M1011_PHY_STATUS_SPD_MASK; | |
338 | phydev->pause = phydev->asym_pause = 0; | |
339 | ||
340 | switch (status) { | |
341 | case MII_M1011_PHY_STATUS_1000: | |
342 | phydev->speed = SPEED_1000; | |
343 | break; | |
344 | ||
345 | case MII_M1011_PHY_STATUS_100: | |
346 | phydev->speed = SPEED_100; | |
347 | break; | |
348 | ||
349 | default: | |
350 | phydev->speed = SPEED_10; | |
351 | break; | |
352 | } | |
353 | ||
354 | if (phydev->duplex == DUPLEX_FULL) { | |
355 | phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0; | |
356 | phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0; | |
357 | } | |
358 | } else { | |
359 | int bmcr = phy_read(phydev, MII_BMCR); | |
360 | ||
361 | if (bmcr < 0) | |
362 | return bmcr; | |
363 | ||
364 | if (bmcr & BMCR_FULLDPLX) | |
365 | phydev->duplex = DUPLEX_FULL; | |
366 | else | |
367 | phydev->duplex = DUPLEX_HALF; | |
368 | ||
369 | if (bmcr & BMCR_SPEED1000) | |
370 | phydev->speed = SPEED_1000; | |
371 | else if (bmcr & BMCR_SPEED100) | |
372 | phydev->speed = SPEED_100; | |
373 | else | |
374 | phydev->speed = SPEED_10; | |
375 | ||
376 | phydev->pause = phydev->asym_pause = 0; | |
377 | } | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
e5479239 OJ |
382 | static struct phy_driver marvell_drivers[] = { |
383 | { | |
384 | .phy_id = 0x01410c60, | |
385 | .phy_id_mask = 0xfffffff0, | |
386 | .name = "Marvell 88E1101", | |
387 | .features = PHY_GBIT_FEATURES, | |
388 | .flags = PHY_HAS_INTERRUPT, | |
389 | .config_aneg = &marvell_config_aneg, | |
390 | .read_status = &genphy_read_status, | |
391 | .ack_interrupt = &marvell_ack_interrupt, | |
392 | .config_intr = &marvell_config_intr, | |
ac8c635a | 393 | .driver = { .owner = THIS_MODULE }, |
e5479239 | 394 | }, |
85cfb534 OJ |
395 | { |
396 | .phy_id = 0x01410c90, | |
397 | .phy_id_mask = 0xfffffff0, | |
398 | .name = "Marvell 88E1112", | |
399 | .features = PHY_GBIT_FEATURES, | |
400 | .flags = PHY_HAS_INTERRUPT, | |
401 | .config_init = &m88e1111_config_init, | |
402 | .config_aneg = &marvell_config_aneg, | |
403 | .read_status = &genphy_read_status, | |
404 | .ack_interrupt = &marvell_ack_interrupt, | |
405 | .config_intr = &marvell_config_intr, | |
ac8c635a | 406 | .driver = { .owner = THIS_MODULE }, |
85cfb534 | 407 | }, |
e5479239 OJ |
408 | { |
409 | .phy_id = 0x01410cc0, | |
410 | .phy_id_mask = 0xfffffff0, | |
411 | .name = "Marvell 88E1111", | |
412 | .features = PHY_GBIT_FEATURES, | |
413 | .flags = PHY_HAS_INTERRUPT, | |
414 | .config_init = &m88e1111_config_init, | |
415 | .config_aneg = &marvell_config_aneg, | |
be937f1f | 416 | .read_status = &marvell_read_status, |
e5479239 OJ |
417 | .ack_interrupt = &marvell_ack_interrupt, |
418 | .config_intr = &marvell_config_intr, | |
ac8c635a | 419 | .driver = { .owner = THIS_MODULE }, |
e5479239 OJ |
420 | }, |
421 | { | |
422 | .phy_id = 0x01410cd0, | |
423 | .phy_id_mask = 0xfffffff0, | |
424 | .name = "Marvell 88E1145", | |
425 | .features = PHY_GBIT_FEATURES, | |
426 | .flags = PHY_HAS_INTERRUPT, | |
427 | .config_init = &m88e1145_config_init, | |
428 | .config_aneg = &marvell_config_aneg, | |
429 | .read_status = &genphy_read_status, | |
430 | .ack_interrupt = &marvell_ack_interrupt, | |
431 | .config_intr = &marvell_config_intr, | |
ac8c635a OJ |
432 | .driver = { .owner = THIS_MODULE }, |
433 | }, | |
434 | { | |
435 | .phy_id = 0x01410e30, | |
436 | .phy_id_mask = 0xfffffff0, | |
437 | .name = "Marvell 88E1240", | |
438 | .features = PHY_GBIT_FEATURES, | |
439 | .flags = PHY_HAS_INTERRUPT, | |
440 | .config_init = &m88e1111_config_init, | |
441 | .config_aneg = &marvell_config_aneg, | |
442 | .read_status = &genphy_read_status, | |
443 | .ack_interrupt = &marvell_ack_interrupt, | |
444 | .config_intr = &marvell_config_intr, | |
445 | .driver = { .owner = THIS_MODULE }, | |
446 | }, | |
00db8189 AF |
447 | }; |
448 | ||
449 | static int __init marvell_init(void) | |
450 | { | |
76884679 | 451 | int ret; |
e5479239 | 452 | int i; |
76884679 | 453 | |
e5479239 OJ |
454 | for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++) { |
455 | ret = phy_driver_register(&marvell_drivers[i]); | |
76884679 | 456 | |
e5479239 OJ |
457 | if (ret) { |
458 | while (i-- > 0) | |
459 | phy_driver_unregister(&marvell_drivers[i]); | |
460 | return ret; | |
461 | } | |
462 | } | |
76884679 AF |
463 | |
464 | return 0; | |
00db8189 AF |
465 | } |
466 | ||
467 | static void __exit marvell_exit(void) | |
468 | { | |
e5479239 OJ |
469 | int i; |
470 | ||
471 | for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++) | |
472 | phy_driver_unregister(&marvell_drivers[i]); | |
00db8189 AF |
473 | } |
474 | ||
475 | module_init(marvell_init); | |
476 | module_exit(marvell_exit); |