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Merge branch 'batman-adv-fixes'
[deliverable/linux.git] / drivers / net / phy / marvell.c
CommitLineData
00db8189
AF		 1/*
2 * drivers/net/phy/marvell.c
3 *
4 * Driver for Marvell PHYs
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 *
3871c387
MS		 10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
11 *
00db8189
AF		 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
00db8189 18#include <linux/kernel.h>
00db8189
AF		 19#include <linux/string.h>
20#include <linux/errno.h>
21#include <linux/unistd.h>
00db8189
AF		 22#include <linux/interrupt.h>
23#include <linux/init.h>
24#include <linux/delay.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/spinlock.h>
29#include <linux/mm.h>
30#include <linux/module.h>
00db8189
AF		 31#include <linux/mii.h>
32#include <linux/ethtool.h>
33#include <linux/phy.h>
2f495c39 34#include <linux/marvell_phy.h>
cf41a51d 35#include <linux/of.h>
00db8189 36
eea3b201 37#include <linux/io.h>
00db8189 38#include <asm/irq.h>
eea3b201 39#include <linux/uaccess.h>
00db8189 40
27d916d6
DD		 41#define MII_MARVELL_PHY_PAGE 22
42
00db8189
AF		 43#define MII_M1011_IEVENT 0x13
44#define MII_M1011_IEVENT_CLEAR 0x0000
45
46#define MII_M1011_IMASK 0x12
47#define MII_M1011_IMASK_INIT 0x6400
48#define MII_M1011_IMASK_CLEAR 0x0000
49
76884679 50#define MII_M1011_PHY_SCR 0x10
239aa55b
DT		 51#define MII_M1011_PHY_SCR_MDI 0x0000
52#define MII_M1011_PHY_SCR_MDI_X 0x0020
76884679
AF		 53#define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
54
07151bc9 55#define MII_M1145_PHY_EXT_ADDR_PAGE 0x16
b0224175 56#define MII_M1145_PHY_EXT_SR 0x1b
76884679
AF		 57#define MII_M1145_PHY_EXT_CR 0x14
58#define MII_M1145_RGMII_RX_DELAY 0x0080
59#define MII_M1145_RGMII_TX_DELAY 0x0002
b0224175
VND		 60#define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
61#define MII_M1145_HWCFG_MODE_MASK 0xf
62#define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
76884679 63
99d881f9
VB		 64#define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
65#define MII_M1145_HWCFG_MODE_MASK 0xf
66#define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
67
76884679
AF		 68#define MII_M1111_PHY_LED_CONTROL 0x18
69#define MII_M1111_PHY_LED_DIRECT 0x4100
70#define MII_M1111_PHY_LED_COMBINE 0x411c
895ee682
KP		 71#define MII_M1111_PHY_EXT_CR 0x14
72#define MII_M1111_RX_DELAY 0x80
73#define MII_M1111_TX_DELAY 0x2
74#define MII_M1111_PHY_EXT_SR 0x1b
be937f1f
AS		 75
76#define MII_M1111_HWCFG_MODE_MASK 0xf
77#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
78#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
4117b5be 79#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
5f8cbc13 80#define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
be937f1f
AS		 81#define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
82#define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
83
84#define MII_M1111_COPPER 0
85#define MII_M1111_FIBER 1
86
c477d044
CC		 87#define MII_88E1121_PHY_MSCR_PAGE 2
88#define MII_88E1121_PHY_MSCR_REG 21
89#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
90#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
91#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
92
337ac9d5
CC		 93#define MII_88E1318S_PHY_MSCR1_REG 16
94#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
3ff1c259 95
3871c387
MS		 96/* Copper Specific Interrupt Enable Register */
97#define MII_88E1318S_PHY_CSIER 0x12
98/* WOL Event Interrupt Enable */
99#define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
100
101/* LED Timer Control Register */
102#define MII_88E1318S_PHY_LED_PAGE 0x03
103#define MII_88E1318S_PHY_LED_TCR 0x12
104#define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
105#define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
106#define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
107
108/* Magic Packet MAC address registers */
109#define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
110#define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
111#define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
112
113#define MII_88E1318S_PHY_WOL_PAGE 0x11
114#define MII_88E1318S_PHY_WOL_CTRL 0x10
115#define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
116#define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
117
140bc929
SP		 118#define MII_88E1121_PHY_LED_CTRL 16
119#define MII_88E1121_PHY_LED_PAGE 3
120#define MII_88E1121_PHY_LED_DEF 0x0030
140bc929 121
be937f1f
AS		 122#define MII_M1011_PHY_STATUS 0x11
123#define MII_M1011_PHY_STATUS_1000 0x8000
124#define MII_M1011_PHY_STATUS_100 0x4000
125#define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
126#define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
127#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
128#define MII_M1011_PHY_STATUS_LINK 0x0400
129
3da09a51
MS		 130#define MII_M1116R_CONTROL_REG_MAC 21
131
6b358aed
SH		 132#define MII_88E3016_PHY_SPEC_CTRL 0x10
133#define MII_88E3016_DISABLE_SCRAMBLER 0x0200
134#define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
76884679 135
930b37ee
SR		 136#define MII_88E1510_GEN_CTRL_REG_1 0x14
137#define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
138#define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
139#define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
140
00db8189
AF		 141MODULE_DESCRIPTION("Marvell PHY driver");
142MODULE_AUTHOR("Andy Fleming");
143MODULE_LICENSE("GPL");
144
d2fa47d9
AL		 145struct marvell_hw_stat {
146 const char *string;
147 u8 page;
148 u8 reg;
149 u8 bits;
150};
151
152static struct marvell_hw_stat marvell_hw_stats[] = {
153 { "phy_receive_errors", 0, 21, 16},
154 { "phy_idle_errors", 0, 10, 8 },
155};
156
157struct marvell_priv {
158 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
159};
160
00db8189
AF		 161static int marvell_ack_interrupt(struct phy_device *phydev)
162{
163 int err;
164
165 /* Clear the interrupts by reading the reg */
166 err = phy_read(phydev, MII_M1011_IEVENT);
167
168 if (err < 0)
169 return err;
170
171 return 0;
172}
173
174static int marvell_config_intr(struct phy_device *phydev)
175{
176 int err;
177
76884679 178 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
00db8189
AF		 179 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
180 else
181 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
182
183 return err;
184}
185
239aa55b
DT		 186static int marvell_set_polarity(struct phy_device *phydev, int polarity)
187{
188 int reg;
189 int err;
190 int val;
191
192 /* get the current settings */
193 reg = phy_read(phydev, MII_M1011_PHY_SCR);
194 if (reg < 0)
195 return reg;
196
197 val = reg;
198 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
199 switch (polarity) {
200 case ETH_TP_MDI:
201 val |= MII_M1011_PHY_SCR_MDI;
202 break;
203 case ETH_TP_MDI_X:
204 val |= MII_M1011_PHY_SCR_MDI_X;
205 break;
206 case ETH_TP_MDI_AUTO:
207 case ETH_TP_MDI_INVALID:
208 default:
209 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
210 break;
211 }
212
213 if (val != reg) {
214 /* Set the new polarity value in the register */
215 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
216 if (err)
217 return err;
218 }
219
220 return 0;
221}
222
00db8189
AF		 223static int marvell_config_aneg(struct phy_device *phydev)
224{
225 int err;
226
227 /* The Marvell PHY has an errata which requires
228 * that certain registers get written in order
229 * to restart autonegotiation */
230 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
231
232 if (err < 0)
233 return err;
234
235 err = phy_write(phydev, 0x1d, 0x1f);
236 if (err < 0)
237 return err;
238
239 err = phy_write(phydev, 0x1e, 0x200c);
240 if (err < 0)
241 return err;
242
243 err = phy_write(phydev, 0x1d, 0x5);
244 if (err < 0)
245 return err;
246
247 err = phy_write(phydev, 0x1e, 0);
248 if (err < 0)
249 return err;
250
251 err = phy_write(phydev, 0x1e, 0x100);
252 if (err < 0)
253 return err;
254
239aa55b 255 err = marvell_set_polarity(phydev, phydev->mdix);
76884679
AF		 256 if (err < 0)
257 return err;
258
259 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
260 MII_M1111_PHY_LED_DIRECT);
261 if (err < 0)
262 return err;
00db8189
AF		 263
264 err = genphy_config_aneg(phydev);
8ff44985
AV		 265 if (err < 0)
266 return err;
00db8189 267
8ff44985
AV		 268 if (phydev->autoneg != AUTONEG_ENABLE) {
269 int bmcr;
270
271 /*
272 * A write to speed/duplex bits (that is performed by
273 * genphy_config_aneg() call above) must be followed by
274 * a software reset. Otherwise, the write has no effect.
275 */
276 bmcr = phy_read(phydev, MII_BMCR);
277 if (bmcr < 0)
278 return bmcr;
279
280 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
281 if (err < 0)
282 return err;
283 }
284
285 return 0;
00db8189
AF		 286}
287
cf41a51d
DD		 288#ifdef CONFIG_OF_MDIO
289/*
290 * Set and/or override some configuration registers based on the
291 * marvell,reg-init property stored in the of_node for the phydev.
292 *
293 * marvell,reg-init = <reg-page reg mask value>,...;
294 *
295 * There may be one or more sets of <reg-page reg mask value>:
296 *
297 * reg-page: which register bank to use.
298 * reg: the register.
299 * mask: if non-zero, ANDed with existing register value.
300 * value: ORed with the masked value and written to the regiser.
301 *
302 */
303static int marvell_of_reg_init(struct phy_device *phydev)
304{
305 const __be32 *paddr;
306 int len, i, saved_page, current_page, page_changed, ret;
307
e5a03bfd 308 if (!phydev->mdio.dev.of_node)
cf41a51d
DD		 309 return 0;
310
e5a03bfd
AL		 311 paddr = of_get_property(phydev->mdio.dev.of_node,
312 "marvell,reg-init", &len);
cf41a51d
DD		 313 if (!paddr || len < (4 * sizeof(*paddr)))
314 return 0;
315
316 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
317 if (saved_page < 0)
318 return saved_page;
319 page_changed = 0;
320 current_page = saved_page;
321
322 ret = 0;
323 len /= sizeof(*paddr);
324 for (i = 0; i < len - 3; i += 4) {
325 u16 reg_page = be32_to_cpup(paddr + i);
326 u16 reg = be32_to_cpup(paddr + i + 1);
327 u16 mask = be32_to_cpup(paddr + i + 2);
328 u16 val_bits = be32_to_cpup(paddr + i + 3);
329 int val;
330
331 if (reg_page != current_page) {
332 current_page = reg_page;
333 page_changed = 1;
334 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
335 if (ret < 0)
336 goto err;
337 }
338
339 val = 0;
340 if (mask) {
341 val = phy_read(phydev, reg);
342 if (val < 0) {
343 ret = val;
344 goto err;
345 }
346 val &= mask;
347 }
348 val |= val_bits;
349
350 ret = phy_write(phydev, reg, val);
351 if (ret < 0)
352 goto err;
353
354 }
355err:
356 if (page_changed) {
357 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
358 if (ret == 0)
359 ret = i;
360 }
361 return ret;
362}
363#else
364static int marvell_of_reg_init(struct phy_device *phydev)
365{
366 return 0;
367}
368#endif /* CONFIG_OF_MDIO */
369
140bc929
SP		 370static int m88e1121_config_aneg(struct phy_device *phydev)
371{
c477d044
CC		 372 int err, oldpage, mscr;
373
27d916d6 374 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
c477d044 375
27d916d6 376 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
c477d044
CC		 377 MII_88E1121_PHY_MSCR_PAGE);
378 if (err < 0)
379 return err;
be8c6480 380
32a64161 381 if (phy_interface_is_rgmii(phydev)) {
be8c6480
AP		 382
383 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
384 MII_88E1121_PHY_MSCR_DELAY_MASK;
385
386 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
387 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
388 MII_88E1121_PHY_MSCR_TX_DELAY);
389 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
390 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
391 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
392 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
393
394 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
395 if (err < 0)
396 return err;
397 }
c477d044 398
27d916d6 399 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
140bc929
SP		 400
401 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
402 if (err < 0)
403 return err;
404
405 err = phy_write(phydev, MII_M1011_PHY_SCR,
406 MII_M1011_PHY_SCR_AUTO_CROSS);
407 if (err < 0)
408 return err;
409
fdecf36f 410 return genphy_config_aneg(phydev);
140bc929
SP		 411}
412
337ac9d5 413static int m88e1318_config_aneg(struct phy_device *phydev)
3ff1c259
CC		 414{
415 int err, oldpage, mscr;
416
27d916d6 417 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
3ff1c259 418
27d916d6 419 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
3ff1c259
CC		 420 MII_88E1121_PHY_MSCR_PAGE);
421 if (err < 0)
422 return err;
423
337ac9d5
CC		 424 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
425 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
3ff1c259 426
337ac9d5 427 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
3ff1c259
CC		 428 if (err < 0)
429 return err;
430
27d916d6 431 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
3ff1c259
CC		 432 if (err < 0)
433 return err;
434
435 return m88e1121_config_aneg(phydev);
436}
437
10e24caa
MS		 438static int m88e1510_config_aneg(struct phy_device *phydev)
439{
440 int err;
441
442 err = m88e1318_config_aneg(phydev);
443 if (err < 0)
444 return err;
445
79be1a1c
CG		 446 return 0;
447}
448
449static int marvell_config_init(struct phy_device *phydev)
450{
451 /* Set registers from marvell,reg-init DT property */
10e24caa
MS		 452 return marvell_of_reg_init(phydev);
453}
454
3da09a51
MS		 455static int m88e1116r_config_init(struct phy_device *phydev)
456{
457 int temp;
458 int err;
459
460 temp = phy_read(phydev, MII_BMCR);
461 temp |= BMCR_RESET;
462 err = phy_write(phydev, MII_BMCR, temp);
463 if (err < 0)
464 return err;
465
466 mdelay(500);
467
468 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
469 if (err < 0)
470 return err;
471
472 temp = phy_read(phydev, MII_M1011_PHY_SCR);
473 temp |= (7 << 12); /* max number of gigabit attempts */
474 temp |= (1 << 11); /* enable downshift */
475 temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
476 err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
477 if (err < 0)
478 return err;
479
480 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
481 if (err < 0)
482 return err;
483 temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
484 temp |= (1 << 5);
485 temp |= (1 << 4);
486 err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
487 if (err < 0)
488 return err;
489 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
490 if (err < 0)
491 return err;
492
493 temp = phy_read(phydev, MII_BMCR);
494 temp |= BMCR_RESET;
495 err = phy_write(phydev, MII_BMCR, temp);
496 if (err < 0)
497 return err;
498
499 mdelay(500);
500
79be1a1c 501 return marvell_config_init(phydev);
3da09a51
MS		 502}
503
6b358aed
SH		 504static int m88e3016_config_init(struct phy_device *phydev)
505{
506 int reg;
507
508 /* Enable Scrambler and Auto-Crossover */
509 reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
510 if (reg < 0)
511 return reg;
512
513 reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
514 reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
515
516 reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
517 if (reg < 0)
518 return reg;
519
79be1a1c 520 return marvell_config_init(phydev);
6b358aed
SH		 521}
522
895ee682
KP		 523static int m88e1111_config_init(struct phy_device *phydev)
524{
525 int err;
be937f1f 526 int temp;
be937f1f 527
32a64161 528 if (phy_interface_is_rgmii(phydev)) {
895ee682 529
9daf5a76
KP		 530 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
531 if (temp < 0)
532 return temp;
895ee682 533
9daf5a76 534 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
895ee682 535 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
9daf5a76
KP		 536 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
537 temp &= ~MII_M1111_TX_DELAY;
538 temp |= MII_M1111_RX_DELAY;
539 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
540 temp &= ~MII_M1111_RX_DELAY;
541 temp |= MII_M1111_TX_DELAY;
895ee682
KP		 542 }
543
9daf5a76
KP		 544 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
545 if (err < 0)
546 return err;
547
895ee682
KP		 548 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
549 if (temp < 0)
550 return temp;
551
552 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
be937f1f 553
7239016d 554 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
be937f1f
AS		 555 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
556 else
557 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
895ee682
KP		 558
559 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
560 if (err < 0)
561 return err;
562 }
563
4117b5be 564 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
4117b5be
KJ		 565 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
566 if (temp < 0)
567 return temp;
568
569 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
570 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
32d0c1e1 571 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
4117b5be
KJ		 572
573 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
574 if (err < 0)
575 return err;
07151bc9
MB		 576
577 /* make sure copper is selected */
578 err = phy_read(phydev, MII_M1145_PHY_EXT_ADDR_PAGE);
579 if (err < 0)
580 return err;
581
582 err = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE,
583 err & (~0xff));
584 if (err < 0)
585 return err;
4117b5be
KJ		 586 }
587
5f8cbc13
LYB		 588 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
589 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
590 if (temp < 0)
591 return temp;
592 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
593 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
594 if (err < 0)
595 return err;
596
597 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
598 if (temp < 0)
599 return temp;
600 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
601 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
602 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
603 if (err < 0)
604 return err;
605
606 /* soft reset */
607 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
608 if (err < 0)
609 return err;
610 do
611 temp = phy_read(phydev, MII_BMCR);
612 while (temp & BMCR_RESET);
613
614 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
615 if (temp < 0)
616 return temp;
617 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
618 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
619 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
620 if (err < 0)
621 return err;
622 }
623
cf41a51d
DD		 624 err = marvell_of_reg_init(phydev);
625 if (err < 0)
626 return err;
5f8cbc13 627
cc90cb3b 628 return phy_write(phydev, MII_BMCR, BMCR_RESET);
895ee682
KP		 629}
630
fdecf36f
CG		 631static int m88e1121_config_init(struct phy_device *phydev)
632{
633 int err, oldpage;
634
635 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
636
637 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
638 if (err < 0)
639 return err;
640
641 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
642 err = phy_write(phydev, MII_88E1121_PHY_LED_CTRL,
643 MII_88E1121_PHY_LED_DEF);
644 if (err < 0)
645 return err;
646
647 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
648
649 /* Set marvell,reg-init configuration from device tree */
650 return marvell_config_init(phydev);
651}
652
407353ec
CG		 653static int m88e1510_config_init(struct phy_device *phydev)
654{
655 int err;
656 int temp;
657
658 /* SGMII-to-Copper mode initialization */
659 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
660 /* Select page 18 */
661 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 18);
662 if (err < 0)
663 return err;
664
665 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
666 temp = phy_read(phydev, MII_88E1510_GEN_CTRL_REG_1);
667 temp &= ~MII_88E1510_GEN_CTRL_REG_1_MODE_MASK;
668 temp |= MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII;
669 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
670 if (err < 0)
671 return err;
672
673 /* PHY reset is necessary after changing MODE[2:0] */
674 temp |= MII_88E1510_GEN_CTRL_REG_1_RESET;
675 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
676 if (err < 0)
677 return err;
678
679 /* Reset page selection */
680 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
681 if (err < 0)
682 return err;
683 }
684
fdecf36f 685 return m88e1121_config_init(phydev);
407353ec
CG		 686}
687
605f196e
RM		 688static int m88e1118_config_aneg(struct phy_device *phydev)
689{
690 int err;
691
692 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
693 if (err < 0)
694 return err;
695
696 err = phy_write(phydev, MII_M1011_PHY_SCR,
697 MII_M1011_PHY_SCR_AUTO_CROSS);
698 if (err < 0)
699 return err;
700
701 err = genphy_config_aneg(phydev);
702 return 0;
703}
704
705static int m88e1118_config_init(struct phy_device *phydev)
706{
707 int err;
708
709 /* Change address */
27d916d6 710 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
605f196e
RM		 711 if (err < 0)
712 return err;
713
714 /* Enable 1000 Mbit */
715 err = phy_write(phydev, 0x15, 0x1070);
716 if (err < 0)
717 return err;
718
719 /* Change address */
27d916d6 720 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
605f196e
RM		 721 if (err < 0)
722 return err;
723
724 /* Adjust LED Control */
2f495c39
BH		 725 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
726 err = phy_write(phydev, 0x10, 0x1100);
727 else
728 err = phy_write(phydev, 0x10, 0x021e);
605f196e
RM		 729 if (err < 0)
730 return err;
731
cf41a51d
DD		 732 err = marvell_of_reg_init(phydev);
733 if (err < 0)
734 return err;
735
605f196e 736 /* Reset address */
27d916d6 737 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
605f196e
RM		 738 if (err < 0)
739 return err;
740
cc90cb3b 741 return phy_write(phydev, MII_BMCR, BMCR_RESET);
605f196e
RM		 742}
743
90600732
DD		 744static int m88e1149_config_init(struct phy_device *phydev)
745{
746 int err;
747
748 /* Change address */
749 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
750 if (err < 0)
751 return err;
752
753 /* Enable 1000 Mbit */
754 err = phy_write(phydev, 0x15, 0x1048);
755 if (err < 0)
756 return err;
757
cf41a51d
DD		 758 err = marvell_of_reg_init(phydev);
759 if (err < 0)
760 return err;
761
90600732
DD		 762 /* Reset address */
763 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
764 if (err < 0)
765 return err;
766
cc90cb3b 767 return phy_write(phydev, MII_BMCR, BMCR_RESET);
90600732
DD		 768}
769
76884679
AF		 770static int m88e1145_config_init(struct phy_device *phydev)
771{
772 int err;
b0224175 773 int temp;
76884679
AF		 774
775 /* Take care of errata E0 & E1 */
776 err = phy_write(phydev, 0x1d, 0x001b);
777 if (err < 0)
778 return err;
779
780 err = phy_write(phydev, 0x1e, 0x418f);
781 if (err < 0)
782 return err;
783
784 err = phy_write(phydev, 0x1d, 0x0016);
785 if (err < 0)
786 return err;
787
788 err = phy_write(phydev, 0x1e, 0xa2da);
789 if (err < 0)
790 return err;
791
895ee682 792 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
76884679
AF		 793 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
794 if (temp < 0)
795 return temp;
796
797 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
798
799 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
800 if (err < 0)
801 return err;
802
2f495c39 803 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
76884679
AF		 804 err = phy_write(phydev, 0x1d, 0x0012);
805 if (err < 0)
806 return err;
807
808 temp = phy_read(phydev, 0x1e);
809 if (temp < 0)
810 return temp;
811
812 temp &= 0xf03f;
813 temp |= 2 << 9; /* 36 ohm */
814 temp |= 2 << 6; /* 39 ohm */
815
816 err = phy_write(phydev, 0x1e, temp);
817 if (err < 0)
818 return err;
819
820 err = phy_write(phydev, 0x1d, 0x3);
821 if (err < 0)
822 return err;
823
824 err = phy_write(phydev, 0x1e, 0x8000);
825 if (err < 0)
826 return err;
827 }
828 }
829
b0224175
VND		 830 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
831 temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
832 if (temp < 0)
833 return temp;
834
99d881f9 835 temp &= ~MII_M1145_HWCFG_MODE_MASK;
b0224175
VND		 836 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
837 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
838
839 err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
840 if (err < 0)
841 return err;
842 }
843
cf41a51d
DD		 844 err = marvell_of_reg_init(phydev);
845 if (err < 0)
846 return err;
847
76884679
AF		 848 return 0;
849}
00db8189 850
be937f1f
AS		 851/* marvell_read_status
852 *
853 * Generic status code does not detect Fiber correctly!
f0c88f9c 854 * Description:
be937f1f
AS		 855 * Check the link, then figure out the current state
856 * by comparing what we advertise with what the link partner
857 * advertises. Start by checking the gigabit possibilities,
858 * then move on to 10/100.
859 */
860static int marvell_read_status(struct phy_device *phydev)
861{
862 int adv;
863 int err;
864 int lpa;
357cd64c 865 int lpagb;
be937f1f
AS		 866 int status = 0;
867
868 /* Update the link, but return if there
869 * was an error */
870 err = genphy_update_link(phydev);
871 if (err)
872 return err;
873
874 if (AUTONEG_ENABLE == phydev->autoneg) {
875 status = phy_read(phydev, MII_M1011_PHY_STATUS);
876 if (status < 0)
877 return status;
878
879 lpa = phy_read(phydev, MII_LPA);
880 if (lpa < 0)
881 return lpa;
882
357cd64c
RK		 883 lpagb = phy_read(phydev, MII_STAT1000);
884 if (lpagb < 0)
885 return lpagb;
886
be937f1f
AS		 887 adv = phy_read(phydev, MII_ADVERTISE);
888 if (adv < 0)
889 return adv;
890
357cd64c
RK		 891 phydev->lp_advertising = mii_stat1000_to_ethtool_lpa_t(lpagb) |
892 mii_lpa_to_ethtool_lpa_t(lpa);
893
be937f1f
AS		 894 lpa &= adv;
895
896 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
897 phydev->duplex = DUPLEX_FULL;
898 else
899 phydev->duplex = DUPLEX_HALF;
900
901 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
902 phydev->pause = phydev->asym_pause = 0;
903
904 switch (status) {
905 case MII_M1011_PHY_STATUS_1000:
906 phydev->speed = SPEED_1000;
907 break;
908
909 case MII_M1011_PHY_STATUS_100:
910 phydev->speed = SPEED_100;
911 break;
912
913 default:
914 phydev->speed = SPEED_10;
915 break;
916 }
917
918 if (phydev->duplex == DUPLEX_FULL) {
919 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
920 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
921 }
922 } else {
923 int bmcr = phy_read(phydev, MII_BMCR);
924
925 if (bmcr < 0)
926 return bmcr;
927
928 if (bmcr & BMCR_FULLDPLX)
929 phydev->duplex = DUPLEX_FULL;
930 else
931 phydev->duplex = DUPLEX_HALF;
932
933 if (bmcr & BMCR_SPEED1000)
934 phydev->speed = SPEED_1000;
935 else if (bmcr & BMCR_SPEED100)
936 phydev->speed = SPEED_100;
937 else
938 phydev->speed = SPEED_10;
939
940 phydev->pause = phydev->asym_pause = 0;
357cd64c 941 phydev->lp_advertising = 0;
be937f1f
AS		 942 }
943
944 return 0;
945}
946
6b358aed
SH		 947static int marvell_aneg_done(struct phy_device *phydev)
948{
949 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
950 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
951}
952
dcd07be3
AG		 953static int m88e1121_did_interrupt(struct phy_device *phydev)
954{
955 int imask;
956
957 imask = phy_read(phydev, MII_M1011_IEVENT);
958
959 if (imask & MII_M1011_IMASK_INIT)
960 return 1;
961
962 return 0;
963}
964
3871c387
MS		 965static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
966{
967 wol->supported = WAKE_MAGIC;
968 wol->wolopts = 0;
969
970 if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
971 MII_88E1318S_PHY_WOL_PAGE) < 0)
972 return;
973
974 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
975 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
976 wol->wolopts |= WAKE_MAGIC;
977
978 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
979 return;
980}
981
982static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
983{
984 int err, oldpage, temp;
985
986 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
987
988 if (wol->wolopts & WAKE_MAGIC) {
989 /* Explicitly switch to page 0x00, just to be sure */
990 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
991 if (err < 0)
992 return err;
993
994 /* Enable the WOL interrupt */
995 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
996 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
997 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
998 if (err < 0)
999 return err;
1000
1001 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1002 MII_88E1318S_PHY_LED_PAGE);
1003 if (err < 0)
1004 return err;
1005
1006 /* Setup LED[2] as interrupt pin (active low) */
1007 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
1008 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
1009 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
1010 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
1011 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
1012 if (err < 0)
1013 return err;
1014
1015 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1016 MII_88E1318S_PHY_WOL_PAGE);
1017 if (err < 0)
1018 return err;
1019
1020 /* Store the device address for the magic packet */
1021 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1022 ((phydev->attached_dev->dev_addr[5] << 8) |
1023 phydev->attached_dev->dev_addr[4]));
1024 if (err < 0)
1025 return err;
1026 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1027 ((phydev->attached_dev->dev_addr[3] << 8) |
1028 phydev->attached_dev->dev_addr[2]));
1029 if (err < 0)
1030 return err;
1031 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1032 ((phydev->attached_dev->dev_addr[1] << 8) |
1033 phydev->attached_dev->dev_addr[0]));
1034 if (err < 0)
1035 return err;
1036
1037 /* Clear WOL status and enable magic packet matching */
1038 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1039 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1040 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1041 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1042 if (err < 0)
1043 return err;
1044 } else {
1045 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1046 MII_88E1318S_PHY_WOL_PAGE);
1047 if (err < 0)
1048 return err;
1049
1050 /* Clear WOL status and disable magic packet matching */
1051 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1052 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1053 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1054 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1055 if (err < 0)
1056 return err;
1057 }
1058
1059 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
1060 if (err < 0)
1061 return err;
1062
1063 return 0;
1064}
1065
d2fa47d9
AL		 1066static int marvell_get_sset_count(struct phy_device *phydev)
1067{
1068 return ARRAY_SIZE(marvell_hw_stats);
1069}
1070
1071static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1072{
1073 int i;
1074
1075 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++) {
1076 memcpy(data + i * ETH_GSTRING_LEN,
1077 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1078 }
1079}
1080
1081#ifndef UINT64_MAX
1082#define UINT64_MAX (u64)(~((u64)0))
1083#endif
1084static u64 marvell_get_stat(struct phy_device *phydev, int i)
1085{
1086 struct marvell_hw_stat stat = marvell_hw_stats[i];
1087 struct marvell_priv *priv = phydev->priv;
321b4d4b
AL		 1088 int err, oldpage, val;
1089 u64 ret;
d2fa47d9
AL		 1090
1091 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
1092 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1093 stat.page);
1094 if (err < 0)
1095 return UINT64_MAX;
1096
1097 val = phy_read(phydev, stat.reg);
1098 if (val < 0) {
321b4d4b 1099 ret = UINT64_MAX;
d2fa47d9
AL		 1100 } else {
1101 val = val & ((1 << stat.bits) - 1);
1102 priv->stats[i] += val;
321b4d4b 1103 ret = priv->stats[i];
d2fa47d9
AL		 1104 }
1105
1106 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
1107
321b4d4b 1108 return ret;
d2fa47d9
AL		 1109}
1110
1111static void marvell_get_stats(struct phy_device *phydev,
1112 struct ethtool_stats *stats, u64 *data)
1113{
1114 int i;
1115
1116 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++)
1117 data[i] = marvell_get_stat(phydev, i);
1118}
1119
1120static int marvell_probe(struct phy_device *phydev)
1121{
1122 struct marvell_priv *priv;
1123
e5a03bfd 1124 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
d2fa47d9
AL		 1125 if (!priv)
1126 return -ENOMEM;
1127
1128 phydev->priv = priv;
1129
1130 return 0;
1131}
1132
e5479239
OJ		 1133static struct phy_driver marvell_drivers[] = {
1134 {
2f495c39
BH		 1135 .phy_id = MARVELL_PHY_ID_88E1101,
1136 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 1137 .name = "Marvell 88E1101",
1138 .features = PHY_GBIT_FEATURES,
d2fa47d9 1139 .probe = marvell_probe,
e5479239 1140 .flags = PHY_HAS_INTERRUPT,
79be1a1c 1141 .config_init = &marvell_config_init,
e5479239
OJ		 1142 .config_aneg = &marvell_config_aneg,
1143 .read_status = &genphy_read_status,
1144 .ack_interrupt = &marvell_ack_interrupt,
1145 .config_intr = &marvell_config_intr,
0898b448
SH		 1146 .resume = &genphy_resume,
1147 .suspend = &genphy_suspend,
d2fa47d9
AL		 1148 .get_sset_count = marvell_get_sset_count,
1149 .get_strings = marvell_get_strings,
1150 .get_stats = marvell_get_stats,
e5479239 1151 },
85cfb534 1152 {
2f495c39
BH		 1153 .phy_id = MARVELL_PHY_ID_88E1112,
1154 .phy_id_mask = MARVELL_PHY_ID_MASK,
85cfb534
OJ		 1155 .name = "Marvell 88E1112",
1156 .features = PHY_GBIT_FEATURES,
1157 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1158 .probe = marvell_probe,
85cfb534
OJ		 1159 .config_init = &m88e1111_config_init,
1160 .config_aneg = &marvell_config_aneg,
1161 .read_status = &genphy_read_status,
1162 .ack_interrupt = &marvell_ack_interrupt,
1163 .config_intr = &marvell_config_intr,
0898b448
SH		 1164 .resume = &genphy_resume,
1165 .suspend = &genphy_suspend,
d2fa47d9
AL		 1166 .get_sset_count = marvell_get_sset_count,
1167 .get_strings = marvell_get_strings,
1168 .get_stats = marvell_get_stats,
85cfb534 1169 },
e5479239 1170 {
2f495c39
BH		 1171 .phy_id = MARVELL_PHY_ID_88E1111,
1172 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 1173 .name = "Marvell 88E1111",
1174 .features = PHY_GBIT_FEATURES,
1175 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1176 .probe = marvell_probe,
e5479239
OJ		 1177 .config_init = &m88e1111_config_init,
1178 .config_aneg = &marvell_config_aneg,
be937f1f 1179 .read_status = &marvell_read_status,
e5479239
OJ		 1180 .ack_interrupt = &marvell_ack_interrupt,
1181 .config_intr = &marvell_config_intr,
0898b448
SH		 1182 .resume = &genphy_resume,
1183 .suspend = &genphy_suspend,
d2fa47d9
AL		 1184 .get_sset_count = marvell_get_sset_count,
1185 .get_strings = marvell_get_strings,
1186 .get_stats = marvell_get_stats,
e5479239 1187 },
605f196e 1188 {
2f495c39
BH		 1189 .phy_id = MARVELL_PHY_ID_88E1118,
1190 .phy_id_mask = MARVELL_PHY_ID_MASK,
605f196e
RM		 1191 .name = "Marvell 88E1118",
1192 .features = PHY_GBIT_FEATURES,
1193 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1194 .probe = marvell_probe,
605f196e
RM		 1195 .config_init = &m88e1118_config_init,
1196 .config_aneg = &m88e1118_config_aneg,
1197 .read_status = &genphy_read_status,
1198 .ack_interrupt = &marvell_ack_interrupt,
1199 .config_intr = &marvell_config_intr,
0898b448
SH		 1200 .resume = &genphy_resume,
1201 .suspend = &genphy_suspend,
d2fa47d9
AL		 1202 .get_sset_count = marvell_get_sset_count,
1203 .get_strings = marvell_get_strings,
1204 .get_stats = marvell_get_stats,
605f196e 1205 },
140bc929 1206 {
2f495c39
BH		 1207 .phy_id = MARVELL_PHY_ID_88E1121R,
1208 .phy_id_mask = MARVELL_PHY_ID_MASK,
140bc929
SP		 1209 .name = "Marvell 88E1121R",
1210 .features = PHY_GBIT_FEATURES,
1211 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1212 .probe = marvell_probe,
fdecf36f 1213 .config_init = &m88e1121_config_init,
140bc929
SP		 1214 .config_aneg = &m88e1121_config_aneg,
1215 .read_status = &marvell_read_status,
1216 .ack_interrupt = &marvell_ack_interrupt,
1217 .config_intr = &marvell_config_intr,
dcd07be3 1218 .did_interrupt = &m88e1121_did_interrupt,
0898b448
SH		 1219 .resume = &genphy_resume,
1220 .suspend = &genphy_suspend,
d2fa47d9
AL		 1221 .get_sset_count = marvell_get_sset_count,
1222 .get_strings = marvell_get_strings,
1223 .get_stats = marvell_get_stats,
140bc929 1224 },
3ff1c259 1225 {
337ac9d5 1226 .phy_id = MARVELL_PHY_ID_88E1318S,
6ba74014 1227 .phy_id_mask = MARVELL_PHY_ID_MASK,
337ac9d5 1228 .name = "Marvell 88E1318S",
3ff1c259
CC		 1229 .features = PHY_GBIT_FEATURES,
1230 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1231 .probe = marvell_probe,
fdecf36f 1232 .config_init = &m88e1121_config_init,
337ac9d5 1233 .config_aneg = &m88e1318_config_aneg,
3ff1c259
CC		 1234 .read_status = &marvell_read_status,
1235 .ack_interrupt = &marvell_ack_interrupt,
1236 .config_intr = &marvell_config_intr,
1237 .did_interrupt = &m88e1121_did_interrupt,
3871c387
MS		 1238 .get_wol = &m88e1318_get_wol,
1239 .set_wol = &m88e1318_set_wol,
0898b448
SH		 1240 .resume = &genphy_resume,
1241 .suspend = &genphy_suspend,
d2fa47d9
AL		 1242 .get_sset_count = marvell_get_sset_count,
1243 .get_strings = marvell_get_strings,
1244 .get_stats = marvell_get_stats,
3ff1c259 1245 },
e5479239 1246 {
2f495c39
BH		 1247 .phy_id = MARVELL_PHY_ID_88E1145,
1248 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 1249 .name = "Marvell 88E1145",
1250 .features = PHY_GBIT_FEATURES,
1251 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1252 .probe = marvell_probe,
e5479239
OJ		 1253 .config_init = &m88e1145_config_init,
1254 .config_aneg = &marvell_config_aneg,
1255 .read_status = &genphy_read_status,
1256 .ack_interrupt = &marvell_ack_interrupt,
1257 .config_intr = &marvell_config_intr,
0898b448
SH		 1258 .resume = &genphy_resume,
1259 .suspend = &genphy_suspend,
d2fa47d9
AL		 1260 .get_sset_count = marvell_get_sset_count,
1261 .get_strings = marvell_get_strings,
1262 .get_stats = marvell_get_stats,
ac8c635a 1263 },
90600732
DD		 1264 {
1265 .phy_id = MARVELL_PHY_ID_88E1149R,
1266 .phy_id_mask = MARVELL_PHY_ID_MASK,
1267 .name = "Marvell 88E1149R",
1268 .features = PHY_GBIT_FEATURES,
1269 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1270 .probe = marvell_probe,
90600732
DD		 1271 .config_init = &m88e1149_config_init,
1272 .config_aneg = &m88e1118_config_aneg,
1273 .read_status = &genphy_read_status,
1274 .ack_interrupt = &marvell_ack_interrupt,
1275 .config_intr = &marvell_config_intr,
0898b448
SH		 1276 .resume = &genphy_resume,
1277 .suspend = &genphy_suspend,
d2fa47d9
AL		 1278 .get_sset_count = marvell_get_sset_count,
1279 .get_strings = marvell_get_strings,
1280 .get_stats = marvell_get_stats,
90600732 1281 },
ac8c635a 1282 {
2f495c39
BH		 1283 .phy_id = MARVELL_PHY_ID_88E1240,
1284 .phy_id_mask = MARVELL_PHY_ID_MASK,
ac8c635a
OJ		 1285 .name = "Marvell 88E1240",
1286 .features = PHY_GBIT_FEATURES,
1287 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1288 .probe = marvell_probe,
ac8c635a
OJ		 1289 .config_init = &m88e1111_config_init,
1290 .config_aneg = &marvell_config_aneg,
1291 .read_status = &genphy_read_status,
1292 .ack_interrupt = &marvell_ack_interrupt,
1293 .config_intr = &marvell_config_intr,
0898b448
SH		 1294 .resume = &genphy_resume,
1295 .suspend = &genphy_suspend,
d2fa47d9
AL		 1296 .get_sset_count = marvell_get_sset_count,
1297 .get_strings = marvell_get_strings,
1298 .get_stats = marvell_get_stats,
ac8c635a 1299 },
3da09a51
MS		 1300 {
1301 .phy_id = MARVELL_PHY_ID_88E1116R,
1302 .phy_id_mask = MARVELL_PHY_ID_MASK,
1303 .name = "Marvell 88E1116R",
1304 .features = PHY_GBIT_FEATURES,
1305 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1306 .probe = marvell_probe,
3da09a51
MS		 1307 .config_init = &m88e1116r_config_init,
1308 .config_aneg = &genphy_config_aneg,
1309 .read_status = &genphy_read_status,
1310 .ack_interrupt = &marvell_ack_interrupt,
1311 .config_intr = &marvell_config_intr,
0898b448
SH		 1312 .resume = &genphy_resume,
1313 .suspend = &genphy_suspend,
d2fa47d9
AL		 1314 .get_sset_count = marvell_get_sset_count,
1315 .get_strings = marvell_get_strings,
1316 .get_stats = marvell_get_stats,
3da09a51 1317 },
10e24caa
MS		 1318 {
1319 .phy_id = MARVELL_PHY_ID_88E1510,
1320 .phy_id_mask = MARVELL_PHY_ID_MASK,
1321 .name = "Marvell 88E1510",
1322 .features = PHY_GBIT_FEATURES,
1323 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1324 .probe = marvell_probe,
930b37ee 1325 .config_init = &m88e1510_config_init,
10e24caa
MS		 1326 .config_aneg = &m88e1510_config_aneg,
1327 .read_status = &marvell_read_status,
1328 .ack_interrupt = &marvell_ack_interrupt,
1329 .config_intr = &marvell_config_intr,
1330 .did_interrupt = &m88e1121_did_interrupt,
0898b448
SH		 1331 .resume = &genphy_resume,
1332 .suspend = &genphy_suspend,
d2fa47d9
AL		 1333 .get_sset_count = marvell_get_sset_count,
1334 .get_strings = marvell_get_strings,
1335 .get_stats = marvell_get_stats,
10e24caa 1336 },
819ec8e1
AL		 1337 {
1338 .phy_id = MARVELL_PHY_ID_88E1540,
1339 .phy_id_mask = MARVELL_PHY_ID_MASK,
1340 .name = "Marvell 88E1540",
1341 .features = PHY_GBIT_FEATURES,
1342 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1343 .probe = marvell_probe,
79be1a1c 1344 .config_init = &marvell_config_init,
819ec8e1
AL		 1345 .config_aneg = &m88e1510_config_aneg,
1346 .read_status = &marvell_read_status,
1347 .ack_interrupt = &marvell_ack_interrupt,
1348 .config_intr = &marvell_config_intr,
1349 .did_interrupt = &m88e1121_did_interrupt,
1350 .resume = &genphy_resume,
1351 .suspend = &genphy_suspend,
d2fa47d9
AL		 1352 .get_sset_count = marvell_get_sset_count,
1353 .get_strings = marvell_get_strings,
1354 .get_stats = marvell_get_stats,
819ec8e1 1355 },
6b358aed
SH		 1356 {
1357 .phy_id = MARVELL_PHY_ID_88E3016,
1358 .phy_id_mask = MARVELL_PHY_ID_MASK,
1359 .name = "Marvell 88E3016",
1360 .features = PHY_BASIC_FEATURES,
1361 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1362 .probe = marvell_probe,
6b358aed
SH		 1363 .config_aneg = &genphy_config_aneg,
1364 .config_init = &m88e3016_config_init,
1365 .aneg_done = &marvell_aneg_done,
1366 .read_status = &marvell_read_status,
1367 .ack_interrupt = &marvell_ack_interrupt,
1368 .config_intr = &marvell_config_intr,
1369 .did_interrupt = &m88e1121_did_interrupt,
1370 .resume = &genphy_resume,
1371 .suspend = &genphy_suspend,
d2fa47d9
AL		 1372 .get_sset_count = marvell_get_sset_count,
1373 .get_strings = marvell_get_strings,
1374 .get_stats = marvell_get_stats,
6b358aed 1375 },
00db8189
AF		 1376};
1377
50fd7150 1378module_phy_driver(marvell_drivers);
4e4f10f6 1379
cf93c945 1380static struct mdio_device_id __maybe_unused marvell_tbl[] = {
f5e1cabf
MS		 1381 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
1382 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
1383 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
1384 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
1385 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
1386 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
1387 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
1388 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
1389 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
3da09a51 1390 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
10e24caa 1391 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
819ec8e1 1392 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
6b358aed 1393 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
4e4f10f6
DW		 1394 { }
1395};
1396
1397MODULE_DEVICE_TABLE(mdio, marvell_tbl);
Linux kernel - Deliverables
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