[deliverable/linux.git] / drivers / net / phy / mdio-octeon.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2009,2011 Cavium, Inc.
 */

#include <linux/platform_device.h>
#include <linux/of_mdio.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/gfp.h>
#include <linux/phy.h>
#include <linux/io.h>

#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-smix-defs.h>

#define DRV_VERSION "1.0"
#define DRV_DESCRIPTION "Cavium Networks Octeon SMI/MDIO driver"

#define SMI_CMD		0x0
#define SMI_WR_DAT	0x8
#define SMI_RD_DAT	0x10
#define SMI_CLK		0x18
#define SMI_EN		0x20

struct octeon_mdiobus {
	struct mii_bus *mii_bus;
	u64 register_base;
	resource_size_t mdio_phys;
	resource_size_t regsize;
	int phy_irq[PHY_MAX_ADDR];
};

static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
{
	struct octeon_mdiobus *p = bus->priv;
	union cvmx_smix_cmd smi_cmd;
	union cvmx_smix_rd_dat smi_rd;
	int timeout = 1000;

	smi_cmd.u64 = 0;
	smi_cmd.s.phy_op = 1; /* MDIO_CLAUSE_22_READ */
	smi_cmd.s.phy_adr = phy_id;
	smi_cmd.s.reg_adr = regnum;
	cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);

	do {
		/*
		 * Wait 1000 clocks so we don't saturate the RSL bus
		 * doing reads.
		 */
		__delay(1000);
		smi_rd.u64 = cvmx_read_csr(p->register_base + SMI_RD_DAT);
	} while (smi_rd.s.pending && --timeout);

	if (smi_rd.s.val)
		return smi_rd.s.dat;
	else
		return -EIO;
}

static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id,
				int regnum, u16 val)
{
	struct octeon_mdiobus *p = bus->priv;
	union cvmx_smix_cmd smi_cmd;
	union cvmx_smix_wr_dat smi_wr;
	int timeout = 1000;

	smi_wr.u64 = 0;
	smi_wr.s.dat = val;
	cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64);

	smi_cmd.u64 = 0;
	smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_22_WRITE */
	smi_cmd.s.phy_adr = phy_id;
	smi_cmd.s.reg_adr = regnum;
	cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);

	do {
		/*
		 * Wait 1000 clocks so we don't saturate the RSL bus
		 * doing reads.
		 */
		__delay(1000);
		smi_wr.u64 = cvmx_read_csr(p->register_base + SMI_WR_DAT);
	} while (smi_wr.s.pending && --timeout);

	if (timeout <= 0)
		return -EIO;

	return 0;
}

static int octeon_mdiobus_probe(struct platform_device *pdev)
{
	struct octeon_mdiobus *bus;
	struct resource *res_mem;
	union cvmx_smix_en smi_en;
	int err = -ENOENT;

	bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
	if (!bus)
		return -ENOMEM;

	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	if (res_mem == NULL) {
		dev_err(&pdev->dev, "found no memory resource\n");
		err = -ENXIO;
		goto fail;
	}
	bus->mdio_phys = res_mem->start;
	bus->regsize = resource_size(res_mem);
	if (!devm_request_mem_region(&pdev->dev, bus->mdio_phys, bus->regsize,
				     res_mem->name)) {
		dev_err(&pdev->dev, "request_mem_region failed\n");
		goto fail;
	}
	bus->register_base =
		(u64)devm_ioremap(&pdev->dev, bus->mdio_phys, bus->regsize);

	bus->mii_bus = mdiobus_alloc();

	if (!bus->mii_bus)
		goto fail;

	smi_en.u64 = 0;
	smi_en.s.en = 1;
	cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64);

	bus->mii_bus->priv = bus;
	bus->mii_bus->irq = bus->phy_irq;
	bus->mii_bus->name = "mdio-octeon";
	snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%llx", bus->register_base);
	bus->mii_bus->parent = &pdev->dev;

	bus->mii_bus->read = octeon_mdiobus_read;
	bus->mii_bus->write = octeon_mdiobus_write;

	dev_set_drvdata(&pdev->dev, bus);

	err = of_mdiobus_register(bus->mii_bus, pdev->dev.of_node);
	if (err)
		goto fail_register;

	dev_info(&pdev->dev, "Version " DRV_VERSION "\n");

	return 0;
fail_register:
	mdiobus_free(bus->mii_bus);
fail:
	smi_en.u64 = 0;
	cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64);
	return err;
}

static int octeon_mdiobus_remove(struct platform_device *pdev)
{
	struct octeon_mdiobus *bus;
	union cvmx_smix_en smi_en;

	bus = dev_get_drvdata(&pdev->dev);

	mdiobus_unregister(bus->mii_bus);
	mdiobus_free(bus->mii_bus);
	smi_en.u64 = 0;
	cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64);
	return 0;
}

static struct of_device_id octeon_mdiobus_match[] = {
	{
		.compatible = "cavium,octeon-3860-mdio",
	},
	{},
};
MODULE_DEVICE_TABLE(of, octeon_mdiobus_match);

static struct platform_driver octeon_mdiobus_driver = {
	.driver = {
		.name		= "mdio-octeon",
		.owner		= THIS_MODULE,
		.of_match_table = octeon_mdiobus_match,
	},
	.probe		= octeon_mdiobus_probe,
	.remove		= octeon_mdiobus_remove,
};

void octeon_mdiobus_force_mod_depencency(void)
{
	/* Let ethernet drivers force us to be loaded.  */
}
EXPORT_SYMBOL(octeon_mdiobus_force_mod_depencency);

static int __init octeon_mdiobus_mod_init(void)
{
	return platform_driver_register(&octeon_mdiobus_driver);
}

static void __exit octeon_mdiobus_mod_exit(void)
{
	platform_driver_unregister(&octeon_mdiobus_driver);
}

module_init(octeon_mdiobus_mod_init);
module_exit(octeon_mdiobus_mod_exit);

MODULE_DESCRIPTION(DRV_DESCRIPTION);
MODULE_VERSION(DRV_VERSION);
MODULE_AUTHOR("David Daney");
MODULE_LICENSE("GPL");
Commit	Line	Data
25d967b7 DD	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
2fd46f47	6	* Copyright (C) 2009,2011 Cavium, Inc.
25d967b7 DD	7	*/
25d967b7 DD	8
25d967b7	9	#include <linux/platform_device.h>
2fd46f47 DD	10	#include <linux/of_mdio.h>
	11	#include <linux/delay.h>
	12	#include <linux/module.h>
	13	#include <linux/init.h>
	14	#include <linux/gfp.h>
25d967b7	15	#include <linux/phy.h>
2fd46f47	16	#include <linux/io.h>
25d967b7 DD	17
	18	#include <asm/octeon/octeon.h>
	19	#include <asm/octeon/cvmx-smix-defs.h>
	20
	21	#define DRV_VERSION "1.0"
	22	#define DRV_DESCRIPTION "Cavium Networks Octeon SMI/MDIO driver"
	23
2fd46f47 DD	24	#define SMI_CMD 0x0
	25	#define SMI_WR_DAT 0x8
	26	#define SMI_RD_DAT 0x10
	27	#define SMI_CLK 0x18
	28	#define SMI_EN 0x20
	29
25d967b7 DD	30	struct octeon_mdiobus {
25d967b7 DD	31	struct mii_bus *mii_bus;
2fd46f47 DD	32	u64 register_base;
	33	resource_size_t mdio_phys;
	34	resource_size_t regsize;
25d967b7 DD	35	int phy_irq[PHY_MAX_ADDR];
	36	};
	37
	38	static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
	39	{
	40	struct octeon_mdiobus *p = bus->priv;
	41	union cvmx_smix_cmd smi_cmd;
	42	union cvmx_smix_rd_dat smi_rd;
	43	int timeout = 1000;
	44
	45	smi_cmd.u64 = 0;
	46	smi_cmd.s.phy_op = 1; /* MDIO_CLAUSE_22_READ */
	47	smi_cmd.s.phy_adr = phy_id;
	48	smi_cmd.s.reg_adr = regnum;
2fd46f47	49	cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
25d967b7 DD	50
	51	do {
	52	/*
	53	* Wait 1000 clocks so we don't saturate the RSL bus
	54	* doing reads.
	55	*/
2fd46f47 DD	56	__delay(1000);
2fd46f47 DD	57	smi_rd.u64 = cvmx_read_csr(p->register_base + SMI_RD_DAT);
25d967b7 DD	58	} while (smi_rd.s.pending && --timeout);
	59
	60	if (smi_rd.s.val)
	61	return smi_rd.s.dat;
	62	else
	63	return -EIO;
	64	}
	65
	66	static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id,
	67	int regnum, u16 val)
	68	{
	69	struct octeon_mdiobus *p = bus->priv;
	70	union cvmx_smix_cmd smi_cmd;
	71	union cvmx_smix_wr_dat smi_wr;
	72	int timeout = 1000;
	73
	74	smi_wr.u64 = 0;
	75	smi_wr.s.dat = val;
2fd46f47	76	cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64);
25d967b7 DD	77
	78	smi_cmd.u64 = 0;
	79	smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_22_WRITE */
	80	smi_cmd.s.phy_adr = phy_id;
	81	smi_cmd.s.reg_adr = regnum;
2fd46f47	82	cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
25d967b7 DD	83
	84	do {
	85	/*
	86	* Wait 1000 clocks so we don't saturate the RSL bus
	87	* doing reads.
	88	*/
2fd46f47 DD	89	__delay(1000);
2fd46f47 DD	90	smi_wr.u64 = cvmx_read_csr(p->register_base + SMI_WR_DAT);
25d967b7 DD	91	} while (smi_wr.s.pending && --timeout);
	92
	93	if (timeout <= 0)
	94	return -EIO;
	95
	96	return 0;
	97	}
	98
633d1594	99	static int octeon_mdiobus_probe(struct platform_device *pdev)
25d967b7 DD	100	{
25d967b7 DD	101	struct octeon_mdiobus *bus;
2fd46f47	102	struct resource *res_mem;
6c17812d	103	union cvmx_smix_en smi_en;
25d967b7 DD	104	int err = -ENOENT;
	105
	106	bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
	107	if (!bus)
	108	return -ENOMEM;
	109
2fd46f47 DD	110	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	111
	112	if (res_mem == NULL) {
	113	dev_err(&pdev->dev, "found no memory resource\n");
	114	err = -ENXIO;
	115	goto fail;
	116	}
	117	bus->mdio_phys = res_mem->start;
	118	bus->regsize = resource_size(res_mem);
	119	if (!devm_request_mem_region(&pdev->dev, bus->mdio_phys, bus->regsize,
	120	res_mem->name)) {
	121	dev_err(&pdev->dev, "request_mem_region failed\n");
	122	goto fail;
	123	}
	124	bus->register_base =
	125	(u64)devm_ioremap(&pdev->dev, bus->mdio_phys, bus->regsize);
25d967b7 DD	126
	127	bus->mii_bus = mdiobus_alloc();
	128
	129	if (!bus->mii_bus)
2fd46f47	130	goto fail;
25d967b7	131
6c17812d DD	132	smi_en.u64 = 0;
6c17812d DD	133	smi_en.s.en = 1;
2fd46f47	134	cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64);
25d967b7 DD	135
	136	bus->mii_bus->priv = bus;
	137	bus->mii_bus->irq = bus->phy_irq;
	138	bus->mii_bus->name = "mdio-octeon";
2fd46f47	139	snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%llx", bus->register_base);
25d967b7 DD	140	bus->mii_bus->parent = &pdev->dev;
	141
	142	bus->mii_bus->read = octeon_mdiobus_read;
	143	bus->mii_bus->write = octeon_mdiobus_write;
	144
	145	dev_set_drvdata(&pdev->dev, bus);
	146
2fd46f47	147	err = of_mdiobus_register(bus->mii_bus, pdev->dev.of_node);
25d967b7	148	if (err)
2fd46f47	149	goto fail_register;
25d967b7 DD	150
	151	dev_info(&pdev->dev, "Version " DRV_VERSION "\n");
	152
	153	return 0;
2fd46f47	154	fail_register:
25d967b7	155	mdiobus_free(bus->mii_bus);
2fd46f47	156	fail:
6c17812d	157	smi_en.u64 = 0;
2fd46f47	158	cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64);
25d967b7 DD	159	return err;
	160	}
	161
633d1594	162	static int octeon_mdiobus_remove(struct platform_device *pdev)
25d967b7 DD	163	{
25d967b7 DD	164	struct octeon_mdiobus *bus;
6c17812d	165	union cvmx_smix_en smi_en;
25d967b7 DD	166
	167	bus = dev_get_drvdata(&pdev->dev);
	168
	169	mdiobus_unregister(bus->mii_bus);
	170	mdiobus_free(bus->mii_bus);
6c17812d	171	smi_en.u64 = 0;
2fd46f47	172	cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64);
25d967b7 DD	173	return 0;
	174	}
	175
2fd46f47 DD	176	static struct of_device_id octeon_mdiobus_match[] = {
	177	{
	178	.compatible = "cavium,octeon-3860-mdio",
	179	},
	180	{},
	181	};
	182	MODULE_DEVICE_TABLE(of, octeon_mdiobus_match);
	183
25d967b7 DD	184	static struct platform_driver octeon_mdiobus_driver = {
	185	.driver = {
	186	.name = "mdio-octeon",
	187	.owner = THIS_MODULE,
2fd46f47	188	.of_match_table = octeon_mdiobus_match,
25d967b7 DD	189	},
25d967b7 DD	190	.probe = octeon_mdiobus_probe,
633d1594	191	.remove = octeon_mdiobus_remove,
25d967b7 DD	192	};
	193
	194	void octeon_mdiobus_force_mod_depencency(void)
	195	{
	196	/* Let ethernet drivers force us to be loaded. */
	197	}
	198	EXPORT_SYMBOL(octeon_mdiobus_force_mod_depencency);
	199
	200	static int __init octeon_mdiobus_mod_init(void)
	201	{
	202	return platform_driver_register(&octeon_mdiobus_driver);
	203	}
	204
	205	static void __exit octeon_mdiobus_mod_exit(void)
	206	{
	207	platform_driver_unregister(&octeon_mdiobus_driver);
	208	}
	209
	210	module_init(octeon_mdiobus_mod_init);
	211	module_exit(octeon_mdiobus_mod_exit);
	212
	213	MODULE_DESCRIPTION(DRV_DESCRIPTION);
	214	MODULE_VERSION(DRV_VERSION);
	215	MODULE_AUTHOR("David Daney");
	216	MODULE_LICENSE("GPL");