[deliverable/linux.git] / drivers / net / phy / mdio-octeon.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2009-2012 Cavium, Inc.
 */

#include <linux/platform_device.h>
#include <linux/of_address.h>
#include <linux/of_mdio.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/gfp.h>
#include <linux/phy.h>
#include <linux/io.h>

#ifdef CONFIG_CAVIUM_OCTEON_SOC
#include <asm/octeon/octeon.h>
#endif

#define DRV_VERSION "1.1"
#define DRV_DESCRIPTION "Cavium Networks Octeon/ThunderX SMI/MDIO driver"

#define SMI_CMD		0x0
#define SMI_WR_DAT	0x8
#define SMI_RD_DAT	0x10
#define SMI_CLK		0x18
#define SMI_EN		0x20

#ifdef __BIG_ENDIAN_BITFIELD
#define OCT_MDIO_BITFIELD_FIELD(field, more)	\
	field;					\
	more

#else
#define OCT_MDIO_BITFIELD_FIELD(field, more)	\
	more					\
	field;

#endif

union cvmx_smix_clk {
	u64 u64;
	struct cvmx_smix_clk_s {
	  OCT_MDIO_BITFIELD_FIELD(u64 reserved_25_63:39,
	  OCT_MDIO_BITFIELD_FIELD(u64 mode:1,
	  OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
	  OCT_MDIO_BITFIELD_FIELD(u64 sample_hi:5,
	  OCT_MDIO_BITFIELD_FIELD(u64 sample_mode:1,
	  OCT_MDIO_BITFIELD_FIELD(u64 reserved_14_14:1,
	  OCT_MDIO_BITFIELD_FIELD(u64 clk_idle:1,
	  OCT_MDIO_BITFIELD_FIELD(u64 preamble:1,
	  OCT_MDIO_BITFIELD_FIELD(u64 sample:4,
	  OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
	  ;))))))))))
	} s;
};

union cvmx_smix_cmd {
	u64 u64;
	struct cvmx_smix_cmd_s {
	  OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
	  OCT_MDIO_BITFIELD_FIELD(u64 phy_op:2,
	  OCT_MDIO_BITFIELD_FIELD(u64 reserved_13_15:3,
	  OCT_MDIO_BITFIELD_FIELD(u64 phy_adr:5,
	  OCT_MDIO_BITFIELD_FIELD(u64 reserved_5_7:3,
	  OCT_MDIO_BITFIELD_FIELD(u64 reg_adr:5,
	  ;))))))
	} s;
};

union cvmx_smix_en {
	u64 u64;
	struct cvmx_smix_en_s {
	  OCT_MDIO_BITFIELD_FIELD(u64 reserved_1_63:63,
	  OCT_MDIO_BITFIELD_FIELD(u64 en:1,
	  ;))
	} s;
};

union cvmx_smix_rd_dat {
	u64 u64;
	struct cvmx_smix_rd_dat_s {
	  OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
	  OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
	  OCT_MDIO_BITFIELD_FIELD(u64 val:1,
	  OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
	  ;))))
	} s;
};

union cvmx_smix_wr_dat {
	u64 u64;
	struct cvmx_smix_wr_dat_s {
	  OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
	  OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
	  OCT_MDIO_BITFIELD_FIELD(u64 val:1,
	  OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
	  ;))))
	} s;
};

enum octeon_mdiobus_mode {
	UNINIT = 0,
	C22,
	C45
};

struct octeon_mdiobus {
	struct mii_bus *mii_bus;
	u64 register_base;
	resource_size_t mdio_phys;
	resource_size_t regsize;
	enum octeon_mdiobus_mode mode;
};

#ifdef CONFIG_CAVIUM_OCTEON_SOC
static void oct_mdio_writeq(u64 val, u64 addr)
{
	cvmx_write_csr(addr, val);
}

static u64 oct_mdio_readq(u64 addr)
{
	return cvmx_read_csr(addr);
}
#else
#define oct_mdio_writeq(val, addr)	writeq_relaxed(val, (void *)addr)
#define oct_mdio_readq(addr)		readq_relaxed((void *)addr)
#endif

static void octeon_mdiobus_set_mode(struct octeon_mdiobus *p,
				    enum octeon_mdiobus_mode m)
{
	union cvmx_smix_clk smi_clk;

	if (m == p->mode)
		return;

	smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK);
	smi_clk.s.mode = (m == C45) ? 1 : 0;
	smi_clk.s.preamble = 1;
	oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK);
	p->mode = m;
}

static int octeon_mdiobus_c45_addr(struct octeon_mdiobus *p,
				   int phy_id, int regnum)
{
	union cvmx_smix_cmd smi_cmd;
	union cvmx_smix_wr_dat smi_wr;
	int timeout = 1000;

	octeon_mdiobus_set_mode(p, C45);

	smi_wr.u64 = 0;
	smi_wr.s.dat = regnum & 0xffff;
	oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);

	regnum = (regnum >> 16) & 0x1f;

	smi_cmd.u64 = 0;
	smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_45_ADDRESS */
	smi_cmd.s.phy_adr = phy_id;
	smi_cmd.s.reg_adr = regnum;
	oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);

	do {
		/* Wait 1000 clocks so we don't saturate the RSL bus
		 * doing reads.
		 */
		__delay(1000);
		smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
	} while (smi_wr.s.pending && --timeout);

	if (timeout <= 0)
		return -EIO;
	return 0;
}

static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
{
	struct octeon_mdiobus *p = bus->priv;
	union cvmx_smix_cmd smi_cmd;
	union cvmx_smix_rd_dat smi_rd;
	unsigned int op = 1; /* MDIO_CLAUSE_22_READ */
	int timeout = 1000;

	if (regnum & MII_ADDR_C45) {
		int r = octeon_mdiobus_c45_addr(p, phy_id, regnum);
		if (r < 0)
			return r;

		regnum = (regnum >> 16) & 0x1f;
		op = 3; /* MDIO_CLAUSE_45_READ */
	} else {
		octeon_mdiobus_set_mode(p, C22);
	}


	smi_cmd.u64 = 0;
	smi_cmd.s.phy_op = op;
	smi_cmd.s.phy_adr = phy_id;
	smi_cmd.s.reg_adr = regnum;
	oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);

	do {
		/* Wait 1000 clocks so we don't saturate the RSL bus
		 * doing reads.
		 */
		__delay(1000);
		smi_rd.u64 = oct_mdio_readq(p->register_base + SMI_RD_DAT);
	} while (smi_rd.s.pending && --timeout);

	if (smi_rd.s.val)
		return smi_rd.s.dat;
	else
		return -EIO;
}

static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id,
				int regnum, u16 val)
{
	struct octeon_mdiobus *p = bus->priv;
	union cvmx_smix_cmd smi_cmd;
	union cvmx_smix_wr_dat smi_wr;
	unsigned int op = 0; /* MDIO_CLAUSE_22_WRITE */
	int timeout = 1000;


	if (regnum & MII_ADDR_C45) {
		int r = octeon_mdiobus_c45_addr(p, phy_id, regnum);
		if (r < 0)
			return r;

		regnum = (regnum >> 16) & 0x1f;
		op = 1; /* MDIO_CLAUSE_45_WRITE */
	} else {
		octeon_mdiobus_set_mode(p, C22);
	}

	smi_wr.u64 = 0;
	smi_wr.s.dat = val;
	oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);

	smi_cmd.u64 = 0;
	smi_cmd.s.phy_op = op;
	smi_cmd.s.phy_adr = phy_id;
	smi_cmd.s.reg_adr = regnum;
	oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);

	do {
		/* Wait 1000 clocks so we don't saturate the RSL bus
		 * doing reads.
		 */
		__delay(1000);
		smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
	} while (smi_wr.s.pending && --timeout);

	if (timeout <= 0)
		return -EIO;

	return 0;
}

static int octeon_mdiobus_probe(struct platform_device *pdev)
{
	struct octeon_mdiobus *bus;
	struct mii_bus *mii_bus;
	struct resource *res_mem;
	union cvmx_smix_en smi_en;
	int err = -ENOENT;

	mii_bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*bus));
	if (!mii_bus)
		return -ENOMEM;

	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res_mem == NULL) {
		dev_err(&pdev->dev, "found no memory resource\n");
		return -ENXIO;
	}

	bus = mii_bus->priv;
	bus->mii_bus = mii_bus;
	bus->mdio_phys = res_mem->start;
	bus->regsize = resource_size(res_mem);

	if (!devm_request_mem_region(&pdev->dev, bus->mdio_phys, bus->regsize,
				     res_mem->name)) {
		dev_err(&pdev->dev, "request_mem_region failed\n");
		return -ENXIO;
	}

	bus->register_base =
		(u64)devm_ioremap(&pdev->dev, bus->mdio_phys, bus->regsize);
	if (!bus->register_base) {
		dev_err(&pdev->dev, "dev_ioremap failed\n");
		return -ENOMEM;
	}

	smi_en.u64 = 0;
	smi_en.s.en = 1;
	oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);

	bus->mii_bus->priv = bus;
	bus->mii_bus->name = "mdio-octeon";
	snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%llx", bus->register_base);
	bus->mii_bus->parent = &pdev->dev;

	bus->mii_bus->read = octeon_mdiobus_read;
	bus->mii_bus->write = octeon_mdiobus_write;

	platform_set_drvdata(pdev, bus);

	err = of_mdiobus_register(bus->mii_bus, pdev->dev.of_node);
	if (err)
		goto fail_register;

	dev_info(&pdev->dev, "Version " DRV_VERSION "\n");

	return 0;
fail_register:
	mdiobus_free(bus->mii_bus);
	smi_en.u64 = 0;
	oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
	return err;
}

static int octeon_mdiobus_remove(struct platform_device *pdev)
{
	struct octeon_mdiobus *bus;
	union cvmx_smix_en smi_en;

	bus = platform_get_drvdata(pdev);

	mdiobus_unregister(bus->mii_bus);
	mdiobus_free(bus->mii_bus);
	smi_en.u64 = 0;
	oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
	return 0;
}

static const struct of_device_id octeon_mdiobus_match[] = {
	{
		.compatible = "cavium,octeon-3860-mdio",
	},
	{},
};
MODULE_DEVICE_TABLE(of, octeon_mdiobus_match);

static struct platform_driver octeon_mdiobus_driver = {
	.driver = {
		.name		= "mdio-octeon",
		.of_match_table = octeon_mdiobus_match,
	},
	.probe		= octeon_mdiobus_probe,
	.remove		= octeon_mdiobus_remove,
};

void octeon_mdiobus_force_mod_depencency(void)
{
	/* Let ethernet drivers force us to be loaded.  */
}
EXPORT_SYMBOL(octeon_mdiobus_force_mod_depencency);

module_platform_driver(octeon_mdiobus_driver);

MODULE_DESCRIPTION(DRV_DESCRIPTION);
MODULE_VERSION(DRV_VERSION);
MODULE_AUTHOR("David Daney");
MODULE_LICENSE("GPL");
Commit	Line	Data
25d967b7 DD	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
775ae9b2	6	* Copyright (C) 2009-2012 Cavium, Inc.
25d967b7 DD	7	*/
25d967b7 DD	8
25d967b7	9	#include <linux/platform_device.h>
a6d67864	10	#include <linux/of_address.h>
2fd46f47 DD	11	#include <linux/of_mdio.h>
	12	#include <linux/delay.h>
	13	#include <linux/module.h>
2fd46f47	14	#include <linux/gfp.h>
25d967b7	15	#include <linux/phy.h>
2fd46f47	16	#include <linux/io.h>
25d967b7	17
a6d67864	18	#ifdef CONFIG_CAVIUM_OCTEON_SOC
25d967b7	19	#include <asm/octeon/octeon.h>
a6d67864	20	#endif
25d967b7	21
a6d67864 RMC	22	#define DRV_VERSION "1.1"
a6d67864 RMC	23	#define DRV_DESCRIPTION "Cavium Networks Octeon/ThunderX SMI/MDIO driver"
25d967b7	24
2fd46f47 DD	25	#define SMI_CMD 0x0
	26	#define SMI_WR_DAT 0x8
	27	#define SMI_RD_DAT 0x10
	28	#define SMI_CLK 0x18
	29	#define SMI_EN 0x20
	30
a6d67864 RMC	31	#ifdef __BIG_ENDIAN_BITFIELD
	32	#define OCT_MDIO_BITFIELD_FIELD(field, more) \
	33	field; \
	34	more
	35
	36	#else
	37	#define OCT_MDIO_BITFIELD_FIELD(field, more) \
	38	more \
	39	field;
	40
	41	#endif
	42
	43	union cvmx_smix_clk {
	44	u64 u64;
	45	struct cvmx_smix_clk_s {
	46	OCT_MDIO_BITFIELD_FIELD(u64 reserved_25_63:39,
	47	OCT_MDIO_BITFIELD_FIELD(u64 mode:1,
	48	OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
	49	OCT_MDIO_BITFIELD_FIELD(u64 sample_hi:5,
	50	OCT_MDIO_BITFIELD_FIELD(u64 sample_mode:1,
	51	OCT_MDIO_BITFIELD_FIELD(u64 reserved_14_14:1,
	52	OCT_MDIO_BITFIELD_FIELD(u64 clk_idle:1,
	53	OCT_MDIO_BITFIELD_FIELD(u64 preamble:1,
	54	OCT_MDIO_BITFIELD_FIELD(u64 sample:4,
	55	OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
	56	;))))))))))
	57	} s;
	58	};
	59
	60	union cvmx_smix_cmd {
	61	u64 u64;
	62	struct cvmx_smix_cmd_s {
	63	OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
	64	OCT_MDIO_BITFIELD_FIELD(u64 phy_op:2,
	65	OCT_MDIO_BITFIELD_FIELD(u64 reserved_13_15:3,
	66	OCT_MDIO_BITFIELD_FIELD(u64 phy_adr:5,
	67	OCT_MDIO_BITFIELD_FIELD(u64 reserved_5_7:3,
	68	OCT_MDIO_BITFIELD_FIELD(u64 reg_adr:5,
	69	;))))))
	70	} s;
	71	};
	72
	73	union cvmx_smix_en {
	74	u64 u64;
	75	struct cvmx_smix_en_s {
	76	OCT_MDIO_BITFIELD_FIELD(u64 reserved_1_63:63,
	77	OCT_MDIO_BITFIELD_FIELD(u64 en:1,
	78	;))
	79	} s;
	80	};
	81
	82	union cvmx_smix_rd_dat {
	83	u64 u64;
	84	struct cvmx_smix_rd_dat_s {
	85	OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
	86	OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
	87	OCT_MDIO_BITFIELD_FIELD(u64 val:1,
	88	OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
	89	;))))
	90	} s;
	91	};
	92
	93	union cvmx_smix_wr_dat {
	94	u64 u64;
95	struct cvmx_smix_wr_dat_s {
96	OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
97	OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
98	OCT_MDIO_BITFIELD_FIELD(u64 val:1,
99	OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
100	;))))
101	} s;
102	};
103
775ae9b2 DD	104	enum octeon_mdiobus_mode {
	105	UNINIT = 0,
	106	C22,
	107	C45
	108	};
	109
25d967b7 DD	110	struct octeon_mdiobus {
25d967b7 DD	111	struct mii_bus *mii_bus;
2fd46f47 DD	112	u64 register_base;
	113	resource_size_t mdio_phys;
	114	resource_size_t regsize;
775ae9b2	115	enum octeon_mdiobus_mode mode;
25d967b7 DD	116	};
25d967b7 DD	117
a6d67864 RMC	118	#ifdef CONFIG_CAVIUM_OCTEON_SOC
	119	static void oct_mdio_writeq(u64 val, u64 addr)
	120	{
	121	cvmx_write_csr(addr, val);
	122	}
	123
	124	static u64 oct_mdio_readq(u64 addr)
	125	{
	126	return cvmx_read_csr(addr);
	127	}
	128	#else
	129	#define oct_mdio_writeq(val, addr) writeq_relaxed(val, (void *)addr)
	130	#define oct_mdio_readq(addr) readq_relaxed((void *)addr)
	131	#endif
	132
775ae9b2 DD	133	static void octeon_mdiobus_set_mode(struct octeon_mdiobus *p,
	134	enum octeon_mdiobus_mode m)
	135	{
	136	union cvmx_smix_clk smi_clk;
	137
	138	if (m == p->mode)
	139	return;
	140
a6d67864	141	smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK);
775ae9b2 DD	142	smi_clk.s.mode = (m == C45) ? 1 : 0;
775ae9b2 DD	143	smi_clk.s.preamble = 1;
a6d67864	144	oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK);
775ae9b2 DD	145	p->mode = m;
	146	}
	147
	148	static int octeon_mdiobus_c45_addr(struct octeon_mdiobus *p,
	149	int phy_id, int regnum)
	150	{
	151	union cvmx_smix_cmd smi_cmd;
	152	union cvmx_smix_wr_dat smi_wr;
	153	int timeout = 1000;
	154
	155	octeon_mdiobus_set_mode(p, C45);
	156
	157	smi_wr.u64 = 0;
	158	smi_wr.s.dat = regnum & 0xffff;
a6d67864	159	oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
775ae9b2 DD	160
	161	regnum = (regnum >> 16) & 0x1f;
	162
	163	smi_cmd.u64 = 0;
	164	smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_45_ADDRESS */
	165	smi_cmd.s.phy_adr = phy_id;
	166	smi_cmd.s.reg_adr = regnum;
a6d67864	167	oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
775ae9b2 DD	168
	169	do {
	170	/* Wait 1000 clocks so we don't saturate the RSL bus
	171	* doing reads.
	172	*/
	173	__delay(1000);
a6d67864	174	smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
775ae9b2 DD	175	} while (smi_wr.s.pending && --timeout);
	176
	177	if (timeout <= 0)
	178	return -EIO;
	179	return 0;
	180	}
	181
25d967b7 DD	182	static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
	183	{
	184	struct octeon_mdiobus *p = bus->priv;
	185	union cvmx_smix_cmd smi_cmd;
	186	union cvmx_smix_rd_dat smi_rd;
775ae9b2	187	unsigned int op = 1; /* MDIO_CLAUSE_22_READ */
25d967b7 DD	188	int timeout = 1000;
25d967b7 DD	189
775ae9b2 DD	190	if (regnum & MII_ADDR_C45) {
	191	int r = octeon_mdiobus_c45_addr(p, phy_id, regnum);
	192	if (r < 0)
	193	return r;
	194
	195	regnum = (regnum >> 16) & 0x1f;
	196	op = 3; /* MDIO_CLAUSE_45_READ */
	197	} else {
	198	octeon_mdiobus_set_mode(p, C22);
	199	}
	200
	201
25d967b7	202	smi_cmd.u64 = 0;
775ae9b2	203	smi_cmd.s.phy_op = op;
25d967b7 DD	204	smi_cmd.s.phy_adr = phy_id;
25d967b7 DD	205	smi_cmd.s.reg_adr = regnum;
a6d67864	206	oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
25d967b7 DD	207
25d967b7 DD	208	do {
775ae9b2	209	/* Wait 1000 clocks so we don't saturate the RSL bus
25d967b7 DD	210	* doing reads.
25d967b7 DD	211	*/
2fd46f47	212	__delay(1000);
a6d67864	213	smi_rd.u64 = oct_mdio_readq(p->register_base + SMI_RD_DAT);
25d967b7 DD	214	} while (smi_rd.s.pending && --timeout);
	215
	216	if (smi_rd.s.val)
	217	return smi_rd.s.dat;
	218	else
	219	return -EIO;
	220	}
	221
	222	static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id,
	223	int regnum, u16 val)
	224	{
	225	struct octeon_mdiobus *p = bus->priv;
	226	union cvmx_smix_cmd smi_cmd;
	227	union cvmx_smix_wr_dat smi_wr;
775ae9b2	228	unsigned int op = 0; /* MDIO_CLAUSE_22_WRITE */
25d967b7 DD	229	int timeout = 1000;
25d967b7 DD	230
775ae9b2 DD	231
	232	if (regnum & MII_ADDR_C45) {
	233	int r = octeon_mdiobus_c45_addr(p, phy_id, regnum);
	234	if (r < 0)
	235	return r;
	236
	237	regnum = (regnum >> 16) & 0x1f;
	238	op = 1; /* MDIO_CLAUSE_45_WRITE */
	239	} else {
	240	octeon_mdiobus_set_mode(p, C22);
	241	}
	242
25d967b7 DD	243	smi_wr.u64 = 0;
25d967b7 DD	244	smi_wr.s.dat = val;
a6d67864	245	oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
25d967b7 DD	246
25d967b7 DD	247	smi_cmd.u64 = 0;
775ae9b2	248	smi_cmd.s.phy_op = op;
25d967b7 DD	249	smi_cmd.s.phy_adr = phy_id;
25d967b7 DD	250	smi_cmd.s.reg_adr = regnum;
a6d67864	251	oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
25d967b7 DD	252
25d967b7 DD	253	do {
775ae9b2	254	/* Wait 1000 clocks so we don't saturate the RSL bus
25d967b7 DD	255	* doing reads.
25d967b7 DD	256	*/
2fd46f47	257	__delay(1000);
a6d67864	258	smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
25d967b7 DD	259	} while (smi_wr.s.pending && --timeout);
	260
	261	if (timeout <= 0)
	262	return -EIO;
	263
	264	return 0;
	265	}
	266
633d1594	267	static int octeon_mdiobus_probe(struct platform_device *pdev)
25d967b7 DD	268	{
25d967b7 DD	269	struct octeon_mdiobus *bus;
35d2aeac	270	struct mii_bus *mii_bus;
2fd46f47	271	struct resource *res_mem;
6c17812d	272	union cvmx_smix_en smi_en;
25d967b7 DD	273	int err = -ENOENT;
25d967b7 DD	274
35d2aeac AL	275	mii_bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*bus));
35d2aeac AL	276	if (!mii_bus)
25d967b7 DD	277	return -ENOMEM;
25d967b7 DD	278
2fd46f47	279	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2fd46f47 DD	280	if (res_mem == NULL) {
2fd46f47 DD	281	dev_err(&pdev->dev, "found no memory resource\n");
de9e397e	282	return -ENXIO;
2fd46f47	283	}
de9e397e	284
35d2aeac AL	285	bus = mii_bus->priv;
35d2aeac AL	286	bus->mii_bus = mii_bus;
2fd46f47 DD	287	bus->mdio_phys = res_mem->start;
2fd46f47 DD	288	bus->regsize = resource_size(res_mem);
de9e397e	289
2fd46f47 DD	290	if (!devm_request_mem_region(&pdev->dev, bus->mdio_phys, bus->regsize,
	291	res_mem->name)) {
	292	dev_err(&pdev->dev, "request_mem_region failed\n");
de9e397e	293	return -ENXIO;
2fd46f47	294	}
de9e397e	295
2fd46f47 DD	296	bus->register_base =
2fd46f47 DD	297	(u64)devm_ioremap(&pdev->dev, bus->mdio_phys, bus->regsize);
de9e397e RMC	298	if (!bus->register_base) {
	299	dev_err(&pdev->dev, "dev_ioremap failed\n");
	300	return -ENOMEM;
	301	}
25d967b7	302
6c17812d DD	303	smi_en.u64 = 0;
6c17812d DD	304	smi_en.s.en = 1;
a6d67864	305	oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
25d967b7 DD	306
25d967b7 DD	307	bus->mii_bus->priv = bus;
25d967b7	308	bus->mii_bus->name = "mdio-octeon";
2fd46f47	309	snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%llx", bus->register_base);
25d967b7 DD	310	bus->mii_bus->parent = &pdev->dev;
	311
	312	bus->mii_bus->read = octeon_mdiobus_read;
	313	bus->mii_bus->write = octeon_mdiobus_write;
	314
f8825669	315	platform_set_drvdata(pdev, bus);
25d967b7	316
2fd46f47	317	err = of_mdiobus_register(bus->mii_bus, pdev->dev.of_node);
25d967b7	318	if (err)
2fd46f47	319	goto fail_register;
25d967b7 DD	320
	321	dev_info(&pdev->dev, "Version " DRV_VERSION "\n");
	322
	323	return 0;
2fd46f47	324	fail_register:
25d967b7	325	mdiobus_free(bus->mii_bus);
6c17812d	326	smi_en.u64 = 0;
a6d67864	327	oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
25d967b7 DD	328	return err;
	329	}
	330
633d1594	331	static int octeon_mdiobus_remove(struct platform_device *pdev)
25d967b7 DD	332	{
25d967b7 DD	333	struct octeon_mdiobus *bus;
6c17812d	334	union cvmx_smix_en smi_en;
25d967b7	335
2c0c4fbe	336	bus = platform_get_drvdata(pdev);
25d967b7 DD	337
	338	mdiobus_unregister(bus->mii_bus);
	339	mdiobus_free(bus->mii_bus);
6c17812d	340	smi_en.u64 = 0;
a6d67864	341	oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
25d967b7 DD	342	return 0;
	343	}
	344
d8a7dadb	345	static const struct of_device_id octeon_mdiobus_match[] = {
2fd46f47 DD	346	{
	347	.compatible = "cavium,octeon-3860-mdio",
	348	},
	349	{},
	350	};
	351	MODULE_DEVICE_TABLE(of, octeon_mdiobus_match);
	352
25d967b7 DD	353	static struct platform_driver octeon_mdiobus_driver = {
	354	.driver = {
	355	.name = "mdio-octeon",
2fd46f47	356	.of_match_table = octeon_mdiobus_match,
25d967b7 DD	357	},
25d967b7 DD	358	.probe = octeon_mdiobus_probe,
633d1594	359	.remove = octeon_mdiobus_remove,
25d967b7 DD	360	};
	361
	362	void octeon_mdiobus_force_mod_depencency(void)
	363	{
	364	/* Let ethernet drivers force us to be loaded. */
	365	}
	366	EXPORT_SYMBOL(octeon_mdiobus_force_mod_depencency);
	367
9fad0c94	368	module_platform_driver(octeon_mdiobus_driver);
25d967b7 DD	369
	370	MODULE_DESCRIPTION(DRV_DESCRIPTION);
	371	MODULE_VERSION(DRV_VERSION);
	372	MODULE_AUTHOR("David Daney");
	373	MODULE_LICENSE("GPL");