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Merge remote-tracking branch 'mac80211-next/master'
[deliverable/linux.git] / drivers / net / phy / micrel.c
CommitLineData
d0507009
DC		 1/*
2 * drivers/net/phy/micrel.c
3 *
4 * Driver for Micrel PHYs
5 *
6 * Author: David J. Choi
7 *
7ab59dc1 8 * Copyright (c) 2010-2013 Micrel, Inc.
ee0dc2fb 9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
d0507009
DC		 10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
7ab59dc1
DC		 16 * Support : Micrel Phys:
17 * Giga phys: ksz9021, ksz9031
18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
19 * ksz8021, ksz8031, ksz8051,
20 * ksz8081, ksz8091,
21 * ksz8061,
22 * Switch : ksz8873, ksz886x
d0507009
DC		 23 */
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/phy.h>
d606ef3f 28#include <linux/micrel_phy.h>
954c3967 29#include <linux/of.h>
1fadee0c 30#include <linux/clk.h>
d0507009 31
212ea99a
MV		 32/* Operation Mode Strap Override */
33#define MII_KSZPHY_OMSO 0x16
00aee095 34#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
2b0ba96c 35#define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
00aee095
JH		 36#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
37#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
212ea99a 38
51f932c4
CD		 39/* general Interrupt control/status reg in vendor specific block. */
40#define MII_KSZPHY_INTCS 0x1B
00aee095
JH		 41#define KSZPHY_INTCS_JABBER BIT(15)
42#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
43#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
44#define KSZPHY_INTCS_PARELLEL BIT(12)
45#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
46#define KSZPHY_INTCS_LINK_DOWN BIT(10)
47#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
48#define KSZPHY_INTCS_LINK_UP BIT(8)
51f932c4
CD		 49#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
50 KSZPHY_INTCS_LINK_DOWN)
51
5a16778e
JH		 52/* PHY Control 1 */
53#define MII_KSZPHY_CTRL_1 0x1e
54
55/* PHY Control 2 / PHY Control (if no PHY Control 1) */
56#define MII_KSZPHY_CTRL_2 0x1f
57#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
51f932c4 58/* bitmap of PHY register to set interrupt mode */
00aee095 59#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
63f44b2b 60#define KSZPHY_RMII_REF_CLK_SEL BIT(7)
51f932c4 61
954c3967
SC		 62/* Write/read to/from extended registers */
63#define MII_KSZPHY_EXTREG 0x0b
64#define KSZPHY_EXTREG_WRITE 0x8000
65
66#define MII_KSZPHY_EXTREG_WRITE 0x0c
67#define MII_KSZPHY_EXTREG_READ 0x0d
68
69/* Extended registers */
70#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
71#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
72#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
73
74#define PS_TO_REG 200
75
2b2427d0
AL		 76struct kszphy_hw_stat {
77 const char *string;
78 u8 reg;
79 u8 bits;
80};
81
82static struct kszphy_hw_stat kszphy_hw_stats[] = {
83 { "phy_receive_errors", 21, 16},
84 { "phy_idle_errors", 10, 8 },
85};
86
e6a423a8
JH		 87struct kszphy_type {
88 u32 led_mode_reg;
c6f9575c 89 u16 interrupt_level_mask;
0f95903e 90 bool has_broadcast_disable;
2b0ba96c 91 bool has_nand_tree_disable;
63f44b2b 92 bool has_rmii_ref_clk_sel;
e6a423a8
JH		 93};
94
95struct kszphy_priv {
96 const struct kszphy_type *type;
e7a792e9 97 int led_mode;
63f44b2b
JH		 98 bool rmii_ref_clk_sel;
99 bool rmii_ref_clk_sel_val;
2b2427d0 100 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
e6a423a8
JH		 101};
102
103static const struct kszphy_type ksz8021_type = {
104 .led_mode_reg = MII_KSZPHY_CTRL_2,
d0e1df9c 105 .has_broadcast_disable = true,
2b0ba96c 106 .has_nand_tree_disable = true,
63f44b2b 107 .has_rmii_ref_clk_sel = true,
e6a423a8
JH		 108};
109
110static const struct kszphy_type ksz8041_type = {
111 .led_mode_reg = MII_KSZPHY_CTRL_1,
112};
113
114static const struct kszphy_type ksz8051_type = {
115 .led_mode_reg = MII_KSZPHY_CTRL_2,
2b0ba96c 116 .has_nand_tree_disable = true,
e6a423a8
JH		 117};
118
119static const struct kszphy_type ksz8081_type = {
120 .led_mode_reg = MII_KSZPHY_CTRL_2,
0f95903e 121 .has_broadcast_disable = true,
2b0ba96c 122 .has_nand_tree_disable = true,
86dc1342 123 .has_rmii_ref_clk_sel = true,
e6a423a8
JH		 124};
125
c6f9575c
JH		 126static const struct kszphy_type ks8737_type = {
127 .interrupt_level_mask = BIT(14),
128};
129
130static const struct kszphy_type ksz9021_type = {
131 .interrupt_level_mask = BIT(14),
132};
133
954c3967 134static int kszphy_extended_write(struct phy_device *phydev,
756b5089 135 u32 regnum, u16 val)
954c3967
SC		 136{
137 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
138 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
139}
140
141static int kszphy_extended_read(struct phy_device *phydev,
756b5089 142 u32 regnum)
954c3967
SC		 143{
144 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
145 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
146}
147
51f932c4
CD		 148static int kszphy_ack_interrupt(struct phy_device *phydev)
149{
150 /* bit[7..0] int status, which is a read and clear register. */
151 int rc;
152
153 rc = phy_read(phydev, MII_KSZPHY_INTCS);
154
155 return (rc < 0) ? rc : 0;
156}
157
51f932c4
CD		 158static int kszphy_config_intr(struct phy_device *phydev)
159{
c6f9575c
JH		 160 const struct kszphy_type *type = phydev->drv->driver_data;
161 int temp;
162 u16 mask;
51f932c4 163
c6f9575c
JH		 164 if (type && type->interrupt_level_mask)
165 mask = type->interrupt_level_mask;
166 else
167 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
51f932c4
CD		 168
169 /* set the interrupt pin active low */
170 temp = phy_read(phydev, MII_KSZPHY_CTRL);
5bb8fc0d
JH		 171 if (temp < 0)
172 return temp;
c6f9575c 173 temp &= ~mask;
51f932c4 174 phy_write(phydev, MII_KSZPHY_CTRL, temp);
51f932c4 175
c6f9575c
JH		 176 /* enable / disable interrupts */
177 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
178 temp = KSZPHY_INTCS_ALL;
179 else
180 temp = 0;
51f932c4 181
c6f9575c 182 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
51f932c4 183}
d0507009 184
63f44b2b
JH		 185static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
186{
187 int ctrl;
188
189 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
190 if (ctrl < 0)
191 return ctrl;
192
193 if (val)
194 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
195 else
196 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
197
198 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
199}
200
e7a792e9 201static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
20d8435a 202{
5a16778e 203 int rc, temp, shift;
8620546c 204
5a16778e
JH		 205 switch (reg) {
206 case MII_KSZPHY_CTRL_1:
207 shift = 14;
208 break;
209 case MII_KSZPHY_CTRL_2:
210 shift = 4;
211 break;
212 default:
213 return -EINVAL;
214 }
215
20d8435a 216 temp = phy_read(phydev, reg);
b7035860
JH		 217 if (temp < 0) {
218 rc = temp;
219 goto out;
220 }
20d8435a 221
28bdc499 222 temp &= ~(3 << shift);
20d8435a
BD		 223 temp |= val << shift;
224 rc = phy_write(phydev, reg, temp);
b7035860
JH		 225out:
226 if (rc < 0)
72ba48be 227 phydev_err(phydev, "failed to set led mode\n");
20d8435a 228
b7035860 229 return rc;
20d8435a
BD		 230}
231
bde15129
JH		 232/* Disable PHY address 0 as the broadcast address, so that it can be used as a
233 * unique (non-broadcast) address on a shared bus.
234 */
235static int kszphy_broadcast_disable(struct phy_device *phydev)
236{
237 int ret;
238
239 ret = phy_read(phydev, MII_KSZPHY_OMSO);
240 if (ret < 0)
241 goto out;
242
243 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
244out:
245 if (ret)
72ba48be 246 phydev_err(phydev, "failed to disable broadcast address\n");
bde15129
JH		 247
248 return ret;
249}
250
2b0ba96c
SR		 251static int kszphy_nand_tree_disable(struct phy_device *phydev)
252{
253 int ret;
254
255 ret = phy_read(phydev, MII_KSZPHY_OMSO);
256 if (ret < 0)
257 goto out;
258
259 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
260 return 0;
261
262 ret = phy_write(phydev, MII_KSZPHY_OMSO,
263 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
264out:
265 if (ret)
72ba48be 266 phydev_err(phydev, "failed to disable NAND tree mode\n");
2b0ba96c
SR		 267
268 return ret;
269}
270
d0507009
DC		 271static int kszphy_config_init(struct phy_device *phydev)
272{
e6a423a8
JH		 273 struct kszphy_priv *priv = phydev->priv;
274 const struct kszphy_type *type;
63f44b2b 275 int ret;
d0507009 276
e6a423a8
JH		 277 if (!priv)
278 return 0;
279
280 type = priv->type;
281
0f95903e
JH		 282 if (type->has_broadcast_disable)
283 kszphy_broadcast_disable(phydev);
284
2b0ba96c
SR		 285 if (type->has_nand_tree_disable)
286 kszphy_nand_tree_disable(phydev);
287
63f44b2b
JH		 288 if (priv->rmii_ref_clk_sel) {
289 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
290 if (ret) {
72ba48be
AL		 291 phydev_err(phydev,
292 "failed to set rmii reference clock\n");
63f44b2b
JH		 293 return ret;
294 }
295 }
296
e7a792e9
JH		 297 if (priv->led_mode >= 0)
298 kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode);
e6a423a8 299
99f81afc
AB		 300 if (phy_interrupt_is_valid(phydev)) {
301 int ctl = phy_read(phydev, MII_BMCR);
302
303 if (ctl < 0)
304 return ctl;
305
306 ret = phy_write(phydev, MII_BMCR, ctl & ~BMCR_ANENABLE);
307 if (ret < 0)
308 return ret;
309 }
310
e6a423a8 311 return 0;
20d8435a
BD		 312}
313
77501a79
PZ		 314static int ksz8041_config_init(struct phy_device *phydev)
315{
316 struct device_node *of_node = phydev->mdio.dev.of_node;
317
318 /* Limit supported and advertised modes in fiber mode */
319 if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
320 phydev->dev_flags |= MICREL_PHY_FXEN;
321 phydev->supported &= SUPPORTED_FIBRE |
322 SUPPORTED_100baseT_Full |
323 SUPPORTED_100baseT_Half;
324 phydev->advertising &= ADVERTISED_FIBRE |
325 ADVERTISED_100baseT_Full |
326 ADVERTISED_100baseT_Half;
327 phydev->autoneg = AUTONEG_DISABLE;
328 }
329
330 return kszphy_config_init(phydev);
331}
332
333static int ksz8041_config_aneg(struct phy_device *phydev)
334{
335 /* Skip auto-negotiation in fiber mode */
336 if (phydev->dev_flags & MICREL_PHY_FXEN) {
337 phydev->speed = SPEED_100;
338 return 0;
339 }
340
341 return genphy_config_aneg(phydev);
342}
343
954c3967 344static int ksz9021_load_values_from_of(struct phy_device *phydev,
3c9a9f7f
JA		 345 const struct device_node *of_node,
346 u16 reg,
347 const char *field1, const char *field2,
348 const char *field3, const char *field4)
954c3967
SC		 349{
350 int val1 = -1;
351 int val2 = -2;
352 int val3 = -3;
353 int val4 = -4;
354 int newval;
355 int matches = 0;
356
357 if (!of_property_read_u32(of_node, field1, &val1))
358 matches++;
359
360 if (!of_property_read_u32(of_node, field2, &val2))
361 matches++;
362
363 if (!of_property_read_u32(of_node, field3, &val3))
364 matches++;
365
366 if (!of_property_read_u32(of_node, field4, &val4))
367 matches++;
368
369 if (!matches)
370 return 0;
371
372 if (matches < 4)
373 newval = kszphy_extended_read(phydev, reg);
374 else
375 newval = 0;
376
377 if (val1 != -1)
378 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
379
6a119745 380 if (val2 != -2)
954c3967
SC		 381 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
382
6a119745 383 if (val3 != -3)
954c3967
SC		 384 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
385
6a119745 386 if (val4 != -4)
954c3967
SC		 387 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
388
389 return kszphy_extended_write(phydev, reg, newval);
390}
391
392static int ksz9021_config_init(struct phy_device *phydev)
393{
e5a03bfd 394 const struct device *dev = &phydev->mdio.dev;
3c9a9f7f 395 const struct device_node *of_node = dev->of_node;
651df218
AL		 396 const struct device *dev_walker;
397
398 /* The Micrel driver has a deprecated option to place phy OF
399 * properties in the MAC node. Walk up the tree of devices to
400 * find a device with an OF node.
401 */
e5a03bfd 402 dev_walker = &phydev->mdio.dev;
651df218
AL		 403 do {
404 of_node = dev_walker->of_node;
405 dev_walker = dev_walker->parent;
406
407 } while (!of_node && dev_walker);
954c3967
SC		 408
409 if (of_node) {
410 ksz9021_load_values_from_of(phydev, of_node,
411 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
412 "txen-skew-ps", "txc-skew-ps",
413 "rxdv-skew-ps", "rxc-skew-ps");
414 ksz9021_load_values_from_of(phydev, of_node,
415 MII_KSZPHY_RX_DATA_PAD_SKEW,
416 "rxd0-skew-ps", "rxd1-skew-ps",
417 "rxd2-skew-ps", "rxd3-skew-ps");
418 ksz9021_load_values_from_of(phydev, of_node,
419 MII_KSZPHY_TX_DATA_PAD_SKEW,
420 "txd0-skew-ps", "txd1-skew-ps",
421 "txd2-skew-ps", "txd3-skew-ps");
422 }
423 return 0;
424}
425
6e4b8273
HC		 426#define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
427#define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
428#define OP_DATA 1
429#define KSZ9031_PS_TO_REG 60
430
431/* Extended registers */
6270e1ae
JA		 432/* MMD Address 0x0 */
433#define MII_KSZ9031RN_FLP_BURST_TX_LO 3
434#define MII_KSZ9031RN_FLP_BURST_TX_HI 4
435
ae6c97bb 436/* MMD Address 0x2 */
6e4b8273
HC		 437#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
438#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
439#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
440#define MII_KSZ9031RN_CLK_PAD_SKEW 8
441
442static int ksz9031_extended_write(struct phy_device *phydev,
443 u8 mode, u32 dev_addr, u32 regnum, u16 val)
444{
445 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
446 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
447 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
448 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
449}
450
451static int ksz9031_extended_read(struct phy_device *phydev,
452 u8 mode, u32 dev_addr, u32 regnum)
453{
454 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
455 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
456 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
457 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
458}
459
460static int ksz9031_of_load_skew_values(struct phy_device *phydev,
3c9a9f7f 461 const struct device_node *of_node,
6e4b8273 462 u16 reg, size_t field_sz,
3c9a9f7f 463 const char *field[], u8 numfields)
6e4b8273
HC		 464{
465 int val[4] = {-1, -2, -3, -4};
466 int matches = 0;
467 u16 mask;
468 u16 maxval;
469 u16 newval;
470 int i;
471
472 for (i = 0; i < numfields; i++)
473 if (!of_property_read_u32(of_node, field[i], val + i))
474 matches++;
475
476 if (!matches)
477 return 0;
478
479 if (matches < numfields)
480 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
481 else
482 newval = 0;
483
484 maxval = (field_sz == 4) ? 0xf : 0x1f;
485 for (i = 0; i < numfields; i++)
486 if (val[i] != -(i + 1)) {
487 mask = 0xffff;
488 mask ^= maxval << (field_sz * i);
489 newval = (newval & mask) |
490 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
491 << (field_sz * i));
492 }
493
494 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
495}
496
6270e1ae
JA		 497static int ksz9031_center_flp_timing(struct phy_device *phydev)
498{
499 int result;
500
501 /* Center KSZ9031RNX FLP timing at 16ms. */
502 result = ksz9031_extended_write(phydev, OP_DATA, 0,
503 MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
504 result = ksz9031_extended_write(phydev, OP_DATA, 0,
505 MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
506
507 if (result)
508 return result;
509
510 return genphy_restart_aneg(phydev);
511}
512
6e4b8273
HC		 513static int ksz9031_config_init(struct phy_device *phydev)
514{
e5a03bfd 515 const struct device *dev = &phydev->mdio.dev;
3c9a9f7f
JA		 516 const struct device_node *of_node = dev->of_node;
517 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
518 static const char *rx_data_skews[4] = {
6e4b8273
HC		 519 "rxd0-skew-ps", "rxd1-skew-ps",
520 "rxd2-skew-ps", "rxd3-skew-ps"
521 };
3c9a9f7f 522 static const char *tx_data_skews[4] = {
6e4b8273
HC		 523 "txd0-skew-ps", "txd1-skew-ps",
524 "txd2-skew-ps", "txd3-skew-ps"
525 };
3c9a9f7f 526 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
b4c19f71 527 const struct device *dev_walker;
6e4b8273 528
b4c19f71
RH		 529 /* The Micrel driver has a deprecated option to place phy OF
530 * properties in the MAC node. Walk up the tree of devices to
531 * find a device with an OF node.
532 */
9d367edd 533 dev_walker = &phydev->mdio.dev;
b4c19f71
RH		 534 do {
535 of_node = dev_walker->of_node;
536 dev_walker = dev_walker->parent;
537 } while (!of_node && dev_walker);
6e4b8273
HC		 538
539 if (of_node) {
540 ksz9031_of_load_skew_values(phydev, of_node,
541 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
542 clk_skews, 2);
543
544 ksz9031_of_load_skew_values(phydev, of_node,
545 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
546 control_skews, 2);
547
548 ksz9031_of_load_skew_values(phydev, of_node,
549 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
550 rx_data_skews, 4);
551
552 ksz9031_of_load_skew_values(phydev, of_node,
553 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
554 tx_data_skews, 4);
555 }
6270e1ae
JA		 556
557 return ksz9031_center_flp_timing(phydev);
6e4b8273
HC		 558}
559
93272e07 560#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
00aee095
JH		 561#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
562#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
32d73b14 563static int ksz8873mll_read_status(struct phy_device *phydev)
93272e07
JCPV		 564{
565 int regval;
566
567 /* dummy read */
568 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
569
570 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
571
572 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
573 phydev->duplex = DUPLEX_HALF;
574 else
575 phydev->duplex = DUPLEX_FULL;
576
577 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
578 phydev->speed = SPEED_10;
579 else
580 phydev->speed = SPEED_100;
581
582 phydev->link = 1;
583 phydev->pause = phydev->asym_pause = 0;
584
585 return 0;
586}
587
d2fd719b
NS		 588static int ksz9031_read_status(struct phy_device *phydev)
589{
590 int err;
591 int regval;
592
593 err = genphy_read_status(phydev);
594 if (err)
595 return err;
596
597 /* Make sure the PHY is not broken. Read idle error count,
598 * and reset the PHY if it is maxed out.
599 */
600 regval = phy_read(phydev, MII_STAT1000);
601 if ((regval & 0xFF) == 0xFF) {
602 phy_init_hw(phydev);
603 phydev->link = 0;
604 }
605
606 return 0;
607}
608
93272e07
JCPV		 609static int ksz8873mll_config_aneg(struct phy_device *phydev)
610{
611 return 0;
612}
613
19936942
VB		 614/* This routine returns -1 as an indication to the caller that the
615 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
616 * MMD extended PHY registers.
617 */
618static int
619ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
620 int regnum)
621{
622 return -1;
623}
624
625/* This routine does nothing since the Micrel ksz9021 does not support
626 * standard IEEE MMD extended PHY registers.
627 */
628static void
629ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
630 int regnum, u32 val)
631{
632}
633
2b2427d0
AL		 634static int kszphy_get_sset_count(struct phy_device *phydev)
635{
636 return ARRAY_SIZE(kszphy_hw_stats);
637}
638
639static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
640{
641 int i;
642
643 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
644 memcpy(data + i * ETH_GSTRING_LEN,
645 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
646 }
647}
648
649#ifndef UINT64_MAX
650#define UINT64_MAX (u64)(~((u64)0))
651#endif
652static u64 kszphy_get_stat(struct phy_device *phydev, int i)
653{
654 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
655 struct kszphy_priv *priv = phydev->priv;
321b4d4b
AL		 656 int val;
657 u64 ret;
2b2427d0
AL		 658
659 val = phy_read(phydev, stat.reg);
660 if (val < 0) {
321b4d4b 661 ret = UINT64_MAX;
2b2427d0
AL		 662 } else {
663 val = val & ((1 << stat.bits) - 1);
664 priv->stats[i] += val;
321b4d4b 665 ret = priv->stats[i];
2b2427d0
AL		 666 }
667
321b4d4b 668 return ret;
2b2427d0
AL		 669}
670
671static void kszphy_get_stats(struct phy_device *phydev,
672 struct ethtool_stats *stats, u64 *data)
673{
674 int i;
675
676 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
677 data[i] = kszphy_get_stat(phydev, i);
678}
679
836384d2 680static int kszphy_suspend(struct phy_device *phydev)
f5aba91d 681{
836384d2
WY		 682 /* Disable PHY Interrupts */
683 if (phy_interrupt_is_valid(phydev)) {
684 phydev->interrupts = PHY_INTERRUPT_DISABLED;
685 if (phydev->drv->config_intr)
686 phydev->drv->config_intr(phydev);
687 }
f5aba91d 688
836384d2
WY		 689 return genphy_suspend(phydev);
690}
f5aba91d 691
836384d2
WY		 692static int kszphy_resume(struct phy_device *phydev)
693{
694 genphy_resume(phydev);
f5aba91d 695
836384d2
WY		 696 /* Enable PHY Interrupts */
697 if (phy_interrupt_is_valid(phydev)) {
698 phydev->interrupts = PHY_INTERRUPT_ENABLED;
699 if (phydev->drv->config_intr)
700 phydev->drv->config_intr(phydev);
701 }
f5aba91d
AB		 702
703 return 0;
704}
705
e6a423a8
JH		 706static int kszphy_probe(struct phy_device *phydev)
707{
708 const struct kszphy_type *type = phydev->drv->driver_data;
e5a03bfd 709 const struct device_node *np = phydev->mdio.dev.of_node;
e6a423a8 710 struct kszphy_priv *priv;
63f44b2b 711 struct clk *clk;
e7a792e9 712 int ret;
e6a423a8 713
e5a03bfd 714 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
e6a423a8
JH		 715 if (!priv)
716 return -ENOMEM;
717
718 phydev->priv = priv;
719
720 priv->type = type;
721
e7a792e9
JH		 722 if (type->led_mode_reg) {
723 ret = of_property_read_u32(np, "micrel,led-mode",
724 &priv->led_mode);
725 if (ret)
726 priv->led_mode = -1;
727
728 if (priv->led_mode > 3) {
72ba48be
AL		 729 phydev_err(phydev, "invalid led mode: 0x%02x\n",
730 priv->led_mode);
e7a792e9
JH		 731 priv->led_mode = -1;
732 }
733 } else {
734 priv->led_mode = -1;
735 }
736
e5a03bfd 737 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
bced8701
NC		 738 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
739 if (!IS_ERR_OR_NULL(clk)) {
1fadee0c 740 unsigned long rate = clk_get_rate(clk);
86dc1342 741 bool rmii_ref_clk_sel_25_mhz;
1fadee0c 742
63f44b2b 743 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
86dc1342
JH		 744 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
745 "micrel,rmii-reference-clock-select-25-mhz");
63f44b2b 746
1fadee0c 747 if (rate > 24500000 && rate < 25500000) {
86dc1342 748 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
1fadee0c 749 } else if (rate > 49500000 && rate < 50500000) {
86dc1342 750 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
1fadee0c 751 } else {
72ba48be
AL		 752 phydev_err(phydev, "Clock rate out of range: %ld\n",
753 rate);
1fadee0c
SH		 754 return -EINVAL;
755 }
756 }
757
63f44b2b
JH		 758 /* Support legacy board-file configuration */
759 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
760 priv->rmii_ref_clk_sel = true;
761 priv->rmii_ref_clk_sel_val = true;
762 }
763
764 return 0;
1fadee0c
SH		 765}
766
d5bf9071
CH		 767static struct phy_driver ksphy_driver[] = {
768{
51f932c4 769 .phy_id = PHY_ID_KS8737,
f893a99e 770 .phy_id_mask = MICREL_PHY_ID_MASK,
51f932c4
CD		 771 .name = "Micrel KS8737",
772 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
773 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
c6f9575c 774 .driver_data = &ks8737_type,
51f932c4
CD		 775 .config_init = kszphy_config_init,
776 .config_aneg = genphy_config_aneg,
777 .read_status = genphy_read_status,
778 .ack_interrupt = kszphy_ack_interrupt,
c6f9575c 779 .config_intr = kszphy_config_intr,
2b2427d0
AL		 780 .get_sset_count = kszphy_get_sset_count,
781 .get_strings = kszphy_get_strings,
782 .get_stats = kszphy_get_stats,
1a5465f5
PV		 783 .suspend = genphy_suspend,
784 .resume = genphy_resume,
212ea99a
MV		 785}, {
786 .phy_id = PHY_ID_KSZ8021,
787 .phy_id_mask = 0x00ffffff,
7ab59dc1 788 .name = "Micrel KSZ8021 or KSZ8031",
212ea99a
MV		 789 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
790 SUPPORTED_Asym_Pause),
791 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
e6a423a8 792 .driver_data = &ksz8021_type,
63f44b2b 793 .probe = kszphy_probe,
d0e1df9c 794 .config_init = kszphy_config_init,
212ea99a
MV		 795 .config_aneg = genphy_config_aneg,
796 .read_status = genphy_read_status,
797 .ack_interrupt = kszphy_ack_interrupt,
798 .config_intr = kszphy_config_intr,
2b2427d0
AL		 799 .get_sset_count = kszphy_get_sset_count,
800 .get_strings = kszphy_get_strings,
801 .get_stats = kszphy_get_stats,
1a5465f5
PV		 802 .suspend = genphy_suspend,
803 .resume = genphy_resume,
b818d1a7
HP		 804}, {
805 .phy_id = PHY_ID_KSZ8031,
806 .phy_id_mask = 0x00ffffff,
807 .name = "Micrel KSZ8031",
808 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
809 SUPPORTED_Asym_Pause),
810 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
e6a423a8 811 .driver_data = &ksz8021_type,
63f44b2b 812 .probe = kszphy_probe,
d0e1df9c 813 .config_init = kszphy_config_init,
b818d1a7
HP		 814 .config_aneg = genphy_config_aneg,
815 .read_status = genphy_read_status,
816 .ack_interrupt = kszphy_ack_interrupt,
817 .config_intr = kszphy_config_intr,
2b2427d0
AL		 818 .get_sset_count = kszphy_get_sset_count,
819 .get_strings = kszphy_get_strings,
820 .get_stats = kszphy_get_stats,
1a5465f5
PV		 821 .suspend = genphy_suspend,
822 .resume = genphy_resume,
d5bf9071 823}, {
510d573f 824 .phy_id = PHY_ID_KSZ8041,
f893a99e 825 .phy_id_mask = MICREL_PHY_ID_MASK,
510d573f 826 .name = "Micrel KSZ8041",
51f932c4
CD		 827 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
828 | SUPPORTED_Asym_Pause),
829 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
e6a423a8
JH		 830 .driver_data = &ksz8041_type,
831 .probe = kszphy_probe,
77501a79
PZ		 832 .config_init = ksz8041_config_init,
833 .config_aneg = ksz8041_config_aneg,
51f932c4
CD		 834 .read_status = genphy_read_status,
835 .ack_interrupt = kszphy_ack_interrupt,
836 .config_intr = kszphy_config_intr,
2b2427d0
AL		 837 .get_sset_count = kszphy_get_sset_count,
838 .get_strings = kszphy_get_strings,
839 .get_stats = kszphy_get_stats,
1a5465f5
PV		 840 .suspend = genphy_suspend,
841 .resume = genphy_resume,
4bd7b512
SS		 842}, {
843 .phy_id = PHY_ID_KSZ8041RNLI,
f893a99e 844 .phy_id_mask = MICREL_PHY_ID_MASK,
4bd7b512
SS		 845 .name = "Micrel KSZ8041RNLI",
846 .features = PHY_BASIC_FEATURES |
847 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
848 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
e6a423a8
JH		 849 .driver_data = &ksz8041_type,
850 .probe = kszphy_probe,
851 .config_init = kszphy_config_init,
4bd7b512
SS		 852 .config_aneg = genphy_config_aneg,
853 .read_status = genphy_read_status,
854 .ack_interrupt = kszphy_ack_interrupt,
855 .config_intr = kszphy_config_intr,
2b2427d0
AL		 856 .get_sset_count = kszphy_get_sset_count,
857 .get_strings = kszphy_get_strings,
858 .get_stats = kszphy_get_stats,
4bd7b512
SS		 859 .suspend = genphy_suspend,
860 .resume = genphy_resume,
d5bf9071 861}, {
510d573f 862 .phy_id = PHY_ID_KSZ8051,
f893a99e 863 .phy_id_mask = MICREL_PHY_ID_MASK,
510d573f 864 .name = "Micrel KSZ8051",
51f932c4
CD		 865 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
866 | SUPPORTED_Asym_Pause),
867 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
e6a423a8
JH		 868 .driver_data = &ksz8051_type,
869 .probe = kszphy_probe,
63f44b2b 870 .config_init = kszphy_config_init,
d0507009
DC		 871 .config_aneg = genphy_config_aneg,
872 .read_status = genphy_read_status,
51f932c4
CD		 873 .ack_interrupt = kszphy_ack_interrupt,
874 .config_intr = kszphy_config_intr,
2b2427d0
AL		 875 .get_sset_count = kszphy_get_sset_count,
876 .get_strings = kszphy_get_strings,
877 .get_stats = kszphy_get_stats,
1a5465f5
PV		 878 .suspend = genphy_suspend,
879 .resume = genphy_resume,
d5bf9071 880}, {
510d573f
MV		 881 .phy_id = PHY_ID_KSZ8001,
882 .name = "Micrel KSZ8001 or KS8721",
ecd5a323 883 .phy_id_mask = 0x00fffffc,
51f932c4
CD		 884 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
885 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
e6a423a8
JH		 886 .driver_data = &ksz8041_type,
887 .probe = kszphy_probe,
888 .config_init = kszphy_config_init,
d0507009
DC		 889 .config_aneg = genphy_config_aneg,
890 .read_status = genphy_read_status,
51f932c4
CD		 891 .ack_interrupt = kszphy_ack_interrupt,
892 .config_intr = kszphy_config_intr,
2b2427d0
AL		 893 .get_sset_count = kszphy_get_sset_count,
894 .get_strings = kszphy_get_strings,
895 .get_stats = kszphy_get_stats,
1a5465f5
PV		 896 .suspend = genphy_suspend,
897 .resume = genphy_resume,
7ab59dc1
DC		 898}, {
899 .phy_id = PHY_ID_KSZ8081,
900 .name = "Micrel KSZ8081 or KSZ8091",
f893a99e 901 .phy_id_mask = MICREL_PHY_ID_MASK,
7ab59dc1
DC		 902 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
903 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
e6a423a8
JH		 904 .driver_data = &ksz8081_type,
905 .probe = kszphy_probe,
0f95903e 906 .config_init = kszphy_config_init,
7ab59dc1
DC		 907 .config_aneg = genphy_config_aneg,
908 .read_status = genphy_read_status,
909 .ack_interrupt = kszphy_ack_interrupt,
910 .config_intr = kszphy_config_intr,
2b2427d0
AL		 911 .get_sset_count = kszphy_get_sset_count,
912 .get_strings = kszphy_get_strings,
913 .get_stats = kszphy_get_stats,
836384d2 914 .suspend = kszphy_suspend,
f5aba91d 915 .resume = kszphy_resume,
7ab59dc1
DC		 916}, {
917 .phy_id = PHY_ID_KSZ8061,
918 .name = "Micrel KSZ8061",
f893a99e 919 .phy_id_mask = MICREL_PHY_ID_MASK,
7ab59dc1
DC		 920 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
921 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
922 .config_init = kszphy_config_init,
923 .config_aneg = genphy_config_aneg,
924 .read_status = genphy_read_status,
925 .ack_interrupt = kszphy_ack_interrupt,
926 .config_intr = kszphy_config_intr,
2b2427d0
AL		 927 .get_sset_count = kszphy_get_sset_count,
928 .get_strings = kszphy_get_strings,
929 .get_stats = kszphy_get_stats,
1a5465f5
PV		 930 .suspend = genphy_suspend,
931 .resume = genphy_resume,
d5bf9071 932}, {
d0507009 933 .phy_id = PHY_ID_KSZ9021,
48d7d0ad 934 .phy_id_mask = 0x000ffffe,
d0507009 935 .name = "Micrel KSZ9021 Gigabit PHY",
32fcafbc 936 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
51f932c4 937 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
c6f9575c 938 .driver_data = &ksz9021_type,
954c3967 939 .config_init = ksz9021_config_init,
d0507009
DC		 940 .config_aneg = genphy_config_aneg,
941 .read_status = genphy_read_status,
51f932c4 942 .ack_interrupt = kszphy_ack_interrupt,
c6f9575c 943 .config_intr = kszphy_config_intr,
2b2427d0
AL		 944 .get_sset_count = kszphy_get_sset_count,
945 .get_strings = kszphy_get_strings,
946 .get_stats = kszphy_get_stats,
1a5465f5
PV		 947 .suspend = genphy_suspend,
948 .resume = genphy_resume,
19936942
VB		 949 .read_mmd_indirect = ksz9021_rd_mmd_phyreg,
950 .write_mmd_indirect = ksz9021_wr_mmd_phyreg,
7ab59dc1
DC		 951}, {
952 .phy_id = PHY_ID_KSZ9031,
f893a99e 953 .phy_id_mask = MICREL_PHY_ID_MASK,
7ab59dc1 954 .name = "Micrel KSZ9031 Gigabit PHY",
95e8b103 955 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
7ab59dc1 956 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
c6f9575c 957 .driver_data = &ksz9021_type,
6e4b8273 958 .config_init = ksz9031_config_init,
7ab59dc1 959 .config_aneg = genphy_config_aneg,
d2fd719b 960 .read_status = ksz9031_read_status,
7ab59dc1 961 .ack_interrupt = kszphy_ack_interrupt,
c6f9575c 962 .config_intr = kszphy_config_intr,
2b2427d0
AL		 963 .get_sset_count = kszphy_get_sset_count,
964 .get_strings = kszphy_get_strings,
965 .get_stats = kszphy_get_stats,
1a5465f5 966 .suspend = genphy_suspend,
f64f1482 967 .resume = kszphy_resume,
93272e07
JCPV		 968}, {
969 .phy_id = PHY_ID_KSZ8873MLL,
f893a99e 970 .phy_id_mask = MICREL_PHY_ID_MASK,
93272e07
JCPV		 971 .name = "Micrel KSZ8873MLL Switch",
972 .features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
973 .flags = PHY_HAS_MAGICANEG,
974 .config_init = kszphy_config_init,
975 .config_aneg = ksz8873mll_config_aneg,
976 .read_status = ksz8873mll_read_status,
2b2427d0
AL		 977 .get_sset_count = kszphy_get_sset_count,
978 .get_strings = kszphy_get_strings,
979 .get_stats = kszphy_get_stats,
1a5465f5
PV		 980 .suspend = genphy_suspend,
981 .resume = genphy_resume,
7ab59dc1
DC		 982}, {
983 .phy_id = PHY_ID_KSZ886X,
f893a99e 984 .phy_id_mask = MICREL_PHY_ID_MASK,
7ab59dc1
DC		 985 .name = "Micrel KSZ886X Switch",
986 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
987 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
988 .config_init = kszphy_config_init,
989 .config_aneg = genphy_config_aneg,
990 .read_status = genphy_read_status,
2b2427d0
AL		 991 .get_sset_count = kszphy_get_sset_count,
992 .get_strings = kszphy_get_strings,
993 .get_stats = kszphy_get_stats,
1a5465f5
PV		 994 .suspend = genphy_suspend,
995 .resume = genphy_resume,
d5bf9071 996} };
d0507009 997
50fd7150 998module_phy_driver(ksphy_driver);
d0507009
DC		 999
1000MODULE_DESCRIPTION("Micrel PHY driver");
1001MODULE_AUTHOR("David J. Choi");
1002MODULE_LICENSE("GPL");
52a60ed2 1003
cf93c945 1004static struct mdio_device_id __maybe_unused micrel_tbl[] = {
48d7d0ad 1005 { PHY_ID_KSZ9021, 0x000ffffe },
f893a99e 1006 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
ecd5a323 1007 { PHY_ID_KSZ8001, 0x00fffffc },
f893a99e 1008 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
212ea99a 1009 { PHY_ID_KSZ8021, 0x00ffffff },
b818d1a7 1010 { PHY_ID_KSZ8031, 0x00ffffff },
f893a99e
FE		 1011 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1012 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1013 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1014 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1015 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1016 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
52a60ed2
DM		 1017 { }
1018};
1019
1020MODULE_DEVICE_TABLE(mdio, micrel_tbl);
Linux kernel - Deliverables
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