[deliverable/linux.git] / drivers / net / phy / micrel.c

/*
 * drivers/net/phy/micrel.c
 *
 * Driver for Micrel PHYs
 *
 * Author: David J. Choi
 *
 * Copyright (c) 2010-2013 Micrel, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Support : Micrel Phys:
 *		Giga phys: ksz9021, ksz9031
 *		100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
 *			   ksz8021, ksz8031, ksz8051,
 *			   ksz8081, ksz8091,
 *			   ksz8061,
 *		Switch : ksz8873, ksz886x
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/phy.h>
#include <linux/micrel_phy.h>

/* Operation Mode Strap Override */
#define MII_KSZPHY_OMSO				0x16
#define KSZPHY_OMSO_B_CAST_OFF			(1 << 9)
#define KSZPHY_OMSO_RMII_OVERRIDE		(1 << 1)
#define KSZPHY_OMSO_MII_OVERRIDE		(1 << 0)

/* general Interrupt control/status reg in vendor specific block. */
#define MII_KSZPHY_INTCS			0x1B
#define	KSZPHY_INTCS_JABBER			(1 << 15)
#define	KSZPHY_INTCS_RECEIVE_ERR		(1 << 14)
#define	KSZPHY_INTCS_PAGE_RECEIVE		(1 << 13)
#define	KSZPHY_INTCS_PARELLEL			(1 << 12)
#define	KSZPHY_INTCS_LINK_PARTNER_ACK		(1 << 11)
#define	KSZPHY_INTCS_LINK_DOWN			(1 << 10)
#define	KSZPHY_INTCS_REMOTE_FAULT		(1 << 9)
#define	KSZPHY_INTCS_LINK_UP			(1 << 8)
#define	KSZPHY_INTCS_ALL			(KSZPHY_INTCS_LINK_UP |\
						KSZPHY_INTCS_LINK_DOWN)

/* general PHY control reg in vendor specific block. */
#define	MII_KSZPHY_CTRL			0x1F
/* bitmap of PHY register to set interrupt mode */
#define KSZPHY_CTRL_INT_ACTIVE_HIGH		(1 << 9)
#define KSZ9021_CTRL_INT_ACTIVE_HIGH		(1 << 14)
#define KS8737_CTRL_INT_ACTIVE_HIGH		(1 << 14)
#define KSZ8051_RMII_50MHZ_CLK			(1 << 7)

static int kszphy_ack_interrupt(struct phy_device *phydev)
{
	/* bit[7..0] int status, which is a read and clear register. */
	int rc;

	rc = phy_read(phydev, MII_KSZPHY_INTCS);

	return (rc < 0) ? rc : 0;
}

static int kszphy_set_interrupt(struct phy_device *phydev)
{
	int temp;
	temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
		KSZPHY_INTCS_ALL : 0;
	return phy_write(phydev, MII_KSZPHY_INTCS, temp);
}

static int kszphy_config_intr(struct phy_device *phydev)
{
	int temp, rc;

	/* set the interrupt pin active low */
	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	rc = kszphy_set_interrupt(phydev);
	return rc < 0 ? rc : 0;
}

static int ksz9021_config_intr(struct phy_device *phydev)
{
	int temp, rc;

	/* set the interrupt pin active low */
	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	rc = kszphy_set_interrupt(phydev);
	return rc < 0 ? rc : 0;
}

static int ks8737_config_intr(struct phy_device *phydev)
{
	int temp, rc;

	/* set the interrupt pin active low */
	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	rc = kszphy_set_interrupt(phydev);
	return rc < 0 ? rc : 0;
}

static int kszphy_config_init(struct phy_device *phydev)
{
	return 0;
}

static int ksz8021_config_init(struct phy_device *phydev)
{
	const u16 val = KSZPHY_OMSO_B_CAST_OFF | KSZPHY_OMSO_RMII_OVERRIDE;
	phy_write(phydev, MII_KSZPHY_OMSO, val);
	return 0;
}

static int ks8051_config_init(struct phy_device *phydev)
{
	int regval;

	if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
		regval = phy_read(phydev, MII_KSZPHY_CTRL);
		regval |= KSZ8051_RMII_50MHZ_CLK;
		phy_write(phydev, MII_KSZPHY_CTRL, regval);
	}

	return 0;
}

#define KSZ8873MLL_GLOBAL_CONTROL_4	0x06
#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX	(1 << 6)
#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED	(1 << 4)
int ksz8873mll_read_status(struct phy_device *phydev)
{
	int regval;

	/* dummy read */
	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);

	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);

	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
		phydev->duplex = DUPLEX_HALF;
	else
		phydev->duplex = DUPLEX_FULL;

	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
		phydev->speed = SPEED_10;
	else
		phydev->speed = SPEED_100;

	phydev->link = 1;
	phydev->pause = phydev->asym_pause = 0;

	return 0;
}

static int ksz8873mll_config_aneg(struct phy_device *phydev)
{
	return 0;
}

static struct phy_driver ksphy_driver[] = {
{
	.phy_id		= PHY_ID_KS8737,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KS8737",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= ks8737_config_intr,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8021,
	.phy_id_mask	= 0x00ffffff,
	.name		= "Micrel KSZ8021 or KSZ8031",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
			   SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= ksz8021_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8041,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ8041",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause
				| SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8051,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ8051",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause
				| SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= ks8051_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8001,
	.name		= "Micrel KSZ8001 or KS8721",
	.phy_id_mask	= 0x00ffffff,
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8081,
	.name		= "Micrel KSZ8081 or KSZ8091",
	.phy_id_mask	= 0x00fffff0,
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8061,
	.name		= "Micrel KSZ8061",
	.phy_id_mask	= 0x00fffff0,
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ9021,
	.phy_id_mask	= 0x000ffffe,
	.name		= "Micrel KSZ9021 Gigabit PHY",
	.features	= (PHY_GBIT_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= ksz9021_config_intr,
	.driver		= { .owner = THIS_MODULE, },
}, {
	.phy_id		= PHY_ID_KSZ9031,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ9031 Gigabit PHY",
	.features	= (PHY_GBIT_FEATURES | SUPPORTED_Pause
				| SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= ksz9021_config_intr,
	.driver		= { .owner = THIS_MODULE, },
}, {
	.phy_id		= PHY_ID_KSZ8873MLL,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ8873MLL Switch",
	.features	= (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG,
	.config_init	= kszphy_config_init,
	.config_aneg	= ksz8873mll_config_aneg,
	.read_status	= ksz8873mll_read_status,
	.driver		= { .owner = THIS_MODULE, },
}, {
	.phy_id		= PHY_ID_KSZ886X,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ886X Switch",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.driver		= { .owner = THIS_MODULE, },
} };

static int __init ksphy_init(void)
{
	return phy_drivers_register(ksphy_driver,
		ARRAY_SIZE(ksphy_driver));
}

static void __exit ksphy_exit(void)
{
	phy_drivers_unregister(ksphy_driver,
		ARRAY_SIZE(ksphy_driver));
}

module_init(ksphy_init);
module_exit(ksphy_exit);

MODULE_DESCRIPTION("Micrel PHY driver");
MODULE_AUTHOR("David J. Choi");
MODULE_LICENSE("GPL");

static struct mdio_device_id __maybe_unused micrel_tbl[] = {
	{ PHY_ID_KSZ9021, 0x000ffffe },
	{ PHY_ID_KSZ9031, 0x00fffff0 },
	{ PHY_ID_KSZ8001, 0x00ffffff },
	{ PHY_ID_KS8737, 0x00fffff0 },
	{ PHY_ID_KSZ8021, 0x00ffffff },
	{ PHY_ID_KSZ8041, 0x00fffff0 },
	{ PHY_ID_KSZ8051, 0x00fffff0 },
	{ PHY_ID_KSZ8061, 0x00fffff0 },
	{ PHY_ID_KSZ8081, 0x00fffff0 },
	{ PHY_ID_KSZ8873MLL, 0x00fffff0 },
	{ PHY_ID_KSZ886X, 0x00fffff0 },
	{ }
};

MODULE_DEVICE_TABLE(mdio, micrel_tbl);
Commit	Line	Data
d0507009 DC	1	/*
	2	* drivers/net/phy/micrel.c
	3	*
	4	* Driver for Micrel PHYs
	5	*
	6	* Author: David J. Choi
	7	*
7ab59dc1	8	* Copyright (c) 2010-2013 Micrel, Inc.
d0507009 DC	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*
7ab59dc1 DC	15	* Support : Micrel Phys:
	16	* Giga phys: ksz9021, ksz9031
	17	* 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
	18	* ksz8021, ksz8031, ksz8051,
	19	* ksz8081, ksz8091,
	20	* ksz8061,
	21	* Switch : ksz8873, ksz886x
d0507009 DC	22	*/
	23
	24	#include <linux/kernel.h>
	25	#include <linux/module.h>
	26	#include <linux/phy.h>
d606ef3f	27	#include <linux/micrel_phy.h>
d0507009	28
212ea99a MV	29	/* Operation Mode Strap Override */
	30	#define MII_KSZPHY_OMSO 0x16
	31	#define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
	32	#define KSZPHY_OMSO_RMII_OVERRIDE (1 << 1)
	33	#define KSZPHY_OMSO_MII_OVERRIDE (1 << 0)
	34
51f932c4 CD	35	/* general Interrupt control/status reg in vendor specific block. */
	36	#define MII_KSZPHY_INTCS 0x1B
	37	#define KSZPHY_INTCS_JABBER (1 << 15)
	38	#define KSZPHY_INTCS_RECEIVE_ERR (1 << 14)
	39	#define KSZPHY_INTCS_PAGE_RECEIVE (1 << 13)
	40	#define KSZPHY_INTCS_PARELLEL (1 << 12)
	41	#define KSZPHY_INTCS_LINK_PARTNER_ACK (1 << 11)
	42	#define KSZPHY_INTCS_LINK_DOWN (1 << 10)
	43	#define KSZPHY_INTCS_REMOTE_FAULT (1 << 9)
	44	#define KSZPHY_INTCS_LINK_UP (1 << 8)
	45	#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP \|\
	46	KSZPHY_INTCS_LINK_DOWN)
	47
	48	/* general PHY control reg in vendor specific block. */
	49	#define MII_KSZPHY_CTRL 0x1F
	50	/* bitmap of PHY register to set interrupt mode */
	51	#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9)
	52	#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14)
	53	#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
d606ef3f	54	#define KSZ8051_RMII_50MHZ_CLK (1 << 7)
51f932c4 CD	55
	56	static int kszphy_ack_interrupt(struct phy_device *phydev)
	57	{
	58	/* bit[7..0] int status, which is a read and clear register. */
	59	int rc;
	60
	61	rc = phy_read(phydev, MII_KSZPHY_INTCS);
	62
	63	return (rc < 0) ? rc : 0;
	64	}
	65
	66	static int kszphy_set_interrupt(struct phy_device *phydev)
	67	{
	68	int temp;
	69	temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
	70	KSZPHY_INTCS_ALL : 0;
	71	return phy_write(phydev, MII_KSZPHY_INTCS, temp);
	72	}
	73
	74	static int kszphy_config_intr(struct phy_device *phydev)
	75	{
	76	int temp, rc;
	77
	78	/* set the interrupt pin active low */
	79	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	80	temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
	81	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	82	rc = kszphy_set_interrupt(phydev);
	83	return rc < 0 ? rc : 0;
	84	}
	85
	86	static int ksz9021_config_intr(struct phy_device *phydev)
	87	{
	88	int temp, rc;
	89
	90	/* set the interrupt pin active low */
	91	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	92	temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
	93	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	94	rc = kszphy_set_interrupt(phydev);
	95	return rc < 0 ? rc : 0;
	96	}
	97
	98	static int ks8737_config_intr(struct phy_device *phydev)
	99	{
	100	int temp, rc;
	101
	102	/* set the interrupt pin active low */
	103	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	104	temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
	105	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	106	rc = kszphy_set_interrupt(phydev);
	107	return rc < 0 ? rc : 0;
	108	}
d0507009 DC	109
	110	static int kszphy_config_init(struct phy_device *phydev)
	111	{
	112	return 0;
	113	}
	114
212ea99a MV	115	static int ksz8021_config_init(struct phy_device *phydev)
	116	{
	117	const u16 val = KSZPHY_OMSO_B_CAST_OFF \| KSZPHY_OMSO_RMII_OVERRIDE;
	118	phy_write(phydev, MII_KSZPHY_OMSO, val);
	119	return 0;
	120	}
	121
d606ef3f BS	122	static int ks8051_config_init(struct phy_device *phydev)
	123	{
	124	int regval;
	125
	126	if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
	127	regval = phy_read(phydev, MII_KSZPHY_CTRL);
	128	regval \|= KSZ8051_RMII_50MHZ_CLK;
	129	phy_write(phydev, MII_KSZPHY_CTRL, regval);
	130	}
	131
	132	return 0;
	133	}
	134
93272e07 JCPV	135	#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
	136	#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX (1 << 6)
	137	#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED (1 << 4)
	138	int ksz8873mll_read_status(struct phy_device *phydev)
	139	{
	140	int regval;
	141
	142	/* dummy read */
	143	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
	144
	145	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
	146
	147	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
	148	phydev->duplex = DUPLEX_HALF;
	149	else
	150	phydev->duplex = DUPLEX_FULL;
	151
	152	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
	153	phydev->speed = SPEED_10;
	154	else
	155	phydev->speed = SPEED_100;
	156
	157	phydev->link = 1;
	158	phydev->pause = phydev->asym_pause = 0;
	159
	160	return 0;
	161	}
	162
	163	static int ksz8873mll_config_aneg(struct phy_device *phydev)
	164	{
	165	return 0;
	166	}
	167
d5bf9071 CH	168	static struct phy_driver ksphy_driver[] = {
d5bf9071 CH	169	{
51f932c4 CD	170	.phy_id = PHY_ID_KS8737,
	171	.phy_id_mask = 0x00fffff0,
	172	.name = "Micrel KS8737",
	173	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
	174	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	175	.config_init = kszphy_config_init,
	176	.config_aneg = genphy_config_aneg,
	177	.read_status = genphy_read_status,
	178	.ack_interrupt = kszphy_ack_interrupt,
	179	.config_intr = ks8737_config_intr,
	180	.driver = { .owner = THIS_MODULE,},
212ea99a MV	181	}, {
	182	.phy_id = PHY_ID_KSZ8021,
	183	.phy_id_mask = 0x00ffffff,
7ab59dc1	184	.name = "Micrel KSZ8021 or KSZ8031",
212ea99a MV	185	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause \|
	186	SUPPORTED_Asym_Pause),
	187	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	188	.config_init = ksz8021_config_init,
	189	.config_aneg = genphy_config_aneg,
	190	.read_status = genphy_read_status,
	191	.ack_interrupt = kszphy_ack_interrupt,
	192	.config_intr = kszphy_config_intr,
	193	.driver = { .owner = THIS_MODULE,},
d5bf9071	194	}, {
510d573f	195	.phy_id = PHY_ID_KSZ8041,
51f932c4	196	.phy_id_mask = 0x00fffff0,
510d573f	197	.name = "Micrel KSZ8041",
51f932c4 CD	198	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause
	199	\| SUPPORTED_Asym_Pause),
	200	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	201	.config_init = kszphy_config_init,
	202	.config_aneg = genphy_config_aneg,
	203	.read_status = genphy_read_status,
	204	.ack_interrupt = kszphy_ack_interrupt,
	205	.config_intr = kszphy_config_intr,
	206	.driver = { .owner = THIS_MODULE,},
d5bf9071	207	}, {
510d573f	208	.phy_id = PHY_ID_KSZ8051,
d0507009	209	.phy_id_mask = 0x00fffff0,
510d573f	210	.name = "Micrel KSZ8051",
51f932c4 CD	211	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause
	212	\| SUPPORTED_Asym_Pause),
	213	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
d606ef3f	214	.config_init = ks8051_config_init,
d0507009 DC	215	.config_aneg = genphy_config_aneg,
d0507009 DC	216	.read_status = genphy_read_status,
51f932c4 CD	217	.ack_interrupt = kszphy_ack_interrupt,
51f932c4 CD	218	.config_intr = kszphy_config_intr,
d0507009	219	.driver = { .owner = THIS_MODULE,},
d5bf9071	220	}, {
510d573f MV	221	.phy_id = PHY_ID_KSZ8001,
510d573f MV	222	.name = "Micrel KSZ8001 or KS8721",
48d7d0ad	223	.phy_id_mask = 0x00ffffff,
51f932c4 CD	224	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
51f932c4 CD	225	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
d0507009 DC	226	.config_init = kszphy_config_init,
	227	.config_aneg = genphy_config_aneg,
	228	.read_status = genphy_read_status,
51f932c4 CD	229	.ack_interrupt = kszphy_ack_interrupt,
51f932c4 CD	230	.config_intr = kszphy_config_intr,
d0507009	231	.driver = { .owner = THIS_MODULE,},
7ab59dc1 DC	232	}, {
	233	.phy_id = PHY_ID_KSZ8081,
	234	.name = "Micrel KSZ8081 or KSZ8091",
	235	.phy_id_mask = 0x00fffff0,
	236	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
	237	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	238	.config_init = kszphy_config_init,
	239	.config_aneg = genphy_config_aneg,
	240	.read_status = genphy_read_status,
	241	.ack_interrupt = kszphy_ack_interrupt,
	242	.config_intr = kszphy_config_intr,
	243	.driver = { .owner = THIS_MODULE,},
	244	}, {
	245	.phy_id = PHY_ID_KSZ8061,
	246	.name = "Micrel KSZ8061",
	247	.phy_id_mask = 0x00fffff0,
	248	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
	249	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	250	.config_init = kszphy_config_init,
	251	.config_aneg = genphy_config_aneg,
	252	.read_status = genphy_read_status,
	253	.ack_interrupt = kszphy_ack_interrupt,
	254	.config_intr = kszphy_config_intr,
	255	.driver = { .owner = THIS_MODULE,},
d5bf9071	256	}, {
d0507009	257	.phy_id = PHY_ID_KSZ9021,
48d7d0ad	258	.phy_id_mask = 0x000ffffe,
d0507009	259	.name = "Micrel KSZ9021 Gigabit PHY",
32fcafbc	260	.features = (PHY_GBIT_FEATURES \| SUPPORTED_Pause),
51f932c4	261	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
d0507009 DC	262	.config_init = kszphy_config_init,
	263	.config_aneg = genphy_config_aneg,
	264	.read_status = genphy_read_status,
51f932c4 CD	265	.ack_interrupt = kszphy_ack_interrupt,
51f932c4 CD	266	.config_intr = ksz9021_config_intr,
d0507009	267	.driver = { .owner = THIS_MODULE, },
7ab59dc1 DC	268	}, {
	269	.phy_id = PHY_ID_KSZ9031,
	270	.phy_id_mask = 0x00fffff0,
	271	.name = "Micrel KSZ9031 Gigabit PHY",
	272	.features = (PHY_GBIT_FEATURES \| SUPPORTED_Pause
	273	\| SUPPORTED_Asym_Pause),
	274	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	275	.config_init = kszphy_config_init,
	276	.config_aneg = genphy_config_aneg,
	277	.read_status = genphy_read_status,
	278	.ack_interrupt = kszphy_ack_interrupt,
	279	.config_intr = ksz9021_config_intr,
	280	.driver = { .owner = THIS_MODULE, },
93272e07 JCPV	281	}, {
	282	.phy_id = PHY_ID_KSZ8873MLL,
	283	.phy_id_mask = 0x00fffff0,
	284	.name = "Micrel KSZ8873MLL Switch",
	285	.features = (SUPPORTED_Pause \| SUPPORTED_Asym_Pause),
	286	.flags = PHY_HAS_MAGICANEG,
	287	.config_init = kszphy_config_init,
	288	.config_aneg = ksz8873mll_config_aneg,
	289	.read_status = ksz8873mll_read_status,
	290	.driver = { .owner = THIS_MODULE, },
7ab59dc1 DC	291	}, {
	292	.phy_id = PHY_ID_KSZ886X,
	293	.phy_id_mask = 0x00fffff0,
	294	.name = "Micrel KSZ886X Switch",
	295	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
	296	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	297	.config_init = kszphy_config_init,
	298	.config_aneg = genphy_config_aneg,
	299	.read_status = genphy_read_status,
	300	.driver = { .owner = THIS_MODULE, },
d5bf9071	301	} };
d0507009 DC	302
	303	static int __init ksphy_init(void)
	304	{
d5bf9071 CH	305	return phy_drivers_register(ksphy_driver,
d5bf9071 CH	306	ARRAY_SIZE(ksphy_driver));
d0507009 DC	307	}
	308
	309	static void __exit ksphy_exit(void)
	310	{
d5bf9071 CH	311	phy_drivers_unregister(ksphy_driver,
d5bf9071 CH	312	ARRAY_SIZE(ksphy_driver));
d0507009 DC	313	}
	314
	315	module_init(ksphy_init);
	316	module_exit(ksphy_exit);
	317
	318	MODULE_DESCRIPTION("Micrel PHY driver");
	319	MODULE_AUTHOR("David J. Choi");
	320	MODULE_LICENSE("GPL");
52a60ed2	321
cf93c945	322	static struct mdio_device_id __maybe_unused micrel_tbl[] = {
48d7d0ad	323	{ PHY_ID_KSZ9021, 0x000ffffe },
7ab59dc1	324	{ PHY_ID_KSZ9031, 0x00fffff0 },
510d573f	325	{ PHY_ID_KSZ8001, 0x00ffffff },
51f932c4	326	{ PHY_ID_KS8737, 0x00fffff0 },
212ea99a	327	{ PHY_ID_KSZ8021, 0x00ffffff },
510d573f MV	328	{ PHY_ID_KSZ8041, 0x00fffff0 },
510d573f MV	329	{ PHY_ID_KSZ8051, 0x00fffff0 },
7ab59dc1 DC	330	{ PHY_ID_KSZ8061, 0x00fffff0 },
7ab59dc1 DC	331	{ PHY_ID_KSZ8081, 0x00fffff0 },
93272e07	332	{ PHY_ID_KSZ8873MLL, 0x00fffff0 },
7ab59dc1	333	{ PHY_ID_KSZ886X, 0x00fffff0 },
52a60ed2 DM	334	{ }
	335	};
	336
	337	MODULE_DEVICE_TABLE(mdio, micrel_tbl);