[deliverable/linux.git] / drivers / net / phy / micrel.c

/*
 * drivers/net/phy/micrel.c
 *
 * Driver for Micrel PHYs
 *
 * Author: David J. Choi
 *
 * Copyright (c) 2010-2013 Micrel, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Support : Micrel Phys:
 *		Giga phys: ksz9021, ksz9031
 *		100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
 *			   ksz8021, ksz8031, ksz8051,
 *			   ksz8081, ksz8091,
 *			   ksz8061,
 *		Switch : ksz8873, ksz886x
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/phy.h>
#include <linux/micrel_phy.h>

/* Operation Mode Strap Override */
#define MII_KSZPHY_OMSO				0x16
#define KSZPHY_OMSO_B_CAST_OFF			(1 << 9)
#define KSZPHY_OMSO_RMII_OVERRIDE		(1 << 1)
#define KSZPHY_OMSO_MII_OVERRIDE		(1 << 0)

/* general Interrupt control/status reg in vendor specific block. */
#define MII_KSZPHY_INTCS			0x1B
#define	KSZPHY_INTCS_JABBER			(1 << 15)
#define	KSZPHY_INTCS_RECEIVE_ERR		(1 << 14)
#define	KSZPHY_INTCS_PAGE_RECEIVE		(1 << 13)
#define	KSZPHY_INTCS_PARELLEL			(1 << 12)
#define	KSZPHY_INTCS_LINK_PARTNER_ACK		(1 << 11)
#define	KSZPHY_INTCS_LINK_DOWN			(1 << 10)
#define	KSZPHY_INTCS_REMOTE_FAULT		(1 << 9)
#define	KSZPHY_INTCS_LINK_UP			(1 << 8)
#define	KSZPHY_INTCS_ALL			(KSZPHY_INTCS_LINK_UP |\
						KSZPHY_INTCS_LINK_DOWN)

/* general PHY control reg in vendor specific block. */
#define	MII_KSZPHY_CTRL			0x1F
/* bitmap of PHY register to set interrupt mode */
#define KSZPHY_CTRL_INT_ACTIVE_HIGH		(1 << 9)
#define KSZ9021_CTRL_INT_ACTIVE_HIGH		(1 << 14)
#define KS8737_CTRL_INT_ACTIVE_HIGH		(1 << 14)
#define KSZ8051_RMII_50MHZ_CLK			(1 << 7)

static int ksz_config_flags(struct phy_device *phydev)
{
	int regval;

	if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
		regval = phy_read(phydev, MII_KSZPHY_CTRL);
		regval |= KSZ8051_RMII_50MHZ_CLK;
		return phy_write(phydev, MII_KSZPHY_CTRL, regval);
	}
	return 0;
}

static int kszphy_ack_interrupt(struct phy_device *phydev)
{
	/* bit[7..0] int status, which is a read and clear register. */
	int rc;

	rc = phy_read(phydev, MII_KSZPHY_INTCS);

	return (rc < 0) ? rc : 0;
}

static int kszphy_set_interrupt(struct phy_device *phydev)
{
	int temp;
	temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
		KSZPHY_INTCS_ALL : 0;
	return phy_write(phydev, MII_KSZPHY_INTCS, temp);
}

static int kszphy_config_intr(struct phy_device *phydev)
{
	int temp, rc;

	/* set the interrupt pin active low */
	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	rc = kszphy_set_interrupt(phydev);
	return rc < 0 ? rc : 0;
}

static int ksz9021_config_intr(struct phy_device *phydev)
{
	int temp, rc;

	/* set the interrupt pin active low */
	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	rc = kszphy_set_interrupt(phydev);
	return rc < 0 ? rc : 0;
}

static int ks8737_config_intr(struct phy_device *phydev)
{
	int temp, rc;

	/* set the interrupt pin active low */
	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	rc = kszphy_set_interrupt(phydev);
	return rc < 0 ? rc : 0;
}

static int kszphy_config_init(struct phy_device *phydev)
{
	return 0;
}

static int ksz8021_config_init(struct phy_device *phydev)
{
	int rc;
	const u16 val = KSZPHY_OMSO_B_CAST_OFF | KSZPHY_OMSO_RMII_OVERRIDE;
	phy_write(phydev, MII_KSZPHY_OMSO, val);
	rc = ksz_config_flags(phydev);
	return rc < 0 ? rc : 0;
}

static int ks8051_config_init(struct phy_device *phydev)
{
	int rc;

	rc = ksz_config_flags(phydev);
	return rc < 0 ? rc : 0;
}

#define KSZ8873MLL_GLOBAL_CONTROL_4	0x06
#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX	(1 << 6)
#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED	(1 << 4)
int ksz8873mll_read_status(struct phy_device *phydev)
{
	int regval;

	/* dummy read */
	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);

	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);

	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
		phydev->duplex = DUPLEX_HALF;
	else
		phydev->duplex = DUPLEX_FULL;

	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
		phydev->speed = SPEED_10;
	else
		phydev->speed = SPEED_100;

	phydev->link = 1;
	phydev->pause = phydev->asym_pause = 0;

	return 0;
}

static int ksz8873mll_config_aneg(struct phy_device *phydev)
{
	return 0;
}

static struct phy_driver ksphy_driver[] = {
{
	.phy_id		= PHY_ID_KS8737,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KS8737",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= ks8737_config_intr,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8021,
	.phy_id_mask	= 0x00ffffff,
	.name		= "Micrel KSZ8021 or KSZ8031",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
			   SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= ksz8021_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8031,
	.phy_id_mask	= 0x00ffffff,
	.name		= "Micrel KSZ8031",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
			   SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= ksz8021_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8041,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ8041",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause
				| SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8051,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ8051",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause
				| SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= ks8051_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8001,
	.name		= "Micrel KSZ8001 or KS8721",
	.phy_id_mask	= 0x00ffffff,
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8081,
	.name		= "Micrel KSZ8081 or KSZ8091",
	.phy_id_mask	= 0x00fffff0,
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8061,
	.name		= "Micrel KSZ8061",
	.phy_id_mask	= 0x00fffff0,
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ9021,
	.phy_id_mask	= 0x000ffffe,
	.name		= "Micrel KSZ9021 Gigabit PHY",
	.features	= (PHY_GBIT_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= ksz9021_config_intr,
	.driver		= { .owner = THIS_MODULE, },
}, {
	.phy_id		= PHY_ID_KSZ9031,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ9031 Gigabit PHY",
	.features	= (PHY_GBIT_FEATURES | SUPPORTED_Pause
				| SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= ksz9021_config_intr,
	.driver		= { .owner = THIS_MODULE, },
}, {
	.phy_id		= PHY_ID_KSZ8873MLL,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ8873MLL Switch",
	.features	= (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG,
	.config_init	= kszphy_config_init,
	.config_aneg	= ksz8873mll_config_aneg,
	.read_status	= ksz8873mll_read_status,
	.driver		= { .owner = THIS_MODULE, },
}, {
	.phy_id		= PHY_ID_KSZ886X,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ886X Switch",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.driver		= { .owner = THIS_MODULE, },
} };

static int __init ksphy_init(void)
{
	return phy_drivers_register(ksphy_driver,
		ARRAY_SIZE(ksphy_driver));
}

static void __exit ksphy_exit(void)
{
	phy_drivers_unregister(ksphy_driver,
		ARRAY_SIZE(ksphy_driver));
}

module_init(ksphy_init);
module_exit(ksphy_exit);

MODULE_DESCRIPTION("Micrel PHY driver");
MODULE_AUTHOR("David J. Choi");
MODULE_LICENSE("GPL");

static struct mdio_device_id __maybe_unused micrel_tbl[] = {
	{ PHY_ID_KSZ9021, 0x000ffffe },
	{ PHY_ID_KSZ9031, 0x00fffff0 },
	{ PHY_ID_KSZ8001, 0x00ffffff },
	{ PHY_ID_KS8737, 0x00fffff0 },
	{ PHY_ID_KSZ8021, 0x00ffffff },
	{ PHY_ID_KSZ8031, 0x00ffffff },
	{ PHY_ID_KSZ8041, 0x00fffff0 },
	{ PHY_ID_KSZ8051, 0x00fffff0 },
	{ PHY_ID_KSZ8061, 0x00fffff0 },
	{ PHY_ID_KSZ8081, 0x00fffff0 },
	{ PHY_ID_KSZ8873MLL, 0x00fffff0 },
	{ PHY_ID_KSZ886X, 0x00fffff0 },
	{ }
};

MODULE_DEVICE_TABLE(mdio, micrel_tbl);
Commit	Line	Data
d0507009 DC	1	/*
	2	* drivers/net/phy/micrel.c
	3	*
	4	* Driver for Micrel PHYs
	5	*
	6	* Author: David J. Choi
	7	*
7ab59dc1	8	* Copyright (c) 2010-2013 Micrel, Inc.
d0507009 DC	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*
7ab59dc1 DC	15	* Support : Micrel Phys:
	16	* Giga phys: ksz9021, ksz9031
	17	* 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
	18	* ksz8021, ksz8031, ksz8051,
	19	* ksz8081, ksz8091,
	20	* ksz8061,
	21	* Switch : ksz8873, ksz886x
d0507009 DC	22	*/
	23
	24	#include <linux/kernel.h>
	25	#include <linux/module.h>
	26	#include <linux/phy.h>
d606ef3f	27	#include <linux/micrel_phy.h>
d0507009	28
212ea99a MV	29	/* Operation Mode Strap Override */
	30	#define MII_KSZPHY_OMSO 0x16
	31	#define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
	32	#define KSZPHY_OMSO_RMII_OVERRIDE (1 << 1)
	33	#define KSZPHY_OMSO_MII_OVERRIDE (1 << 0)
	34
51f932c4 CD	35	/* general Interrupt control/status reg in vendor specific block. */
	36	#define MII_KSZPHY_INTCS 0x1B
	37	#define KSZPHY_INTCS_JABBER (1 << 15)
	38	#define KSZPHY_INTCS_RECEIVE_ERR (1 << 14)
	39	#define KSZPHY_INTCS_PAGE_RECEIVE (1 << 13)
	40	#define KSZPHY_INTCS_PARELLEL (1 << 12)
	41	#define KSZPHY_INTCS_LINK_PARTNER_ACK (1 << 11)
	42	#define KSZPHY_INTCS_LINK_DOWN (1 << 10)
	43	#define KSZPHY_INTCS_REMOTE_FAULT (1 << 9)
	44	#define KSZPHY_INTCS_LINK_UP (1 << 8)
	45	#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP \|\
	46	KSZPHY_INTCS_LINK_DOWN)
	47
	48	/* general PHY control reg in vendor specific block. */
	49	#define MII_KSZPHY_CTRL 0x1F
	50	/* bitmap of PHY register to set interrupt mode */
	51	#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9)
	52	#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14)
	53	#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
d606ef3f	54	#define KSZ8051_RMII_50MHZ_CLK (1 << 7)
51f932c4	55
b6bb4dfc HP	56	static int ksz_config_flags(struct phy_device *phydev)
	57	{
	58	int regval;
	59
	60	if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
	61	regval = phy_read(phydev, MII_KSZPHY_CTRL);
	62	regval \|= KSZ8051_RMII_50MHZ_CLK;
	63	return phy_write(phydev, MII_KSZPHY_CTRL, regval);
	64	}
	65	return 0;
	66	}
	67
51f932c4 CD	68	static int kszphy_ack_interrupt(struct phy_device *phydev)
	69	{
	70	/* bit[7..0] int status, which is a read and clear register. */
	71	int rc;
	72
	73	rc = phy_read(phydev, MII_KSZPHY_INTCS);
	74
	75	return (rc < 0) ? rc : 0;
	76	}
	77
	78	static int kszphy_set_interrupt(struct phy_device *phydev)
	79	{
	80	int temp;
	81	temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
	82	KSZPHY_INTCS_ALL : 0;
	83	return phy_write(phydev, MII_KSZPHY_INTCS, temp);
	84	}
	85
	86	static int kszphy_config_intr(struct phy_device *phydev)
	87	{
	88	int temp, rc;
	89
	90	/* set the interrupt pin active low */
	91	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	92	temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
	93	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	94	rc = kszphy_set_interrupt(phydev);
	95	return rc < 0 ? rc : 0;
	96	}
	97
	98	static int ksz9021_config_intr(struct phy_device *phydev)
	99	{
	100	int temp, rc;
	101
	102	/* set the interrupt pin active low */
	103	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	104	temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
	105	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	106	rc = kszphy_set_interrupt(phydev);
	107	return rc < 0 ? rc : 0;
	108	}
	109
	110	static int ks8737_config_intr(struct phy_device *phydev)
	111	{
	112	int temp, rc;
	113
	114	/* set the interrupt pin active low */
	115	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	116	temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
	117	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	118	rc = kszphy_set_interrupt(phydev);
	119	return rc < 0 ? rc : 0;
	120	}
d0507009 DC	121
	122	static int kszphy_config_init(struct phy_device *phydev)
	123	{
	124	return 0;
	125	}
	126
212ea99a MV	127	static int ksz8021_config_init(struct phy_device *phydev)
212ea99a MV	128	{
b6bb4dfc	129	int rc;
212ea99a MV	130	const u16 val = KSZPHY_OMSO_B_CAST_OFF \| KSZPHY_OMSO_RMII_OVERRIDE;
212ea99a MV	131	phy_write(phydev, MII_KSZPHY_OMSO, val);
b6bb4dfc HP	132	rc = ksz_config_flags(phydev);
b6bb4dfc HP	133	return rc < 0 ? rc : 0;
212ea99a MV	134	}
212ea99a MV	135
d606ef3f BS	136	static int ks8051_config_init(struct phy_device *phydev)
d606ef3f BS	137	{
b6bb4dfc	138	int rc;
d606ef3f	139
b6bb4dfc HP	140	rc = ksz_config_flags(phydev);
b6bb4dfc HP	141	return rc < 0 ? rc : 0;
d606ef3f BS	142	}
d606ef3f BS	143
93272e07 JCPV	144	#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
	145	#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX (1 << 6)
	146	#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED (1 << 4)
	147	int ksz8873mll_read_status(struct phy_device *phydev)
	148	{
	149	int regval;
	150
	151	/* dummy read */
	152	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
	153
	154	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
	155
	156	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
	157	phydev->duplex = DUPLEX_HALF;
	158	else
	159	phydev->duplex = DUPLEX_FULL;
	160
	161	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
	162	phydev->speed = SPEED_10;
	163	else
	164	phydev->speed = SPEED_100;
	165
	166	phydev->link = 1;
	167	phydev->pause = phydev->asym_pause = 0;
	168
	169	return 0;
	170	}
	171
	172	static int ksz8873mll_config_aneg(struct phy_device *phydev)
	173	{
	174	return 0;
	175	}
	176
d5bf9071 CH	177	static struct phy_driver ksphy_driver[] = {
d5bf9071 CH	178	{
51f932c4 CD	179	.phy_id = PHY_ID_KS8737,
	180	.phy_id_mask = 0x00fffff0,
	181	.name = "Micrel KS8737",
	182	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
	183	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	184	.config_init = kszphy_config_init,
	185	.config_aneg = genphy_config_aneg,
	186	.read_status = genphy_read_status,
	187	.ack_interrupt = kszphy_ack_interrupt,
	188	.config_intr = ks8737_config_intr,
	189	.driver = { .owner = THIS_MODULE,},
212ea99a MV	190	}, {
	191	.phy_id = PHY_ID_KSZ8021,
	192	.phy_id_mask = 0x00ffffff,
7ab59dc1	193	.name = "Micrel KSZ8021 or KSZ8031",
212ea99a MV	194	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause \|
	195	SUPPORTED_Asym_Pause),
	196	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	197	.config_init = ksz8021_config_init,
	198	.config_aneg = genphy_config_aneg,
	199	.read_status = genphy_read_status,
	200	.ack_interrupt = kszphy_ack_interrupt,
	201	.config_intr = kszphy_config_intr,
	202	.driver = { .owner = THIS_MODULE,},
b818d1a7 HP	203	}, {
	204	.phy_id = PHY_ID_KSZ8031,
	205	.phy_id_mask = 0x00ffffff,
	206	.name = "Micrel KSZ8031",
	207	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause \|
	208	SUPPORTED_Asym_Pause),
	209	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	210	.config_init = ksz8021_config_init,
	211	.config_aneg = genphy_config_aneg,
	212	.read_status = genphy_read_status,
	213	.ack_interrupt = kszphy_ack_interrupt,
	214	.config_intr = kszphy_config_intr,
	215	.driver = { .owner = THIS_MODULE,},
d5bf9071	216	}, {
510d573f	217	.phy_id = PHY_ID_KSZ8041,
51f932c4	218	.phy_id_mask = 0x00fffff0,
510d573f	219	.name = "Micrel KSZ8041",
51f932c4 CD	220	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause
	221	\| SUPPORTED_Asym_Pause),
	222	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	223	.config_init = kszphy_config_init,
	224	.config_aneg = genphy_config_aneg,
	225	.read_status = genphy_read_status,
	226	.ack_interrupt = kszphy_ack_interrupt,
	227	.config_intr = kszphy_config_intr,
	228	.driver = { .owner = THIS_MODULE,},
d5bf9071	229	}, {
510d573f	230	.phy_id = PHY_ID_KSZ8051,
d0507009	231	.phy_id_mask = 0x00fffff0,
510d573f	232	.name = "Micrel KSZ8051",
51f932c4 CD	233	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause
	234	\| SUPPORTED_Asym_Pause),
	235	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
d606ef3f	236	.config_init = ks8051_config_init,
d0507009 DC	237	.config_aneg = genphy_config_aneg,
d0507009 DC	238	.read_status = genphy_read_status,
51f932c4 CD	239	.ack_interrupt = kszphy_ack_interrupt,
51f932c4 CD	240	.config_intr = kszphy_config_intr,
d0507009	241	.driver = { .owner = THIS_MODULE,},
d5bf9071	242	}, {
510d573f MV	243	.phy_id = PHY_ID_KSZ8001,
510d573f MV	244	.name = "Micrel KSZ8001 or KS8721",
48d7d0ad	245	.phy_id_mask = 0x00ffffff,
51f932c4 CD	246	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
51f932c4 CD	247	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
d0507009 DC	248	.config_init = kszphy_config_init,
	249	.config_aneg = genphy_config_aneg,
	250	.read_status = genphy_read_status,
51f932c4 CD	251	.ack_interrupt = kszphy_ack_interrupt,
51f932c4 CD	252	.config_intr = kszphy_config_intr,
d0507009	253	.driver = { .owner = THIS_MODULE,},
7ab59dc1 DC	254	}, {
	255	.phy_id = PHY_ID_KSZ8081,
	256	.name = "Micrel KSZ8081 or KSZ8091",
	257	.phy_id_mask = 0x00fffff0,
	258	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
	259	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	260	.config_init = kszphy_config_init,
	261	.config_aneg = genphy_config_aneg,
	262	.read_status = genphy_read_status,
	263	.ack_interrupt = kszphy_ack_interrupt,
	264	.config_intr = kszphy_config_intr,
	265	.driver = { .owner = THIS_MODULE,},
	266	}, {
	267	.phy_id = PHY_ID_KSZ8061,
	268	.name = "Micrel KSZ8061",
	269	.phy_id_mask = 0x00fffff0,
	270	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
	271	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	272	.config_init = kszphy_config_init,
	273	.config_aneg = genphy_config_aneg,
	274	.read_status = genphy_read_status,
	275	.ack_interrupt = kszphy_ack_interrupt,
	276	.config_intr = kszphy_config_intr,
	277	.driver = { .owner = THIS_MODULE,},
d5bf9071	278	}, {
d0507009	279	.phy_id = PHY_ID_KSZ9021,
48d7d0ad	280	.phy_id_mask = 0x000ffffe,
d0507009	281	.name = "Micrel KSZ9021 Gigabit PHY",
32fcafbc	282	.features = (PHY_GBIT_FEATURES \| SUPPORTED_Pause),
51f932c4	283	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
d0507009 DC	284	.config_init = kszphy_config_init,
	285	.config_aneg = genphy_config_aneg,
	286	.read_status = genphy_read_status,
51f932c4 CD	287	.ack_interrupt = kszphy_ack_interrupt,
51f932c4 CD	288	.config_intr = ksz9021_config_intr,
d0507009	289	.driver = { .owner = THIS_MODULE, },
7ab59dc1 DC	290	}, {
	291	.phy_id = PHY_ID_KSZ9031,
	292	.phy_id_mask = 0x00fffff0,
	293	.name = "Micrel KSZ9031 Gigabit PHY",
	294	.features = (PHY_GBIT_FEATURES \| SUPPORTED_Pause
	295	\| SUPPORTED_Asym_Pause),
	296	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	297	.config_init = kszphy_config_init,
	298	.config_aneg = genphy_config_aneg,
	299	.read_status = genphy_read_status,
	300	.ack_interrupt = kszphy_ack_interrupt,
	301	.config_intr = ksz9021_config_intr,
	302	.driver = { .owner = THIS_MODULE, },
93272e07 JCPV	303	}, {
	304	.phy_id = PHY_ID_KSZ8873MLL,
	305	.phy_id_mask = 0x00fffff0,
	306	.name = "Micrel KSZ8873MLL Switch",
	307	.features = (SUPPORTED_Pause \| SUPPORTED_Asym_Pause),
	308	.flags = PHY_HAS_MAGICANEG,
	309	.config_init = kszphy_config_init,
	310	.config_aneg = ksz8873mll_config_aneg,
	311	.read_status = ksz8873mll_read_status,
	312	.driver = { .owner = THIS_MODULE, },
7ab59dc1 DC	313	}, {
	314	.phy_id = PHY_ID_KSZ886X,
	315	.phy_id_mask = 0x00fffff0,
	316	.name = "Micrel KSZ886X Switch",
	317	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
	318	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	319	.config_init = kszphy_config_init,
	320	.config_aneg = genphy_config_aneg,
	321	.read_status = genphy_read_status,
	322	.driver = { .owner = THIS_MODULE, },
d5bf9071	323	} };
d0507009 DC	324
	325	static int __init ksphy_init(void)
	326	{
d5bf9071 CH	327	return phy_drivers_register(ksphy_driver,
d5bf9071 CH	328	ARRAY_SIZE(ksphy_driver));
d0507009 DC	329	}
	330
	331	static void __exit ksphy_exit(void)
	332	{
d5bf9071 CH	333	phy_drivers_unregister(ksphy_driver,
d5bf9071 CH	334	ARRAY_SIZE(ksphy_driver));
d0507009 DC	335	}
	336
	337	module_init(ksphy_init);
	338	module_exit(ksphy_exit);
	339
	340	MODULE_DESCRIPTION("Micrel PHY driver");
	341	MODULE_AUTHOR("David J. Choi");
	342	MODULE_LICENSE("GPL");
52a60ed2	343
cf93c945	344	static struct mdio_device_id __maybe_unused micrel_tbl[] = {
48d7d0ad	345	{ PHY_ID_KSZ9021, 0x000ffffe },
7ab59dc1	346	{ PHY_ID_KSZ9031, 0x00fffff0 },
510d573f	347	{ PHY_ID_KSZ8001, 0x00ffffff },
51f932c4	348	{ PHY_ID_KS8737, 0x00fffff0 },
212ea99a	349	{ PHY_ID_KSZ8021, 0x00ffffff },
b818d1a7	350	{ PHY_ID_KSZ8031, 0x00ffffff },
510d573f MV	351	{ PHY_ID_KSZ8041, 0x00fffff0 },
510d573f MV	352	{ PHY_ID_KSZ8051, 0x00fffff0 },
7ab59dc1 DC	353	{ PHY_ID_KSZ8061, 0x00fffff0 },
7ab59dc1 DC	354	{ PHY_ID_KSZ8081, 0x00fffff0 },
93272e07	355	{ PHY_ID_KSZ8873MLL, 0x00fffff0 },
7ab59dc1	356	{ PHY_ID_KSZ886X, 0x00fffff0 },
52a60ed2 DM	357	{ }
	358	};
	359
	360	MODULE_DEVICE_TABLE(mdio, micrel_tbl);