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net: phy: micrel: disable broadcast for KSZ8081/KSZ8091
[deliverable/linux.git] / drivers / net / phy / micrel.c
CommitLineData
d0507009
DC		 1/*
2 * drivers/net/phy/micrel.c
3 *
4 * Driver for Micrel PHYs
5 *
6 * Author: David J. Choi
7 *
7ab59dc1 8 * Copyright (c) 2010-2013 Micrel, Inc.
d0507009
DC		 9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
7ab59dc1
DC		 15 * Support : Micrel Phys:
16 * Giga phys: ksz9021, ksz9031
17 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
18 * ksz8021, ksz8031, ksz8051,
19 * ksz8081, ksz8091,
20 * ksz8061,
21 * Switch : ksz8873, ksz886x
d0507009
DC		 22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/phy.h>
d606ef3f 27#include <linux/micrel_phy.h>
954c3967 28#include <linux/of.h>
1fadee0c 29#include <linux/clk.h>
d0507009 30
212ea99a
MV		 31/* Operation Mode Strap Override */
32#define MII_KSZPHY_OMSO 0x16
00aee095
JH		 33#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
34#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
35#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
212ea99a 36
51f932c4
CD		 37/* general Interrupt control/status reg in vendor specific block. */
38#define MII_KSZPHY_INTCS 0x1B
00aee095
JH		 39#define KSZPHY_INTCS_JABBER BIT(15)
40#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
41#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
42#define KSZPHY_INTCS_PARELLEL BIT(12)
43#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
44#define KSZPHY_INTCS_LINK_DOWN BIT(10)
45#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
46#define KSZPHY_INTCS_LINK_UP BIT(8)
51f932c4
CD		 47#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
48 KSZPHY_INTCS_LINK_DOWN)
49
50/* general PHY control reg in vendor specific block. */
51#define MII_KSZPHY_CTRL 0x1F
52/* bitmap of PHY register to set interrupt mode */
00aee095
JH		 53#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
54#define KSZ9021_CTRL_INT_ACTIVE_HIGH BIT(14)
55#define KS8737_CTRL_INT_ACTIVE_HIGH BIT(14)
56#define KSZ8051_RMII_50MHZ_CLK BIT(7)
51f932c4 57
954c3967
SC		 58/* Write/read to/from extended registers */
59#define MII_KSZPHY_EXTREG 0x0b
60#define KSZPHY_EXTREG_WRITE 0x8000
61
62#define MII_KSZPHY_EXTREG_WRITE 0x0c
63#define MII_KSZPHY_EXTREG_READ 0x0d
64
65/* Extended registers */
66#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
67#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
68#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
69
70#define PS_TO_REG 200
71
b6bb4dfc
HP		 72static int ksz_config_flags(struct phy_device *phydev)
73{
74 int regval;
75
1fadee0c 76 if (phydev->dev_flags & (MICREL_PHY_50MHZ_CLK | MICREL_PHY_25MHZ_CLK)) {
b6bb4dfc 77 regval = phy_read(phydev, MII_KSZPHY_CTRL);
1fadee0c
SH		 78 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK)
79 regval |= KSZ8051_RMII_50MHZ_CLK;
80 else
81 regval &= ~KSZ8051_RMII_50MHZ_CLK;
b6bb4dfc
HP		 82 return phy_write(phydev, MII_KSZPHY_CTRL, regval);
83 }
84 return 0;
85}
86
954c3967 87static int kszphy_extended_write(struct phy_device *phydev,
756b5089 88 u32 regnum, u16 val)
954c3967
SC		 89{
90 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
91 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
92}
93
94static int kszphy_extended_read(struct phy_device *phydev,
756b5089 95 u32 regnum)
954c3967
SC		 96{
97 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
98 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
99}
100
51f932c4
CD		 101static int kszphy_ack_interrupt(struct phy_device *phydev)
102{
103 /* bit[7..0] int status, which is a read and clear register. */
104 int rc;
105
106 rc = phy_read(phydev, MII_KSZPHY_INTCS);
107
108 return (rc < 0) ? rc : 0;
109}
110
111static int kszphy_set_interrupt(struct phy_device *phydev)
112{
113 int temp;
114 temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
115 KSZPHY_INTCS_ALL : 0;
116 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
117}
118
119static int kszphy_config_intr(struct phy_device *phydev)
120{
121 int temp, rc;
122
123 /* set the interrupt pin active low */
124 temp = phy_read(phydev, MII_KSZPHY_CTRL);
5bb8fc0d
JH		 125 if (temp < 0)
126 return temp;
51f932c4
CD		 127 temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
128 phy_write(phydev, MII_KSZPHY_CTRL, temp);
129 rc = kszphy_set_interrupt(phydev);
130 return rc < 0 ? rc : 0;
131}
132
133static int ksz9021_config_intr(struct phy_device *phydev)
134{
135 int temp, rc;
136
137 /* set the interrupt pin active low */
138 temp = phy_read(phydev, MII_KSZPHY_CTRL);
5bb8fc0d
JH		 139 if (temp < 0)
140 return temp;
51f932c4
CD		 141 temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
142 phy_write(phydev, MII_KSZPHY_CTRL, temp);
143 rc = kszphy_set_interrupt(phydev);
144 return rc < 0 ? rc : 0;
145}
146
147static int ks8737_config_intr(struct phy_device *phydev)
148{
149 int temp, rc;
150
151 /* set the interrupt pin active low */
152 temp = phy_read(phydev, MII_KSZPHY_CTRL);
5bb8fc0d
JH		 153 if (temp < 0)
154 return temp;
51f932c4
CD		 155 temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
156 phy_write(phydev, MII_KSZPHY_CTRL, temp);
157 rc = kszphy_set_interrupt(phydev);
158 return rc < 0 ? rc : 0;
159}
d0507009 160
20d8435a
BD		 161static int kszphy_setup_led(struct phy_device *phydev,
162 unsigned int reg, unsigned int shift)
163{
164
165 struct device *dev = &phydev->dev;
166 struct device_node *of_node = dev->of_node;
167 int rc, temp;
168 u32 val;
169
170 if (!of_node && dev->parent->of_node)
171 of_node = dev->parent->of_node;
172
173 if (of_property_read_u32(of_node, "micrel,led-mode", &val))
174 return 0;
175
176 temp = phy_read(phydev, reg);
177 if (temp < 0)
178 return temp;
179
28bdc499 180 temp &= ~(3 << shift);
20d8435a
BD		 181 temp |= val << shift;
182 rc = phy_write(phydev, reg, temp);
183
184 return rc < 0 ? rc : 0;
185}
186
bde15129
JH		 187/* Disable PHY address 0 as the broadcast address, so that it can be used as a
188 * unique (non-broadcast) address on a shared bus.
189 */
190static int kszphy_broadcast_disable(struct phy_device *phydev)
191{
192 int ret;
193
194 ret = phy_read(phydev, MII_KSZPHY_OMSO);
195 if (ret < 0)
196 goto out;
197
198 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
199out:
200 if (ret)
201 dev_err(&phydev->dev, "failed to disable broadcast address\n");
202
203 return ret;
204}
205
d0507009
DC		 206static int kszphy_config_init(struct phy_device *phydev)
207{
208 return 0;
209}
210
20d8435a
BD		 211static int kszphy_config_init_led8041(struct phy_device *phydev)
212{
213 /* single led control, register 0x1e bits 15..14 */
214 return kszphy_setup_led(phydev, 0x1e, 14);
215}
216
212ea99a
MV		 217static int ksz8021_config_init(struct phy_device *phydev)
218{
20d8435a
BD		 219 int rc;
220
221 rc = kszphy_setup_led(phydev, 0x1f, 4);
222 if (rc)
223 dev_err(&phydev->dev, "failed to set led mode\n");
224
b6bb4dfc 225 rc = ksz_config_flags(phydev);
b838b4ac
BT		 226 if (rc < 0)
227 return rc;
bde15129
JH		 228
229 rc = kszphy_broadcast_disable(phydev);
230
b6bb4dfc 231 return rc < 0 ? rc : 0;
212ea99a
MV		 232}
233
d606ef3f
BS		 234static int ks8051_config_init(struct phy_device *phydev)
235{
b6bb4dfc 236 int rc;
d606ef3f 237
20d8435a
BD		 238 rc = kszphy_setup_led(phydev, 0x1f, 4);
239 if (rc)
240 dev_err(&phydev->dev, "failed to set led mode\n");
241
b6bb4dfc
HP		 242 rc = ksz_config_flags(phydev);
243 return rc < 0 ? rc : 0;
d606ef3f
BS		 244}
245
57a38eff
JH		 246static int ksz8081_config_init(struct phy_device *phydev)
247{
248 kszphy_broadcast_disable(phydev);
249
250 return 0;
251}
252
954c3967
SC		 253static int ksz9021_load_values_from_of(struct phy_device *phydev,
254 struct device_node *of_node, u16 reg,
255 char *field1, char *field2,
256 char *field3, char *field4)
257{
258 int val1 = -1;
259 int val2 = -2;
260 int val3 = -3;
261 int val4 = -4;
262 int newval;
263 int matches = 0;
264
265 if (!of_property_read_u32(of_node, field1, &val1))
266 matches++;
267
268 if (!of_property_read_u32(of_node, field2, &val2))
269 matches++;
270
271 if (!of_property_read_u32(of_node, field3, &val3))
272 matches++;
273
274 if (!of_property_read_u32(of_node, field4, &val4))
275 matches++;
276
277 if (!matches)
278 return 0;
279
280 if (matches < 4)
281 newval = kszphy_extended_read(phydev, reg);
282 else
283 newval = 0;
284
285 if (val1 != -1)
286 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
287
6a119745 288 if (val2 != -2)
954c3967
SC		 289 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
290
6a119745 291 if (val3 != -3)
954c3967
SC		 292 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
293
6a119745 294 if (val4 != -4)
954c3967
SC		 295 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
296
297 return kszphy_extended_write(phydev, reg, newval);
298}
299
300static int ksz9021_config_init(struct phy_device *phydev)
301{
302 struct device *dev = &phydev->dev;
303 struct device_node *of_node = dev->of_node;
304
305 if (!of_node && dev->parent->of_node)
306 of_node = dev->parent->of_node;
307
308 if (of_node) {
309 ksz9021_load_values_from_of(phydev, of_node,
310 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
311 "txen-skew-ps", "txc-skew-ps",
312 "rxdv-skew-ps", "rxc-skew-ps");
313 ksz9021_load_values_from_of(phydev, of_node,
314 MII_KSZPHY_RX_DATA_PAD_SKEW,
315 "rxd0-skew-ps", "rxd1-skew-ps",
316 "rxd2-skew-ps", "rxd3-skew-ps");
317 ksz9021_load_values_from_of(phydev, of_node,
318 MII_KSZPHY_TX_DATA_PAD_SKEW,
319 "txd0-skew-ps", "txd1-skew-ps",
320 "txd2-skew-ps", "txd3-skew-ps");
321 }
322 return 0;
323}
324
6e4b8273
HC		 325#define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
326#define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
327#define OP_DATA 1
328#define KSZ9031_PS_TO_REG 60
329
330/* Extended registers */
331#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
332#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
333#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
334#define MII_KSZ9031RN_CLK_PAD_SKEW 8
335
336static int ksz9031_extended_write(struct phy_device *phydev,
337 u8 mode, u32 dev_addr, u32 regnum, u16 val)
338{
339 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
340 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
341 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
342 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
343}
344
345static int ksz9031_extended_read(struct phy_device *phydev,
346 u8 mode, u32 dev_addr, u32 regnum)
347{
348 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
349 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
350 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
351 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
352}
353
354static int ksz9031_of_load_skew_values(struct phy_device *phydev,
355 struct device_node *of_node,
356 u16 reg, size_t field_sz,
357 char *field[], u8 numfields)
358{
359 int val[4] = {-1, -2, -3, -4};
360 int matches = 0;
361 u16 mask;
362 u16 maxval;
363 u16 newval;
364 int i;
365
366 for (i = 0; i < numfields; i++)
367 if (!of_property_read_u32(of_node, field[i], val + i))
368 matches++;
369
370 if (!matches)
371 return 0;
372
373 if (matches < numfields)
374 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
375 else
376 newval = 0;
377
378 maxval = (field_sz == 4) ? 0xf : 0x1f;
379 for (i = 0; i < numfields; i++)
380 if (val[i] != -(i + 1)) {
381 mask = 0xffff;
382 mask ^= maxval << (field_sz * i);
383 newval = (newval & mask) |
384 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
385 << (field_sz * i));
386 }
387
388 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
389}
390
391static int ksz9031_config_init(struct phy_device *phydev)
392{
393 struct device *dev = &phydev->dev;
394 struct device_node *of_node = dev->of_node;
395 char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
396 char *rx_data_skews[4] = {
397 "rxd0-skew-ps", "rxd1-skew-ps",
398 "rxd2-skew-ps", "rxd3-skew-ps"
399 };
400 char *tx_data_skews[4] = {
401 "txd0-skew-ps", "txd1-skew-ps",
402 "txd2-skew-ps", "txd3-skew-ps"
403 };
404 char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
405
406 if (!of_node && dev->parent->of_node)
407 of_node = dev->parent->of_node;
408
409 if (of_node) {
410 ksz9031_of_load_skew_values(phydev, of_node,
411 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
412 clk_skews, 2);
413
414 ksz9031_of_load_skew_values(phydev, of_node,
415 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
416 control_skews, 2);
417
418 ksz9031_of_load_skew_values(phydev, of_node,
419 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
420 rx_data_skews, 4);
421
422 ksz9031_of_load_skew_values(phydev, of_node,
423 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
424 tx_data_skews, 4);
425 }
426 return 0;
427}
428
93272e07 429#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
00aee095
JH		 430#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
431#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
32d73b14 432static int ksz8873mll_read_status(struct phy_device *phydev)
93272e07
JCPV		 433{
434 int regval;
435
436 /* dummy read */
437 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
438
439 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
440
441 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
442 phydev->duplex = DUPLEX_HALF;
443 else
444 phydev->duplex = DUPLEX_FULL;
445
446 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
447 phydev->speed = SPEED_10;
448 else
449 phydev->speed = SPEED_100;
450
451 phydev->link = 1;
452 phydev->pause = phydev->asym_pause = 0;
453
454 return 0;
455}
456
457static int ksz8873mll_config_aneg(struct phy_device *phydev)
458{
459 return 0;
460}
461
19936942
VB		 462/* This routine returns -1 as an indication to the caller that the
463 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
464 * MMD extended PHY registers.
465 */
466static int
467ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
468 int regnum)
469{
470 return -1;
471}
472
473/* This routine does nothing since the Micrel ksz9021 does not support
474 * standard IEEE MMD extended PHY registers.
475 */
476static void
477ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
478 int regnum, u32 val)
479{
480}
481
1fadee0c
SH		 482static int ksz8021_probe(struct phy_device *phydev)
483{
484 struct clk *clk;
485
486 clk = devm_clk_get(&phydev->dev, "rmii-ref");
487 if (!IS_ERR(clk)) {
488 unsigned long rate = clk_get_rate(clk);
489
490 if (rate > 24500000 && rate < 25500000) {
491 phydev->dev_flags |= MICREL_PHY_25MHZ_CLK;
492 } else if (rate > 49500000 && rate < 50500000) {
493 phydev->dev_flags |= MICREL_PHY_50MHZ_CLK;
494 } else {
495 dev_err(&phydev->dev, "Clock rate out of range: %ld\n", rate);
496 return -EINVAL;
497 }
498 }
499
500 return 0;
501}
502
d5bf9071
CH		 503static struct phy_driver ksphy_driver[] = {
504{
51f932c4
CD		 505 .phy_id = PHY_ID_KS8737,
506 .phy_id_mask = 0x00fffff0,
507 .name = "Micrel KS8737",
508 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
509 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
510 .config_init = kszphy_config_init,
511 .config_aneg = genphy_config_aneg,
512 .read_status = genphy_read_status,
513 .ack_interrupt = kszphy_ack_interrupt,
514 .config_intr = ks8737_config_intr,
1a5465f5
PV		 515 .suspend = genphy_suspend,
516 .resume = genphy_resume,
51f932c4 517 .driver = { .owner = THIS_MODULE,},
212ea99a
MV		 518}, {
519 .phy_id = PHY_ID_KSZ8021,
520 .phy_id_mask = 0x00ffffff,
7ab59dc1 521 .name = "Micrel KSZ8021 or KSZ8031",
212ea99a
MV		 522 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
523 SUPPORTED_Asym_Pause),
524 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
1fadee0c 525 .probe = ksz8021_probe,
212ea99a
MV		 526 .config_init = ksz8021_config_init,
527 .config_aneg = genphy_config_aneg,
528 .read_status = genphy_read_status,
529 .ack_interrupt = kszphy_ack_interrupt,
530 .config_intr = kszphy_config_intr,
1a5465f5
PV		 531 .suspend = genphy_suspend,
532 .resume = genphy_resume,
212ea99a 533 .driver = { .owner = THIS_MODULE,},
b818d1a7
HP		 534}, {
535 .phy_id = PHY_ID_KSZ8031,
536 .phy_id_mask = 0x00ffffff,
537 .name = "Micrel KSZ8031",
538 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
539 SUPPORTED_Asym_Pause),
540 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
1fadee0c 541 .probe = ksz8021_probe,
b818d1a7
HP		 542 .config_init = ksz8021_config_init,
543 .config_aneg = genphy_config_aneg,
544 .read_status = genphy_read_status,
545 .ack_interrupt = kszphy_ack_interrupt,
546 .config_intr = kszphy_config_intr,
1a5465f5
PV		 547 .suspend = genphy_suspend,
548 .resume = genphy_resume,
b818d1a7 549 .driver = { .owner = THIS_MODULE,},
d5bf9071 550}, {
510d573f 551 .phy_id = PHY_ID_KSZ8041,
51f932c4 552 .phy_id_mask = 0x00fffff0,
510d573f 553 .name = "Micrel KSZ8041",
51f932c4
CD		 554 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
555 | SUPPORTED_Asym_Pause),
556 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
20d8435a 557 .config_init = kszphy_config_init_led8041,
51f932c4
CD		 558 .config_aneg = genphy_config_aneg,
559 .read_status = genphy_read_status,
560 .ack_interrupt = kszphy_ack_interrupt,
561 .config_intr = kszphy_config_intr,
1a5465f5
PV		 562 .suspend = genphy_suspend,
563 .resume = genphy_resume,
51f932c4 564 .driver = { .owner = THIS_MODULE,},
4bd7b512
SS		 565}, {
566 .phy_id = PHY_ID_KSZ8041RNLI,
567 .phy_id_mask = 0x00fffff0,
568 .name = "Micrel KSZ8041RNLI",
569 .features = PHY_BASIC_FEATURES |
570 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
571 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
20d8435a 572 .config_init = kszphy_config_init_led8041,
4bd7b512
SS		 573 .config_aneg = genphy_config_aneg,
574 .read_status = genphy_read_status,
575 .ack_interrupt = kszphy_ack_interrupt,
576 .config_intr = kszphy_config_intr,
577 .suspend = genphy_suspend,
578 .resume = genphy_resume,
579 .driver = { .owner = THIS_MODULE,},
d5bf9071 580}, {
510d573f 581 .phy_id = PHY_ID_KSZ8051,
d0507009 582 .phy_id_mask = 0x00fffff0,
510d573f 583 .name = "Micrel KSZ8051",
51f932c4
CD		 584 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
585 | SUPPORTED_Asym_Pause),
586 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
d606ef3f 587 .config_init = ks8051_config_init,
d0507009
DC		 588 .config_aneg = genphy_config_aneg,
589 .read_status = genphy_read_status,
51f932c4
CD		 590 .ack_interrupt = kszphy_ack_interrupt,
591 .config_intr = kszphy_config_intr,
1a5465f5
PV		 592 .suspend = genphy_suspend,
593 .resume = genphy_resume,
d0507009 594 .driver = { .owner = THIS_MODULE,},
d5bf9071 595}, {
510d573f
MV		 596 .phy_id = PHY_ID_KSZ8001,
597 .name = "Micrel KSZ8001 or KS8721",
48d7d0ad 598 .phy_id_mask = 0x00ffffff,
51f932c4
CD		 599 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
600 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
20d8435a 601 .config_init = kszphy_config_init_led8041,
d0507009
DC		 602 .config_aneg = genphy_config_aneg,
603 .read_status = genphy_read_status,
51f932c4
CD		 604 .ack_interrupt = kszphy_ack_interrupt,
605 .config_intr = kszphy_config_intr,
1a5465f5
PV		 606 .suspend = genphy_suspend,
607 .resume = genphy_resume,
d0507009 608 .driver = { .owner = THIS_MODULE,},
7ab59dc1
DC		 609}, {
610 .phy_id = PHY_ID_KSZ8081,
611 .name = "Micrel KSZ8081 or KSZ8091",
612 .phy_id_mask = 0x00fffff0,
613 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
614 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
57a38eff 615 .config_init = ksz8081_config_init,
7ab59dc1
DC		 616 .config_aneg = genphy_config_aneg,
617 .read_status = genphy_read_status,
618 .ack_interrupt = kszphy_ack_interrupt,
619 .config_intr = kszphy_config_intr,
1a5465f5
PV		 620 .suspend = genphy_suspend,
621 .resume = genphy_resume,
7ab59dc1
DC		 622 .driver = { .owner = THIS_MODULE,},
623}, {
624 .phy_id = PHY_ID_KSZ8061,
625 .name = "Micrel KSZ8061",
626 .phy_id_mask = 0x00fffff0,
627 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
628 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
629 .config_init = kszphy_config_init,
630 .config_aneg = genphy_config_aneg,
631 .read_status = genphy_read_status,
632 .ack_interrupt = kszphy_ack_interrupt,
633 .config_intr = kszphy_config_intr,
1a5465f5
PV		 634 .suspend = genphy_suspend,
635 .resume = genphy_resume,
7ab59dc1 636 .driver = { .owner = THIS_MODULE,},
d5bf9071 637}, {
d0507009 638 .phy_id = PHY_ID_KSZ9021,
48d7d0ad 639 .phy_id_mask = 0x000ffffe,
d0507009 640 .name = "Micrel KSZ9021 Gigabit PHY",
32fcafbc 641 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
51f932c4 642 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
954c3967 643 .config_init = ksz9021_config_init,
d0507009
DC		 644 .config_aneg = genphy_config_aneg,
645 .read_status = genphy_read_status,
51f932c4
CD		 646 .ack_interrupt = kszphy_ack_interrupt,
647 .config_intr = ksz9021_config_intr,
1a5465f5
PV		 648 .suspend = genphy_suspend,
649 .resume = genphy_resume,
19936942
VB		 650 .read_mmd_indirect = ksz9021_rd_mmd_phyreg,
651 .write_mmd_indirect = ksz9021_wr_mmd_phyreg,
d0507009 652 .driver = { .owner = THIS_MODULE, },
7ab59dc1
DC		 653}, {
654 .phy_id = PHY_ID_KSZ9031,
655 .phy_id_mask = 0x00fffff0,
656 .name = "Micrel KSZ9031 Gigabit PHY",
95e8b103 657 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
7ab59dc1 658 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
6e4b8273 659 .config_init = ksz9031_config_init,
7ab59dc1
DC		 660 .config_aneg = genphy_config_aneg,
661 .read_status = genphy_read_status,
662 .ack_interrupt = kszphy_ack_interrupt,
663 .config_intr = ksz9021_config_intr,
1a5465f5
PV		 664 .suspend = genphy_suspend,
665 .resume = genphy_resume,
7ab59dc1 666 .driver = { .owner = THIS_MODULE, },
93272e07
JCPV		 667}, {
668 .phy_id = PHY_ID_KSZ8873MLL,
669 .phy_id_mask = 0x00fffff0,
670 .name = "Micrel KSZ8873MLL Switch",
671 .features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
672 .flags = PHY_HAS_MAGICANEG,
673 .config_init = kszphy_config_init,
674 .config_aneg = ksz8873mll_config_aneg,
675 .read_status = ksz8873mll_read_status,
1a5465f5
PV		 676 .suspend = genphy_suspend,
677 .resume = genphy_resume,
93272e07 678 .driver = { .owner = THIS_MODULE, },
7ab59dc1
DC		 679}, {
680 .phy_id = PHY_ID_KSZ886X,
681 .phy_id_mask = 0x00fffff0,
682 .name = "Micrel KSZ886X Switch",
683 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
684 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
685 .config_init = kszphy_config_init,
686 .config_aneg = genphy_config_aneg,
687 .read_status = genphy_read_status,
1a5465f5
PV		 688 .suspend = genphy_suspend,
689 .resume = genphy_resume,
7ab59dc1 690 .driver = { .owner = THIS_MODULE, },
d5bf9071 691} };
d0507009 692
50fd7150 693module_phy_driver(ksphy_driver);
d0507009
DC		 694
695MODULE_DESCRIPTION("Micrel PHY driver");
696MODULE_AUTHOR("David J. Choi");
697MODULE_LICENSE("GPL");
52a60ed2 698
cf93c945 699static struct mdio_device_id __maybe_unused micrel_tbl[] = {
48d7d0ad 700 { PHY_ID_KSZ9021, 0x000ffffe },
7ab59dc1 701 { PHY_ID_KSZ9031, 0x00fffff0 },
510d573f 702 { PHY_ID_KSZ8001, 0x00ffffff },
51f932c4 703 { PHY_ID_KS8737, 0x00fffff0 },
212ea99a 704 { PHY_ID_KSZ8021, 0x00ffffff },
b818d1a7 705 { PHY_ID_KSZ8031, 0x00ffffff },
510d573f
MV		 706 { PHY_ID_KSZ8041, 0x00fffff0 },
707 { PHY_ID_KSZ8051, 0x00fffff0 },
7ab59dc1
DC		 708 { PHY_ID_KSZ8061, 0x00fffff0 },
709 { PHY_ID_KSZ8081, 0x00fffff0 },
93272e07 710 { PHY_ID_KSZ8873MLL, 0x00fffff0 },
7ab59dc1 711 { PHY_ID_KSZ886X, 0x00fffff0 },
52a60ed2
DM		 712 { }
713};
714
715MODULE_DEVICE_TABLE(mdio, micrel_tbl);
Linux kernel - Deliverables
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