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net: phy: micrel: enable led-mode for KSZ8081/KSZ8091
[deliverable/linux.git] / drivers / net / phy / micrel.c
CommitLineData
d0507009
DC		 1/*
2 * drivers/net/phy/micrel.c
3 *
4 * Driver for Micrel PHYs
5 *
6 * Author: David J. Choi
7 *
7ab59dc1 8 * Copyright (c) 2010-2013 Micrel, Inc.
d0507009
DC		 9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
7ab59dc1
DC		 15 * Support : Micrel Phys:
16 * Giga phys: ksz9021, ksz9031
17 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
18 * ksz8021, ksz8031, ksz8051,
19 * ksz8081, ksz8091,
20 * ksz8061,
21 * Switch : ksz8873, ksz886x
d0507009
DC		 22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/phy.h>
d606ef3f 27#include <linux/micrel_phy.h>
954c3967 28#include <linux/of.h>
1fadee0c 29#include <linux/clk.h>
d0507009 30
212ea99a
MV		 31/* Operation Mode Strap Override */
32#define MII_KSZPHY_OMSO 0x16
00aee095
JH		 33#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
34#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
35#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
212ea99a 36
51f932c4
CD		 37/* general Interrupt control/status reg in vendor specific block. */
38#define MII_KSZPHY_INTCS 0x1B
00aee095
JH		 39#define KSZPHY_INTCS_JABBER BIT(15)
40#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
41#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
42#define KSZPHY_INTCS_PARELLEL BIT(12)
43#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
44#define KSZPHY_INTCS_LINK_DOWN BIT(10)
45#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
46#define KSZPHY_INTCS_LINK_UP BIT(8)
51f932c4
CD		 47#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
48 KSZPHY_INTCS_LINK_DOWN)
49
5a16778e
JH		 50/* PHY Control 1 */
51#define MII_KSZPHY_CTRL_1 0x1e
52
53/* PHY Control 2 / PHY Control (if no PHY Control 1) */
54#define MII_KSZPHY_CTRL_2 0x1f
55#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
51f932c4 56/* bitmap of PHY register to set interrupt mode */
00aee095
JH		 57#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
58#define KSZ9021_CTRL_INT_ACTIVE_HIGH BIT(14)
59#define KS8737_CTRL_INT_ACTIVE_HIGH BIT(14)
60#define KSZ8051_RMII_50MHZ_CLK BIT(7)
51f932c4 61
954c3967
SC		 62/* Write/read to/from extended registers */
63#define MII_KSZPHY_EXTREG 0x0b
64#define KSZPHY_EXTREG_WRITE 0x8000
65
66#define MII_KSZPHY_EXTREG_WRITE 0x0c
67#define MII_KSZPHY_EXTREG_READ 0x0d
68
69/* Extended registers */
70#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
71#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
72#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
73
74#define PS_TO_REG 200
75
b6bb4dfc
HP		 76static int ksz_config_flags(struct phy_device *phydev)
77{
78 int regval;
79
1fadee0c 80 if (phydev->dev_flags & (MICREL_PHY_50MHZ_CLK | MICREL_PHY_25MHZ_CLK)) {
b6bb4dfc 81 regval = phy_read(phydev, MII_KSZPHY_CTRL);
1fadee0c
SH		 82 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK)
83 regval |= KSZ8051_RMII_50MHZ_CLK;
84 else
85 regval &= ~KSZ8051_RMII_50MHZ_CLK;
b6bb4dfc
HP		 86 return phy_write(phydev, MII_KSZPHY_CTRL, regval);
87 }
88 return 0;
89}
90
954c3967 91static int kszphy_extended_write(struct phy_device *phydev,
756b5089 92 u32 regnum, u16 val)
954c3967
SC		 93{
94 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
95 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
96}
97
98static int kszphy_extended_read(struct phy_device *phydev,
756b5089 99 u32 regnum)
954c3967
SC		 100{
101 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
102 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
103}
104
51f932c4
CD		 105static int kszphy_ack_interrupt(struct phy_device *phydev)
106{
107 /* bit[7..0] int status, which is a read and clear register. */
108 int rc;
109
110 rc = phy_read(phydev, MII_KSZPHY_INTCS);
111
112 return (rc < 0) ? rc : 0;
113}
114
115static int kszphy_set_interrupt(struct phy_device *phydev)
116{
117 int temp;
118 temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
119 KSZPHY_INTCS_ALL : 0;
120 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
121}
122
123static int kszphy_config_intr(struct phy_device *phydev)
124{
125 int temp, rc;
126
127 /* set the interrupt pin active low */
128 temp = phy_read(phydev, MII_KSZPHY_CTRL);
5bb8fc0d
JH		 129 if (temp < 0)
130 return temp;
51f932c4
CD		 131 temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
132 phy_write(phydev, MII_KSZPHY_CTRL, temp);
133 rc = kszphy_set_interrupt(phydev);
134 return rc < 0 ? rc : 0;
135}
136
137static int ksz9021_config_intr(struct phy_device *phydev)
138{
139 int temp, rc;
140
141 /* set the interrupt pin active low */
142 temp = phy_read(phydev, MII_KSZPHY_CTRL);
5bb8fc0d
JH		 143 if (temp < 0)
144 return temp;
51f932c4
CD		 145 temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
146 phy_write(phydev, MII_KSZPHY_CTRL, temp);
147 rc = kszphy_set_interrupt(phydev);
148 return rc < 0 ? rc : 0;
149}
150
151static int ks8737_config_intr(struct phy_device *phydev)
152{
153 int temp, rc;
154
155 /* set the interrupt pin active low */
156 temp = phy_read(phydev, MII_KSZPHY_CTRL);
5bb8fc0d
JH		 157 if (temp < 0)
158 return temp;
51f932c4
CD		 159 temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
160 phy_write(phydev, MII_KSZPHY_CTRL, temp);
161 rc = kszphy_set_interrupt(phydev);
162 return rc < 0 ? rc : 0;
163}
d0507009 164
5a16778e 165static int kszphy_setup_led(struct phy_device *phydev, u32 reg)
20d8435a
BD		 166{
167
168 struct device *dev = &phydev->dev;
169 struct device_node *of_node = dev->of_node;
5a16778e 170 int rc, temp, shift;
20d8435a
BD		 171 u32 val;
172
173 if (!of_node && dev->parent->of_node)
174 of_node = dev->parent->of_node;
175
176 if (of_property_read_u32(of_node, "micrel,led-mode", &val))
177 return 0;
178
8620546c
JH		 179 if (val > 3) {
180 dev_err(&phydev->dev, "invalid led mode: 0x%02x\n", val);
181 return -EINVAL;
182 }
183
5a16778e
JH		 184 switch (reg) {
185 case MII_KSZPHY_CTRL_1:
186 shift = 14;
187 break;
188 case MII_KSZPHY_CTRL_2:
189 shift = 4;
190 break;
191 default:
192 return -EINVAL;
193 }
194
20d8435a 195 temp = phy_read(phydev, reg);
b7035860
JH		 196 if (temp < 0) {
197 rc = temp;
198 goto out;
199 }
20d8435a 200
28bdc499 201 temp &= ~(3 << shift);
20d8435a
BD		 202 temp |= val << shift;
203 rc = phy_write(phydev, reg, temp);
b7035860
JH		 204out:
205 if (rc < 0)
206 dev_err(&phydev->dev, "failed to set led mode\n");
20d8435a 207
b7035860 208 return rc;
20d8435a
BD		 209}
210
bde15129
JH		 211/* Disable PHY address 0 as the broadcast address, so that it can be used as a
212 * unique (non-broadcast) address on a shared bus.
213 */
214static int kszphy_broadcast_disable(struct phy_device *phydev)
215{
216 int ret;
217
218 ret = phy_read(phydev, MII_KSZPHY_OMSO);
219 if (ret < 0)
220 goto out;
221
222 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
223out:
224 if (ret)
225 dev_err(&phydev->dev, "failed to disable broadcast address\n");
226
227 return ret;
228}
229
d0507009
DC		 230static int kszphy_config_init(struct phy_device *phydev)
231{
232 return 0;
233}
234
20d8435a
BD		 235static int kszphy_config_init_led8041(struct phy_device *phydev)
236{
5a16778e 237 return kszphy_setup_led(phydev, MII_KSZPHY_CTRL_1);
20d8435a
BD		 238}
239
212ea99a
MV		 240static int ksz8021_config_init(struct phy_device *phydev)
241{
20d8435a
BD		 242 int rc;
243
5a16778e 244 kszphy_setup_led(phydev, MII_KSZPHY_CTRL_2);
20d8435a 245
b6bb4dfc 246 rc = ksz_config_flags(phydev);
b838b4ac
BT		 247 if (rc < 0)
248 return rc;
bde15129
JH		 249
250 rc = kszphy_broadcast_disable(phydev);
251
b6bb4dfc 252 return rc < 0 ? rc : 0;
212ea99a
MV		 253}
254
d606ef3f
BS		 255static int ks8051_config_init(struct phy_device *phydev)
256{
b6bb4dfc 257 int rc;
d606ef3f 258
5a16778e 259 kszphy_setup_led(phydev, MII_KSZPHY_CTRL_2);
20d8435a 260
b6bb4dfc
HP		 261 rc = ksz_config_flags(phydev);
262 return rc < 0 ? rc : 0;
d606ef3f
BS		 263}
264
57a38eff
JH		 265static int ksz8081_config_init(struct phy_device *phydev)
266{
267 kszphy_broadcast_disable(phydev);
7b52314c 268 kszphy_setup_led(phydev, MII_KSZPHY_CTRL_2);
57a38eff
JH		 269
270 return 0;
271}
272
954c3967
SC		 273static int ksz9021_load_values_from_of(struct phy_device *phydev,
274 struct device_node *of_node, u16 reg,
275 char *field1, char *field2,
276 char *field3, char *field4)
277{
278 int val1 = -1;
279 int val2 = -2;
280 int val3 = -3;
281 int val4 = -4;
282 int newval;
283 int matches = 0;
284
285 if (!of_property_read_u32(of_node, field1, &val1))
286 matches++;
287
288 if (!of_property_read_u32(of_node, field2, &val2))
289 matches++;
290
291 if (!of_property_read_u32(of_node, field3, &val3))
292 matches++;
293
294 if (!of_property_read_u32(of_node, field4, &val4))
295 matches++;
296
297 if (!matches)
298 return 0;
299
300 if (matches < 4)
301 newval = kszphy_extended_read(phydev, reg);
302 else
303 newval = 0;
304
305 if (val1 != -1)
306 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
307
6a119745 308 if (val2 != -2)
954c3967
SC		 309 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
310
6a119745 311 if (val3 != -3)
954c3967
SC		 312 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
313
6a119745 314 if (val4 != -4)
954c3967
SC		 315 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
316
317 return kszphy_extended_write(phydev, reg, newval);
318}
319
320static int ksz9021_config_init(struct phy_device *phydev)
321{
322 struct device *dev = &phydev->dev;
323 struct device_node *of_node = dev->of_node;
324
325 if (!of_node && dev->parent->of_node)
326 of_node = dev->parent->of_node;
327
328 if (of_node) {
329 ksz9021_load_values_from_of(phydev, of_node,
330 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
331 "txen-skew-ps", "txc-skew-ps",
332 "rxdv-skew-ps", "rxc-skew-ps");
333 ksz9021_load_values_from_of(phydev, of_node,
334 MII_KSZPHY_RX_DATA_PAD_SKEW,
335 "rxd0-skew-ps", "rxd1-skew-ps",
336 "rxd2-skew-ps", "rxd3-skew-ps");
337 ksz9021_load_values_from_of(phydev, of_node,
338 MII_KSZPHY_TX_DATA_PAD_SKEW,
339 "txd0-skew-ps", "txd1-skew-ps",
340 "txd2-skew-ps", "txd3-skew-ps");
341 }
342 return 0;
343}
344
6e4b8273
HC		 345#define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
346#define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
347#define OP_DATA 1
348#define KSZ9031_PS_TO_REG 60
349
350/* Extended registers */
351#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
352#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
353#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
354#define MII_KSZ9031RN_CLK_PAD_SKEW 8
355
356static int ksz9031_extended_write(struct phy_device *phydev,
357 u8 mode, u32 dev_addr, u32 regnum, u16 val)
358{
359 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
360 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
361 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
362 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
363}
364
365static int ksz9031_extended_read(struct phy_device *phydev,
366 u8 mode, u32 dev_addr, u32 regnum)
367{
368 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
369 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
370 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
371 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
372}
373
374static int ksz9031_of_load_skew_values(struct phy_device *phydev,
375 struct device_node *of_node,
376 u16 reg, size_t field_sz,
377 char *field[], u8 numfields)
378{
379 int val[4] = {-1, -2, -3, -4};
380 int matches = 0;
381 u16 mask;
382 u16 maxval;
383 u16 newval;
384 int i;
385
386 for (i = 0; i < numfields; i++)
387 if (!of_property_read_u32(of_node, field[i], val + i))
388 matches++;
389
390 if (!matches)
391 return 0;
392
393 if (matches < numfields)
394 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
395 else
396 newval = 0;
397
398 maxval = (field_sz == 4) ? 0xf : 0x1f;
399 for (i = 0; i < numfields; i++)
400 if (val[i] != -(i + 1)) {
401 mask = 0xffff;
402 mask ^= maxval << (field_sz * i);
403 newval = (newval & mask) |
404 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
405 << (field_sz * i));
406 }
407
408 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
409}
410
411static int ksz9031_config_init(struct phy_device *phydev)
412{
413 struct device *dev = &phydev->dev;
414 struct device_node *of_node = dev->of_node;
415 char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
416 char *rx_data_skews[4] = {
417 "rxd0-skew-ps", "rxd1-skew-ps",
418 "rxd2-skew-ps", "rxd3-skew-ps"
419 };
420 char *tx_data_skews[4] = {
421 "txd0-skew-ps", "txd1-skew-ps",
422 "txd2-skew-ps", "txd3-skew-ps"
423 };
424 char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
425
426 if (!of_node && dev->parent->of_node)
427 of_node = dev->parent->of_node;
428
429 if (of_node) {
430 ksz9031_of_load_skew_values(phydev, of_node,
431 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
432 clk_skews, 2);
433
434 ksz9031_of_load_skew_values(phydev, of_node,
435 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
436 control_skews, 2);
437
438 ksz9031_of_load_skew_values(phydev, of_node,
439 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
440 rx_data_skews, 4);
441
442 ksz9031_of_load_skew_values(phydev, of_node,
443 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
444 tx_data_skews, 4);
445 }
446 return 0;
447}
448
93272e07 449#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
00aee095
JH		 450#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
451#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
32d73b14 452static int ksz8873mll_read_status(struct phy_device *phydev)
93272e07
JCPV		 453{
454 int regval;
455
456 /* dummy read */
457 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
458
459 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
460
461 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
462 phydev->duplex = DUPLEX_HALF;
463 else
464 phydev->duplex = DUPLEX_FULL;
465
466 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
467 phydev->speed = SPEED_10;
468 else
469 phydev->speed = SPEED_100;
470
471 phydev->link = 1;
472 phydev->pause = phydev->asym_pause = 0;
473
474 return 0;
475}
476
477static int ksz8873mll_config_aneg(struct phy_device *phydev)
478{
479 return 0;
480}
481
19936942
VB		 482/* This routine returns -1 as an indication to the caller that the
483 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
484 * MMD extended PHY registers.
485 */
486static int
487ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
488 int regnum)
489{
490 return -1;
491}
492
493/* This routine does nothing since the Micrel ksz9021 does not support
494 * standard IEEE MMD extended PHY registers.
495 */
496static void
497ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
498 int regnum, u32 val)
499{
500}
501
1fadee0c
SH		 502static int ksz8021_probe(struct phy_device *phydev)
503{
504 struct clk *clk;
505
506 clk = devm_clk_get(&phydev->dev, "rmii-ref");
507 if (!IS_ERR(clk)) {
508 unsigned long rate = clk_get_rate(clk);
509
510 if (rate > 24500000 && rate < 25500000) {
511 phydev->dev_flags |= MICREL_PHY_25MHZ_CLK;
512 } else if (rate > 49500000 && rate < 50500000) {
513 phydev->dev_flags |= MICREL_PHY_50MHZ_CLK;
514 } else {
515 dev_err(&phydev->dev, "Clock rate out of range: %ld\n", rate);
516 return -EINVAL;
517 }
518 }
519
520 return 0;
521}
522
d5bf9071
CH		 523static struct phy_driver ksphy_driver[] = {
524{
51f932c4
CD		 525 .phy_id = PHY_ID_KS8737,
526 .phy_id_mask = 0x00fffff0,
527 .name = "Micrel KS8737",
528 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
529 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
530 .config_init = kszphy_config_init,
531 .config_aneg = genphy_config_aneg,
532 .read_status = genphy_read_status,
533 .ack_interrupt = kszphy_ack_interrupt,
534 .config_intr = ks8737_config_intr,
1a5465f5
PV		 535 .suspend = genphy_suspend,
536 .resume = genphy_resume,
51f932c4 537 .driver = { .owner = THIS_MODULE,},
212ea99a
MV		 538}, {
539 .phy_id = PHY_ID_KSZ8021,
540 .phy_id_mask = 0x00ffffff,
7ab59dc1 541 .name = "Micrel KSZ8021 or KSZ8031",
212ea99a
MV		 542 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
543 SUPPORTED_Asym_Pause),
544 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
1fadee0c 545 .probe = ksz8021_probe,
212ea99a
MV		 546 .config_init = ksz8021_config_init,
547 .config_aneg = genphy_config_aneg,
548 .read_status = genphy_read_status,
549 .ack_interrupt = kszphy_ack_interrupt,
550 .config_intr = kszphy_config_intr,
1a5465f5
PV		 551 .suspend = genphy_suspend,
552 .resume = genphy_resume,
212ea99a 553 .driver = { .owner = THIS_MODULE,},
b818d1a7
HP		 554}, {
555 .phy_id = PHY_ID_KSZ8031,
556 .phy_id_mask = 0x00ffffff,
557 .name = "Micrel KSZ8031",
558 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
559 SUPPORTED_Asym_Pause),
560 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
1fadee0c 561 .probe = ksz8021_probe,
b818d1a7
HP		 562 .config_init = ksz8021_config_init,
563 .config_aneg = genphy_config_aneg,
564 .read_status = genphy_read_status,
565 .ack_interrupt = kszphy_ack_interrupt,
566 .config_intr = kszphy_config_intr,
1a5465f5
PV		 567 .suspend = genphy_suspend,
568 .resume = genphy_resume,
b818d1a7 569 .driver = { .owner = THIS_MODULE,},
d5bf9071 570}, {
510d573f 571 .phy_id = PHY_ID_KSZ8041,
51f932c4 572 .phy_id_mask = 0x00fffff0,
510d573f 573 .name = "Micrel KSZ8041",
51f932c4
CD		 574 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
575 | SUPPORTED_Asym_Pause),
576 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
20d8435a 577 .config_init = kszphy_config_init_led8041,
51f932c4
CD		 578 .config_aneg = genphy_config_aneg,
579 .read_status = genphy_read_status,
580 .ack_interrupt = kszphy_ack_interrupt,
581 .config_intr = kszphy_config_intr,
1a5465f5
PV		 582 .suspend = genphy_suspend,
583 .resume = genphy_resume,
51f932c4 584 .driver = { .owner = THIS_MODULE,},
4bd7b512
SS		 585}, {
586 .phy_id = PHY_ID_KSZ8041RNLI,
587 .phy_id_mask = 0x00fffff0,
588 .name = "Micrel KSZ8041RNLI",
589 .features = PHY_BASIC_FEATURES |
590 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
591 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
20d8435a 592 .config_init = kszphy_config_init_led8041,
4bd7b512
SS		 593 .config_aneg = genphy_config_aneg,
594 .read_status = genphy_read_status,
595 .ack_interrupt = kszphy_ack_interrupt,
596 .config_intr = kszphy_config_intr,
597 .suspend = genphy_suspend,
598 .resume = genphy_resume,
599 .driver = { .owner = THIS_MODULE,},
d5bf9071 600}, {
510d573f 601 .phy_id = PHY_ID_KSZ8051,
d0507009 602 .phy_id_mask = 0x00fffff0,
510d573f 603 .name = "Micrel KSZ8051",
51f932c4
CD		 604 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
605 | SUPPORTED_Asym_Pause),
606 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
d606ef3f 607 .config_init = ks8051_config_init,
d0507009
DC		 608 .config_aneg = genphy_config_aneg,
609 .read_status = genphy_read_status,
51f932c4
CD		 610 .ack_interrupt = kszphy_ack_interrupt,
611 .config_intr = kszphy_config_intr,
1a5465f5
PV		 612 .suspend = genphy_suspend,
613 .resume = genphy_resume,
d0507009 614 .driver = { .owner = THIS_MODULE,},
d5bf9071 615}, {
510d573f
MV		 616 .phy_id = PHY_ID_KSZ8001,
617 .name = "Micrel KSZ8001 or KS8721",
48d7d0ad 618 .phy_id_mask = 0x00ffffff,
51f932c4
CD		 619 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
620 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
20d8435a 621 .config_init = kszphy_config_init_led8041,
d0507009
DC		 622 .config_aneg = genphy_config_aneg,
623 .read_status = genphy_read_status,
51f932c4
CD		 624 .ack_interrupt = kszphy_ack_interrupt,
625 .config_intr = kszphy_config_intr,
1a5465f5
PV		 626 .suspend = genphy_suspend,
627 .resume = genphy_resume,
d0507009 628 .driver = { .owner = THIS_MODULE,},
7ab59dc1
DC		 629}, {
630 .phy_id = PHY_ID_KSZ8081,
631 .name = "Micrel KSZ8081 or KSZ8091",
632 .phy_id_mask = 0x00fffff0,
633 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
634 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
57a38eff 635 .config_init = ksz8081_config_init,
7ab59dc1
DC		 636 .config_aneg = genphy_config_aneg,
637 .read_status = genphy_read_status,
638 .ack_interrupt = kszphy_ack_interrupt,
639 .config_intr = kszphy_config_intr,
1a5465f5
PV		 640 .suspend = genphy_suspend,
641 .resume = genphy_resume,
7ab59dc1
DC		 642 .driver = { .owner = THIS_MODULE,},
643}, {
644 .phy_id = PHY_ID_KSZ8061,
645 .name = "Micrel KSZ8061",
646 .phy_id_mask = 0x00fffff0,
647 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
648 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
649 .config_init = kszphy_config_init,
650 .config_aneg = genphy_config_aneg,
651 .read_status = genphy_read_status,
652 .ack_interrupt = kszphy_ack_interrupt,
653 .config_intr = kszphy_config_intr,
1a5465f5
PV		 654 .suspend = genphy_suspend,
655 .resume = genphy_resume,
7ab59dc1 656 .driver = { .owner = THIS_MODULE,},
d5bf9071 657}, {
d0507009 658 .phy_id = PHY_ID_KSZ9021,
48d7d0ad 659 .phy_id_mask = 0x000ffffe,
d0507009 660 .name = "Micrel KSZ9021 Gigabit PHY",
32fcafbc 661 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
51f932c4 662 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
954c3967 663 .config_init = ksz9021_config_init,
d0507009
DC		 664 .config_aneg = genphy_config_aneg,
665 .read_status = genphy_read_status,
51f932c4
CD		 666 .ack_interrupt = kszphy_ack_interrupt,
667 .config_intr = ksz9021_config_intr,
1a5465f5
PV		 668 .suspend = genphy_suspend,
669 .resume = genphy_resume,
19936942
VB		 670 .read_mmd_indirect = ksz9021_rd_mmd_phyreg,
671 .write_mmd_indirect = ksz9021_wr_mmd_phyreg,
d0507009 672 .driver = { .owner = THIS_MODULE, },
7ab59dc1
DC		 673}, {
674 .phy_id = PHY_ID_KSZ9031,
675 .phy_id_mask = 0x00fffff0,
676 .name = "Micrel KSZ9031 Gigabit PHY",
95e8b103 677 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
7ab59dc1 678 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
6e4b8273 679 .config_init = ksz9031_config_init,
7ab59dc1
DC		 680 .config_aneg = genphy_config_aneg,
681 .read_status = genphy_read_status,
682 .ack_interrupt = kszphy_ack_interrupt,
683 .config_intr = ksz9021_config_intr,
1a5465f5
PV		 684 .suspend = genphy_suspend,
685 .resume = genphy_resume,
7ab59dc1 686 .driver = { .owner = THIS_MODULE, },
93272e07
JCPV		 687}, {
688 .phy_id = PHY_ID_KSZ8873MLL,
689 .phy_id_mask = 0x00fffff0,
690 .name = "Micrel KSZ8873MLL Switch",
691 .features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
692 .flags = PHY_HAS_MAGICANEG,
693 .config_init = kszphy_config_init,
694 .config_aneg = ksz8873mll_config_aneg,
695 .read_status = ksz8873mll_read_status,
1a5465f5
PV		 696 .suspend = genphy_suspend,
697 .resume = genphy_resume,
93272e07 698 .driver = { .owner = THIS_MODULE, },
7ab59dc1
DC		 699}, {
700 .phy_id = PHY_ID_KSZ886X,
701 .phy_id_mask = 0x00fffff0,
702 .name = "Micrel KSZ886X Switch",
703 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
704 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
705 .config_init = kszphy_config_init,
706 .config_aneg = genphy_config_aneg,
707 .read_status = genphy_read_status,
1a5465f5
PV		 708 .suspend = genphy_suspend,
709 .resume = genphy_resume,
7ab59dc1 710 .driver = { .owner = THIS_MODULE, },
d5bf9071 711} };
d0507009 712
50fd7150 713module_phy_driver(ksphy_driver);
d0507009
DC		 714
715MODULE_DESCRIPTION("Micrel PHY driver");
716MODULE_AUTHOR("David J. Choi");
717MODULE_LICENSE("GPL");
52a60ed2 718
cf93c945 719static struct mdio_device_id __maybe_unused micrel_tbl[] = {
48d7d0ad 720 { PHY_ID_KSZ9021, 0x000ffffe },
7ab59dc1 721 { PHY_ID_KSZ9031, 0x00fffff0 },
510d573f 722 { PHY_ID_KSZ8001, 0x00ffffff },
51f932c4 723 { PHY_ID_KS8737, 0x00fffff0 },
212ea99a 724 { PHY_ID_KSZ8021, 0x00ffffff },
b818d1a7 725 { PHY_ID_KSZ8031, 0x00ffffff },
510d573f
MV		 726 { PHY_ID_KSZ8041, 0x00fffff0 },
727 { PHY_ID_KSZ8051, 0x00fffff0 },
7ab59dc1
DC		 728 { PHY_ID_KSZ8061, 0x00fffff0 },
729 { PHY_ID_KSZ8081, 0x00fffff0 },
93272e07 730 { PHY_ID_KSZ8873MLL, 0x00fffff0 },
7ab59dc1 731 { PHY_ID_KSZ886X, 0x00fffff0 },
52a60ed2
DM		 732 { }
733};
734
735MODULE_DEVICE_TABLE(mdio, micrel_tbl);
Linux kernel - Deliverables
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