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net: phy: micrel: refactor led-mode error handling
[deliverable/linux.git] / drivers / net / phy / micrel.c
CommitLineData
d0507009
DC		 1/*
2 * drivers/net/phy/micrel.c
3 *
4 * Driver for Micrel PHYs
5 *
6 * Author: David J. Choi
7 *
7ab59dc1 8 * Copyright (c) 2010-2013 Micrel, Inc.
d0507009
DC		 9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
7ab59dc1
DC		 15 * Support : Micrel Phys:
16 * Giga phys: ksz9021, ksz9031
17 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
18 * ksz8021, ksz8031, ksz8051,
19 * ksz8081, ksz8091,
20 * ksz8061,
21 * Switch : ksz8873, ksz886x
d0507009
DC		 22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/phy.h>
d606ef3f 27#include <linux/micrel_phy.h>
954c3967 28#include <linux/of.h>
1fadee0c 29#include <linux/clk.h>
d0507009 30
212ea99a
MV		 31/* Operation Mode Strap Override */
32#define MII_KSZPHY_OMSO 0x16
00aee095
JH		 33#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
34#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
35#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
212ea99a 36
51f932c4
CD		 37/* general Interrupt control/status reg in vendor specific block. */
38#define MII_KSZPHY_INTCS 0x1B
00aee095
JH		 39#define KSZPHY_INTCS_JABBER BIT(15)
40#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
41#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
42#define KSZPHY_INTCS_PARELLEL BIT(12)
43#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
44#define KSZPHY_INTCS_LINK_DOWN BIT(10)
45#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
46#define KSZPHY_INTCS_LINK_UP BIT(8)
51f932c4
CD		 47#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
48 KSZPHY_INTCS_LINK_DOWN)
49
50/* general PHY control reg in vendor specific block. */
51#define MII_KSZPHY_CTRL 0x1F
52/* bitmap of PHY register to set interrupt mode */
00aee095
JH		 53#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
54#define KSZ9021_CTRL_INT_ACTIVE_HIGH BIT(14)
55#define KS8737_CTRL_INT_ACTIVE_HIGH BIT(14)
56#define KSZ8051_RMII_50MHZ_CLK BIT(7)
51f932c4 57
954c3967
SC		 58/* Write/read to/from extended registers */
59#define MII_KSZPHY_EXTREG 0x0b
60#define KSZPHY_EXTREG_WRITE 0x8000
61
62#define MII_KSZPHY_EXTREG_WRITE 0x0c
63#define MII_KSZPHY_EXTREG_READ 0x0d
64
65/* Extended registers */
66#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
67#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
68#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
69
70#define PS_TO_REG 200
71
b6bb4dfc
HP		 72static int ksz_config_flags(struct phy_device *phydev)
73{
74 int regval;
75
1fadee0c 76 if (phydev->dev_flags & (MICREL_PHY_50MHZ_CLK | MICREL_PHY_25MHZ_CLK)) {
b6bb4dfc 77 regval = phy_read(phydev, MII_KSZPHY_CTRL);
1fadee0c
SH		 78 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK)
79 regval |= KSZ8051_RMII_50MHZ_CLK;
80 else
81 regval &= ~KSZ8051_RMII_50MHZ_CLK;
b6bb4dfc
HP		 82 return phy_write(phydev, MII_KSZPHY_CTRL, regval);
83 }
84 return 0;
85}
86
954c3967 87static int kszphy_extended_write(struct phy_device *phydev,
756b5089 88 u32 regnum, u16 val)
954c3967
SC		 89{
90 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
91 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
92}
93
94static int kszphy_extended_read(struct phy_device *phydev,
756b5089 95 u32 regnum)
954c3967
SC		 96{
97 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
98 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
99}
100
51f932c4
CD		 101static int kszphy_ack_interrupt(struct phy_device *phydev)
102{
103 /* bit[7..0] int status, which is a read and clear register. */
104 int rc;
105
106 rc = phy_read(phydev, MII_KSZPHY_INTCS);
107
108 return (rc < 0) ? rc : 0;
109}
110
111static int kszphy_set_interrupt(struct phy_device *phydev)
112{
113 int temp;
114 temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
115 KSZPHY_INTCS_ALL : 0;
116 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
117}
118
119static int kszphy_config_intr(struct phy_device *phydev)
120{
121 int temp, rc;
122
123 /* set the interrupt pin active low */
124 temp = phy_read(phydev, MII_KSZPHY_CTRL);
5bb8fc0d
JH		 125 if (temp < 0)
126 return temp;
51f932c4
CD		 127 temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
128 phy_write(phydev, MII_KSZPHY_CTRL, temp);
129 rc = kszphy_set_interrupt(phydev);
130 return rc < 0 ? rc : 0;
131}
132
133static int ksz9021_config_intr(struct phy_device *phydev)
134{
135 int temp, rc;
136
137 /* set the interrupt pin active low */
138 temp = phy_read(phydev, MII_KSZPHY_CTRL);
5bb8fc0d
JH		 139 if (temp < 0)
140 return temp;
51f932c4
CD		 141 temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
142 phy_write(phydev, MII_KSZPHY_CTRL, temp);
143 rc = kszphy_set_interrupt(phydev);
144 return rc < 0 ? rc : 0;
145}
146
147static int ks8737_config_intr(struct phy_device *phydev)
148{
149 int temp, rc;
150
151 /* set the interrupt pin active low */
152 temp = phy_read(phydev, MII_KSZPHY_CTRL);
5bb8fc0d
JH		 153 if (temp < 0)
154 return temp;
51f932c4
CD		 155 temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
156 phy_write(phydev, MII_KSZPHY_CTRL, temp);
157 rc = kszphy_set_interrupt(phydev);
158 return rc < 0 ? rc : 0;
159}
d0507009 160
20d8435a
BD		 161static int kszphy_setup_led(struct phy_device *phydev,
162 unsigned int reg, unsigned int shift)
163{
164
165 struct device *dev = &phydev->dev;
166 struct device_node *of_node = dev->of_node;
167 int rc, temp;
168 u32 val;
169
170 if (!of_node && dev->parent->of_node)
171 of_node = dev->parent->of_node;
172
173 if (of_property_read_u32(of_node, "micrel,led-mode", &val))
174 return 0;
175
8620546c
JH		 176 if (val > 3) {
177 dev_err(&phydev->dev, "invalid led mode: 0x%02x\n", val);
178 return -EINVAL;
179 }
180
20d8435a 181 temp = phy_read(phydev, reg);
b7035860
JH		 182 if (temp < 0) {
183 rc = temp;
184 goto out;
185 }
20d8435a 186
28bdc499 187 temp &= ~(3 << shift);
20d8435a
BD		 188 temp |= val << shift;
189 rc = phy_write(phydev, reg, temp);
b7035860
JH		 190out:
191 if (rc < 0)
192 dev_err(&phydev->dev, "failed to set led mode\n");
20d8435a 193
b7035860 194 return rc;
20d8435a
BD		 195}
196
bde15129
JH		 197/* Disable PHY address 0 as the broadcast address, so that it can be used as a
198 * unique (non-broadcast) address on a shared bus.
199 */
200static int kszphy_broadcast_disable(struct phy_device *phydev)
201{
202 int ret;
203
204 ret = phy_read(phydev, MII_KSZPHY_OMSO);
205 if (ret < 0)
206 goto out;
207
208 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
209out:
210 if (ret)
211 dev_err(&phydev->dev, "failed to disable broadcast address\n");
212
213 return ret;
214}
215
d0507009
DC		 216static int kszphy_config_init(struct phy_device *phydev)
217{
218 return 0;
219}
220
20d8435a
BD		 221static int kszphy_config_init_led8041(struct phy_device *phydev)
222{
223 /* single led control, register 0x1e bits 15..14 */
224 return kszphy_setup_led(phydev, 0x1e, 14);
225}
226
212ea99a
MV		 227static int ksz8021_config_init(struct phy_device *phydev)
228{
20d8435a
BD		 229 int rc;
230
b7035860 231 kszphy_setup_led(phydev, 0x1f, 4);
20d8435a 232
b6bb4dfc 233 rc = ksz_config_flags(phydev);
b838b4ac
BT		 234 if (rc < 0)
235 return rc;
bde15129
JH		 236
237 rc = kszphy_broadcast_disable(phydev);
238
b6bb4dfc 239 return rc < 0 ? rc : 0;
212ea99a
MV		 240}
241
d606ef3f
BS		 242static int ks8051_config_init(struct phy_device *phydev)
243{
b6bb4dfc 244 int rc;
d606ef3f 245
b7035860 246 kszphy_setup_led(phydev, 0x1f, 4);
20d8435a 247
b6bb4dfc
HP		 248 rc = ksz_config_flags(phydev);
249 return rc < 0 ? rc : 0;
d606ef3f
BS		 250}
251
57a38eff
JH		 252static int ksz8081_config_init(struct phy_device *phydev)
253{
254 kszphy_broadcast_disable(phydev);
255
256 return 0;
257}
258
954c3967
SC		 259static int ksz9021_load_values_from_of(struct phy_device *phydev,
260 struct device_node *of_node, u16 reg,
261 char *field1, char *field2,
262 char *field3, char *field4)
263{
264 int val1 = -1;
265 int val2 = -2;
266 int val3 = -3;
267 int val4 = -4;
268 int newval;
269 int matches = 0;
270
271 if (!of_property_read_u32(of_node, field1, &val1))
272 matches++;
273
274 if (!of_property_read_u32(of_node, field2, &val2))
275 matches++;
276
277 if (!of_property_read_u32(of_node, field3, &val3))
278 matches++;
279
280 if (!of_property_read_u32(of_node, field4, &val4))
281 matches++;
282
283 if (!matches)
284 return 0;
285
286 if (matches < 4)
287 newval = kszphy_extended_read(phydev, reg);
288 else
289 newval = 0;
290
291 if (val1 != -1)
292 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
293
6a119745 294 if (val2 != -2)
954c3967
SC		 295 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
296
6a119745 297 if (val3 != -3)
954c3967
SC		 298 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
299
6a119745 300 if (val4 != -4)
954c3967
SC		 301 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
302
303 return kszphy_extended_write(phydev, reg, newval);
304}
305
306static int ksz9021_config_init(struct phy_device *phydev)
307{
308 struct device *dev = &phydev->dev;
309 struct device_node *of_node = dev->of_node;
310
311 if (!of_node && dev->parent->of_node)
312 of_node = dev->parent->of_node;
313
314 if (of_node) {
315 ksz9021_load_values_from_of(phydev, of_node,
316 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
317 "txen-skew-ps", "txc-skew-ps",
318 "rxdv-skew-ps", "rxc-skew-ps");
319 ksz9021_load_values_from_of(phydev, of_node,
320 MII_KSZPHY_RX_DATA_PAD_SKEW,
321 "rxd0-skew-ps", "rxd1-skew-ps",
322 "rxd2-skew-ps", "rxd3-skew-ps");
323 ksz9021_load_values_from_of(phydev, of_node,
324 MII_KSZPHY_TX_DATA_PAD_SKEW,
325 "txd0-skew-ps", "txd1-skew-ps",
326 "txd2-skew-ps", "txd3-skew-ps");
327 }
328 return 0;
329}
330
6e4b8273
HC		 331#define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
332#define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
333#define OP_DATA 1
334#define KSZ9031_PS_TO_REG 60
335
336/* Extended registers */
337#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
338#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
339#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
340#define MII_KSZ9031RN_CLK_PAD_SKEW 8
341
342static int ksz9031_extended_write(struct phy_device *phydev,
343 u8 mode, u32 dev_addr, u32 regnum, u16 val)
344{
345 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
346 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
347 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
348 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
349}
350
351static int ksz9031_extended_read(struct phy_device *phydev,
352 u8 mode, u32 dev_addr, u32 regnum)
353{
354 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
355 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
356 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
357 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
358}
359
360static int ksz9031_of_load_skew_values(struct phy_device *phydev,
361 struct device_node *of_node,
362 u16 reg, size_t field_sz,
363 char *field[], u8 numfields)
364{
365 int val[4] = {-1, -2, -3, -4};
366 int matches = 0;
367 u16 mask;
368 u16 maxval;
369 u16 newval;
370 int i;
371
372 for (i = 0; i < numfields; i++)
373 if (!of_property_read_u32(of_node, field[i], val + i))
374 matches++;
375
376 if (!matches)
377 return 0;
378
379 if (matches < numfields)
380 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
381 else
382 newval = 0;
383
384 maxval = (field_sz == 4) ? 0xf : 0x1f;
385 for (i = 0; i < numfields; i++)
386 if (val[i] != -(i + 1)) {
387 mask = 0xffff;
388 mask ^= maxval << (field_sz * i);
389 newval = (newval & mask) |
390 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
391 << (field_sz * i));
392 }
393
394 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
395}
396
397static int ksz9031_config_init(struct phy_device *phydev)
398{
399 struct device *dev = &phydev->dev;
400 struct device_node *of_node = dev->of_node;
401 char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
402 char *rx_data_skews[4] = {
403 "rxd0-skew-ps", "rxd1-skew-ps",
404 "rxd2-skew-ps", "rxd3-skew-ps"
405 };
406 char *tx_data_skews[4] = {
407 "txd0-skew-ps", "txd1-skew-ps",
408 "txd2-skew-ps", "txd3-skew-ps"
409 };
410 char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
411
412 if (!of_node && dev->parent->of_node)
413 of_node = dev->parent->of_node;
414
415 if (of_node) {
416 ksz9031_of_load_skew_values(phydev, of_node,
417 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
418 clk_skews, 2);
419
420 ksz9031_of_load_skew_values(phydev, of_node,
421 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
422 control_skews, 2);
423
424 ksz9031_of_load_skew_values(phydev, of_node,
425 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
426 rx_data_skews, 4);
427
428 ksz9031_of_load_skew_values(phydev, of_node,
429 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
430 tx_data_skews, 4);
431 }
432 return 0;
433}
434
93272e07 435#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
00aee095
JH		 436#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
437#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
32d73b14 438static int ksz8873mll_read_status(struct phy_device *phydev)
93272e07
JCPV		 439{
440 int regval;
441
442 /* dummy read */
443 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
444
445 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
446
447 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
448 phydev->duplex = DUPLEX_HALF;
449 else
450 phydev->duplex = DUPLEX_FULL;
451
452 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
453 phydev->speed = SPEED_10;
454 else
455 phydev->speed = SPEED_100;
456
457 phydev->link = 1;
458 phydev->pause = phydev->asym_pause = 0;
459
460 return 0;
461}
462
463static int ksz8873mll_config_aneg(struct phy_device *phydev)
464{
465 return 0;
466}
467
19936942
VB		 468/* This routine returns -1 as an indication to the caller that the
469 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
470 * MMD extended PHY registers.
471 */
472static int
473ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
474 int regnum)
475{
476 return -1;
477}
478
479/* This routine does nothing since the Micrel ksz9021 does not support
480 * standard IEEE MMD extended PHY registers.
481 */
482static void
483ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
484 int regnum, u32 val)
485{
486}
487
1fadee0c
SH		 488static int ksz8021_probe(struct phy_device *phydev)
489{
490 struct clk *clk;
491
492 clk = devm_clk_get(&phydev->dev, "rmii-ref");
493 if (!IS_ERR(clk)) {
494 unsigned long rate = clk_get_rate(clk);
495
496 if (rate > 24500000 && rate < 25500000) {
497 phydev->dev_flags |= MICREL_PHY_25MHZ_CLK;
498 } else if (rate > 49500000 && rate < 50500000) {
499 phydev->dev_flags |= MICREL_PHY_50MHZ_CLK;
500 } else {
501 dev_err(&phydev->dev, "Clock rate out of range: %ld\n", rate);
502 return -EINVAL;
503 }
504 }
505
506 return 0;
507}
508
d5bf9071
CH		 509static struct phy_driver ksphy_driver[] = {
510{
51f932c4
CD		 511 .phy_id = PHY_ID_KS8737,
512 .phy_id_mask = 0x00fffff0,
513 .name = "Micrel KS8737",
514 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
515 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
516 .config_init = kszphy_config_init,
517 .config_aneg = genphy_config_aneg,
518 .read_status = genphy_read_status,
519 .ack_interrupt = kszphy_ack_interrupt,
520 .config_intr = ks8737_config_intr,
1a5465f5
PV		 521 .suspend = genphy_suspend,
522 .resume = genphy_resume,
51f932c4 523 .driver = { .owner = THIS_MODULE,},
212ea99a
MV		 524}, {
525 .phy_id = PHY_ID_KSZ8021,
526 .phy_id_mask = 0x00ffffff,
7ab59dc1 527 .name = "Micrel KSZ8021 or KSZ8031",
212ea99a
MV		 528 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
529 SUPPORTED_Asym_Pause),
530 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
1fadee0c 531 .probe = ksz8021_probe,
212ea99a
MV		 532 .config_init = ksz8021_config_init,
533 .config_aneg = genphy_config_aneg,
534 .read_status = genphy_read_status,
535 .ack_interrupt = kszphy_ack_interrupt,
536 .config_intr = kszphy_config_intr,
1a5465f5
PV		 537 .suspend = genphy_suspend,
538 .resume = genphy_resume,
212ea99a 539 .driver = { .owner = THIS_MODULE,},
b818d1a7
HP		 540}, {
541 .phy_id = PHY_ID_KSZ8031,
542 .phy_id_mask = 0x00ffffff,
543 .name = "Micrel KSZ8031",
544 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
545 SUPPORTED_Asym_Pause),
546 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
1fadee0c 547 .probe = ksz8021_probe,
b818d1a7
HP		 548 .config_init = ksz8021_config_init,
549 .config_aneg = genphy_config_aneg,
550 .read_status = genphy_read_status,
551 .ack_interrupt = kszphy_ack_interrupt,
552 .config_intr = kszphy_config_intr,
1a5465f5
PV		 553 .suspend = genphy_suspend,
554 .resume = genphy_resume,
b818d1a7 555 .driver = { .owner = THIS_MODULE,},
d5bf9071 556}, {
510d573f 557 .phy_id = PHY_ID_KSZ8041,
51f932c4 558 .phy_id_mask = 0x00fffff0,
510d573f 559 .name = "Micrel KSZ8041",
51f932c4
CD		 560 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
561 | SUPPORTED_Asym_Pause),
562 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
20d8435a 563 .config_init = kszphy_config_init_led8041,
51f932c4
CD		 564 .config_aneg = genphy_config_aneg,
565 .read_status = genphy_read_status,
566 .ack_interrupt = kszphy_ack_interrupt,
567 .config_intr = kszphy_config_intr,
1a5465f5
PV		 568 .suspend = genphy_suspend,
569 .resume = genphy_resume,
51f932c4 570 .driver = { .owner = THIS_MODULE,},
4bd7b512
SS		 571}, {
572 .phy_id = PHY_ID_KSZ8041RNLI,
573 .phy_id_mask = 0x00fffff0,
574 .name = "Micrel KSZ8041RNLI",
575 .features = PHY_BASIC_FEATURES |
576 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
577 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
20d8435a 578 .config_init = kszphy_config_init_led8041,
4bd7b512
SS		 579 .config_aneg = genphy_config_aneg,
580 .read_status = genphy_read_status,
581 .ack_interrupt = kszphy_ack_interrupt,
582 .config_intr = kszphy_config_intr,
583 .suspend = genphy_suspend,
584 .resume = genphy_resume,
585 .driver = { .owner = THIS_MODULE,},
d5bf9071 586}, {
510d573f 587 .phy_id = PHY_ID_KSZ8051,
d0507009 588 .phy_id_mask = 0x00fffff0,
510d573f 589 .name = "Micrel KSZ8051",
51f932c4
CD		 590 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
591 | SUPPORTED_Asym_Pause),
592 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
d606ef3f 593 .config_init = ks8051_config_init,
d0507009
DC		 594 .config_aneg = genphy_config_aneg,
595 .read_status = genphy_read_status,
51f932c4
CD		 596 .ack_interrupt = kszphy_ack_interrupt,
597 .config_intr = kszphy_config_intr,
1a5465f5
PV		 598 .suspend = genphy_suspend,
599 .resume = genphy_resume,
d0507009 600 .driver = { .owner = THIS_MODULE,},
d5bf9071 601}, {
510d573f
MV		 602 .phy_id = PHY_ID_KSZ8001,
603 .name = "Micrel KSZ8001 or KS8721",
48d7d0ad 604 .phy_id_mask = 0x00ffffff,
51f932c4
CD		 605 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
606 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
20d8435a 607 .config_init = kszphy_config_init_led8041,
d0507009
DC		 608 .config_aneg = genphy_config_aneg,
609 .read_status = genphy_read_status,
51f932c4
CD		 610 .ack_interrupt = kszphy_ack_interrupt,
611 .config_intr = kszphy_config_intr,
1a5465f5
PV		 612 .suspend = genphy_suspend,
613 .resume = genphy_resume,
d0507009 614 .driver = { .owner = THIS_MODULE,},
7ab59dc1
DC		 615}, {
616 .phy_id = PHY_ID_KSZ8081,
617 .name = "Micrel KSZ8081 or KSZ8091",
618 .phy_id_mask = 0x00fffff0,
619 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
620 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
57a38eff 621 .config_init = ksz8081_config_init,
7ab59dc1
DC		 622 .config_aneg = genphy_config_aneg,
623 .read_status = genphy_read_status,
624 .ack_interrupt = kszphy_ack_interrupt,
625 .config_intr = kszphy_config_intr,
1a5465f5
PV		 626 .suspend = genphy_suspend,
627 .resume = genphy_resume,
7ab59dc1
DC		 628 .driver = { .owner = THIS_MODULE,},
629}, {
630 .phy_id = PHY_ID_KSZ8061,
631 .name = "Micrel KSZ8061",
632 .phy_id_mask = 0x00fffff0,
633 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
634 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
635 .config_init = kszphy_config_init,
636 .config_aneg = genphy_config_aneg,
637 .read_status = genphy_read_status,
638 .ack_interrupt = kszphy_ack_interrupt,
639 .config_intr = kszphy_config_intr,
1a5465f5
PV		 640 .suspend = genphy_suspend,
641 .resume = genphy_resume,
7ab59dc1 642 .driver = { .owner = THIS_MODULE,},
d5bf9071 643}, {
d0507009 644 .phy_id = PHY_ID_KSZ9021,
48d7d0ad 645 .phy_id_mask = 0x000ffffe,
d0507009 646 .name = "Micrel KSZ9021 Gigabit PHY",
32fcafbc 647 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
51f932c4 648 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
954c3967 649 .config_init = ksz9021_config_init,
d0507009
DC		 650 .config_aneg = genphy_config_aneg,
651 .read_status = genphy_read_status,
51f932c4
CD		 652 .ack_interrupt = kszphy_ack_interrupt,
653 .config_intr = ksz9021_config_intr,
1a5465f5
PV		 654 .suspend = genphy_suspend,
655 .resume = genphy_resume,
19936942
VB		 656 .read_mmd_indirect = ksz9021_rd_mmd_phyreg,
657 .write_mmd_indirect = ksz9021_wr_mmd_phyreg,
d0507009 658 .driver = { .owner = THIS_MODULE, },
7ab59dc1
DC		 659}, {
660 .phy_id = PHY_ID_KSZ9031,
661 .phy_id_mask = 0x00fffff0,
662 .name = "Micrel KSZ9031 Gigabit PHY",
95e8b103 663 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
7ab59dc1 664 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
6e4b8273 665 .config_init = ksz9031_config_init,
7ab59dc1
DC		 666 .config_aneg = genphy_config_aneg,
667 .read_status = genphy_read_status,
668 .ack_interrupt = kszphy_ack_interrupt,
669 .config_intr = ksz9021_config_intr,
1a5465f5
PV		 670 .suspend = genphy_suspend,
671 .resume = genphy_resume,
7ab59dc1 672 .driver = { .owner = THIS_MODULE, },
93272e07
JCPV		 673}, {
674 .phy_id = PHY_ID_KSZ8873MLL,
675 .phy_id_mask = 0x00fffff0,
676 .name = "Micrel KSZ8873MLL Switch",
677 .features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
678 .flags = PHY_HAS_MAGICANEG,
679 .config_init = kszphy_config_init,
680 .config_aneg = ksz8873mll_config_aneg,
681 .read_status = ksz8873mll_read_status,
1a5465f5
PV		 682 .suspend = genphy_suspend,
683 .resume = genphy_resume,
93272e07 684 .driver = { .owner = THIS_MODULE, },
7ab59dc1
DC		 685}, {
686 .phy_id = PHY_ID_KSZ886X,
687 .phy_id_mask = 0x00fffff0,
688 .name = "Micrel KSZ886X Switch",
689 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
690 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
691 .config_init = kszphy_config_init,
692 .config_aneg = genphy_config_aneg,
693 .read_status = genphy_read_status,
1a5465f5
PV		 694 .suspend = genphy_suspend,
695 .resume = genphy_resume,
7ab59dc1 696 .driver = { .owner = THIS_MODULE, },
d5bf9071 697} };
d0507009 698
50fd7150 699module_phy_driver(ksphy_driver);
d0507009
DC		 700
701MODULE_DESCRIPTION("Micrel PHY driver");
702MODULE_AUTHOR("David J. Choi");
703MODULE_LICENSE("GPL");
52a60ed2 704
cf93c945 705static struct mdio_device_id __maybe_unused micrel_tbl[] = {
48d7d0ad 706 { PHY_ID_KSZ9021, 0x000ffffe },
7ab59dc1 707 { PHY_ID_KSZ9031, 0x00fffff0 },
510d573f 708 { PHY_ID_KSZ8001, 0x00ffffff },
51f932c4 709 { PHY_ID_KS8737, 0x00fffff0 },
212ea99a 710 { PHY_ID_KSZ8021, 0x00ffffff },
b818d1a7 711 { PHY_ID_KSZ8031, 0x00ffffff },
510d573f
MV		 712 { PHY_ID_KSZ8041, 0x00fffff0 },
713 { PHY_ID_KSZ8051, 0x00fffff0 },
7ab59dc1
DC		 714 { PHY_ID_KSZ8061, 0x00fffff0 },
715 { PHY_ID_KSZ8081, 0x00fffff0 },
93272e07 716 { PHY_ID_KSZ8873MLL, 0x00fffff0 },
7ab59dc1 717 { PHY_ID_KSZ886X, 0x00fffff0 },
52a60ed2
DM		 718 { }
719};
720
721MODULE_DEVICE_TABLE(mdio, micrel_tbl);
Linux kernel - Deliverables
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