[deliverable/linux.git] / drivers / net / phy / qsemi.c

/*
 * drivers/net/phy/qsemi.c
 *
 * Driver for Quality Semiconductor PHYs
 *
 * Author: Andy Fleming
 *
 * Copyright (c) 2004 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/unistd.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/phy.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>

/* ------------------------------------------------------------------------- */
/* The Quality Semiconductor QS6612 is used on the RPX CLLF                  */

/* register definitions */

#define MII_QS6612_MCR		17  /* Mode Control Register      */
#define MII_QS6612_FTR		27  /* Factory Test Register      */
#define MII_QS6612_MCO		28  /* Misc. Control Register     */
#define MII_QS6612_ISR		29  /* Interrupt Source Register  */
#define MII_QS6612_IMR		30  /* Interrupt Mask Register    */
#define MII_QS6612_IMR_INIT	0x003a
#define MII_QS6612_PCR		31  /* 100BaseTx PHY Control Reg. */

#define QS6612_PCR_AN_COMPLETE	0x1000
#define QS6612_PCR_RLBEN	0x0200
#define QS6612_PCR_DCREN	0x0100
#define QS6612_PCR_4B5BEN	0x0040
#define QS6612_PCR_TX_ISOLATE	0x0020
#define QS6612_PCR_MLT3_DIS	0x0002
#define QS6612_PCR_SCRM_DESCRM	0x0001

MODULE_DESCRIPTION("Quality Semiconductor PHY driver");
MODULE_AUTHOR("Andy Fleming");
MODULE_LICENSE("GPL");

/* Returns 0, unless there's a write error */
static int qs6612_config_init(struct phy_device *phydev)
{
	/* The PHY powers up isolated on the RPX,
	 * so send a command to allow operation.
	 * XXX - My docs indicate this should be 0x0940
	 * ...or something.  The current value sets three
	 * reserved bits, bit 11, which specifies it should be
	 * set to one, bit 10, which specifies it should be set
	 * to 0, and bit 7, which doesn't specify.  However, my
	 * docs are preliminary, and I will leave it like this
	 * until someone more knowledgable corrects me or it.
	 * -- Andy Fleming
	 */
	return phy_write(phydev, MII_QS6612_PCR, 0x0dc0);
}

static int qs6612_ack_interrupt(struct phy_device *phydev)
{
	int err;

	err = phy_read(phydev, MII_QS6612_ISR);

	if (err < 0)
		return err;

	err = phy_read(phydev, MII_BMSR);

	if (err < 0)
		return err;

	err = phy_read(phydev, MII_EXPANSION);

	if (err < 0)
		return err;

	return 0;
}

static int qs6612_config_intr(struct phy_device *phydev)
{
	int err;
	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
		err = phy_write(phydev, MII_QS6612_IMR,
				MII_QS6612_IMR_INIT);
	else
		err = phy_write(phydev, MII_QS6612_IMR, 0);

	return err;

}

static struct phy_driver qs6612_driver = {
	.phy_id		= 0x00181440,
	.name		= "QS6612",
	.phy_id_mask	= 0xfffffff0,
	.features	= PHY_BASIC_FEATURES,
	.flags		= PHY_HAS_INTERRUPT,
	.config_init	= qs6612_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= qs6612_ack_interrupt,
	.config_intr	= qs6612_config_intr,
	.driver 	= { .owner = THIS_MODULE,},
};

static int __init qs6612_init(void)
{
	return phy_driver_register(&qs6612_driver);
}

static void __exit qs6612_exit(void)
{
	phy_driver_unregister(&qs6612_driver);
}

module_init(qs6612_init);
module_exit(qs6612_exit);
Commit	Line	Data
00db8189 AF	1	/*
	2	* drivers/net/phy/qsemi.c
	3	*
	4	* Driver for Quality Semiconductor PHYs
	5	*
	6	* Author: Andy Fleming
	7	*
	8	* Copyright (c) 2004 Freescale Semiconductor, Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*
	15	*/
00db8189 AF	16	#include <linux/kernel.h>
	17	#include <linux/sched.h>
	18	#include <linux/string.h>
	19	#include <linux/errno.h>
	20	#include <linux/unistd.h>
	21	#include <linux/slab.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/init.h>
	24	#include <linux/delay.h>
	25	#include <linux/netdevice.h>
	26	#include <linux/etherdevice.h>
	27	#include <linux/skbuff.h>
	28	#include <linux/spinlock.h>
	29	#include <linux/mm.h>
	30	#include <linux/module.h>
00db8189 AF	31	#include <linux/mii.h>
	32	#include <linux/ethtool.h>
	33	#include <linux/phy.h>
	34
	35	#include <asm/io.h>
	36	#include <asm/irq.h>
	37	#include <asm/uaccess.h>
	38
	39	/* ------------------------------------------------------------------------- */
	40	/* The Quality Semiconductor QS6612 is used on the RPX CLLF */
	41
	42	/* register definitions */
	43
	44	#define MII_QS6612_MCR 17 /* Mode Control Register */
	45	#define MII_QS6612_FTR 27 /* Factory Test Register */
	46	#define MII_QS6612_MCO 28 /* Misc. Control Register */
	47	#define MII_QS6612_ISR 29 /* Interrupt Source Register */
	48	#define MII_QS6612_IMR 30 /* Interrupt Mask Register */
	49	#define MII_QS6612_IMR_INIT 0x003a
	50	#define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
	51
	52	#define QS6612_PCR_AN_COMPLETE 0x1000
	53	#define QS6612_PCR_RLBEN 0x0200
	54	#define QS6612_PCR_DCREN 0x0100
	55	#define QS6612_PCR_4B5BEN 0x0040
	56	#define QS6612_PCR_TX_ISOLATE 0x0020
	57	#define QS6612_PCR_MLT3_DIS 0x0002
	58	#define QS6612_PCR_SCRM_DESCRM 0x0001
	59
	60	MODULE_DESCRIPTION("Quality Semiconductor PHY driver");
	61	MODULE_AUTHOR("Andy Fleming");
	62	MODULE_LICENSE("GPL");
	63
	64	/* Returns 0, unless there's a write error */
	65	static int qs6612_config_init(struct phy_device *phydev)
	66	{
	67	/* The PHY powers up isolated on the RPX,
	68	* so send a command to allow operation.
	69	* XXX - My docs indicate this should be 0x0940
	70	* ...or something. The current value sets three
	71	* reserved bits, bit 11, which specifies it should be
	72	* set to one, bit 10, which specifies it should be set
	73	* to 0, and bit 7, which doesn't specify. However, my
	74	* docs are preliminary, and I will leave it like this
	75	* until someone more knowledgable corrects me or it.
	76	* -- Andy Fleming
	77	*/
	78	return phy_write(phydev, MII_QS6612_PCR, 0x0dc0);
	79	}
	80
	81	static int qs6612_ack_interrupt(struct phy_device *phydev)
	82	{
	83	int err;
	84
	85	err = phy_read(phydev, MII_QS6612_ISR);
	86
	87	if (err < 0)
	88	return err;
	89
	90	err = phy_read(phydev, MII_BMSR);
	91
	92	if (err < 0)
	93	return err;
	94
95	err = phy_read(phydev, MII_EXPANSION);
96
97	if (err < 0)
98	return err;
99
100	return 0;
101	}
102
103	static int qs6612_config_intr(struct phy_device *phydev)
104	{
105	int err;
106	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
107	err = phy_write(phydev, MII_QS6612_IMR,
108	MII_QS6612_IMR_INIT);
109	else
110	err = phy_write(phydev, MII_QS6612_IMR, 0);
111
112	return err;
113
114	}
115
116	static struct phy_driver qs6612_driver = {
117	.phy_id = 0x00181440,
118	.name = "QS6612",
119	.phy_id_mask = 0xfffffff0,
120	.features = PHY_BASIC_FEATURES,
121	.flags = PHY_HAS_INTERRUPT,
122	.config_init = qs6612_config_init,
123	.config_aneg = genphy_config_aneg,
124	.read_status = genphy_read_status,
125	.ack_interrupt = qs6612_ack_interrupt,
126	.config_intr = qs6612_config_intr,
127	.driver = { .owner = THIS_MODULE,},
128	};
129
130	static int __init qs6612_init(void)
131	{
132	return phy_driver_register(&qs6612_driver);
133	}
134
135	static void __exit qs6612_exit(void)
136	{
137	phy_driver_unregister(&qs6612_driver);
138	}
139
140	module_init(qs6612_init);
141	module_exit(qs6612_exit);