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ef82a306 JL |
1 | /* |
2 | * Driver for Vitesse PHYs | |
3 | * | |
4 | * Author: Kriston Carson | |
5 | * | |
3fb69bca | 6 | * Copyright (c) 2005, 2009, 2011 Freescale Semiconductor, Inc. |
ef82a306 JL |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
14 | ||
ef82a306 JL |
15 | #include <linux/kernel.h> |
16 | #include <linux/module.h> | |
17 | #include <linux/mii.h> | |
18 | #include <linux/ethtool.h> | |
19 | #include <linux/phy.h> | |
20 | ||
3fb69bca MB |
21 | /* Vitesse Extended Page Magic Register(s) */ |
22 | #define MII_VSC82X4_EXT_PAGE_16E 0x10 | |
23 | #define MII_VSC82X4_EXT_PAGE_17E 0x11 | |
24 | #define MII_VSC82X4_EXT_PAGE_18E 0x12 | |
25 | ||
ef82a306 JL |
26 | /* Vitesse Extended Control Register 1 */ |
27 | #define MII_VSC8244_EXT_CON1 0x17 | |
28 | #define MII_VSC8244_EXTCON1_INIT 0x0000 | |
af2d940d AF |
29 | #define MII_VSC8244_EXTCON1_TX_SKEW_MASK 0x0c00 |
30 | #define MII_VSC8244_EXTCON1_RX_SKEW_MASK 0x0300 | |
31 | #define MII_VSC8244_EXTCON1_TX_SKEW 0x0800 | |
32 | #define MII_VSC8244_EXTCON1_RX_SKEW 0x0200 | |
ef82a306 JL |
33 | |
34 | /* Vitesse Interrupt Mask Register */ | |
35 | #define MII_VSC8244_IMASK 0x19 | |
36 | #define MII_VSC8244_IMASK_IEN 0x8000 | |
37 | #define MII_VSC8244_IMASK_SPEED 0x4000 | |
38 | #define MII_VSC8244_IMASK_LINK 0x2000 | |
39 | #define MII_VSC8244_IMASK_DUPLEX 0x1000 | |
40 | #define MII_VSC8244_IMASK_MASK 0xf000 | |
41 | ||
11c6dd2c TP |
42 | #define MII_VSC8221_IMASK_MASK 0xa000 |
43 | ||
ef82a306 JL |
44 | /* Vitesse Interrupt Status Register */ |
45 | #define MII_VSC8244_ISTAT 0x1a | |
46 | #define MII_VSC8244_ISTAT_STATUS 0x8000 | |
47 | #define MII_VSC8244_ISTAT_SPEED 0x4000 | |
48 | #define MII_VSC8244_ISTAT_LINK 0x2000 | |
49 | #define MII_VSC8244_ISTAT_DUPLEX 0x1000 | |
50 | ||
51 | /* Vitesse Auxiliary Control/Status Register */ | |
2a8626d1 MS |
52 | #define MII_VSC8244_AUX_CONSTAT 0x1c |
53 | #define MII_VSC8244_AUXCONSTAT_INIT 0x0000 | |
54 | #define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020 | |
55 | #define MII_VSC8244_AUXCONSTAT_SPEED 0x0018 | |
56 | #define MII_VSC8244_AUXCONSTAT_GBIT 0x0010 | |
57 | #define MII_VSC8244_AUXCONSTAT_100 0x0008 | |
ef82a306 | 58 | |
11c6dd2c TP |
59 | #define MII_VSC8221_AUXCONSTAT_INIT 0x0004 /* need to set this bit? */ |
60 | #define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004 | |
61 | ||
3fb69bca MB |
62 | /* Vitesse Extended Page Access Register */ |
63 | #define MII_VSC82X4_EXT_PAGE_ACCESS 0x1f | |
64 | ||
0508019c | 65 | #define PHY_ID_VSC8234 0x000fc620 |
11c6dd2c | 66 | #define PHY_ID_VSC8244 0x000fc6c0 |
167f76a8 | 67 | #define PHY_ID_VSC8514 0x00070670 |
c2efef74 | 68 | #define PHY_ID_VSC8574 0x000704a0 |
7729b053 | 69 | #define PHY_ID_VSC8601 0x00070420 |
06ae4f84 | 70 | #define PHY_ID_VSC8662 0x00070660 |
11c6dd2c | 71 | #define PHY_ID_VSC8221 0x000fc550 |
5a1cebd8 | 72 | #define PHY_ID_VSC8211 0x000fc4b0 |
11c6dd2c | 73 | |
ef82a306 JL |
74 | MODULE_DESCRIPTION("Vitesse PHY driver"); |
75 | MODULE_AUTHOR("Kriston Carson"); | |
76 | MODULE_LICENSE("GPL"); | |
77 | ||
baec126c | 78 | static int vsc824x_add_skew(struct phy_device *phydev) |
ef82a306 JL |
79 | { |
80 | int err; | |
fddf86fc | 81 | int extcon; |
ef82a306 | 82 | |
af2d940d AF |
83 | extcon = phy_read(phydev, MII_VSC8244_EXT_CON1); |
84 | ||
85 | if (extcon < 0) | |
fddf86fc | 86 | return extcon; |
af2d940d AF |
87 | |
88 | extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK | | |
89 | MII_VSC8244_EXTCON1_RX_SKEW_MASK); | |
90 | ||
fddf86fc AF |
91 | extcon |= (MII_VSC8244_EXTCON1_TX_SKEW | |
92 | MII_VSC8244_EXTCON1_RX_SKEW); | |
af2d940d AF |
93 | |
94 | err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon); | |
95 | ||
ef82a306 JL |
96 | return err; |
97 | } | |
fddf86fc AF |
98 | |
99 | static int vsc824x_config_init(struct phy_device *phydev) | |
100 | { | |
101 | int err; | |
102 | ||
103 | err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT, | |
104 | MII_VSC8244_AUXCONSTAT_INIT); | |
105 | if (err < 0) | |
106 | return err; | |
107 | ||
108 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) | |
109 | err = vsc824x_add_skew(phydev); | |
110 | ||
111 | return err; | |
112 | } | |
ef82a306 JL |
113 | |
114 | static int vsc824x_ack_interrupt(struct phy_device *phydev) | |
115 | { | |
1d5e83aa | 116 | int err = 0; |
2a8626d1 MS |
117 | |
118 | /* Don't bother to ACK the interrupts if interrupts | |
1d5e83aa AF |
119 | * are disabled. The 824x cannot clear the interrupts |
120 | * if they are disabled. | |
121 | */ | |
122 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) | |
123 | err = phy_read(phydev, MII_VSC8244_ISTAT); | |
ef82a306 JL |
124 | |
125 | return (err < 0) ? err : 0; | |
126 | } | |
127 | ||
11c6dd2c | 128 | static int vsc82xx_config_intr(struct phy_device *phydev) |
ef82a306 JL |
129 | { |
130 | int err; | |
131 | ||
132 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) | |
133 | err = phy_write(phydev, MII_VSC8244_IMASK, | |
0508019c | 134 | (phydev->drv->phy_id == PHY_ID_VSC8234 || |
c2efef74 | 135 | phydev->drv->phy_id == PHY_ID_VSC8244 || |
167f76a8 | 136 | phydev->drv->phy_id == PHY_ID_VSC8514 || |
7729b053 MR |
137 | phydev->drv->phy_id == PHY_ID_VSC8574 || |
138 | phydev->drv->phy_id == PHY_ID_VSC8601) ? | |
11c6dd2c TP |
139 | MII_VSC8244_IMASK_MASK : |
140 | MII_VSC8221_IMASK_MASK); | |
1d5e83aa | 141 | else { |
2a8626d1 | 142 | /* The Vitesse PHY cannot clear the interrupt |
1d5e83aa AF |
143 | * once it has disabled them, so we clear them first |
144 | */ | |
145 | err = phy_read(phydev, MII_VSC8244_ISTAT); | |
146 | ||
52cb1c2b | 147 | if (err < 0) |
1d5e83aa AF |
148 | return err; |
149 | ||
ef82a306 | 150 | err = phy_write(phydev, MII_VSC8244_IMASK, 0); |
1d5e83aa AF |
151 | } |
152 | ||
ef82a306 JL |
153 | return err; |
154 | } | |
155 | ||
11c6dd2c | 156 | static int vsc8221_config_init(struct phy_device *phydev) |
ef82a306 | 157 | { |
11c6dd2c TP |
158 | int err; |
159 | ||
160 | err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT, | |
161 | MII_VSC8221_AUXCONSTAT_INIT); | |
162 | return err; | |
163 | ||
164 | /* Perhaps we should set EXT_CON1 based on the interface? | |
2a8626d1 MS |
165 | * Options are 802.3Z SerDes or SGMII |
166 | */ | |
11c6dd2c TP |
167 | } |
168 | ||
3fb69bca MB |
169 | /* vsc82x4_config_autocross_enable - Enable auto MDI/MDI-X for forced links |
170 | * @phydev: target phy_device struct | |
171 | * | |
172 | * Enable auto MDI/MDI-X when in 10/100 forced link speeds by writing | |
173 | * special values in the VSC8234/VSC8244 extended reserved registers | |
174 | */ | |
175 | static int vsc82x4_config_autocross_enable(struct phy_device *phydev) | |
176 | { | |
177 | int ret; | |
178 | ||
179 | if (phydev->autoneg == AUTONEG_ENABLE || phydev->speed > SPEED_100) | |
180 | return 0; | |
181 | ||
182 | /* map extended registers set 0x10 - 0x1e */ | |
183 | ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x52b5); | |
184 | if (ret >= 0) | |
185 | ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_18E, 0x0012); | |
186 | if (ret >= 0) | |
187 | ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_17E, 0x2803); | |
188 | if (ret >= 0) | |
189 | ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_16E, 0x87fa); | |
190 | /* map standard registers set 0x10 - 0x1e */ | |
191 | if (ret >= 0) | |
192 | ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000); | |
193 | else | |
194 | phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000); | |
195 | ||
196 | return ret; | |
197 | } | |
198 | ||
199 | /* vsc82x4_config_aneg - restart auto-negotiation or write BMCR | |
200 | * @phydev: target phy_device struct | |
201 | * | |
202 | * Description: If auto-negotiation is enabled, we configure the | |
203 | * advertising, and then restart auto-negotiation. If it is not | |
204 | * enabled, then we write the BMCR and also start the auto | |
205 | * MDI/MDI-X feature | |
206 | */ | |
207 | static int vsc82x4_config_aneg(struct phy_device *phydev) | |
208 | { | |
209 | int ret; | |
210 | ||
211 | /* Enable auto MDI/MDI-X when in 10/100 forced link speeds by | |
212 | * writing special values in the VSC8234 extended reserved registers | |
213 | */ | |
214 | if (phydev->autoneg != AUTONEG_ENABLE && phydev->speed <= SPEED_100) { | |
215 | ret = genphy_setup_forced(phydev); | |
216 | ||
217 | if (ret < 0) /* error */ | |
218 | return ret; | |
219 | ||
220 | return vsc82x4_config_autocross_enable(phydev); | |
221 | } | |
222 | ||
223 | return genphy_config_aneg(phydev); | |
224 | } | |
225 | ||
0508019c | 226 | /* Vitesse 82xx */ |
d5bf9071 CH |
227 | static struct phy_driver vsc82xx_driver[] = { |
228 | { | |
0508019c AF |
229 | .phy_id = PHY_ID_VSC8234, |
230 | .name = "Vitesse VSC8234", | |
231 | .phy_id_mask = 0x000ffff0, | |
232 | .features = PHY_GBIT_FEATURES, | |
233 | .flags = PHY_HAS_INTERRUPT, | |
234 | .config_init = &vsc824x_config_init, | |
3fb69bca | 235 | .config_aneg = &vsc82x4_config_aneg, |
0508019c AF |
236 | .read_status = &genphy_read_status, |
237 | .ack_interrupt = &vsc824x_ack_interrupt, | |
238 | .config_intr = &vsc82xx_config_intr, | |
0508019c | 239 | }, { |
d5bf9071 CH |
240 | .phy_id = PHY_ID_VSC8244, |
241 | .name = "Vitesse VSC8244", | |
242 | .phy_id_mask = 0x000fffc0, | |
243 | .features = PHY_GBIT_FEATURES, | |
244 | .flags = PHY_HAS_INTERRUPT, | |
245 | .config_init = &vsc824x_config_init, | |
3fb69bca | 246 | .config_aneg = &vsc82x4_config_aneg, |
d5bf9071 CH |
247 | .read_status = &genphy_read_status, |
248 | .ack_interrupt = &vsc824x_ack_interrupt, | |
249 | .config_intr = &vsc82xx_config_intr, | |
167f76a8 SX |
250 | }, { |
251 | .phy_id = PHY_ID_VSC8514, | |
252 | .name = "Vitesse VSC8514", | |
253 | .phy_id_mask = 0x000ffff0, | |
254 | .features = PHY_GBIT_FEATURES, | |
255 | .flags = PHY_HAS_INTERRUPT, | |
256 | .config_init = &vsc824x_config_init, | |
257 | .config_aneg = &vsc82x4_config_aneg, | |
258 | .read_status = &genphy_read_status, | |
259 | .ack_interrupt = &vsc824x_ack_interrupt, | |
260 | .config_intr = &vsc82xx_config_intr, | |
c2efef74 | 261 | }, { |
262 | .phy_id = PHY_ID_VSC8574, | |
263 | .name = "Vitesse VSC8574", | |
264 | .phy_id_mask = 0x000ffff0, | |
265 | .features = PHY_GBIT_FEATURES, | |
266 | .flags = PHY_HAS_INTERRUPT, | |
267 | .config_init = &vsc824x_config_init, | |
3fb69bca | 268 | .config_aneg = &vsc82x4_config_aneg, |
c2efef74 | 269 | .read_status = &genphy_read_status, |
270 | .ack_interrupt = &vsc824x_ack_interrupt, | |
271 | .config_intr = &vsc82xx_config_intr, | |
7729b053 MR |
272 | }, { |
273 | .phy_id = PHY_ID_VSC8601, | |
274 | .name = "Vitesse VSC8601", | |
275 | .phy_id_mask = 0x000ffff0, | |
276 | .features = PHY_GBIT_FEATURES, | |
277 | .flags = PHY_HAS_INTERRUPT, | |
278 | .config_init = &genphy_config_init, | |
279 | .config_aneg = &genphy_config_aneg, | |
280 | .read_status = &genphy_read_status, | |
281 | .ack_interrupt = &vsc824x_ack_interrupt, | |
282 | .config_intr = &vsc82xx_config_intr, | |
06ae4f84 SS |
283 | }, { |
284 | .phy_id = PHY_ID_VSC8662, | |
285 | .name = "Vitesse VSC8662", | |
286 | .phy_id_mask = 0x000ffff0, | |
287 | .features = PHY_GBIT_FEATURES, | |
288 | .flags = PHY_HAS_INTERRUPT, | |
289 | .config_init = &vsc824x_config_init, | |
3fb69bca | 290 | .config_aneg = &vsc82x4_config_aneg, |
06ae4f84 SS |
291 | .read_status = &genphy_read_status, |
292 | .ack_interrupt = &vsc824x_ack_interrupt, | |
293 | .config_intr = &vsc82xx_config_intr, | |
d5bf9071 CH |
294 | }, { |
295 | /* Vitesse 8221 */ | |
11c6dd2c TP |
296 | .phy_id = PHY_ID_VSC8221, |
297 | .phy_id_mask = 0x000ffff0, | |
298 | .name = "Vitesse VSC8221", | |
299 | .features = PHY_GBIT_FEATURES, | |
300 | .flags = PHY_HAS_INTERRUPT, | |
301 | .config_init = &vsc8221_config_init, | |
302 | .config_aneg = &genphy_config_aneg, | |
303 | .read_status = &genphy_read_status, | |
304 | .ack_interrupt = &vsc824x_ack_interrupt, | |
305 | .config_intr = &vsc82xx_config_intr, | |
5a1cebd8 MS |
306 | }, { |
307 | /* Vitesse 8211 */ | |
308 | .phy_id = PHY_ID_VSC8211, | |
309 | .phy_id_mask = 0x000ffff0, | |
310 | .name = "Vitesse VSC8211", | |
311 | .features = PHY_GBIT_FEATURES, | |
312 | .flags = PHY_HAS_INTERRUPT, | |
313 | .config_init = &vsc8221_config_init, | |
314 | .config_aneg = &genphy_config_aneg, | |
315 | .read_status = &genphy_read_status, | |
316 | .ack_interrupt = &vsc824x_ack_interrupt, | |
317 | .config_intr = &vsc82xx_config_intr, | |
d5bf9071 | 318 | } }; |
11c6dd2c | 319 | |
50fd7150 | 320 | module_phy_driver(vsc82xx_driver); |
4e4f10f6 | 321 | |
cf93c945 | 322 | static struct mdio_device_id __maybe_unused vitesse_tbl[] = { |
0508019c | 323 | { PHY_ID_VSC8234, 0x000ffff0 }, |
4e4f10f6 | 324 | { PHY_ID_VSC8244, 0x000fffc0 }, |
167f76a8 | 325 | { PHY_ID_VSC8514, 0x000ffff0 }, |
c2efef74 | 326 | { PHY_ID_VSC8574, 0x000ffff0 }, |
06ae4f84 | 327 | { PHY_ID_VSC8662, 0x000ffff0 }, |
4e4f10f6 | 328 | { PHY_ID_VSC8221, 0x000ffff0 }, |
5a1cebd8 | 329 | { PHY_ID_VSC8211, 0x000ffff0 }, |
4e4f10f6 DW |
330 | { } |
331 | }; | |
332 | ||
333 | MODULE_DEVICE_TABLE(mdio, vitesse_tbl); |