[deliverable/linux.git] / drivers / net / phy / vitesse.c

/*
 * Driver for Vitesse PHYs
 *
 * Author: Kriston Carson
 *
 * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/phy.h>

/* Vitesse Extended Control Register 1 */
#define MII_VSC8244_EXT_CON1           0x17
#define MII_VSC8244_EXTCON1_INIT       0x0000
#define MII_VSC8244_EXTCON1_TX_SKEW_MASK	0x0c00
#define MII_VSC8244_EXTCON1_RX_SKEW_MASK	0x0300
#define MII_VSC8244_EXTCON1_TX_SKEW	0x0800
#define MII_VSC8244_EXTCON1_RX_SKEW	0x0200

/* Vitesse Interrupt Mask Register */
#define MII_VSC8244_IMASK		0x19
#define MII_VSC8244_IMASK_IEN		0x8000
#define MII_VSC8244_IMASK_SPEED		0x4000
#define MII_VSC8244_IMASK_LINK		0x2000
#define MII_VSC8244_IMASK_DUPLEX	0x1000
#define MII_VSC8244_IMASK_MASK		0xf000

#define MII_VSC8221_IMASK_MASK		0xa000

/* Vitesse Interrupt Status Register */
#define MII_VSC8244_ISTAT		0x1a
#define MII_VSC8244_ISTAT_STATUS	0x8000
#define MII_VSC8244_ISTAT_SPEED		0x4000
#define MII_VSC8244_ISTAT_LINK		0x2000
#define MII_VSC8244_ISTAT_DUPLEX	0x1000

/* Vitesse Auxiliary Control/Status Register */
#define MII_VSC8244_AUX_CONSTAT		0x1c
#define MII_VSC8244_AUXCONSTAT_INIT	0x0000
#define MII_VSC8244_AUXCONSTAT_DUPLEX	0x0020
#define MII_VSC8244_AUXCONSTAT_SPEED	0x0018
#define MII_VSC8244_AUXCONSTAT_GBIT	0x0010
#define MII_VSC8244_AUXCONSTAT_100	0x0008

#define MII_VSC8221_AUXCONSTAT_INIT	0x0004 /* need to set this bit? */
#define MII_VSC8221_AUXCONSTAT_RESERVED	0x0004

#define PHY_ID_VSC8234			0x000fc620
#define PHY_ID_VSC8244			0x000fc6c0
#define PHY_ID_VSC8574			0x000704a0
#define PHY_ID_VSC8662			0x00070660
#define PHY_ID_VSC8221			0x000fc550
#define PHY_ID_VSC8211			0x000fc4b0

MODULE_DESCRIPTION("Vitesse PHY driver");
MODULE_AUTHOR("Kriston Carson");
MODULE_LICENSE("GPL");

static int vsc824x_add_skew(struct phy_device *phydev)
{
	int err;
	int extcon;

	extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);

	if (extcon < 0)
		return extcon;

	extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK |
			MII_VSC8244_EXTCON1_RX_SKEW_MASK);

	extcon |= (MII_VSC8244_EXTCON1_TX_SKEW |
			MII_VSC8244_EXTCON1_RX_SKEW);

	err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);

	return err;
}

static int vsc824x_config_init(struct phy_device *phydev)
{
	int err;

	err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
			MII_VSC8244_AUXCONSTAT_INIT);
	if (err < 0)
		return err;

	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
		err = vsc824x_add_skew(phydev);

	return err;
}

static int vsc824x_ack_interrupt(struct phy_device *phydev)
{
	int err = 0;

	/* Don't bother to ACK the interrupts if interrupts
	 * are disabled.  The 824x cannot clear the interrupts
	 * if they are disabled.
	 */
	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
		err = phy_read(phydev, MII_VSC8244_ISTAT);

	return (err < 0) ? err : 0;
}

static int vsc82xx_config_intr(struct phy_device *phydev)
{
	int err;

	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
		err = phy_write(phydev, MII_VSC8244_IMASK,
			(phydev->drv->phy_id == PHY_ID_VSC8234 ||
			 phydev->drv->phy_id == PHY_ID_VSC8244 ||
			 phydev->drv->phy_id == PHY_ID_VSC8574) ?
				MII_VSC8244_IMASK_MASK :
				MII_VSC8221_IMASK_MASK);
	else {
		/* The Vitesse PHY cannot clear the interrupt
		 * once it has disabled them, so we clear them first
		 */
		err = phy_read(phydev, MII_VSC8244_ISTAT);

		if (err < 0)
			return err;

		err = phy_write(phydev, MII_VSC8244_IMASK, 0);
	}

	return err;
}

static int vsc8221_config_init(struct phy_device *phydev)
{
	int err;

	err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
			MII_VSC8221_AUXCONSTAT_INIT);
	return err;

	/* Perhaps we should set EXT_CON1 based on the interface?
	 * Options are 802.3Z SerDes or SGMII
	 */
}

/* Vitesse 82xx */
static struct phy_driver vsc82xx_driver[] = {
{
	.phy_id         = PHY_ID_VSC8234,
	.name           = "Vitesse VSC8234",
	.phy_id_mask    = 0x000ffff0,
	.features       = PHY_GBIT_FEATURES,
	.flags          = PHY_HAS_INTERRUPT,
	.config_init    = &vsc824x_config_init,
	.config_aneg    = &genphy_config_aneg,
	.read_status    = &genphy_read_status,
	.ack_interrupt  = &vsc824x_ack_interrupt,
	.config_intr    = &vsc82xx_config_intr,
	.driver         = { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_VSC8244,
	.name		= "Vitesse VSC8244",
	.phy_id_mask	= 0x000fffc0,
	.features	= PHY_GBIT_FEATURES,
	.flags		= PHY_HAS_INTERRUPT,
	.config_init	= &vsc824x_config_init,
	.config_aneg	= &genphy_config_aneg,
	.read_status	= &genphy_read_status,
	.ack_interrupt	= &vsc824x_ack_interrupt,
	.config_intr	= &vsc82xx_config_intr,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id         = PHY_ID_VSC8574,
	.name           = "Vitesse VSC8574",
	.phy_id_mask    = 0x000ffff0,
	.features       = PHY_GBIT_FEATURES,
	.flags          = PHY_HAS_INTERRUPT,
	.config_init    = &vsc824x_config_init,
	.config_aneg    = &genphy_config_aneg,
	.read_status    = &genphy_read_status,
	.ack_interrupt  = &vsc824x_ack_interrupt,
	.config_intr    = &vsc82xx_config_intr,
	.driver         = { .owner = THIS_MODULE,},
}, {
	.phy_id         = PHY_ID_VSC8662,
	.name           = "Vitesse VSC8662",
	.phy_id_mask    = 0x000ffff0,
	.features       = PHY_GBIT_FEATURES,
	.flags          = PHY_HAS_INTERRUPT,
	.config_init    = &vsc824x_config_init,
	.config_aneg    = &genphy_config_aneg,
	.read_status    = &genphy_read_status,
	.ack_interrupt  = &vsc824x_ack_interrupt,
	.config_intr    = &vsc82xx_config_intr,
	.driver         = { .owner = THIS_MODULE,},
}, {
	/* Vitesse 8221 */
	.phy_id		= PHY_ID_VSC8221,
	.phy_id_mask	= 0x000ffff0,
	.name		= "Vitesse VSC8221",
	.features	= PHY_GBIT_FEATURES,
	.flags		= PHY_HAS_INTERRUPT,
	.config_init	= &vsc8221_config_init,
	.config_aneg	= &genphy_config_aneg,
	.read_status	= &genphy_read_status,
	.ack_interrupt	= &vsc824x_ack_interrupt,
	.config_intr	= &vsc82xx_config_intr,
	.driver		= { .owner = THIS_MODULE,},
}, {
	/* Vitesse 8211 */
	.phy_id		= PHY_ID_VSC8211,
	.phy_id_mask	= 0x000ffff0,
	.name		= "Vitesse VSC8211",
	.features	= PHY_GBIT_FEATURES,
	.flags		= PHY_HAS_INTERRUPT,
	.config_init	= &vsc8221_config_init,
	.config_aneg	= &genphy_config_aneg,
	.read_status	= &genphy_read_status,
	.ack_interrupt	= &vsc824x_ack_interrupt,
	.config_intr	= &vsc82xx_config_intr,
	.driver		= { .owner = THIS_MODULE,},
} };

static int __init vsc82xx_init(void)
{
	return phy_drivers_register(vsc82xx_driver,
		ARRAY_SIZE(vsc82xx_driver));
}

static void __exit vsc82xx_exit(void)
{
	return phy_drivers_unregister(vsc82xx_driver,
		ARRAY_SIZE(vsc82xx_driver));
}

module_init(vsc82xx_init);
module_exit(vsc82xx_exit);

static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
	{ PHY_ID_VSC8234, 0x000ffff0 },
	{ PHY_ID_VSC8244, 0x000fffc0 },
	{ PHY_ID_VSC8574, 0x000ffff0 },
	{ PHY_ID_VSC8662, 0x000ffff0 },
	{ PHY_ID_VSC8221, 0x000ffff0 },
	{ PHY_ID_VSC8211, 0x000ffff0 },
	{ }
};

MODULE_DEVICE_TABLE(mdio, vitesse_tbl);
Commit	Line	Data
ef82a306 JL	1	/*
	2	* Driver for Vitesse PHYs
	3	*
	4	* Author: Kriston Carson
	5	*
fddf86fc	6	* Copyright (c) 2005, 2009 Freescale Semiconductor, Inc.
ef82a306 JL	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	*/
	14
ef82a306 JL	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/mii.h>
	18	#include <linux/ethtool.h>
	19	#include <linux/phy.h>
	20
	21	/* Vitesse Extended Control Register 1 */
	22	#define MII_VSC8244_EXT_CON1 0x17
	23	#define MII_VSC8244_EXTCON1_INIT 0x0000
af2d940d AF	24	#define MII_VSC8244_EXTCON1_TX_SKEW_MASK 0x0c00
	25	#define MII_VSC8244_EXTCON1_RX_SKEW_MASK 0x0300
	26	#define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
	27	#define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
ef82a306 JL	28
	29	/* Vitesse Interrupt Mask Register */
	30	#define MII_VSC8244_IMASK 0x19
	31	#define MII_VSC8244_IMASK_IEN 0x8000
	32	#define MII_VSC8244_IMASK_SPEED 0x4000
	33	#define MII_VSC8244_IMASK_LINK 0x2000
	34	#define MII_VSC8244_IMASK_DUPLEX 0x1000
	35	#define MII_VSC8244_IMASK_MASK 0xf000
	36
11c6dd2c TP	37	#define MII_VSC8221_IMASK_MASK 0xa000
11c6dd2c TP	38
ef82a306 JL	39	/* Vitesse Interrupt Status Register */
	40	#define MII_VSC8244_ISTAT 0x1a
	41	#define MII_VSC8244_ISTAT_STATUS 0x8000
	42	#define MII_VSC8244_ISTAT_SPEED 0x4000
	43	#define MII_VSC8244_ISTAT_LINK 0x2000
	44	#define MII_VSC8244_ISTAT_DUPLEX 0x1000
	45
	46	/* Vitesse Auxiliary Control/Status Register */
2a8626d1 MS	47	#define MII_VSC8244_AUX_CONSTAT 0x1c
	48	#define MII_VSC8244_AUXCONSTAT_INIT 0x0000
	49	#define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
	50	#define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
	51	#define MII_VSC8244_AUXCONSTAT_GBIT 0x0010
	52	#define MII_VSC8244_AUXCONSTAT_100 0x0008
ef82a306	53
11c6dd2c TP	54	#define MII_VSC8221_AUXCONSTAT_INIT 0x0004 /* need to set this bit? */
	55	#define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004
	56
0508019c	57	#define PHY_ID_VSC8234 0x000fc620
11c6dd2c	58	#define PHY_ID_VSC8244 0x000fc6c0
c2efef74	59	#define PHY_ID_VSC8574 0x000704a0
06ae4f84	60	#define PHY_ID_VSC8662 0x00070660
11c6dd2c	61	#define PHY_ID_VSC8221 0x000fc550
5a1cebd8	62	#define PHY_ID_VSC8211 0x000fc4b0
11c6dd2c	63
ef82a306 JL	64	MODULE_DESCRIPTION("Vitesse PHY driver");
	65	MODULE_AUTHOR("Kriston Carson");
	66	MODULE_LICENSE("GPL");
	67
baec126c	68	static int vsc824x_add_skew(struct phy_device *phydev)
ef82a306 JL	69	{
ef82a306 JL	70	int err;
fddf86fc	71	int extcon;
ef82a306	72
af2d940d AF	73	extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
	74
	75	if (extcon < 0)
fddf86fc	76	return extcon;
af2d940d AF	77
	78	extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK \|
	79	MII_VSC8244_EXTCON1_RX_SKEW_MASK);
	80
fddf86fc AF	81	extcon \|= (MII_VSC8244_EXTCON1_TX_SKEW \|
fddf86fc AF	82	MII_VSC8244_EXTCON1_RX_SKEW);
af2d940d AF	83
	84	err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
	85
ef82a306 JL	86	return err;
ef82a306 JL	87	}
fddf86fc AF	88
	89	static int vsc824x_config_init(struct phy_device *phydev)
	90	{
	91	int err;
	92
	93	err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
	94	MII_VSC8244_AUXCONSTAT_INIT);
	95	if (err < 0)
	96	return err;
	97
	98	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
	99	err = vsc824x_add_skew(phydev);
	100
	101	return err;
	102	}
ef82a306 JL	103
	104	static int vsc824x_ack_interrupt(struct phy_device *phydev)
	105	{
1d5e83aa	106	int err = 0;
2a8626d1 MS	107
2a8626d1 MS	108	/* Don't bother to ACK the interrupts if interrupts
1d5e83aa AF	109	* are disabled. The 824x cannot clear the interrupts
	110	* if they are disabled.
	111	*/
	112	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
	113	err = phy_read(phydev, MII_VSC8244_ISTAT);
ef82a306 JL	114
	115	return (err < 0) ? err : 0;
	116	}
	117
11c6dd2c	118	static int vsc82xx_config_intr(struct phy_device *phydev)
ef82a306 JL	119	{
	120	int err;
	121
	122	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
	123	err = phy_write(phydev, MII_VSC8244_IMASK,
0508019c	124	(phydev->drv->phy_id == PHY_ID_VSC8234 \|\|
c2efef74	125	phydev->drv->phy_id == PHY_ID_VSC8244 \|\|
c2efef74	126	phydev->drv->phy_id == PHY_ID_VSC8574) ?
11c6dd2c TP	127	MII_VSC8244_IMASK_MASK :
11c6dd2c TP	128	MII_VSC8221_IMASK_MASK);
1d5e83aa	129	else {
2a8626d1	130	/* The Vitesse PHY cannot clear the interrupt
1d5e83aa AF	131	* once it has disabled them, so we clear them first
	132	*/
	133	err = phy_read(phydev, MII_VSC8244_ISTAT);
	134
52cb1c2b	135	if (err < 0)
1d5e83aa AF	136	return err;
1d5e83aa AF	137
ef82a306	138	err = phy_write(phydev, MII_VSC8244_IMASK, 0);
1d5e83aa AF	139	}
1d5e83aa AF	140
ef82a306 JL	141	return err;
	142	}
	143
11c6dd2c	144	static int vsc8221_config_init(struct phy_device *phydev)
ef82a306	145	{
11c6dd2c TP	146	int err;
	147
	148	err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
	149	MII_VSC8221_AUXCONSTAT_INIT);
	150	return err;
	151
	152	/* Perhaps we should set EXT_CON1 based on the interface?
2a8626d1 MS	153	* Options are 802.3Z SerDes or SGMII
2a8626d1 MS	154	*/
11c6dd2c TP	155	}
11c6dd2c TP	156
0508019c	157	/* Vitesse 82xx */
d5bf9071 CH	158	static struct phy_driver vsc82xx_driver[] = {
d5bf9071 CH	159	{
0508019c AF	160	.phy_id = PHY_ID_VSC8234,
	161	.name = "Vitesse VSC8234",
	162	.phy_id_mask = 0x000ffff0,
	163	.features = PHY_GBIT_FEATURES,
	164	.flags = PHY_HAS_INTERRUPT,
	165	.config_init = &vsc824x_config_init,
	166	.config_aneg = &genphy_config_aneg,
	167	.read_status = &genphy_read_status,
	168	.ack_interrupt = &vsc824x_ack_interrupt,
	169	.config_intr = &vsc82xx_config_intr,
	170	.driver = { .owner = THIS_MODULE,},
	171	}, {
d5bf9071 CH	172	.phy_id = PHY_ID_VSC8244,
	173	.name = "Vitesse VSC8244",
	174	.phy_id_mask = 0x000fffc0,
	175	.features = PHY_GBIT_FEATURES,
	176	.flags = PHY_HAS_INTERRUPT,
	177	.config_init = &vsc824x_config_init,
	178	.config_aneg = &genphy_config_aneg,
	179	.read_status = &genphy_read_status,
	180	.ack_interrupt = &vsc824x_ack_interrupt,
	181	.config_intr = &vsc82xx_config_intr,
	182	.driver = { .owner = THIS_MODULE,},
c2efef74	183	}, {
	184	.phy_id = PHY_ID_VSC8574,
	185	.name = "Vitesse VSC8574",
	186	.phy_id_mask = 0x000ffff0,
	187	.features = PHY_GBIT_FEATURES,
	188	.flags = PHY_HAS_INTERRUPT,
	189	.config_init = &vsc824x_config_init,
	190	.config_aneg = &genphy_config_aneg,
	191	.read_status = &genphy_read_status,
	192	.ack_interrupt = &vsc824x_ack_interrupt,
	193	.config_intr = &vsc82xx_config_intr,
	194	.driver = { .owner = THIS_MODULE,},
06ae4f84 SS	195	}, {
	196	.phy_id = PHY_ID_VSC8662,
	197	.name = "Vitesse VSC8662",
	198	.phy_id_mask = 0x000ffff0,
	199	.features = PHY_GBIT_FEATURES,
	200	.flags = PHY_HAS_INTERRUPT,
	201	.config_init = &vsc824x_config_init,
	202	.config_aneg = &genphy_config_aneg,
	203	.read_status = &genphy_read_status,
	204	.ack_interrupt = &vsc824x_ack_interrupt,
	205	.config_intr = &vsc82xx_config_intr,
	206	.driver = { .owner = THIS_MODULE,},
d5bf9071 CH	207	}, {
d5bf9071 CH	208	/* Vitesse 8221 */
11c6dd2c TP	209	.phy_id = PHY_ID_VSC8221,
	210	.phy_id_mask = 0x000ffff0,
	211	.name = "Vitesse VSC8221",
	212	.features = PHY_GBIT_FEATURES,
	213	.flags = PHY_HAS_INTERRUPT,
	214	.config_init = &vsc8221_config_init,
	215	.config_aneg = &genphy_config_aneg,
	216	.read_status = &genphy_read_status,
	217	.ack_interrupt = &vsc824x_ack_interrupt,
	218	.config_intr = &vsc82xx_config_intr,
d5bf9071	219	.driver = { .owner = THIS_MODULE,},
5a1cebd8 MS	220	}, {
	221	/* Vitesse 8211 */
	222	.phy_id = PHY_ID_VSC8211,
	223	.phy_id_mask = 0x000ffff0,
	224	.name = "Vitesse VSC8211",
	225	.features = PHY_GBIT_FEATURES,
	226	.flags = PHY_HAS_INTERRUPT,
	227	.config_init = &vsc8221_config_init,
	228	.config_aneg = &genphy_config_aneg,
	229	.read_status = &genphy_read_status,
	230	.ack_interrupt = &vsc824x_ack_interrupt,
	231	.config_intr = &vsc82xx_config_intr,
	232	.driver = { .owner = THIS_MODULE,},
d5bf9071	233	} };
11c6dd2c TP	234
	235	static int __init vsc82xx_init(void)
	236	{
d5bf9071 CH	237	return phy_drivers_register(vsc82xx_driver,
d5bf9071 CH	238	ARRAY_SIZE(vsc82xx_driver));
ef82a306 JL	239	}
ef82a306 JL	240
11c6dd2c	241	static void __exit vsc82xx_exit(void)
ef82a306	242	{
d5bf9071 CH	243	return phy_drivers_unregister(vsc82xx_driver,
d5bf9071 CH	244	ARRAY_SIZE(vsc82xx_driver));
ef82a306 JL	245	}
ef82a306 JL	246
11c6dd2c TP	247	module_init(vsc82xx_init);
11c6dd2c TP	248	module_exit(vsc82xx_exit);
4e4f10f6	249
cf93c945	250	static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
0508019c	251	{ PHY_ID_VSC8234, 0x000ffff0 },
4e4f10f6	252	{ PHY_ID_VSC8244, 0x000fffc0 },
c2efef74	253	{ PHY_ID_VSC8574, 0x000ffff0 },
06ae4f84	254	{ PHY_ID_VSC8662, 0x000ffff0 },
4e4f10f6	255	{ PHY_ID_VSC8221, 0x000ffff0 },
5a1cebd8	256	{ PHY_ID_VSC8211, 0x000ffff0 },
4e4f10f6 DW	257	{ }
	258	};
	259
	260	MODULE_DEVICE_TABLE(mdio, vitesse_tbl);