net: ethernet: macb: Add support for rx_clk
[deliverable/linux.git] / drivers / net / phy / xilinx_gmii2rgmii.c
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1/* Xilinx GMII2RGMII Converter driver
2 *
3 * Copyright (C) 2016 Xilinx, Inc.
4 *
5 * Author: Kedareswara rao Appana <appanad@xilinx.com>
6 *
7 * Description:
8 * This driver is developed for Xilinx GMII2RGMII Converter
9 *
10 * This program is free software: you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation, either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/mii.h>
23#include <linux/mdio.h>
24#include <linux/phy.h>
25#include <linux/of_mdio.h>
26
27#define XILINX_GMII2RGMII_REG 0x10
28#define XILINX_GMII2RGMII_SPEED_MASK (BMCR_SPEED1000 | BMCR_SPEED100)
29
30struct gmii2rgmii {
31 struct phy_device *phy_dev;
32 struct phy_driver *phy_drv;
33 struct phy_driver conv_phy_drv;
34 int addr;
35};
36
37static int xgmiitorgmii_read_status(struct phy_device *phydev)
38{
39 struct gmii2rgmii *priv = phydev->priv;
40 u16 val = 0;
41
42 priv->phy_drv->read_status(phydev);
43
44 val = mdiobus_read(phydev->mdio.bus, priv->addr, XILINX_GMII2RGMII_REG);
45 val &= XILINX_GMII2RGMII_SPEED_MASK;
46
47 if (phydev->speed == SPEED_1000)
48 val |= BMCR_SPEED1000;
49 else if (phydev->speed == SPEED_100)
50 val |= BMCR_SPEED100;
51 else
52 val |= BMCR_SPEED10;
53
54 mdiobus_write(phydev->mdio.bus, priv->addr, XILINX_GMII2RGMII_REG, val);
55
56 return 0;
57}
58
59int xgmiitorgmii_probe(struct mdio_device *mdiodev)
60{
61 struct device *dev = &mdiodev->dev;
62 struct device_node *np = dev->of_node, *phy_node;
63 struct gmii2rgmii *priv;
64
65 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
66 if (!priv)
67 return -ENOMEM;
68
69 phy_node = of_parse_phandle(np, "phy-handle", 0);
64721094 70 if (!phy_node) {
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71 dev_err(dev, "Couldn't parse phy-handle\n");
72 return -ENODEV;
73 }
74
75 priv->phy_dev = of_phy_find_device(phy_node);
76 if (!priv->phy_dev) {
77 dev_info(dev, "Couldn't find phydev\n");
78 return -EPROBE_DEFER;
79 }
80
81 priv->addr = mdiodev->addr;
82 priv->phy_drv = priv->phy_dev->drv;
83 memcpy(&priv->conv_phy_drv, priv->phy_dev->drv,
84 sizeof(struct phy_driver));
85 priv->conv_phy_drv.read_status = xgmiitorgmii_read_status;
86 priv->phy_dev->priv = priv;
87 priv->phy_dev->drv = &priv->conv_phy_drv;
88
89 return 0;
90}
91
92static const struct of_device_id xgmiitorgmii_of_match[] = {
93 { .compatible = "xlnx,gmii-to-rgmii-1.0" },
94 {},
95};
96MODULE_DEVICE_TABLE(of, xgmiitorgmii_of_match);
97
98static struct mdio_driver xgmiitorgmii_driver = {
99 .probe = xgmiitorgmii_probe,
100 .mdiodrv.driver = {
101 .name = "xgmiitorgmii",
102 .of_match_table = xgmiitorgmii_of_match,
103 },
104};
105
106mdio_module_driver(xgmiitorgmii_driver);
107
108MODULE_DESCRIPTION("Xilinx GMII2RGMII converter driver");
109MODULE_LICENSE("GPL");
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