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[netdrvr] Stop using legacy hooks ->self_test_count, ->get_stats_count
[deliverable/linux.git] / drivers / net / qla3xxx.c
CommitLineData
5a4faa87
RM		 1/*
2 * QLogic QLA3xxx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qla3xxx for copyright and licensing details.
6 */
7
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/list.h>
13#include <linux/pci.h>
14#include <linux/dma-mapping.h>
15#include <linux/sched.h>
16#include <linux/slab.h>
17#include <linux/dmapool.h>
18#include <linux/mempool.h>
19#include <linux/spinlock.h>
20#include <linux/kthread.h>
21#include <linux/interrupt.h>
22#include <linux/errno.h>
23#include <linux/ioport.h>
24#include <linux/ip.h>
bd36b0ac 25#include <linux/in.h>
5a4faa87
RM		 26#include <linux/if_arp.h>
27#include <linux/if_ether.h>
28#include <linux/netdevice.h>
29#include <linux/etherdevice.h>
30#include <linux/ethtool.h>
31#include <linux/skbuff.h>
32#include <linux/rtnetlink.h>
33#include <linux/if_vlan.h>
5a4faa87
RM		 34#include <linux/delay.h>
35#include <linux/mm.h>
36
37#include "qla3xxx.h"
38
39#define DRV_NAME "qla3xxx"
40#define DRV_STRING "QLogic ISP3XXX Network Driver"
201f27e6 41#define DRV_VERSION "v2.03.00-k4"
5a4faa87
RM		 42#define PFX DRV_NAME " "
43
44static const char ql3xxx_driver_name[] = DRV_NAME;
45static const char ql3xxx_driver_version[] = DRV_VERSION;
46
47MODULE_AUTHOR("QLogic Corporation");
48MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
49MODULE_LICENSE("GPL");
50MODULE_VERSION(DRV_VERSION);
51
52static const u32 default_msg
53 = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
54 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
55
56static int debug = -1; /* defaults above */
57module_param(debug, int, 0);
58MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
59
60static int msi;
61module_param(msi, int, 0);
62MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
63
64static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
65 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
bd36b0ac 66 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
5a4faa87
RM		 67 /* required last entry */
68 {0,}
69};
70
71MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
72
3efedf2e
RM		 73/*
74 * These are the known PHY's which are used
75 */
76typedef enum {
77 PHY_TYPE_UNKNOWN = 0,
78 PHY_VITESSE_VSC8211,
79 PHY_AGERE_ET1011C,
80 MAX_PHY_DEV_TYPES
81} PHY_DEVICE_et;
82
83typedef struct {
84 PHY_DEVICE_et phyDevice;
85 u32 phyIdOUI;
86 u16 phyIdModel;
87 char *name;
88} PHY_DEVICE_INFO_t;
89
b1fc1fa9 90static const PHY_DEVICE_INFO_t PHY_DEVICES[] =
3efedf2e
RM		 91 {{PHY_TYPE_UNKNOWN, 0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
92 {PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
93 {PHY_AGERE_ET1011C, 0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
94};
95
96
5a4faa87
RM		 97/*
98 * Caller must take hw_lock.
99 */
100static int ql_sem_spinlock(struct ql3_adapter *qdev,
101 u32 sem_mask, u32 sem_bits)
102{
103 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
104 u32 value;
105 unsigned int seconds = 3;
106
107 do {
108 writel((sem_mask | sem_bits),
109 &port_regs->CommonRegs.semaphoreReg);
110 value = readl(&port_regs->CommonRegs.semaphoreReg);
111 if ((value & (sem_mask >> 16)) == sem_bits)
112 return 0;
113 ssleep(1);
114 } while(--seconds);
115 return -1;
116}
117
118static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
119{
120 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
121 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
122 readl(&port_regs->CommonRegs.semaphoreReg);
123}
124
125static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
126{
127 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
128 u32 value;
129
130 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
131 value = readl(&port_regs->CommonRegs.semaphoreReg);
132 return ((value & (sem_mask >> 16)) == sem_bits);
133}
134
135/*
136 * Caller holds hw_lock.
137 */
138static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
139{
140 int i = 0;
141
142 while (1) {
143 if (!ql_sem_lock(qdev,
144 QL_DRVR_SEM_MASK,
145 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
146 * 2) << 1)) {
147 if (i < 10) {
148 ssleep(1);
149 i++;
150 } else {
151 printk(KERN_ERR PFX "%s: Timed out waiting for "
152 "driver lock...\n",
153 qdev->ndev->name);
154 return 0;
155 }
156 } else {
157 printk(KERN_DEBUG PFX
158 "%s: driver lock acquired.\n",
159 qdev->ndev->name);
160 return 1;
161 }
162 }
163}
164
165static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
166{
167 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
168
169 writel(((ISP_CONTROL_NP_MASK << 16) | page),
170 &port_regs->CommonRegs.ispControlStatus);
171 readl(&port_regs->CommonRegs.ispControlStatus);
172 qdev->current_page = page;
173}
174
175static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
176 u32 __iomem * reg)
177{
178 u32 value;
179 unsigned long hw_flags;
180
181 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
182 value = readl(reg);
183 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
184
185 return value;
186}
187
188static u32 ql_read_common_reg(struct ql3_adapter *qdev,
189 u32 __iomem * reg)
190{
191 return readl(reg);
192}
193
194static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
195{
196 u32 value;
197 unsigned long hw_flags;
198
199 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
200
201 if (qdev->current_page != 0)
202 ql_set_register_page(qdev,0);
203 value = readl(reg);
204
205 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
206 return value;
207}
208
209static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
210{
211 if (qdev->current_page != 0)
212 ql_set_register_page(qdev,0);
213 return readl(reg);
214}
215
216static void ql_write_common_reg_l(struct ql3_adapter *qdev,
ee111d11 217 u32 __iomem *reg, u32 value)
5a4faa87
RM		 218{
219 unsigned long hw_flags;
220
221 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
ee111d11 222 writel(value, reg);
5a4faa87
RM		 223 readl(reg);
224 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
225 return;
226}
227
228static void ql_write_common_reg(struct ql3_adapter *qdev,
ee111d11 229 u32 __iomem *reg, u32 value)
5a4faa87 230{
ee111d11 231 writel(value, reg);
5a4faa87
RM		 232 readl(reg);
233 return;
234}
235
80b02e59
RM		 236static void ql_write_nvram_reg(struct ql3_adapter *qdev,
237 u32 __iomem *reg, u32 value)
238{
239 writel(value, reg);
240 readl(reg);
241 udelay(1);
242 return;
243}
244
5a4faa87 245static void ql_write_page0_reg(struct ql3_adapter *qdev,
ee111d11 246 u32 __iomem *reg, u32 value)
5a4faa87
RM		 247{
248 if (qdev->current_page != 0)
249 ql_set_register_page(qdev,0);
ee111d11 250 writel(value, reg);
5a4faa87
RM		 251 readl(reg);
252 return;
253}
254
255/*
256 * Caller holds hw_lock. Only called during init.
257 */
258static void ql_write_page1_reg(struct ql3_adapter *qdev,
ee111d11 259 u32 __iomem *reg, u32 value)
5a4faa87
RM		 260{
261 if (qdev->current_page != 1)
262 ql_set_register_page(qdev,1);
ee111d11 263 writel(value, reg);
5a4faa87
RM		 264 readl(reg);
265 return;
266}
267
268/*
269 * Caller holds hw_lock. Only called during init.
270 */
271static void ql_write_page2_reg(struct ql3_adapter *qdev,
ee111d11 272 u32 __iomem *reg, u32 value)
5a4faa87
RM		 273{
274 if (qdev->current_page != 2)
275 ql_set_register_page(qdev,2);
ee111d11 276 writel(value, reg);
5a4faa87
RM		 277 readl(reg);
278 return;
279}
280
281static void ql_disable_interrupts(struct ql3_adapter *qdev)
282{
283 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
284
285 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
286 (ISP_IMR_ENABLE_INT << 16));
287
288}
289
290static void ql_enable_interrupts(struct ql3_adapter *qdev)
291{
292 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
293
294 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
295 ((0xff << 16) | ISP_IMR_ENABLE_INT));
296
297}
298
299static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
300 struct ql_rcv_buf_cb *lrg_buf_cb)
301{
0f8ab89e
BL		 302 dma_addr_t map;
303 int err;
5a4faa87
RM		 304 lrg_buf_cb->next = NULL;
305
306 if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */
307 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
308 } else {
309 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
310 qdev->lrg_buf_free_tail = lrg_buf_cb;
311 }
312
313 if (!lrg_buf_cb->skb) {
cd238faa
BL		 314 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
315 qdev->lrg_buffer_len);
5a4faa87 316 if (unlikely(!lrg_buf_cb->skb)) {
cd238faa 317 printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
5a4faa87
RM		 318 qdev->ndev->name);
319 qdev->lrg_buf_skb_check++;
320 } else {
321 /*
322 * We save some space to copy the ethhdr from first
323 * buffer
324 */
325 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
326 map = pci_map_single(qdev->pdev,
327 lrg_buf_cb->skb->data,
328 qdev->lrg_buffer_len -
329 QL_HEADER_SPACE,
330 PCI_DMA_FROMDEVICE);
0f8ab89e
BL		 331 err = pci_dma_mapping_error(map);
332 if(err) {
333 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
334 qdev->ndev->name, err);
335 dev_kfree_skb(lrg_buf_cb->skb);
336 lrg_buf_cb->skb = NULL;
337
338 qdev->lrg_buf_skb_check++;
339 return;
340 }
341
5a4faa87
RM		 342 lrg_buf_cb->buf_phy_addr_low =
343 cpu_to_le32(LS_64BITS(map));
344 lrg_buf_cb->buf_phy_addr_high =
345 cpu_to_le32(MS_64BITS(map));
346 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
347 pci_unmap_len_set(lrg_buf_cb, maplen,
348 qdev->lrg_buffer_len -
349 QL_HEADER_SPACE);
350 }
351 }
352
353 qdev->lrg_buf_free_count++;
354}
355
356static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
357 *qdev)
358{
359 struct ql_rcv_buf_cb *lrg_buf_cb;
360
361 if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
362 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
363 qdev->lrg_buf_free_tail = NULL;
364 qdev->lrg_buf_free_count--;
365 }
366
367 return lrg_buf_cb;
368}
369
370static u32 addrBits = EEPROM_NO_ADDR_BITS;
371static u32 dataBits = EEPROM_NO_DATA_BITS;
372
373static void fm93c56a_deselect(struct ql3_adapter *qdev);
374static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
375 unsigned short *value);
376
377/*
378 * Caller holds hw_lock.
379 */
380static void fm93c56a_select(struct ql3_adapter *qdev)
381{
382 struct ql3xxx_port_registers __iomem *port_regs =
383 qdev->mem_map_registers;
384
385 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
80b02e59 386 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87 387 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
80b02e59 388 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 389 ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
390}
391
392/*
393 * Caller holds hw_lock.
394 */
395static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
396{
397 int i;
398 u32 mask;
399 u32 dataBit;
400 u32 previousBit;
401 struct ql3xxx_port_registers __iomem *port_regs =
402 qdev->mem_map_registers;
403
404 /* Clock in a zero, then do the start bit */
80b02e59 405 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 406 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
407 AUBURN_EEPROM_DO_1);
80b02e59 408 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 409 ISP_NVRAM_MASK | qdev->
410 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
411 AUBURN_EEPROM_CLK_RISE);
80b02e59 412 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 413 ISP_NVRAM_MASK | qdev->
414 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
415 AUBURN_EEPROM_CLK_FALL);
416
417 mask = 1 << (FM93C56A_CMD_BITS - 1);
418 /* Force the previous data bit to be different */
419 previousBit = 0xffff;
420 for (i = 0; i < FM93C56A_CMD_BITS; i++) {
421 dataBit =
422 (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
423 if (previousBit != dataBit) {
424 /*
425 * If the bit changed, then change the DO state to
426 * match
427 */
80b02e59 428 ql_write_nvram_reg(qdev,
5a4faa87
RM		 429 &port_regs->CommonRegs.
430 serialPortInterfaceReg,
431 ISP_NVRAM_MASK | qdev->
432 eeprom_cmd_data | dataBit);
433 previousBit = dataBit;
434 }
80b02e59 435 ql_write_nvram_reg(qdev,
5a4faa87
RM		 436 &port_regs->CommonRegs.
437 serialPortInterfaceReg,
438 ISP_NVRAM_MASK | qdev->
439 eeprom_cmd_data | dataBit |
440 AUBURN_EEPROM_CLK_RISE);
80b02e59 441 ql_write_nvram_reg(qdev,
5a4faa87
RM		 442 &port_regs->CommonRegs.
443 serialPortInterfaceReg,
444 ISP_NVRAM_MASK | qdev->
445 eeprom_cmd_data | dataBit |
446 AUBURN_EEPROM_CLK_FALL);
447 cmd = cmd << 1;
448 }
449
450 mask = 1 << (addrBits - 1);
451 /* Force the previous data bit to be different */
452 previousBit = 0xffff;
453 for (i = 0; i < addrBits; i++) {
454 dataBit =
455 (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
456 AUBURN_EEPROM_DO_0;
457 if (previousBit != dataBit) {
458 /*
459 * If the bit changed, then change the DO state to
460 * match
461 */
80b02e59 462 ql_write_nvram_reg(qdev,
5a4faa87
RM		 463 &port_regs->CommonRegs.
464 serialPortInterfaceReg,
465 ISP_NVRAM_MASK | qdev->
466 eeprom_cmd_data | dataBit);
467 previousBit = dataBit;
468 }
80b02e59 469 ql_write_nvram_reg(qdev,
5a4faa87
RM		 470 &port_regs->CommonRegs.
471 serialPortInterfaceReg,
472 ISP_NVRAM_MASK | qdev->
473 eeprom_cmd_data | dataBit |
474 AUBURN_EEPROM_CLK_RISE);
80b02e59 475 ql_write_nvram_reg(qdev,
5a4faa87
RM		 476 &port_regs->CommonRegs.
477 serialPortInterfaceReg,
478 ISP_NVRAM_MASK | qdev->
479 eeprom_cmd_data | dataBit |
480 AUBURN_EEPROM_CLK_FALL);
481 eepromAddr = eepromAddr << 1;
482 }
483}
484
485/*
486 * Caller holds hw_lock.
487 */
488static void fm93c56a_deselect(struct ql3_adapter *qdev)
489{
490 struct ql3xxx_port_registers __iomem *port_regs =
491 qdev->mem_map_registers;
492 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
80b02e59 493 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 494 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
495}
496
497/*
498 * Caller holds hw_lock.
499 */
500static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
501{
502 int i;
503 u32 data = 0;
504 u32 dataBit;
505 struct ql3xxx_port_registers __iomem *port_regs =
506 qdev->mem_map_registers;
507
508 /* Read the data bits */
509 /* The first bit is a dummy. Clock right over it. */
510 for (i = 0; i < dataBits; i++) {
80b02e59 511 ql_write_nvram_reg(qdev,
5a4faa87
RM		 512 &port_regs->CommonRegs.
513 serialPortInterfaceReg,
514 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
515 AUBURN_EEPROM_CLK_RISE);
80b02e59 516 ql_write_nvram_reg(qdev,
5a4faa87
RM		 517 &port_regs->CommonRegs.
518 serialPortInterfaceReg,
519 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
520 AUBURN_EEPROM_CLK_FALL);
521 dataBit =
522 (ql_read_common_reg
523 (qdev,
524 &port_regs->CommonRegs.
525 serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
526 data = (data << 1) | dataBit;
527 }
528 *value = (u16) data;
529}
530
531/*
532 * Caller holds hw_lock.
533 */
534static void eeprom_readword(struct ql3_adapter *qdev,
535 u32 eepromAddr, unsigned short *value)
536{
537 fm93c56a_select(qdev);
538 fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
539 fm93c56a_datain(qdev, value);
540 fm93c56a_deselect(qdev);
541}
542
543static void ql_swap_mac_addr(u8 * macAddress)
544{
545#ifdef __BIG_ENDIAN
546 u8 temp;
547 temp = macAddress[0];
548 macAddress[0] = macAddress[1];
549 macAddress[1] = temp;
550 temp = macAddress[2];
551 macAddress[2] = macAddress[3];
552 macAddress[3] = temp;
553 temp = macAddress[4];
554 macAddress[4] = macAddress[5];
555 macAddress[5] = temp;
556#endif
557}
558
559static int ql_get_nvram_params(struct ql3_adapter *qdev)
560{
561 u16 *pEEPROMData;
562 u16 checksum = 0;
563 u32 index;
564 unsigned long hw_flags;
565
566 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
567
568 pEEPROMData = (u16 *) & qdev->nvram_data;
569 qdev->eeprom_cmd_data = 0;
570 if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
571 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
572 2) << 10)) {
573 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
574 __func__);
575 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
576 return -1;
577 }
578
579 for (index = 0; index < EEPROM_SIZE; index++) {
580 eeprom_readword(qdev, index, pEEPROMData);
581 checksum += *pEEPROMData;
582 pEEPROMData++;
583 }
584 ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
585
586 if (checksum != 0) {
587 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
588 qdev->ndev->name, checksum);
589 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
590 return -1;
591 }
592
593 /*
594 * We have a problem with endianness for the MAC addresses
595 * and the two 8-bit values version, and numPorts. We
596 * have to swap them on big endian systems.
597 */
598 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn0.macAddress);
599 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn1.macAddress);
600 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn2.macAddress);
601 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn3.macAddress);
602 pEEPROMData = (u16 *) & qdev->nvram_data.version;
603 *pEEPROMData = le16_to_cpu(*pEEPROMData);
604
605 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
606 return checksum;
607}
608
609static const u32 PHYAddr[2] = {
610 PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
611};
612
613static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
614{
615 struct ql3xxx_port_registers __iomem *port_regs =
616 qdev->mem_map_registers;
617 u32 temp;
618 int count = 1000;
619
620 while (count) {
621 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
622 if (!(temp & MAC_MII_STATUS_BSY))
623 return 0;
624 udelay(10);
625 count--;
626 }
627 return -1;
628}
629
630static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
631{
632 struct ql3xxx_port_registers __iomem *port_regs =
633 qdev->mem_map_registers;
634 u32 scanControl;
635
636 if (qdev->numPorts > 1) {
637 /* Auto scan will cycle through multiple ports */
638 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
639 } else {
640 scanControl = MAC_MII_CONTROL_SC;
641 }
642
643 /*
644 * Scan register 1 of PHY/PETBI,
645 * Set up to scan both devices
646 * The autoscan starts from the first register, completes
647 * the last one before rolling over to the first
648 */
649 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
650 PHYAddr[0] | MII_SCAN_REGISTER);
651
652 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
653 (scanControl) |
654 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
655}
656
657static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
658{
659 u8 ret;
660 struct ql3xxx_port_registers __iomem *port_regs =
661 qdev->mem_map_registers;
662
663 /* See if scan mode is enabled before we turn it off */
664 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
665 (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
666 /* Scan is enabled */
667 ret = 1;
668 } else {
669 /* Scan is disabled */
670 ret = 0;
671 }
672
673 /*
674 * When disabling scan mode you must first change the MII register
675 * address
676 */
677 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
678 PHYAddr[0] | MII_SCAN_REGISTER);
679
680 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
681 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
682 MAC_MII_CONTROL_RC) << 16));
683
684 return ret;
685}
686
687static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
3efedf2e 688 u16 regAddr, u16 value, u32 phyAddr)
5a4faa87
RM		 689{
690 struct ql3xxx_port_registers __iomem *port_regs =
691 qdev->mem_map_registers;
692 u8 scanWasEnabled;
693
694 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
695
696 if (ql_wait_for_mii_ready(qdev)) {
697 if (netif_msg_link(qdev))
698 printk(KERN_WARNING PFX
699 "%s Timed out waiting for management port to "
700 "get free before issuing command.\n",
701 qdev->ndev->name);
702 return -1;
703 }
704
705 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
3efedf2e 706 phyAddr | regAddr);
5a4faa87
RM		 707
708 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
709
710 /* Wait for write to complete 9/10/04 SJP */
711 if (ql_wait_for_mii_ready(qdev)) {
712 if (netif_msg_link(qdev))
713 printk(KERN_WARNING PFX
714 "%s: Timed out waiting for management port to"
715 "get free before issuing command.\n",
716 qdev->ndev->name);
717 return -1;
718 }
719
720 if (scanWasEnabled)
721 ql_mii_enable_scan_mode(qdev);
722
723 return 0;
724}
725
726static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
3efedf2e 727 u16 * value, u32 phyAddr)
5a4faa87
RM		 728{
729 struct ql3xxx_port_registers __iomem *port_regs =
730 qdev->mem_map_registers;
731 u8 scanWasEnabled;
732 u32 temp;
733
734 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
735
736 if (ql_wait_for_mii_ready(qdev)) {
737 if (netif_msg_link(qdev))
738 printk(KERN_WARNING PFX
739 "%s: Timed out waiting for management port to "
740 "get free before issuing command.\n",
741 qdev->ndev->name);
742 return -1;
743 }
744
745 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
3efedf2e 746 phyAddr | regAddr);
5a4faa87
RM		 747
748 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
749 (MAC_MII_CONTROL_RC << 16));
750
751 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
752 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
753
754 /* Wait for the read to complete */
755 if (ql_wait_for_mii_ready(qdev)) {
756 if (netif_msg_link(qdev))
757 printk(KERN_WARNING PFX
758 "%s: Timed out waiting for management port to "
759 "get free after issuing command.\n",
760 qdev->ndev->name);
761 return -1;
762 }
763
764 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
765 *value = (u16) temp;
766
767 if (scanWasEnabled)
768 ql_mii_enable_scan_mode(qdev);
769
770 return 0;
771}
772
773static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
774{
775 struct ql3xxx_port_registers __iomem *port_regs =
776 qdev->mem_map_registers;
777
778 ql_mii_disable_scan_mode(qdev);
779
780 if (ql_wait_for_mii_ready(qdev)) {
781 if (netif_msg_link(qdev))
782 printk(KERN_WARNING PFX
783 "%s: Timed out waiting for management port to "
784 "get free before issuing command.\n",
785 qdev->ndev->name);
786 return -1;
787 }
788
789 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
790 qdev->PHYAddr | regAddr);
791
792 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
793
794 /* Wait for write to complete. */
795 if (ql_wait_for_mii_ready(qdev)) {
796 if (netif_msg_link(qdev))
797 printk(KERN_WARNING PFX
798 "%s: Timed out waiting for management port to "
799 "get free before issuing command.\n",
800 qdev->ndev->name);
801 return -1;
802 }
803
804 ql_mii_enable_scan_mode(qdev);
805
806 return 0;
807}
808
809static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
810{
811 u32 temp;
812 struct ql3xxx_port_registers __iomem *port_regs =
813 qdev->mem_map_registers;
814
815 ql_mii_disable_scan_mode(qdev);
816
817 if (ql_wait_for_mii_ready(qdev)) {
818 if (netif_msg_link(qdev))
819 printk(KERN_WARNING PFX
820 "%s: Timed out waiting for management port to "
821 "get free before issuing command.\n",
822 qdev->ndev->name);
823 return -1;
824 }
825
826 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
827 qdev->PHYAddr | regAddr);
828
829 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
830 (MAC_MII_CONTROL_RC << 16));
831
832 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
833 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
834
835 /* Wait for the read to complete */
836 if (ql_wait_for_mii_ready(qdev)) {
837 if (netif_msg_link(qdev))
838 printk(KERN_WARNING PFX
839 "%s: Timed out waiting for management port to "
840 "get free before issuing command.\n",
841 qdev->ndev->name);
842 return -1;
843 }
844
845 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
846 *value = (u16) temp;
847
848 ql_mii_enable_scan_mode(qdev);
849
850 return 0;
851}
852
853static void ql_petbi_reset(struct ql3_adapter *qdev)
854{
855 ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
856}
857
858static void ql_petbi_start_neg(struct ql3_adapter *qdev)
859{
860 u16 reg;
861
862 /* Enable Auto-negotiation sense */
863 ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
864 reg |= PETBI_TBI_AUTO_SENSE;
865 ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
866
867 ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
868 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
869
870 ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
871 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
872 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
873
874}
875
3efedf2e 876static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
5a4faa87
RM		 877{
878 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
3efedf2e 879 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 880}
881
3efedf2e 882static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
5a4faa87
RM		 883{
884 u16 reg;
885
886 /* Enable Auto-negotiation sense */
3efedf2e
RM		 887 ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg,
888 PHYAddr[qdev->mac_index]);
5a4faa87 889 reg |= PETBI_TBI_AUTO_SENSE;
3efedf2e
RM		 890 ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg,
891 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 892
893 ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
3efedf2e
RM		 894 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX,
895 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 896
897 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
898 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
899 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
3efedf2e 900 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 901}
902
903static void ql_petbi_init(struct ql3_adapter *qdev)
904{
905 ql_petbi_reset(qdev);
906 ql_petbi_start_neg(qdev);
907}
908
3efedf2e 909static void ql_petbi_init_ex(struct ql3_adapter *qdev)
5a4faa87 910{
3efedf2e
RM		 911 ql_petbi_reset_ex(qdev);
912 ql_petbi_start_neg_ex(qdev);
5a4faa87
RM		 913}
914
915static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
916{
917 u16 reg;
918
919 if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
920 return 0;
921
922 return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
923}
924
3efedf2e
RM		 925static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
926{
927 printk(KERN_INFO "%s: enabling Agere specific PHY\n", qdev->ndev->name);
928 /* power down device bit 11 = 1 */
929 ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);
930 /* enable diagnostic mode bit 2 = 1 */
931 ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);
932 /* 1000MB amplitude adjust (see Agere errata) */
933 ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);
934 /* 1000MB amplitude adjust (see Agere errata) */
935 ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);
936 /* 100MB amplitude adjust (see Agere errata) */
937 ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);
938 /* 100MB amplitude adjust (see Agere errata) */
939 ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);
940 /* 10MB amplitude adjust (see Agere errata) */
941 ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);
942 /* 10MB amplitude adjust (see Agere errata) */
943 ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);
944 /* point to hidden reg 0x2806 */
945 ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);
946 /* Write new PHYAD w/bit 5 set */
947 ql_mii_write_reg_ex(qdev, 0x11, 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);
948 /*
949 * Disable diagnostic mode bit 2 = 0
950 * Power up device bit 11 = 0
951 * Link up (on) and activity (blink)
952 */
953 ql_mii_write_reg(qdev, 0x12, 0x840a);
954 ql_mii_write_reg(qdev, 0x00, 0x1140);
955 ql_mii_write_reg(qdev, 0x1c, 0xfaf0);
956}
957
958static PHY_DEVICE_et getPhyType (struct ql3_adapter *qdev,
959 u16 phyIdReg0, u16 phyIdReg1)
960{
961 PHY_DEVICE_et result = PHY_TYPE_UNKNOWN;
962 u32 oui;
963 u16 model;
964 int i;
965
966 if (phyIdReg0 == 0xffff) {
967 return result;
968 }
969
970 if (phyIdReg1 == 0xffff) {
971 return result;
972 }
973
974 /* oui is split between two registers */
975 oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
976
977 model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
978
979 /* Scan table for this PHY */
980 for(i = 0; i < MAX_PHY_DEV_TYPES; i++) {
981 if ((oui == PHY_DEVICES[i].phyIdOUI) && (model == PHY_DEVICES[i].phyIdModel))
982 {
983 result = PHY_DEVICES[i].phyDevice;
984
985 printk(KERN_INFO "%s: Phy: %s\n",
986 qdev->ndev->name, PHY_DEVICES[i].name);
987
988 break;
989 }
990 }
991
992 return result;
993}
994
5a4faa87
RM		 995static int ql_phy_get_speed(struct ql3_adapter *qdev)
996{
997 u16 reg;
998
3efedf2e
RM		 999 switch(qdev->phyType) {
1000 case PHY_AGERE_ET1011C:
1001 {
1002 if (ql_mii_read_reg(qdev, 0x1A, &reg) < 0)
1003 return 0;
1004
1005 reg = (reg >> 8) & 3;
1006 break;
1007 }
1008 default:
5a4faa87
RM		 1009 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
1010 return 0;
1011
1012 reg = (((reg & 0x18) >> 3) & 3);
3efedf2e 1013 }
5a4faa87 1014
3efedf2e
RM		 1015 switch(reg) {
1016 case 2:
5a4faa87 1017 return SPEED_1000;
3efedf2e 1018 case 1:
5a4faa87 1019 return SPEED_100;
3efedf2e 1020 case 0:
5a4faa87 1021 return SPEED_10;
3efedf2e 1022 default:
5a4faa87 1023 return -1;
3efedf2e 1024 }
5a4faa87
RM		 1025}
1026
1027static int ql_is_full_dup(struct ql3_adapter *qdev)
1028{
1029 u16 reg;
1030
3efedf2e
RM		 1031 switch(qdev->phyType) {
1032 case PHY_AGERE_ET1011C:
1033 {
1034 if (ql_mii_read_reg(qdev, 0x1A, &reg))
1035 return 0;
1036
1037 return ((reg & 0x0080) && (reg & 0x1000)) != 0;
1038 }
1039 case PHY_VITESSE_VSC8211:
1040 default:
1041 {
1042 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
1043 return 0;
1044 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
1045 }
1046 }
5a4faa87
RM		 1047}
1048
1049static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
1050{
1051 u16 reg;
1052
1053 if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
1054 return 0;
1055
1056 return (reg & PHY_NEG_PAUSE) != 0;
1057}
1058
3efedf2e
RM		 1059static int PHY_Setup(struct ql3_adapter *qdev)
1060{
1061 u16 reg1;
1062 u16 reg2;
1063 bool agereAddrChangeNeeded = false;
1064 u32 miiAddr = 0;
1065 int err;
1066
1067 /* Determine the PHY we are using by reading the ID's */
1068 err = ql_mii_read_reg(qdev, PHY_ID_0_REG, &reg1);
1069 if(err != 0) {
1070 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
1071 qdev->ndev->name);
1072 return err;
1073 }
1074
1075 err = ql_mii_read_reg(qdev, PHY_ID_1_REG, &reg2);
1076 if(err != 0) {
1077 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
1078 qdev->ndev->name);
1079 return err;
1080 }
1081
1082 /* Check if we have a Agere PHY */
1083 if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
1084
1085 /* Determine which MII address we should be using
1086 determined by the index of the card */
1087 if (qdev->mac_index == 0) {
1088 miiAddr = MII_AGERE_ADDR_1;
1089 } else {
1090 miiAddr = MII_AGERE_ADDR_2;
1091 }
1092
1093 err =ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, &reg1, miiAddr);
1094 if(err != 0) {
1095 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
1096 qdev->ndev->name);
1097 return err;
1098 }
1099
1100 err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, &reg2, miiAddr);
1101 if(err != 0) {
1102 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
1103 qdev->ndev->name);
1104 return err;
1105 }
1106
1107 /* We need to remember to initialize the Agere PHY */
1108 agereAddrChangeNeeded = true;
1109 }
1110
1111 /* Determine the particular PHY we have on board to apply
1112 PHY specific initializations */
1113 qdev->phyType = getPhyType(qdev, reg1, reg2);
1114
1115 if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
1116 /* need this here so address gets changed */
1117 phyAgereSpecificInit(qdev, miiAddr);
1118 } else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
1119 printk(KERN_ERR "%s: PHY is unknown\n", qdev->ndev->name);
1120 return -EIO;
1121 }
1122
1123 return 0;
1124}
1125
5a4faa87
RM		 1126/*
1127 * Caller holds hw_lock.
1128 */
1129static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
1130{
1131 struct ql3xxx_port_registers __iomem *port_regs =
1132 qdev->mem_map_registers;
1133 u32 value;
1134
1135 if (enable)
1136 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1137 else
1138 value = (MAC_CONFIG_REG_PE << 16);
1139
1140 if (qdev->mac_index)
1141 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1142 else
1143 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1144}
1145
1146/*
1147 * Caller holds hw_lock.
1148 */
1149static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
1150{
1151 struct ql3xxx_port_registers __iomem *port_regs =
1152 qdev->mem_map_registers;
1153 u32 value;
1154
1155 if (enable)
1156 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1157 else
1158 value = (MAC_CONFIG_REG_SR << 16);
1159
1160 if (qdev->mac_index)
1161 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1162 else
1163 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1164}
1165
1166/*
1167 * Caller holds hw_lock.
1168 */
1169static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
1170{
1171 struct ql3xxx_port_registers __iomem *port_regs =
1172 qdev->mem_map_registers;
1173 u32 value;
1174
1175 if (enable)
1176 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1177 else
1178 value = (MAC_CONFIG_REG_GM << 16);
1179
1180 if (qdev->mac_index)
1181 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1182 else
1183 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1184}
1185
1186/*
1187 * Caller holds hw_lock.
1188 */
1189static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1190{
1191 struct ql3xxx_port_registers __iomem *port_regs =
1192 qdev->mem_map_registers;
1193 u32 value;
1194
1195 if (enable)
1196 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1197 else
1198 value = (MAC_CONFIG_REG_FD << 16);
1199
1200 if (qdev->mac_index)
1201 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1202 else
1203 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1204}
1205
1206/*
1207 * Caller holds hw_lock.
1208 */
1209static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1210{
1211 struct ql3xxx_port_registers __iomem *port_regs =
1212 qdev->mem_map_registers;
1213 u32 value;
1214
1215 if (enable)
1216 value =
1217 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1218 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1219 else
1220 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1221
1222 if (qdev->mac_index)
1223 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1224 else
1225 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1226}
1227
1228/*
1229 * Caller holds hw_lock.
1230 */
1231static int ql_is_fiber(struct ql3_adapter *qdev)
1232{
1233 struct ql3xxx_port_registers __iomem *port_regs =
1234 qdev->mem_map_registers;
1235 u32 bitToCheck = 0;
1236 u32 temp;
1237
1238 switch (qdev->mac_index) {
1239 case 0:
1240 bitToCheck = PORT_STATUS_SM0;
1241 break;
1242 case 1:
1243 bitToCheck = PORT_STATUS_SM1;
1244 break;
1245 }
1246
1247 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1248 return (temp & bitToCheck) != 0;
1249}
1250
1251static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1252{
1253 u16 reg;
1254 ql_mii_read_reg(qdev, 0x00, &reg);
1255 return (reg & 0x1000) != 0;
1256}
1257
1258/*
1259 * Caller holds hw_lock.
1260 */
1261static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1262{
1263 struct ql3xxx_port_registers __iomem *port_regs =
1264 qdev->mem_map_registers;
1265 u32 bitToCheck = 0;
1266 u32 temp;
1267
1268 switch (qdev->mac_index) {
1269 case 0:
1270 bitToCheck = PORT_STATUS_AC0;
1271 break;
1272 case 1:
1273 bitToCheck = PORT_STATUS_AC1;
1274 break;
1275 }
1276
1277 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1278 if (temp & bitToCheck) {
1279 if (netif_msg_link(qdev))
1280 printk(KERN_INFO PFX
1281 "%s: Auto-Negotiate complete.\n",
1282 qdev->ndev->name);
1283 return 1;
1284 } else {
1285 if (netif_msg_link(qdev))
1286 printk(KERN_WARNING PFX
1287 "%s: Auto-Negotiate incomplete.\n",
1288 qdev->ndev->name);
1289 return 0;
1290 }
1291}
1292
1293/*
1294 * ql_is_neg_pause() returns 1 if pause was negotiated to be on
1295 */
1296static int ql_is_neg_pause(struct ql3_adapter *qdev)
1297{
1298 if (ql_is_fiber(qdev))
1299 return ql_is_petbi_neg_pause(qdev);
1300 else
1301 return ql_is_phy_neg_pause(qdev);
1302}
1303
1304static int ql_auto_neg_error(struct ql3_adapter *qdev)
1305{
1306 struct ql3xxx_port_registers __iomem *port_regs =
1307 qdev->mem_map_registers;
1308 u32 bitToCheck = 0;
1309 u32 temp;
1310
1311 switch (qdev->mac_index) {
1312 case 0:
1313 bitToCheck = PORT_STATUS_AE0;
1314 break;
1315 case 1:
1316 bitToCheck = PORT_STATUS_AE1;
1317 break;
1318 }
1319 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1320 return (temp & bitToCheck) != 0;
1321}
1322
1323static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1324{
1325 if (ql_is_fiber(qdev))
1326 return SPEED_1000;
1327 else
1328 return ql_phy_get_speed(qdev);
1329}
1330
1331static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1332{
1333 if (ql_is_fiber(qdev))
1334 return 1;
1335 else
1336 return ql_is_full_dup(qdev);
1337}
1338
1339/*
1340 * Caller holds hw_lock.
1341 */
1342static int ql_link_down_detect(struct ql3_adapter *qdev)
1343{
1344 struct ql3xxx_port_registers __iomem *port_regs =
1345 qdev->mem_map_registers;
1346 u32 bitToCheck = 0;
1347 u32 temp;
1348
1349 switch (qdev->mac_index) {
1350 case 0:
1351 bitToCheck = ISP_CONTROL_LINK_DN_0;
1352 break;
1353 case 1:
1354 bitToCheck = ISP_CONTROL_LINK_DN_1;
1355 break;
1356 }
1357
1358 temp =
1359 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1360 return (temp & bitToCheck) != 0;
1361}
1362
1363/*
1364 * Caller holds hw_lock.
1365 */
1366static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1367{
1368 struct ql3xxx_port_registers __iomem *port_regs =
1369 qdev->mem_map_registers;
1370
1371 switch (qdev->mac_index) {
1372 case 0:
1373 ql_write_common_reg(qdev,
1374 &port_regs->CommonRegs.ispControlStatus,
1375 (ISP_CONTROL_LINK_DN_0) |
1376 (ISP_CONTROL_LINK_DN_0 << 16));
1377 break;
1378
1379 case 1:
1380 ql_write_common_reg(qdev,
1381 &port_regs->CommonRegs.ispControlStatus,
1382 (ISP_CONTROL_LINK_DN_1) |
1383 (ISP_CONTROL_LINK_DN_1 << 16));
1384 break;
1385
1386 default:
1387 return 1;
1388 }
1389
1390 return 0;
1391}
1392
1393/*
1394 * Caller holds hw_lock.
1395 */
3efedf2e 1396static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
5a4faa87
RM		 1397{
1398 struct ql3xxx_port_registers __iomem *port_regs =
1399 qdev->mem_map_registers;
1400 u32 bitToCheck = 0;
1401 u32 temp;
1402
3efedf2e 1403 switch (qdev->mac_index) {
5a4faa87
RM		 1404 case 0:
1405 bitToCheck = PORT_STATUS_F1_ENABLED;
1406 break;
1407 case 1:
1408 bitToCheck = PORT_STATUS_F3_ENABLED;
1409 break;
1410 default:
1411 break;
1412 }
1413
1414 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1415 if (temp & bitToCheck) {
1416 if (netif_msg_link(qdev))
1417 printk(KERN_DEBUG PFX
1418 "%s: is not link master.\n", qdev->ndev->name);
1419 return 0;
1420 } else {
1421 if (netif_msg_link(qdev))
1422 printk(KERN_DEBUG PFX
1423 "%s: is link master.\n", qdev->ndev->name);
1424 return 1;
1425 }
1426}
1427
3efedf2e 1428static void ql_phy_reset_ex(struct ql3_adapter *qdev)
5a4faa87 1429{
3efedf2e
RM		 1430 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET,
1431 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 1432}
1433
3efedf2e 1434static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
5a4faa87
RM		 1435{
1436 u16 reg;
3efedf2e
RM		 1437 u16 portConfiguration;
1438
1439 if(qdev->phyType == PHY_AGERE_ET1011C) {
1440 /* turn off external loopback */
1441 ql_mii_write_reg(qdev, 0x13, 0x0000);
1442 }
5a4faa87 1443
3efedf2e
RM		 1444 if(qdev->mac_index == 0)
1445 portConfiguration = qdev->nvram_data.macCfg_port0.portConfiguration;
1446 else
1447 portConfiguration = qdev->nvram_data.macCfg_port1.portConfiguration;
1448
1449 /* Some HBA's in the field are set to 0 and they need to
1450 be reinterpreted with a default value */
1451 if(portConfiguration == 0)
1452 portConfiguration = PORT_CONFIG_DEFAULT;
1453
1454 /* Set the 1000 advertisements */
1455 ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, &reg,
1456 PHYAddr[qdev->mac_index]);
1457 reg &= ~PHY_GIG_ALL_PARAMS;
1458
1459 if(portConfiguration &
1460 PORT_CONFIG_FULL_DUPLEX_ENABLED &
1461 PORT_CONFIG_1000MB_SPEED) {
1462 reg |= PHY_GIG_ADV_1000F;
1463 }
1464
1465 if(portConfiguration &
1466 PORT_CONFIG_HALF_DUPLEX_ENABLED &
1467 PORT_CONFIG_1000MB_SPEED) {
1468 reg |= PHY_GIG_ADV_1000H;
1469 }
1470
1471 ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg,
1472 PHYAddr[qdev->mac_index]);
1473
1474 /* Set the 10/100 & pause negotiation advertisements */
1475 ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, &reg,
1476 PHYAddr[qdev->mac_index]);
1477 reg &= ~PHY_NEG_ALL_PARAMS;
1478
1479 if(portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
1480 reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
1481
1482 if(portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
1483 if(portConfiguration & PORT_CONFIG_100MB_SPEED)
1484 reg |= PHY_NEG_ADV_100F;
1485
1486 if(portConfiguration & PORT_CONFIG_10MB_SPEED)
1487 reg |= PHY_NEG_ADV_10F;
1488 }
1489
1490 if(portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
1491 if(portConfiguration & PORT_CONFIG_100MB_SPEED)
1492 reg |= PHY_NEG_ADV_100H;
1493
1494 if(portConfiguration & PORT_CONFIG_10MB_SPEED)
1495 reg |= PHY_NEG_ADV_10H;
1496 }
1497
1498 if(portConfiguration &
1499 PORT_CONFIG_1000MB_SPEED) {
1500 reg |= 1;
1501 }
1502
1503 ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg,
1504 PHYAddr[qdev->mac_index]);
5a4faa87 1505
3efedf2e
RM		 1506 ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, PHYAddr[qdev->mac_index]);
1507
1508 ql_mii_write_reg_ex(qdev, CONTROL_REG,
1509 reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
1510 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 1511}
1512
3efedf2e 1513static void ql_phy_init_ex(struct ql3_adapter *qdev)
5a4faa87 1514{
3efedf2e
RM		 1515 ql_phy_reset_ex(qdev);
1516 PHY_Setup(qdev);
1517 ql_phy_start_neg_ex(qdev);
5a4faa87
RM		 1518}
1519
1520/*
1521 * Caller holds hw_lock.
1522 */
1523static u32 ql_get_link_state(struct ql3_adapter *qdev)
1524{
1525 struct ql3xxx_port_registers __iomem *port_regs =
1526 qdev->mem_map_registers;
1527 u32 bitToCheck = 0;
1528 u32 temp, linkState;
1529
1530 switch (qdev->mac_index) {
1531 case 0:
1532 bitToCheck = PORT_STATUS_UP0;
1533 break;
1534 case 1:
1535 bitToCheck = PORT_STATUS_UP1;
1536 break;
1537 }
1538 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1539 if (temp & bitToCheck) {
1540 linkState = LS_UP;
1541 } else {
1542 linkState = LS_DOWN;
1543 if (netif_msg_link(qdev))
1544 printk(KERN_WARNING PFX
1545 "%s: Link is down.\n", qdev->ndev->name);
1546 }
1547 return linkState;
1548}
1549
1550static int ql_port_start(struct ql3_adapter *qdev)
1551{
1552 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1553 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3efedf2e
RM		 1554 2) << 7)) {
1555 printk(KERN_ERR "%s: Could not get hw lock for GIO\n",
1556 qdev->ndev->name);
5a4faa87 1557 return -1;
3efedf2e 1558 }
5a4faa87
RM		 1559
1560 if (ql_is_fiber(qdev)) {
1561 ql_petbi_init(qdev);
1562 } else {
1563 /* Copper port */
3efedf2e 1564 ql_phy_init_ex(qdev);
5a4faa87
RM		 1565 }
1566
1567 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1568 return 0;
1569}
1570
1571static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1572{
1573
1574 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1575 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1576 2) << 7))
1577 return -1;
1578
1579 if (!ql_auto_neg_error(qdev)) {
1580 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1581 /* configure the MAC */
1582 if (netif_msg_link(qdev))
1583 printk(KERN_DEBUG PFX
1584 "%s: Configuring link.\n",
1585 qdev->ndev->
1586 name);
1587 ql_mac_cfg_soft_reset(qdev, 1);
1588 ql_mac_cfg_gig(qdev,
1589 (ql_get_link_speed
1590 (qdev) ==
1591 SPEED_1000));
1592 ql_mac_cfg_full_dup(qdev,
1593 ql_is_link_full_dup
1594 (qdev));
1595 ql_mac_cfg_pause(qdev,
1596 ql_is_neg_pause
1597 (qdev));
1598 ql_mac_cfg_soft_reset(qdev, 0);
1599
1600 /* enable the MAC */
1601 if (netif_msg_link(qdev))
1602 printk(KERN_DEBUG PFX
1603 "%s: Enabling mac.\n",
1604 qdev->ndev->
1605 name);
1606 ql_mac_enable(qdev, 1);
1607 }
1608
1609 if (netif_msg_link(qdev))
1610 printk(KERN_DEBUG PFX
1611 "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1612 qdev->ndev->name);
1613 qdev->port_link_state = LS_UP;
1614 netif_start_queue(qdev->ndev);
1615 netif_carrier_on(qdev->ndev);
1616 if (netif_msg_link(qdev))
1617 printk(KERN_INFO PFX
1618 "%s: Link is up at %d Mbps, %s duplex.\n",
1619 qdev->ndev->name,
1620 ql_get_link_speed(qdev),
1621 ql_is_link_full_dup(qdev)
1622 ? "full" : "half");
1623
1624 } else { /* Remote error detected */
1625
1626 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1627 if (netif_msg_link(qdev))
1628 printk(KERN_DEBUG PFX
1629 "%s: Remote error detected. "
1630 "Calling ql_port_start().\n",
1631 qdev->ndev->
1632 name);
1633 /*
1634 * ql_port_start() is shared code and needs
1635 * to lock the PHY on it's own.
1636 */
1637 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1638 if(ql_port_start(qdev)) {/* Restart port */
1639 return -1;
1640 } else
1641 return 0;
1642 }
1643 }
1644 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1645 return 0;
1646}
1647
1648static void ql_link_state_machine(struct ql3_adapter *qdev)
1649{
1650 u32 curr_link_state;
1651 unsigned long hw_flags;
1652
1653 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1654
1655 curr_link_state = ql_get_link_state(qdev);
1656
1657 if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1658 if (netif_msg_link(qdev))
1659 printk(KERN_INFO PFX
1660 "%s: Reset in progress, skip processing link "
1661 "state.\n", qdev->ndev->name);
04f10773
BL		 1662
1663 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87
RM		 1664 return;
1665 }
1666
1667 switch (qdev->port_link_state) {
1668 default:
1669 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1670 ql_port_start(qdev);
1671 }
1672 qdev->port_link_state = LS_DOWN;
1673 /* Fall Through */
1674
1675 case LS_DOWN:
1676 if (netif_msg_link(qdev))
1677 printk(KERN_DEBUG PFX
1678 "%s: port_link_state = LS_DOWN.\n",
1679 qdev->ndev->name);
1680 if (curr_link_state == LS_UP) {
1681 if (netif_msg_link(qdev))
1682 printk(KERN_DEBUG PFX
1683 "%s: curr_link_state = LS_UP.\n",
1684 qdev->ndev->name);
1685 if (ql_is_auto_neg_complete(qdev))
1686 ql_finish_auto_neg(qdev);
1687
1688 if (qdev->port_link_state == LS_UP)
1689 ql_link_down_detect_clear(qdev);
1690
1691 }
1692 break;
1693
1694 case LS_UP:
1695 /*
1696 * See if the link is currently down or went down and came
1697 * back up
1698 */
1699 if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
1700 if (netif_msg_link(qdev))
1701 printk(KERN_INFO PFX "%s: Link is down.\n",
1702 qdev->ndev->name);
1703 qdev->port_link_state = LS_DOWN;
1704 }
1705 break;
1706 }
1707 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1708}
1709
1710/*
1711 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1712 */
1713static void ql_get_phy_owner(struct ql3_adapter *qdev)
1714{
3efedf2e 1715 if (ql_this_adapter_controls_port(qdev))
5a4faa87
RM		 1716 set_bit(QL_LINK_MASTER,&qdev->flags);
1717 else
1718 clear_bit(QL_LINK_MASTER,&qdev->flags);
1719}
1720
1721/*
1722 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1723 */
1724static void ql_init_scan_mode(struct ql3_adapter *qdev)
1725{
1726 ql_mii_enable_scan_mode(qdev);
1727
1728 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
3efedf2e
RM		 1729 if (ql_this_adapter_controls_port(qdev))
1730 ql_petbi_init_ex(qdev);
5a4faa87 1731 } else {
3efedf2e
RM		 1732 if (ql_this_adapter_controls_port(qdev))
1733 ql_phy_init_ex(qdev);
5a4faa87
RM		 1734 }
1735}
1736
1737/*
1738 * MII_Setup needs to be called before taking the PHY out of reset so that the
1739 * management interface clock speed can be set properly. It would be better if
1740 * we had a way to disable MDC until after the PHY is out of reset, but we
1741 * don't have that capability.
1742 */
1743static int ql_mii_setup(struct ql3_adapter *qdev)
1744{
1745 u32 reg;
1746 struct ql3xxx_port_registers __iomem *port_regs =
1747 qdev->mem_map_registers;
1748
1749 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1750 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1751 2) << 7))
1752 return -1;
1753
bd36b0ac
RM		 1754 if (qdev->device_id == QL3032_DEVICE_ID)
1755 ql_write_page0_reg(qdev,
1756 &port_regs->macMIIMgmtControlReg, 0x0f00000);
1757
5a4faa87
RM		 1758 /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1759 reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1760
1761 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1762 reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1763
1764 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1765 return 0;
1766}
1767
1768static u32 ql_supported_modes(struct ql3_adapter *qdev)
1769{
1770 u32 supported;
1771
1772 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1773 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1774 | SUPPORTED_Autoneg;
1775 } else {
1776 supported = SUPPORTED_10baseT_Half
1777 | SUPPORTED_10baseT_Full
1778 | SUPPORTED_100baseT_Half
1779 | SUPPORTED_100baseT_Full
1780 | SUPPORTED_1000baseT_Half
1781 | SUPPORTED_1000baseT_Full
1782 | SUPPORTED_Autoneg | SUPPORTED_TP;
1783 }
1784
1785 return supported;
1786}
1787
1788static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1789{
1790 int status;
1791 unsigned long hw_flags;
1792 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1793 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1794 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
04f10773
BL		 1795 2) << 7)) {
1796 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87 1797 return 0;
04f10773 1798 }
5a4faa87
RM		 1799 status = ql_is_auto_cfg(qdev);
1800 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1801 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1802 return status;
1803}
1804
1805static u32 ql_get_speed(struct ql3_adapter *qdev)
1806{
1807 u32 status;
1808 unsigned long hw_flags;
1809 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1810 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1811 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
04f10773
BL		 1812 2) << 7)) {
1813 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87 1814 return 0;
04f10773 1815 }
5a4faa87
RM		 1816 status = ql_get_link_speed(qdev);
1817 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1818 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1819 return status;
1820}
1821
1822static int ql_get_full_dup(struct ql3_adapter *qdev)
1823{
1824 int status;
1825 unsigned long hw_flags;
1826 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1827 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1828 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
04f10773
BL		 1829 2) << 7)) {
1830 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87 1831 return 0;
04f10773 1832 }
5a4faa87
RM		 1833 status = ql_is_link_full_dup(qdev);
1834 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1835 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1836 return status;
1837}
1838
1839
1840static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1841{
1842 struct ql3_adapter *qdev = netdev_priv(ndev);
1843
1844 ecmd->transceiver = XCVR_INTERNAL;
1845 ecmd->supported = ql_supported_modes(qdev);
1846
1847 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1848 ecmd->port = PORT_FIBRE;
1849 } else {
1850 ecmd->port = PORT_TP;
1851 ecmd->phy_address = qdev->PHYAddr;
1852 }
1853 ecmd->advertising = ql_supported_modes(qdev);
1854 ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1855 ecmd->speed = ql_get_speed(qdev);
1856 ecmd->duplex = ql_get_full_dup(qdev);
1857 return 0;
1858}
1859
1860static void ql_get_drvinfo(struct net_device *ndev,
1861 struct ethtool_drvinfo *drvinfo)
1862{
1863 struct ql3_adapter *qdev = netdev_priv(ndev);
1864 strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1865 strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1866 strncpy(drvinfo->fw_version, "N/A", 32);
1867 strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
5a4faa87
RM		 1868 drvinfo->regdump_len = 0;
1869 drvinfo->eedump_len = 0;
1870}
1871
1872static u32 ql_get_msglevel(struct net_device *ndev)
1873{
1874 struct ql3_adapter *qdev = netdev_priv(ndev);
1875 return qdev->msg_enable;
1876}
1877
1878static void ql_set_msglevel(struct net_device *ndev, u32 value)
1879{
1880 struct ql3_adapter *qdev = netdev_priv(ndev);
1881 qdev->msg_enable = value;
1882}
1883
ec826383
RM		 1884static void ql_get_pauseparam(struct net_device *ndev,
1885 struct ethtool_pauseparam *pause)
1886{
1887 struct ql3_adapter *qdev = netdev_priv(ndev);
1888 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1889
1890 u32 reg;
1891 if(qdev->mac_index == 0)
1892 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1893 else
1894 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1895
1896 pause->autoneg = ql_get_auto_cfg_status(qdev);
1897 pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
1898 pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
1899}
1900
7282d491 1901static const struct ethtool_ops ql3xxx_ethtool_ops = {
5a4faa87
RM		 1902 .get_settings = ql_get_settings,
1903 .get_drvinfo = ql_get_drvinfo,
5a4faa87
RM		 1904 .get_link = ethtool_op_get_link,
1905 .get_msglevel = ql_get_msglevel,
1906 .set_msglevel = ql_set_msglevel,
ec826383 1907 .get_pauseparam = ql_get_pauseparam,
5a4faa87
RM		 1908};
1909
1910static int ql_populate_free_queue(struct ql3_adapter *qdev)
1911{
1912 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
0f8ab89e
BL		 1913 dma_addr_t map;
1914 int err;
5a4faa87
RM		 1915
1916 while (lrg_buf_cb) {
1917 if (!lrg_buf_cb->skb) {
cd238faa
BL		 1918 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
1919 qdev->lrg_buffer_len);
5a4faa87
RM		 1920 if (unlikely(!lrg_buf_cb->skb)) {
1921 printk(KERN_DEBUG PFX
cd238faa 1922 "%s: Failed netdev_alloc_skb().\n",
5a4faa87
RM		 1923 qdev->ndev->name);
1924 break;
1925 } else {
1926 /*
1927 * We save some space to copy the ethhdr from
1928 * first buffer
1929 */
1930 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1931 map = pci_map_single(qdev->pdev,
1932 lrg_buf_cb->skb->data,
1933 qdev->lrg_buffer_len -
1934 QL_HEADER_SPACE,
1935 PCI_DMA_FROMDEVICE);
0f8ab89e
BL		 1936
1937 err = pci_dma_mapping_error(map);
1938 if(err) {
1939 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
1940 qdev->ndev->name, err);
1941 dev_kfree_skb(lrg_buf_cb->skb);
1942 lrg_buf_cb->skb = NULL;
1943 break;
1944 }
1945
1946
5a4faa87
RM		 1947 lrg_buf_cb->buf_phy_addr_low =
1948 cpu_to_le32(LS_64BITS(map));
1949 lrg_buf_cb->buf_phy_addr_high =
1950 cpu_to_le32(MS_64BITS(map));
1951 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1952 pci_unmap_len_set(lrg_buf_cb, maplen,
1953 qdev->lrg_buffer_len -
1954 QL_HEADER_SPACE);
1955 --qdev->lrg_buf_skb_check;
1956 if (!qdev->lrg_buf_skb_check)
1957 return 1;
1958 }
1959 }
1960 lrg_buf_cb = lrg_buf_cb->next;
1961 }
1962 return 0;
1963}
1964
f67cac01
RM		 1965/*
1966 * Caller holds hw_lock.
1967 */
1968static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1969{
1970 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1971 if (qdev->small_buf_release_cnt >= 16) {
1972 while (qdev->small_buf_release_cnt >= 16) {
1973 qdev->small_buf_q_producer_index++;
1974
1975 if (qdev->small_buf_q_producer_index ==
1976 NUM_SBUFQ_ENTRIES)
1977 qdev->small_buf_q_producer_index = 0;
1978 qdev->small_buf_release_cnt -= 8;
1979 }
1980 wmb();
1981 writel(qdev->small_buf_q_producer_index,
1982 &port_regs->CommonRegs.rxSmallQProducerIndex);
1983 }
1984}
1985
5a4faa87
RM		 1986/*
1987 * Caller holds hw_lock.
1988 */
1989static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1990{
1991 struct bufq_addr_element *lrg_buf_q_ele;
1992 int i;
1993 struct ql_rcv_buf_cb *lrg_buf_cb;
1994 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1995
1996 if ((qdev->lrg_buf_free_count >= 8)
1997 && (qdev->lrg_buf_release_cnt >= 16)) {
1998
1999 if (qdev->lrg_buf_skb_check)
2000 if (!ql_populate_free_queue(qdev))
2001 return;
2002
2003 lrg_buf_q_ele = qdev->lrg_buf_next_free;
2004
2005 while ((qdev->lrg_buf_release_cnt >= 16)
2006 && (qdev->lrg_buf_free_count >= 8)) {
2007
2008 for (i = 0; i < 8; i++) {
2009 lrg_buf_cb =
2010 ql_get_from_lrg_buf_free_list(qdev);
2011 lrg_buf_q_ele->addr_high =
2012 lrg_buf_cb->buf_phy_addr_high;
2013 lrg_buf_q_ele->addr_low =
2014 lrg_buf_cb->buf_phy_addr_low;
2015 lrg_buf_q_ele++;
2016
2017 qdev->lrg_buf_release_cnt--;
2018 }
2019
2020 qdev->lrg_buf_q_producer_index++;
2021
1357bfcf 2022 if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries)
5a4faa87
RM		 2023 qdev->lrg_buf_q_producer_index = 0;
2024
2025 if (qdev->lrg_buf_q_producer_index ==
1357bfcf 2026 (qdev->num_lbufq_entries - 1)) {
5a4faa87
RM		 2027 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
2028 }
2029 }
f67cac01 2030 wmb();
5a4faa87 2031 qdev->lrg_buf_next_free = lrg_buf_q_ele;
f67cac01
RM		 2032 writel(qdev->lrg_buf_q_producer_index,
2033 &port_regs->CommonRegs.rxLargeQProducerIndex);
5a4faa87
RM		 2034 }
2035}
2036
2037static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
2038 struct ob_mac_iocb_rsp *mac_rsp)
2039{
2040 struct ql_tx_buf_cb *tx_cb;
bd36b0ac 2041 int i;
e8f4df24 2042 int retval = 0;
5a4faa87 2043
e8f4df24
BL		 2044 if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
2045 printk(KERN_WARNING "Frame short but, frame was padded and sent.\n");
2046 }
2047
5a4faa87 2048 tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
e8f4df24
BL		 2049
2050 /* Check the transmit response flags for any errors */
2051 if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
2052 printk(KERN_ERR "Frame too short to be legal, frame not sent.\n");
2053
09f75cd7 2054 qdev->ndev->stats.tx_errors++;
e8f4df24
BL		 2055 retval = -EIO;
2056 goto frame_not_sent;
2057 }
2058
2059 if(tx_cb->seg_count == 0) {
2060 printk(KERN_ERR "tx_cb->seg_count == 0: %d\n", mac_rsp->transaction_id);
2061
09f75cd7 2062 qdev->ndev->stats.tx_errors++;
e8f4df24
BL		 2063 retval = -EIO;
2064 goto invalid_seg_count;
2065 }
2066
5a4faa87 2067 pci_unmap_single(qdev->pdev,
bd36b0ac
RM		 2068 pci_unmap_addr(&tx_cb->map[0], mapaddr),
2069 pci_unmap_len(&tx_cb->map[0], maplen),
2070 PCI_DMA_TODEVICE);
2071 tx_cb->seg_count--;
2072 if (tx_cb->seg_count) {
2073 for (i = 1; i < tx_cb->seg_count; i++) {
2074 pci_unmap_page(qdev->pdev,
2075 pci_unmap_addr(&tx_cb->map[i],
2076 mapaddr),
2077 pci_unmap_len(&tx_cb->map[i], maplen),
2078 PCI_DMA_TODEVICE);
2079 }
2080 }
09f75cd7
JG		 2081 qdev->ndev->stats.tx_packets++;
2082 qdev->ndev->stats.tx_bytes += tx_cb->skb->len;
e8f4df24
BL		 2083
2084frame_not_sent:
bd36b0ac 2085 dev_kfree_skb_irq(tx_cb->skb);
5a4faa87 2086 tx_cb->skb = NULL;
e8f4df24
BL		 2087
2088invalid_seg_count:
5a4faa87
RM		 2089 atomic_inc(&qdev->tx_count);
2090}
2091
3664006a 2092static void ql_get_sbuf(struct ql3_adapter *qdev)
97916330
RM		 2093{
2094 if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
2095 qdev->small_buf_index = 0;
2096 qdev->small_buf_release_cnt++;
2097}
2098
3664006a 2099static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
97916330
RM		 2100{
2101 struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
2102 lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
2103 qdev->lrg_buf_release_cnt++;
2104 if (++qdev->lrg_buf_index == qdev->num_large_buffers)
2105 qdev->lrg_buf_index = 0;
2106 return(lrg_buf_cb);
2107}
2108
bd36b0ac
RM		 2109/*
2110 * The difference between 3022 and 3032 for inbound completions:
2111 * 3022 uses two buffers per completion. The first buffer contains
2112 * (some) header info, the second the remainder of the headers plus
2113 * the data. For this chip we reserve some space at the top of the
2114 * receive buffer so that the header info in buffer one can be
2115 * prepended to the buffer two. Buffer two is the sent up while
2116 * buffer one is returned to the hardware to be reused.
2117 * 3032 receives all of it's data and headers in one buffer for a
2118 * simpler process. 3032 also supports checksum verification as
2119 * can be seen in ql_process_macip_rx_intr().
2120 */
5a4faa87
RM		 2121static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
2122 struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
2123{
5a4faa87
RM		 2124 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2125 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
5a4faa87
RM		 2126 struct sk_buff *skb;
2127 u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
2128
2129 /*
2130 * Get the inbound address list (small buffer).
2131 */
97916330 2132 ql_get_sbuf(qdev);
5a4faa87 2133
97916330
RM		 2134 if (qdev->device_id == QL3022_DEVICE_ID)
2135 lrg_buf_cb1 = ql_get_lbuf(qdev);
5a4faa87
RM		 2136
2137 /* start of second buffer */
97916330 2138 lrg_buf_cb2 = ql_get_lbuf(qdev);
5a4faa87
RM		 2139 skb = lrg_buf_cb2->skb;
2140
09f75cd7
JG		 2141 qdev->ndev->stats.rx_packets++;
2142 qdev->ndev->stats.rx_bytes += length;
5a4faa87
RM		 2143
2144 skb_put(skb, length);
2145 pci_unmap_single(qdev->pdev,
2146 pci_unmap_addr(lrg_buf_cb2, mapaddr),
2147 pci_unmap_len(lrg_buf_cb2, maplen),
2148 PCI_DMA_FROMDEVICE);
2149 prefetch(skb->data);
5a4faa87
RM		 2150 skb->ip_summed = CHECKSUM_NONE;
2151 skb->protocol = eth_type_trans(skb, qdev->ndev);
2152
2153 netif_receive_skb(skb);
2154 qdev->ndev->last_rx = jiffies;
2155 lrg_buf_cb2->skb = NULL;
2156
bd36b0ac
RM		 2157 if (qdev->device_id == QL3022_DEVICE_ID)
2158 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
5a4faa87
RM		 2159 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2160}
2161
2162static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
2163 struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
2164{
5a4faa87
RM		 2165 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2166 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
bd36b0ac 2167 struct sk_buff *skb1 = NULL, *skb2;
5a4faa87
RM		 2168 struct net_device *ndev = qdev->ndev;
2169 u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
2170 u16 size = 0;
2171
2172 /*
2173 * Get the inbound address list (small buffer).
2174 */
2175
97916330 2176 ql_get_sbuf(qdev);
5a4faa87 2177
bd36b0ac
RM		 2178 if (qdev->device_id == QL3022_DEVICE_ID) {
2179 /* start of first buffer on 3022 */
97916330 2180 lrg_buf_cb1 = ql_get_lbuf(qdev);
bd36b0ac 2181 skb1 = lrg_buf_cb1->skb;
bd36b0ac
RM		 2182 size = ETH_HLEN;
2183 if (*((u16 *) skb1->data) != 0xFFFF)
2184 size += VLAN_ETH_HLEN - ETH_HLEN;
2185 }
5a4faa87
RM		 2186
2187 /* start of second buffer */
97916330 2188 lrg_buf_cb2 = ql_get_lbuf(qdev);
5a4faa87 2189 skb2 = lrg_buf_cb2->skb;
5a4faa87 2190
5a4faa87
RM		 2191 skb_put(skb2, length); /* Just the second buffer length here. */
2192 pci_unmap_single(qdev->pdev,
2193 pci_unmap_addr(lrg_buf_cb2, mapaddr),
2194 pci_unmap_len(lrg_buf_cb2, maplen),
2195 PCI_DMA_FROMDEVICE);
2196 prefetch(skb2->data);
2197
5a4faa87 2198 skb2->ip_summed = CHECKSUM_NONE;
bd36b0ac
RM		 2199 if (qdev->device_id == QL3022_DEVICE_ID) {
2200 /*
2201 * Copy the ethhdr from first buffer to second. This
2202 * is necessary for 3022 IP completions.
2203 */
d626f62b
ACM		 2204 skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN,
2205 skb_push(skb2, size), size);
bd36b0ac
RM		 2206 } else {
2207 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
2208 if (checksum &
2209 (IB_IP_IOCB_RSP_3032_ICE |
b3b1514c 2210 IB_IP_IOCB_RSP_3032_CE)) {
bd36b0ac
RM		 2211 printk(KERN_ERR
2212 "%s: Bad checksum for this %s packet, checksum = %x.\n",
2213 __func__,
2214 ((checksum &
2215 IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
2216 "UDP"),checksum);
b3b1514c
RM		 2217 } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
2218 (checksum & IB_IP_IOCB_RSP_3032_UDP &&
2219 !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
bd36b0ac 2220 skb2->ip_summed = CHECKSUM_UNNECESSARY;
b3b1514c 2221 }
bd36b0ac 2222 }
5a4faa87
RM		 2223 skb2->protocol = eth_type_trans(skb2, qdev->ndev);
2224
2225 netif_receive_skb(skb2);
09f75cd7
JG		 2226 ndev->stats.rx_packets++;
2227 ndev->stats.rx_bytes += length;
5a4faa87
RM		 2228 ndev->last_rx = jiffies;
2229 lrg_buf_cb2->skb = NULL;
2230
bd36b0ac
RM		 2231 if (qdev->device_id == QL3022_DEVICE_ID)
2232 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
5a4faa87
RM		 2233 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2234}
2235
2236static int ql_tx_rx_clean(struct ql3_adapter *qdev,
2237 int *tx_cleaned, int *rx_cleaned, int work_to_do)
2238{
5a4faa87
RM		 2239 struct net_rsp_iocb *net_rsp;
2240 struct net_device *ndev = qdev->ndev;
63b66d12 2241 int work_done = 0;
5a4faa87
RM		 2242
2243 /* While there are entries in the completion queue. */
f67cac01 2244 while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
63b66d12 2245 qdev->rsp_consumer_index) && (work_done < work_to_do)) {
5a4faa87
RM		 2246
2247 net_rsp = qdev->rsp_current;
b323e0e4 2248 rmb();
50626297
RM		 2249 /*
2250 * Fix 4032 chipe undocumented "feature" where bit-8 is set if the
2251 * inbound completion is for a VLAN.
2252 */
2253 if (qdev->device_id == QL3032_DEVICE_ID)
2254 net_rsp->opcode &= 0x7f;
5a4faa87
RM		 2255 switch (net_rsp->opcode) {
2256
2257 case OPCODE_OB_MAC_IOCB_FN0:
2258 case OPCODE_OB_MAC_IOCB_FN2:
2259 ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
2260 net_rsp);
2261 (*tx_cleaned)++;
2262 break;
2263
2264 case OPCODE_IB_MAC_IOCB:
bd36b0ac 2265 case OPCODE_IB_3032_MAC_IOCB:
5a4faa87
RM		 2266 ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
2267 net_rsp);
2268 (*rx_cleaned)++;
2269 break;
2270
2271 case OPCODE_IB_IP_IOCB:
bd36b0ac 2272 case OPCODE_IB_3032_IP_IOCB:
5a4faa87
RM		 2273 ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
2274 net_rsp);
2275 (*rx_cleaned)++;
2276 break;
2277 default:
2278 {
2279 u32 *tmp = (u32 *) net_rsp;
2280 printk(KERN_ERR PFX
2281 "%s: Hit default case, not "
2282 "handled!\n"
2283 " dropping the packet, opcode = "
2284 "%x.\n",
2285 ndev->name, net_rsp->opcode);
2286 printk(KERN_ERR PFX
2287 "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
2288 (unsigned long int)tmp[0],
2289 (unsigned long int)tmp[1],
2290 (unsigned long int)tmp[2],
2291 (unsigned long int)tmp[3]);
2292 }
2293 }
2294
2295 qdev->rsp_consumer_index++;
2296
2297 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2298 qdev->rsp_consumer_index = 0;
2299 qdev->rsp_current = qdev->rsp_q_virt_addr;
2300 } else {
2301 qdev->rsp_current++;
2302 }
63b66d12
RM		 2303
2304 work_done = *tx_cleaned + *rx_cleaned;
5a4faa87
RM		 2305 }
2306
f67cac01 2307 return work_done;
5a4faa87
RM		 2308}
2309
bea3348e 2310static int ql_poll(struct napi_struct *napi, int budget)
5a4faa87 2311{
bea3348e
SH		 2312 struct ql3_adapter *qdev = container_of(napi, struct ql3_adapter, napi);
2313 struct net_device *ndev = qdev->ndev;
5a4faa87 2314 int rx_cleaned = 0, tx_cleaned = 0;
63b66d12
RM		 2315 unsigned long hw_flags;
2316 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
5a4faa87
RM		 2317
2318 if (!netif_carrier_ok(ndev))
2319 goto quit_polling;
2320
bea3348e 2321 ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, budget);
5a4faa87 2322
bea3348e 2323 if (tx_cleaned + rx_cleaned != budget ||
e8f4df24 2324 !netif_running(ndev)) {
5a4faa87 2325quit_polling:
63b66d12 2326 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
bea3348e 2327 __netif_rx_complete(ndev, napi);
f67cac01
RM		 2328 ql_update_small_bufq_prod_index(qdev);
2329 ql_update_lrg_bufq_prod_index(qdev);
2330 writel(qdev->rsp_consumer_index,
2331 &port_regs->CommonRegs.rspQConsumerIndex);
63b66d12
RM		 2332 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2333
5a4faa87 2334 ql_enable_interrupts(qdev);
5a4faa87 2335 }
bea3348e 2336 return tx_cleaned + rx_cleaned;
5a4faa87
RM		 2337}
2338
7d12e780 2339static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
5a4faa87
RM		 2340{
2341
2342 struct net_device *ndev = dev_id;
2343 struct ql3_adapter *qdev = netdev_priv(ndev);
2344 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2345 u32 value;
2346 int handled = 1;
2347 u32 var;
2348
2349 port_regs = qdev->mem_map_registers;
2350
2351 value =
2352 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2353
2354 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2355 spin_lock(&qdev->adapter_lock);
2356 netif_stop_queue(qdev->ndev);
2357 netif_carrier_off(qdev->ndev);
2358 ql_disable_interrupts(qdev);
2359 qdev->port_link_state = LS_DOWN;
2360 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
2361
2362 if (value & ISP_CONTROL_FE) {
2363 /*
2364 * Chip Fatal Error.
2365 */
2366 var =
2367 ql_read_page0_reg_l(qdev,
2368 &port_regs->PortFatalErrStatus);
2369 printk(KERN_WARNING PFX
2370 "%s: Resetting chip. PortFatalErrStatus "
2371 "register = 0x%x\n", ndev->name, var);
2372 set_bit(QL_RESET_START,&qdev->flags) ;
2373 } else {
2374 /*
2375 * Soft Reset Requested.
2376 */
2377 set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2378 printk(KERN_ERR PFX
2379 "%s: Another function issued a reset to the "
2380 "chip. ISR value = %x.\n", ndev->name, value);
2381 }
c4028958 2382 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
5a4faa87
RM		 2383 spin_unlock(&qdev->adapter_lock);
2384 } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
e8f4df24 2385 ql_disable_interrupts(qdev);
bea3348e
SH		 2386 if (likely(netif_rx_schedule_prep(ndev, &qdev->napi))) {
2387 __netif_rx_schedule(ndev, &qdev->napi);
63b66d12 2388 }
5a4faa87
RM		 2389 } else {
2390 return IRQ_NONE;
2391 }
2392
2393 return IRQ_RETVAL(handled);
2394}
2395
bd36b0ac
RM		 2396/*
2397 * Get the total number of segments needed for the
2398 * given number of fragments. This is necessary because
2399 * outbound address lists (OAL) will be used when more than
2400 * two frags are given. Each address list has 5 addr/len
2401 * pairs. The 5th pair in each AOL is used to point to
2402 * the next AOL if more frags are coming.
2403 * That is why the frags:segment count ratio is not linear.
2404 */
e8f4df24
BL		 2405static int ql_get_seg_count(struct ql3_adapter *qdev,
2406 unsigned short frags)
bd36b0ac 2407{
e8f4df24
BL		 2408 if (qdev->device_id == QL3022_DEVICE_ID)
2409 return 1;
2410
bd36b0ac
RM		 2411 switch(frags) {
2412 case 0: return 1; /* just the skb->data seg */
2413 case 1: return 2; /* skb->data + 1 frag */
2414 case 2: return 3; /* skb->data + 2 frags */
2415 case 3: return 5; /* skb->data + 1 frag + 1 AOL containting 2 frags */
2416 case 4: return 6;
2417 case 5: return 7;
2418 case 6: return 8;
2419 case 7: return 10;
2420 case 8: return 11;
2421 case 9: return 12;
2422 case 10: return 13;
2423 case 11: return 15;
2424 case 12: return 16;
2425 case 13: return 17;
2426 case 14: return 18;
2427 case 15: return 20;
2428 case 16: return 21;
2429 case 17: return 22;
2430 case 18: return 23;
2431 }
2432 return -1;
2433}
2434
91e745aa 2435static void ql_hw_csum_setup(const struct sk_buff *skb,
bd36b0ac
RM		 2436 struct ob_mac_iocb_req *mac_iocb_ptr)
2437{
91e745aa 2438 const struct iphdr *ip = ip_hdr(skb);
bd36b0ac 2439
91e745aa
SH		 2440 mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb);
2441 mac_iocb_ptr->ip_hdr_len = ip->ihl;
bd36b0ac 2442
91e745aa
SH		 2443 if (ip->protocol == IPPROTO_TCP) {
2444 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
3e71f6dd 2445 OB_3032MAC_IOCB_REQ_IC;
91e745aa
SH		 2446 } else {
2447 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
3e71f6dd 2448 OB_3032MAC_IOCB_REQ_IC;
bd36b0ac 2449 }
91e745aa 2450
bd36b0ac
RM		 2451}
2452
2453/*
3e71f6dd
RM		 2454 * Map the buffers for this transmit. This will return
2455 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
bd36b0ac 2456 */
3e71f6dd
RM		 2457static int ql_send_map(struct ql3_adapter *qdev,
2458 struct ob_mac_iocb_req *mac_iocb_ptr,
2459 struct ql_tx_buf_cb *tx_cb,
2460 struct sk_buff *skb)
5a4faa87 2461{
bd36b0ac
RM		 2462 struct oal *oal;
2463 struct oal_entry *oal_entry;
63f77926 2464 int len = skb_headlen(skb);
0f8ab89e
BL		 2465 dma_addr_t map;
2466 int err;
2467 int completed_segs, i;
bd36b0ac
RM		 2468 int seg_cnt, seg = 0;
2469 int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
5a4faa87 2470
b6967eb9 2471 seg_cnt = tx_cb->seg_count;
3e71f6dd
RM		 2472 /*
2473 * Map the skb buffer first.
2474 */
bd36b0ac 2475 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
0f8ab89e
BL		 2476
2477 err = pci_dma_mapping_error(map);
2478 if(err) {
2479 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2480 qdev->ndev->name, err);
2481
2482 return NETDEV_TX_BUSY;
2483 }
2484
bd36b0ac
RM		 2485 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2486 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2487 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2488 oal_entry->len = cpu_to_le32(len);
2489 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2490 pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
2491 seg++;
2492
e8f4df24 2493 if (seg_cnt == 1) {
bd36b0ac
RM		 2494 /* Terminate the last segment. */
2495 oal_entry->len =
2496 cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2497 } else {
bd36b0ac 2498 oal = tx_cb->oal;
0f8ab89e
BL		 2499 for (completed_segs=0; completed_segs<frag_cnt; completed_segs++,seg++) {
2500 skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
bd36b0ac
RM		 2501 oal_entry++;
2502 if ((seg == 2 && seg_cnt > 3) || /* Check for continuation */
2503 (seg == 7 && seg_cnt > 8) || /* requirements. It's strange */
2504 (seg == 12 && seg_cnt > 13) || /* but necessary. */
2505 (seg == 17 && seg_cnt > 18)) {
2506 /* Continuation entry points to outbound address list. */
2507 map = pci_map_single(qdev->pdev, oal,
2508 sizeof(struct oal),
2509 PCI_DMA_TODEVICE);
0f8ab89e
BL		 2510
2511 err = pci_dma_mapping_error(map);
2512 if(err) {
2513
2514 printk(KERN_ERR "%s: PCI mapping outbound address list with error: %d\n",
2515 qdev->ndev->name, err);
2516 goto map_error;
2517 }
2518
bd36b0ac
RM		 2519 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2520 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2521 oal_entry->len =
2522 cpu_to_le32(sizeof(struct oal) |
2523 OAL_CONT_ENTRY);
2524 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
2525 map);
2526 pci_unmap_len_set(&tx_cb->map[seg], maplen,
b6967eb9 2527 sizeof(struct oal));
bd36b0ac
RM		 2528 oal_entry = (struct oal_entry *)oal;
2529 oal++;
2530 seg++;
2531 }
5a4faa87 2532
bd36b0ac
RM		 2533 map =
2534 pci_map_page(qdev->pdev, frag->page,
2535 frag->page_offset, frag->size,
2536 PCI_DMA_TODEVICE);
0f8ab89e
BL		 2537
2538 err = pci_dma_mapping_error(map);
2539 if(err) {
2540 printk(KERN_ERR "%s: PCI mapping frags failed with error: %d\n",
2541 qdev->ndev->name, err);
2542 goto map_error;
2543 }
2544
bd36b0ac
RM		 2545 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2546 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2547 oal_entry->len = cpu_to_le32(frag->size);
2548 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2549 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2550 frag->size);
2551 }
2552 /* Terminate the last segment. */
2553 oal_entry->len =
2554 cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2555 }
0f8ab89e 2556
3e71f6dd 2557 return NETDEV_TX_OK;
0f8ab89e
BL		 2558
2559map_error:
2560 /* A PCI mapping failed and now we will need to back out
2561 * We need to traverse through the oal's and associated pages which
2562 * have been mapped and now we must unmap them to clean up properly
2563 */
2564
2565 seg = 1;
2566 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2567 oal = tx_cb->oal;
2568 for (i=0; i<completed_segs; i++,seg++) {
2569 oal_entry++;
2570
2571 if((seg == 2 && seg_cnt > 3) || /* Check for continuation */
2572 (seg == 7 && seg_cnt > 8) || /* requirements. It's strange */
2573 (seg == 12 && seg_cnt > 13) || /* but necessary. */
2574 (seg == 17 && seg_cnt > 18)) {
2575 pci_unmap_single(qdev->pdev,
2576 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2577 pci_unmap_len(&tx_cb->map[seg], maplen),
2578 PCI_DMA_TODEVICE);
2579 oal++;
2580 seg++;
2581 }
2582
2583 pci_unmap_page(qdev->pdev,
2584 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2585 pci_unmap_len(&tx_cb->map[seg], maplen),
2586 PCI_DMA_TODEVICE);
2587 }
2588
2589 pci_unmap_single(qdev->pdev,
2590 pci_unmap_addr(&tx_cb->map[0], mapaddr),
2591 pci_unmap_addr(&tx_cb->map[0], maplen),
2592 PCI_DMA_TODEVICE);
2593
2594 return NETDEV_TX_BUSY;
2595
3e71f6dd
RM		 2596}
2597
2598/*
2599 * The difference between 3022 and 3032 sends:
2600 * 3022 only supports a simple single segment transmission.
2601 * 3032 supports checksumming and scatter/gather lists (fragments).
2602 * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2603 * in the IOCB plus a chain of outbound address lists (OAL) that
2604 * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th)
2605 * will used to point to an OAL when more ALP entries are required.
2606 * The IOCB is always the top of the chain followed by one or more
2607 * OALs (when necessary).
2608 */
2609static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2610{
2611 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2612 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2613 struct ql_tx_buf_cb *tx_cb;
2614 u32 tot_len = skb->len;
2615 struct ob_mac_iocb_req *mac_iocb_ptr;
2616
2617 if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
3e71f6dd
RM		 2618 return NETDEV_TX_BUSY;
2619 }
2620
2621 tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
e8f4df24
BL		 2622 if((tx_cb->seg_count = ql_get_seg_count(qdev,
2623 (skb_shinfo(skb)->nr_frags))) == -1) {
3e71f6dd
RM		 2624 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2625 return NETDEV_TX_OK;
2626 }
2627
2628 mac_iocb_ptr = tx_cb->queue_entry;
d8a759ff 2629 memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
3e71f6dd
RM		 2630 mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2631 mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2632 mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2633 mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2634 mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2635 tx_cb->skb = skb;
e8f4df24
BL		 2636 if (qdev->device_id == QL3032_DEVICE_ID &&
2637 skb->ip_summed == CHECKSUM_PARTIAL)
3e71f6dd
RM		 2638 ql_hw_csum_setup(skb, mac_iocb_ptr);
2639
2640 if(ql_send_map(qdev,mac_iocb_ptr,tx_cb,skb) != NETDEV_TX_OK) {
2641 printk(KERN_ERR PFX"%s: Could not map the segments!\n",__func__);
2642 return NETDEV_TX_BUSY;
2643 }
2644
bd36b0ac 2645 wmb();
5a4faa87
RM		 2646 qdev->req_producer_index++;
2647 if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2648 qdev->req_producer_index = 0;
2649 wmb();
2650 ql_write_common_reg_l(qdev,
ee111d11 2651 &port_regs->CommonRegs.reqQProducerIndex,
5a4faa87
RM		 2652 qdev->req_producer_index);
2653
2654 ndev->trans_start = jiffies;
2655 if (netif_msg_tx_queued(qdev))
2656 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2657 ndev->name, qdev->req_producer_index, skb->len);
2658
bd36b0ac 2659 atomic_dec(&qdev->tx_count);
5a4faa87
RM		 2660 return NETDEV_TX_OK;
2661}
bd36b0ac 2662
5a4faa87
RM		 2663static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2664{
2665 qdev->req_q_size =
2666 (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2667
2668 qdev->req_q_virt_addr =
2669 pci_alloc_consistent(qdev->pdev,
2670 (size_t) qdev->req_q_size,
2671 &qdev->req_q_phy_addr);
2672
2673 if ((qdev->req_q_virt_addr == NULL) ||
2674 LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2675 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2676 qdev->ndev->name);
2677 return -ENOMEM;
2678 }
2679
2680 qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2681
2682 qdev->rsp_q_virt_addr =
2683 pci_alloc_consistent(qdev->pdev,
2684 (size_t) qdev->rsp_q_size,
2685 &qdev->rsp_q_phy_addr);
2686
2687 if ((qdev->rsp_q_virt_addr == NULL) ||
2688 LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2689 printk(KERN_ERR PFX
2690 "%s: rspQ allocation failed\n",
2691 qdev->ndev->name);
2692 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2693 qdev->req_q_virt_addr,
2694 qdev->req_q_phy_addr);
2695 return -ENOMEM;
2696 }
2697
2698 set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2699
2700 return 0;
2701}
2702
2703static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2704{
2705 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2706 printk(KERN_INFO PFX
2707 "%s: Already done.\n", qdev->ndev->name);
2708 return;
2709 }
2710
2711 pci_free_consistent(qdev->pdev,
2712 qdev->req_q_size,
2713 qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2714
2715 qdev->req_q_virt_addr = NULL;
2716
2717 pci_free_consistent(qdev->pdev,
2718 qdev->rsp_q_size,
2719 qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2720
2721 qdev->rsp_q_virt_addr = NULL;
2722
2723 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2724}
2725
2726static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2727{
2728 /* Create Large Buffer Queue */
2729 qdev->lrg_buf_q_size =
1357bfcf 2730 qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
5a4faa87
RM		 2731 if (qdev->lrg_buf_q_size < PAGE_SIZE)
2732 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2733 else
2734 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2735
1357bfcf
RM		 2736 qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL);
2737 if (qdev->lrg_buf == NULL) {
2738 printk(KERN_ERR PFX
2739 "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name);
2740 return -ENOMEM;
2741 }
2742
5a4faa87
RM		 2743 qdev->lrg_buf_q_alloc_virt_addr =
2744 pci_alloc_consistent(qdev->pdev,
2745 qdev->lrg_buf_q_alloc_size,
2746 &qdev->lrg_buf_q_alloc_phy_addr);
2747
2748 if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2749 printk(KERN_ERR PFX
2750 "%s: lBufQ failed\n", qdev->ndev->name);
2751 return -ENOMEM;
2752 }
2753 qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2754 qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2755
2756 /* Create Small Buffer Queue */
2757 qdev->small_buf_q_size =
2758 NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2759 if (qdev->small_buf_q_size < PAGE_SIZE)
2760 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2761 else
2762 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2763
2764 qdev->small_buf_q_alloc_virt_addr =
2765 pci_alloc_consistent(qdev->pdev,
2766 qdev->small_buf_q_alloc_size,
2767 &qdev->small_buf_q_alloc_phy_addr);
2768
2769 if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2770 printk(KERN_ERR PFX
2771 "%s: Small Buffer Queue allocation failed.\n",
2772 qdev->ndev->name);
2773 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2774 qdev->lrg_buf_q_alloc_virt_addr,
2775 qdev->lrg_buf_q_alloc_phy_addr);
2776 return -ENOMEM;
2777 }
2778
2779 qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2780 qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2781 set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2782 return 0;
2783}
2784
2785static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2786{
2787 if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2788 printk(KERN_INFO PFX
2789 "%s: Already done.\n", qdev->ndev->name);
2790 return;
2791 }
1357bfcf 2792 if(qdev->lrg_buf) kfree(qdev->lrg_buf);
5a4faa87
RM		 2793 pci_free_consistent(qdev->pdev,
2794 qdev->lrg_buf_q_alloc_size,
2795 qdev->lrg_buf_q_alloc_virt_addr,
2796 qdev->lrg_buf_q_alloc_phy_addr);
2797
2798 qdev->lrg_buf_q_virt_addr = NULL;
2799
2800 pci_free_consistent(qdev->pdev,
2801 qdev->small_buf_q_alloc_size,
2802 qdev->small_buf_q_alloc_virt_addr,
2803 qdev->small_buf_q_alloc_phy_addr);
2804
2805 qdev->small_buf_q_virt_addr = NULL;
2806
2807 clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2808}
2809
2810static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2811{
2812 int i;
2813 struct bufq_addr_element *small_buf_q_entry;
2814
2815 /* Currently we allocate on one of memory and use it for smallbuffers */
2816 qdev->small_buf_total_size =
2817 (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2818 QL_SMALL_BUFFER_SIZE);
2819
2820 qdev->small_buf_virt_addr =
2821 pci_alloc_consistent(qdev->pdev,
2822 qdev->small_buf_total_size,
2823 &qdev->small_buf_phy_addr);
2824
2825 if (qdev->small_buf_virt_addr == NULL) {
2826 printk(KERN_ERR PFX
2827 "%s: Failed to get small buffer memory.\n",
2828 qdev->ndev->name);
2829 return -ENOMEM;
2830 }
2831
2832 qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2833 qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2834
2835 small_buf_q_entry = qdev->small_buf_q_virt_addr;
2836
5a4faa87
RM		 2837 /* Initialize the small buffer queue. */
2838 for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2839 small_buf_q_entry->addr_high =
2840 cpu_to_le32(qdev->small_buf_phy_addr_high);
2841 small_buf_q_entry->addr_low =
2842 cpu_to_le32(qdev->small_buf_phy_addr_low +
2843 (i * QL_SMALL_BUFFER_SIZE));
2844 small_buf_q_entry++;
2845 }
2846 qdev->small_buf_index = 0;
2847 set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2848 return 0;
2849}
2850
2851static void ql_free_small_buffers(struct ql3_adapter *qdev)
2852{
2853 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2854 printk(KERN_INFO PFX
2855 "%s: Already done.\n", qdev->ndev->name);
2856 return;
2857 }
2858 if (qdev->small_buf_virt_addr != NULL) {
2859 pci_free_consistent(qdev->pdev,
2860 qdev->small_buf_total_size,
2861 qdev->small_buf_virt_addr,
2862 qdev->small_buf_phy_addr);
2863
2864 qdev->small_buf_virt_addr = NULL;
2865 }
2866}
2867
2868static void ql_free_large_buffers(struct ql3_adapter *qdev)
2869{
2870 int i = 0;
2871 struct ql_rcv_buf_cb *lrg_buf_cb;
2872
1357bfcf 2873 for (i = 0; i < qdev->num_large_buffers; i++) {
5a4faa87
RM		 2874 lrg_buf_cb = &qdev->lrg_buf[i];
2875 if (lrg_buf_cb->skb) {
2876 dev_kfree_skb(lrg_buf_cb->skb);
2877 pci_unmap_single(qdev->pdev,
2878 pci_unmap_addr(lrg_buf_cb, mapaddr),
2879 pci_unmap_len(lrg_buf_cb, maplen),
2880 PCI_DMA_FROMDEVICE);
2881 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2882 } else {
2883 break;
2884 }
2885 }
2886}
2887
2888static void ql_init_large_buffers(struct ql3_adapter *qdev)
2889{
2890 int i;
2891 struct ql_rcv_buf_cb *lrg_buf_cb;
2892 struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2893
1357bfcf 2894 for (i = 0; i < qdev->num_large_buffers; i++) {
5a4faa87
RM		 2895 lrg_buf_cb = &qdev->lrg_buf[i];
2896 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2897 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2898 buf_addr_ele++;
2899 }
2900 qdev->lrg_buf_index = 0;
2901 qdev->lrg_buf_skb_check = 0;
2902}
2903
2904static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2905{
2906 int i;
2907 struct ql_rcv_buf_cb *lrg_buf_cb;
2908 struct sk_buff *skb;
0f8ab89e
BL		 2909 dma_addr_t map;
2910 int err;
5a4faa87 2911
1357bfcf 2912 for (i = 0; i < qdev->num_large_buffers; i++) {
cd238faa
BL		 2913 skb = netdev_alloc_skb(qdev->ndev,
2914 qdev->lrg_buffer_len);
5a4faa87
RM		 2915 if (unlikely(!skb)) {
2916 /* Better luck next round */
2917 printk(KERN_ERR PFX
2918 "%s: large buff alloc failed, "
2919 "for %d bytes at index %d.\n",
2920 qdev->ndev->name,
2921 qdev->lrg_buffer_len * 2, i);
2922 ql_free_large_buffers(qdev);
2923 return -ENOMEM;
2924 } else {
2925
2926 lrg_buf_cb = &qdev->lrg_buf[i];
2927 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2928 lrg_buf_cb->index = i;
2929 lrg_buf_cb->skb = skb;
2930 /*
2931 * We save some space to copy the ethhdr from first
2932 * buffer
2933 */
2934 skb_reserve(skb, QL_HEADER_SPACE);
2935 map = pci_map_single(qdev->pdev,
2936 skb->data,
2937 qdev->lrg_buffer_len -
2938 QL_HEADER_SPACE,
2939 PCI_DMA_FROMDEVICE);
0f8ab89e
BL		 2940
2941 err = pci_dma_mapping_error(map);
2942 if(err) {
2943 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2944 qdev->ndev->name, err);
2945 ql_free_large_buffers(qdev);
2946 return -ENOMEM;
2947 }
2948
5a4faa87
RM		 2949 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2950 pci_unmap_len_set(lrg_buf_cb, maplen,
2951 qdev->lrg_buffer_len -
2952 QL_HEADER_SPACE);
2953 lrg_buf_cb->buf_phy_addr_low =
2954 cpu_to_le32(LS_64BITS(map));
2955 lrg_buf_cb->buf_phy_addr_high =
2956 cpu_to_le32(MS_64BITS(map));
2957 }
2958 }
2959 return 0;
2960}
2961
bd36b0ac
RM		 2962static void ql_free_send_free_list(struct ql3_adapter *qdev)
2963{
2964 struct ql_tx_buf_cb *tx_cb;
2965 int i;
2966
2967 tx_cb = &qdev->tx_buf[0];
2968 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2969 if (tx_cb->oal) {
2970 kfree(tx_cb->oal);
2971 tx_cb->oal = NULL;
2972 }
2973 tx_cb++;
2974 }
2975}
2976
2977static int ql_create_send_free_list(struct ql3_adapter *qdev)
5a4faa87
RM		 2978{
2979 struct ql_tx_buf_cb *tx_cb;
2980 int i;
2981 struct ob_mac_iocb_req *req_q_curr =
2982 qdev->req_q_virt_addr;
2983
2984 /* Create free list of transmit buffers */
2985 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
bd36b0ac 2986
5a4faa87
RM		 2987 tx_cb = &qdev->tx_buf[i];
2988 tx_cb->skb = NULL;
2989 tx_cb->queue_entry = req_q_curr;
2990 req_q_curr++;
bd36b0ac
RM		 2991 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2992 if (tx_cb->oal == NULL)
2993 return -1;
5a4faa87 2994 }
bd36b0ac 2995 return 0;
5a4faa87
RM		 2996}
2997
2998static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2999{
1357bfcf
RM		 3000 if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
3001 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
5a4faa87 3002 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
1357bfcf 3003 }
5a4faa87 3004 else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
1357bfcf
RM		 3005 /*
3006 * Bigger buffers, so less of them.
3007 */
3008 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
5a4faa87
RM		 3009 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
3010 } else {
3011 printk(KERN_ERR PFX
3012 "%s: Invalid mtu size. Only 1500 and 9000 are accepted.\n",
3013 qdev->ndev->name);
3014 return -ENOMEM;
3015 }
1357bfcf 3016 qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
5a4faa87
RM		 3017 qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
3018 qdev->max_frame_size =
3019 (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
3020
3021 /*
3022 * First allocate a page of shared memory and use it for shadow
3023 * locations of Network Request Queue Consumer Address Register and
3024 * Network Completion Queue Producer Index Register
3025 */
3026 qdev->shadow_reg_virt_addr =
3027 pci_alloc_consistent(qdev->pdev,
3028 PAGE_SIZE, &qdev->shadow_reg_phy_addr);
3029
3030 if (qdev->shadow_reg_virt_addr != NULL) {
3031 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
3032 qdev->req_consumer_index_phy_addr_high =
3033 MS_64BITS(qdev->shadow_reg_phy_addr);
3034 qdev->req_consumer_index_phy_addr_low =
3035 LS_64BITS(qdev->shadow_reg_phy_addr);
3036
3037 qdev->prsp_producer_index =
3038 (u32 *) (((u8 *) qdev->preq_consumer_index) + 8);
3039 qdev->rsp_producer_index_phy_addr_high =
3040 qdev->req_consumer_index_phy_addr_high;
3041 qdev->rsp_producer_index_phy_addr_low =
3042 qdev->req_consumer_index_phy_addr_low + 8;
3043 } else {
3044 printk(KERN_ERR PFX
3045 "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
3046 return -ENOMEM;
3047 }
3048
3049 if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
3050 printk(KERN_ERR PFX
3051 "%s: ql_alloc_net_req_rsp_queues failed.\n",
3052 qdev->ndev->name);
3053 goto err_req_rsp;
3054 }
3055
3056 if (ql_alloc_buffer_queues(qdev) != 0) {
3057 printk(KERN_ERR PFX
3058 "%s: ql_alloc_buffer_queues failed.\n",
3059 qdev->ndev->name);
3060 goto err_buffer_queues;
3061 }
3062
3063 if (ql_alloc_small_buffers(qdev) != 0) {
3064 printk(KERN_ERR PFX
3065 "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
3066 goto err_small_buffers;
3067 }
3068
3069 if (ql_alloc_large_buffers(qdev) != 0) {
3070 printk(KERN_ERR PFX
3071 "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
3072 goto err_small_buffers;
3073 }
3074
3075 /* Initialize the large buffer queue. */
3076 ql_init_large_buffers(qdev);
bd36b0ac
RM		 3077 if (ql_create_send_free_list(qdev))
3078 goto err_free_list;
5a4faa87
RM		 3079
3080 qdev->rsp_current = qdev->rsp_q_virt_addr;
3081
3082 return 0;
bd36b0ac
RM		 3083err_free_list:
3084 ql_free_send_free_list(qdev);
5a4faa87
RM		 3085err_small_buffers:
3086 ql_free_buffer_queues(qdev);
3087err_buffer_queues:
3088 ql_free_net_req_rsp_queues(qdev);
3089err_req_rsp:
3090 pci_free_consistent(qdev->pdev,
3091 PAGE_SIZE,
3092 qdev->shadow_reg_virt_addr,
3093 qdev->shadow_reg_phy_addr);
3094
3095 return -ENOMEM;
3096}
3097
3098static void ql_free_mem_resources(struct ql3_adapter *qdev)
3099{
bd36b0ac 3100 ql_free_send_free_list(qdev);
5a4faa87
RM		 3101 ql_free_large_buffers(qdev);
3102 ql_free_small_buffers(qdev);
3103 ql_free_buffer_queues(qdev);
3104 ql_free_net_req_rsp_queues(qdev);
3105 if (qdev->shadow_reg_virt_addr != NULL) {
3106 pci_free_consistent(qdev->pdev,
3107 PAGE_SIZE,
3108 qdev->shadow_reg_virt_addr,
3109 qdev->shadow_reg_phy_addr);
3110 qdev->shadow_reg_virt_addr = NULL;
3111 }
3112}
3113
3114static int ql_init_misc_registers(struct ql3_adapter *qdev)
3115{
ee111d11
AV		 3116 struct ql3xxx_local_ram_registers __iomem *local_ram =
3117 (void __iomem *)qdev->mem_map_registers;
5a4faa87
RM		 3118
3119 if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
3120 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3121 2) << 4))
3122 return -1;
3123
3124 ql_write_page2_reg(qdev,
3125 &local_ram->bufletSize, qdev->nvram_data.bufletSize);
3126
3127 ql_write_page2_reg(qdev,
3128 &local_ram->maxBufletCount,
3129 qdev->nvram_data.bufletCount);
3130
3131 ql_write_page2_reg(qdev,
3132 &local_ram->freeBufletThresholdLow,
3133 (qdev->nvram_data.tcpWindowThreshold25 << 16) |
3134 (qdev->nvram_data.tcpWindowThreshold0));
3135
3136 ql_write_page2_reg(qdev,
3137 &local_ram->freeBufletThresholdHigh,
3138 qdev->nvram_data.tcpWindowThreshold50);
3139
3140 ql_write_page2_reg(qdev,
3141 &local_ram->ipHashTableBase,
3142 (qdev->nvram_data.ipHashTableBaseHi << 16) |
3143 qdev->nvram_data.ipHashTableBaseLo);
3144 ql_write_page2_reg(qdev,
3145 &local_ram->ipHashTableCount,
3146 qdev->nvram_data.ipHashTableSize);
3147 ql_write_page2_reg(qdev,
3148 &local_ram->tcpHashTableBase,
3149 (qdev->nvram_data.tcpHashTableBaseHi << 16) |
3150 qdev->nvram_data.tcpHashTableBaseLo);
3151 ql_write_page2_reg(qdev,
3152 &local_ram->tcpHashTableCount,
3153 qdev->nvram_data.tcpHashTableSize);
3154 ql_write_page2_reg(qdev,
3155 &local_ram->ncbBase,
3156 (qdev->nvram_data.ncbTableBaseHi << 16) |
3157 qdev->nvram_data.ncbTableBaseLo);
3158 ql_write_page2_reg(qdev,
3159 &local_ram->maxNcbCount,
3160 qdev->nvram_data.ncbTableSize);
3161 ql_write_page2_reg(qdev,
3162 &local_ram->drbBase,
3163 (qdev->nvram_data.drbTableBaseHi << 16) |
3164 qdev->nvram_data.drbTableBaseLo);
3165 ql_write_page2_reg(qdev,
3166 &local_ram->maxDrbCount,
3167 qdev->nvram_data.drbTableSize);
3168 ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
3169 return 0;
3170}
3171
3172static int ql_adapter_initialize(struct ql3_adapter *qdev)
3173{
3174 u32 value;
3175 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3176 struct ql3xxx_host_memory_registers __iomem *hmem_regs =
ee111d11 3177 (void __iomem *)port_regs;
5a4faa87
RM		 3178 u32 delay = 10;
3179 int status = 0;
3180
3181 if(ql_mii_setup(qdev))
3182 return -1;
3183
3184 /* Bring out PHY out of reset */
3185 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
3186 (ISP_SERIAL_PORT_IF_WE |
3187 (ISP_SERIAL_PORT_IF_WE << 16)));
3188
3189 qdev->port_link_state = LS_DOWN;
3190 netif_carrier_off(qdev->ndev);
3191
3192 /* V2 chip fix for ARS-39168. */
3193 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
3194 (ISP_SERIAL_PORT_IF_SDE |
3195 (ISP_SERIAL_PORT_IF_SDE << 16)));
3196
3197 /* Request Queue Registers */
3198 *((u32 *) (qdev->preq_consumer_index)) = 0;
3199 atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
3200 qdev->req_producer_index = 0;
3201
3202 ql_write_page1_reg(qdev,
3203 &hmem_regs->reqConsumerIndexAddrHigh,
3204 qdev->req_consumer_index_phy_addr_high);
3205 ql_write_page1_reg(qdev,
3206 &hmem_regs->reqConsumerIndexAddrLow,
3207 qdev->req_consumer_index_phy_addr_low);
3208
3209 ql_write_page1_reg(qdev,
3210 &hmem_regs->reqBaseAddrHigh,
3211 MS_64BITS(qdev->req_q_phy_addr));
3212 ql_write_page1_reg(qdev,
3213 &hmem_regs->reqBaseAddrLow,
3214 LS_64BITS(qdev->req_q_phy_addr));
3215 ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
3216
3217 /* Response Queue Registers */
3218 *((u16 *) (qdev->prsp_producer_index)) = 0;
3219 qdev->rsp_consumer_index = 0;
3220 qdev->rsp_current = qdev->rsp_q_virt_addr;
3221
3222 ql_write_page1_reg(qdev,
3223 &hmem_regs->rspProducerIndexAddrHigh,
3224 qdev->rsp_producer_index_phy_addr_high);
3225
3226 ql_write_page1_reg(qdev,
3227 &hmem_regs->rspProducerIndexAddrLow,
3228 qdev->rsp_producer_index_phy_addr_low);
3229
3230 ql_write_page1_reg(qdev,
3231 &hmem_regs->rspBaseAddrHigh,
3232 MS_64BITS(qdev->rsp_q_phy_addr));
3233
3234 ql_write_page1_reg(qdev,
3235 &hmem_regs->rspBaseAddrLow,
3236 LS_64BITS(qdev->rsp_q_phy_addr));
3237
3238 ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
3239
3240 /* Large Buffer Queue */
3241 ql_write_page1_reg(qdev,
3242 &hmem_regs->rxLargeQBaseAddrHigh,
3243 MS_64BITS(qdev->lrg_buf_q_phy_addr));
3244
3245 ql_write_page1_reg(qdev,
3246 &hmem_regs->rxLargeQBaseAddrLow,
3247 LS_64BITS(qdev->lrg_buf_q_phy_addr));
3248
1357bfcf 3249 ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries);
5a4faa87
RM		 3250
3251 ql_write_page1_reg(qdev,
3252 &hmem_regs->rxLargeBufferLength,
3253 qdev->lrg_buffer_len);
3254
3255 /* Small Buffer Queue */
3256 ql_write_page1_reg(qdev,
3257 &hmem_regs->rxSmallQBaseAddrHigh,
3258 MS_64BITS(qdev->small_buf_q_phy_addr));
3259
3260 ql_write_page1_reg(qdev,
3261 &hmem_regs->rxSmallQBaseAddrLow,
3262 LS_64BITS(qdev->small_buf_q_phy_addr));
3263
3264 ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3265 ql_write_page1_reg(qdev,
3266 &hmem_regs->rxSmallBufferLength,
3267 QL_SMALL_BUFFER_SIZE);
3268
3269 qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3270 qdev->small_buf_release_cnt = 8;
1357bfcf 3271 qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
5a4faa87
RM		 3272 qdev->lrg_buf_release_cnt = 8;
3273 qdev->lrg_buf_next_free =
3274 (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
3275 qdev->small_buf_index = 0;
3276 qdev->lrg_buf_index = 0;
3277 qdev->lrg_buf_free_count = 0;
3278 qdev->lrg_buf_free_head = NULL;
3279 qdev->lrg_buf_free_tail = NULL;
3280
3281 ql_write_common_reg(qdev,
ee111d11 3282 &port_regs->CommonRegs.
5a4faa87
RM		 3283 rxSmallQProducerIndex,
3284 qdev->small_buf_q_producer_index);
3285 ql_write_common_reg(qdev,
ee111d11 3286 &port_regs->CommonRegs.
5a4faa87
RM		 3287 rxLargeQProducerIndex,
3288 qdev->lrg_buf_q_producer_index);
3289
3290 /*
3291 * Find out if the chip has already been initialized. If it has, then
3292 * we skip some of the initialization.
3293 */
3294 clear_bit(QL_LINK_MASTER, &qdev->flags);
3295 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3296 if ((value & PORT_STATUS_IC) == 0) {
3297
3298 /* Chip has not been configured yet, so let it rip. */
3299 if(ql_init_misc_registers(qdev)) {
3300 status = -1;
3301 goto out;
3302 }
3303
5a4faa87
RM		 3304 value = qdev->nvram_data.tcpMaxWindowSize;
3305 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3306
3307 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3308
3309 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3310 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3311 * 2) << 13)) {
3312 status = -1;
3313 goto out;
3314 }
3315 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3316 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3317 (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3318 16) | (INTERNAL_CHIP_SD |
3319 INTERNAL_CHIP_WE)));
3320 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3321 }
3322
b3b1514c
RM		 3323 if (qdev->mac_index)
3324 ql_write_page0_reg(qdev,
3325 &port_regs->mac1MaxFrameLengthReg,
3326 qdev->max_frame_size);
3327 else
3328 ql_write_page0_reg(qdev,
3329 &port_regs->mac0MaxFrameLengthReg,
3330 qdev->max_frame_size);
5a4faa87
RM		 3331
3332 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3333 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3334 2) << 7)) {
3335 status = -1;
3336 goto out;
3337 }
3338
3efedf2e 3339 PHY_Setup(qdev);
5a4faa87
RM		 3340 ql_init_scan_mode(qdev);
3341 ql_get_phy_owner(qdev);
3342
3343 /* Load the MAC Configuration */
3344
3345 /* Program lower 32 bits of the MAC address */
3346 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3347 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3348 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3349 ((qdev->ndev->dev_addr[2] << 24)
3350 | (qdev->ndev->dev_addr[3] << 16)
3351 | (qdev->ndev->dev_addr[4] << 8)
3352 | qdev->ndev->dev_addr[5]));
3353
3354 /* Program top 16 bits of the MAC address */
3355 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3356 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3357 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3358 ((qdev->ndev->dev_addr[0] << 8)
3359 | qdev->ndev->dev_addr[1]));
3360
3361 /* Enable Primary MAC */
3362 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3363 ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3364 MAC_ADDR_INDIRECT_PTR_REG_PE));
3365
3366 /* Clear Primary and Secondary IP addresses */
3367 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3368 ((IP_ADDR_INDEX_REG_MASK << 16) |
3369 (qdev->mac_index << 2)));
3370 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3371
3372 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3373 ((IP_ADDR_INDEX_REG_MASK << 16) |
3374 ((qdev->mac_index << 2) + 1)));
3375 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3376
3377 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3378
3379 /* Indicate Configuration Complete */
3380 ql_write_page0_reg(qdev,
3381 &port_regs->portControl,
3382 ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3383
3384 do {
3385 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3386 if (value & PORT_STATUS_IC)
3387 break;
3388 msleep(500);
3389 } while (--delay);
3390
3391 if (delay == 0) {
3392 printk(KERN_ERR PFX
3393 "%s: Hw Initialization timeout.\n", qdev->ndev->name);
3394 status = -1;
3395 goto out;
3396 }
3397
3398 /* Enable Ethernet Function */
bd36b0ac
RM		 3399 if (qdev->device_id == QL3032_DEVICE_ID) {
3400 value =
3401 (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
b3b1514c
RM		 3402 QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3403 QL3032_PORT_CONTROL_ET);
bd36b0ac
RM		 3404 ql_write_page0_reg(qdev, &port_regs->functionControl,
3405 ((value << 16) | value));
3406 } else {
3407 value =
3408 (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3409 PORT_CONTROL_HH);
3410 ql_write_page0_reg(qdev, &port_regs->portControl,
3411 ((value << 16) | value));
3412 }
3413
5a4faa87
RM		 3414
3415out:
3416 return status;
3417}
3418
3419/*
3420 * Caller holds hw_lock.
3421 */
3422static int ql_adapter_reset(struct ql3_adapter *qdev)
3423{
3424 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3425 int status = 0;
3426 u16 value;
3427 int max_wait_time;
3428
3429 set_bit(QL_RESET_ACTIVE, &qdev->flags);
3430 clear_bit(QL_RESET_DONE, &qdev->flags);
3431
3432 /*
3433 * Issue soft reset to chip.
3434 */
3435 printk(KERN_DEBUG PFX
3436 "%s: Issue soft reset to chip.\n",
3437 qdev->ndev->name);
3438 ql_write_common_reg(qdev,
ee111d11 3439 &port_regs->CommonRegs.ispControlStatus,
5a4faa87
RM		 3440 ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3441
3442 /* Wait 3 seconds for reset to complete. */
3443 printk(KERN_DEBUG PFX
3444 "%s: Wait 10 milliseconds for reset to complete.\n",
3445 qdev->ndev->name);
3446
3447 /* Wait until the firmware tells us the Soft Reset is done */
3448 max_wait_time = 5;
3449 do {
3450 value =
3451 ql_read_common_reg(qdev,
3452 &port_regs->CommonRegs.ispControlStatus);
3453 if ((value & ISP_CONTROL_SR) == 0)
3454 break;
3455
3456 ssleep(1);
3457 } while ((--max_wait_time));
3458
3459 /*
3460 * Also, make sure that the Network Reset Interrupt bit has been
3461 * cleared after the soft reset has taken place.
3462 */
3463 value =
3464 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3465 if (value & ISP_CONTROL_RI) {
3466 printk(KERN_DEBUG PFX
3467 "ql_adapter_reset: clearing RI after reset.\n");
3468 ql_write_common_reg(qdev,
ee111d11 3469 &port_regs->CommonRegs.
5a4faa87
RM		 3470 ispControlStatus,
3471 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3472 }
3473
3474 if (max_wait_time == 0) {
3475 /* Issue Force Soft Reset */
3476 ql_write_common_reg(qdev,
ee111d11 3477 &port_regs->CommonRegs.
5a4faa87
RM		 3478 ispControlStatus,
3479 ((ISP_CONTROL_FSR << 16) |
3480 ISP_CONTROL_FSR));
3481 /*
3482 * Wait until the firmware tells us the Force Soft Reset is
3483 * done
3484 */
3485 max_wait_time = 5;
3486 do {
3487 value =
3488 ql_read_common_reg(qdev,
3489 &port_regs->CommonRegs.
3490 ispControlStatus);
3491 if ((value & ISP_CONTROL_FSR) == 0) {
3492 break;
3493 }
3494 ssleep(1);
3495 } while ((--max_wait_time));
3496 }
3497 if (max_wait_time == 0)
3498 status = 1;
3499
3500 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3501 set_bit(QL_RESET_DONE, &qdev->flags);
3502 return status;
3503}
3504
3505static void ql_set_mac_info(struct ql3_adapter *qdev)
3506{
3507 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3508 u32 value, port_status;
3509 u8 func_number;
3510
3511 /* Get the function number */
3512 value =
3513 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3514 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3515 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3516 switch (value & ISP_CONTROL_FN_MASK) {
3517 case ISP_CONTROL_FN0_NET:
3518 qdev->mac_index = 0;
3519 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3520 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3521 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3522 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3523 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3524 if (port_status & PORT_STATUS_SM0)
3525 set_bit(QL_LINK_OPTICAL,&qdev->flags);
3526 else
3527 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3528 break;
3529
3530 case ISP_CONTROL_FN1_NET:
3531 qdev->mac_index = 1;
3532 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3533 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3534 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3535 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3536 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3537 if (port_status & PORT_STATUS_SM1)
3538 set_bit(QL_LINK_OPTICAL,&qdev->flags);
3539 else
3540 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3541 break;
3542
3543 case ISP_CONTROL_FN0_SCSI:
3544 case ISP_CONTROL_FN1_SCSI:
3545 default:
3546 printk(KERN_DEBUG PFX
3547 "%s: Invalid function number, ispControlStatus = 0x%x\n",
3548 qdev->ndev->name,value);
3549 break;
3550 }
3551 qdev->numPorts = qdev->nvram_data.numPorts;
3552}
3553
3554static void ql_display_dev_info(struct net_device *ndev)
3555{
3556 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3557 struct pci_dev *pdev = qdev->pdev;
0795af57 3558 DECLARE_MAC_BUF(mac);
5a4faa87
RM		 3559
3560 printk(KERN_INFO PFX
bd36b0ac
RM		 3561 "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3562 DRV_NAME, qdev->index, qdev->chip_rev_id,
3563 (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
3564 qdev->pci_slot);
5a4faa87
RM		 3565 printk(KERN_INFO PFX
3566 "%s Interface.\n",
3567 test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
3568
3569 /*
3570 * Print PCI bus width/type.
3571 */
3572 printk(KERN_INFO PFX
3573 "Bus interface is %s %s.\n",
3574 ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3575 ((qdev->pci_x) ? "PCI-X" : "PCI"));
3576
3577 printk(KERN_INFO PFX
3578 "mem IO base address adjusted = 0x%p\n",
3579 qdev->mem_map_registers);
3580 printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
3581
3582 if (netif_msg_probe(qdev))
3583 printk(KERN_INFO PFX
0795af57
JP		 3584 "%s: MAC address %s\n",
3585 ndev->name, print_mac(mac, ndev->dev_addr));
5a4faa87
RM		 3586}
3587
3588static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3589{
3590 struct net_device *ndev = qdev->ndev;
3591 int retval = 0;
3592
3593 netif_stop_queue(ndev);
3594 netif_carrier_off(ndev);
3595
3596 clear_bit(QL_ADAPTER_UP,&qdev->flags);
3597 clear_bit(QL_LINK_MASTER,&qdev->flags);
3598
3599 ql_disable_interrupts(qdev);
3600
3601 free_irq(qdev->pdev->irq, ndev);
3602
3603 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3604 printk(KERN_INFO PFX
3605 "%s: calling pci_disable_msi().\n", qdev->ndev->name);
3606 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3607 pci_disable_msi(qdev->pdev);
3608 }
3609
3610 del_timer_sync(&qdev->adapter_timer);
3611
bea3348e 3612 napi_disable(&qdev->napi);
5a4faa87
RM		 3613
3614 if (do_reset) {
3615 int soft_reset;
3616 unsigned long hw_flags;
3617
3618 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3619 if (ql_wait_for_drvr_lock(qdev)) {
3620 if ((soft_reset = ql_adapter_reset(qdev))) {
3621 printk(KERN_ERR PFX
3622 "%s: ql_adapter_reset(%d) FAILED!\n",
3623 ndev->name, qdev->index);
3624 }
3625 printk(KERN_ERR PFX
3626 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
3627 } else {
3628 printk(KERN_ERR PFX
3629 "%s: Could not acquire driver lock to do "
3630 "reset!\n", ndev->name);
3631 retval = -1;
3632 }
3633 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3634 }
3635 ql_free_mem_resources(qdev);
3636 return retval;
3637}
3638
3639static int ql_adapter_up(struct ql3_adapter *qdev)
3640{
3641 struct net_device *ndev = qdev->ndev;
3642 int err;
38515e90 3643 unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
5a4faa87
RM		 3644 unsigned long hw_flags;
3645
3646 if (ql_alloc_mem_resources(qdev)) {
3647 printk(KERN_ERR PFX
3648 "%s Unable to allocate buffers.\n", ndev->name);
3649 return -ENOMEM;
3650 }
3651
3652 if (qdev->msi) {
3653 if (pci_enable_msi(qdev->pdev)) {
3654 printk(KERN_ERR PFX
3655 "%s: User requested MSI, but MSI failed to "
3656 "initialize. Continuing without MSI.\n",
3657 qdev->ndev->name);
3658 qdev->msi = 0;
3659 } else {
3660 printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3661 set_bit(QL_MSI_ENABLED,&qdev->flags);
38515e90 3662 irq_flags &= ~IRQF_SHARED;
5a4faa87
RM		 3663 }
3664 }
3665
3666 if ((err = request_irq(qdev->pdev->irq,
3667 ql3xxx_isr,
3668 irq_flags, ndev->name, ndev))) {
3669 printk(KERN_ERR PFX
3670 "%s: Failed to reserve interrupt %d already in use.\n",
3671 ndev->name, qdev->pdev->irq);
3672 goto err_irq;
3673 }
3674
3675 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3676
3677 if ((err = ql_wait_for_drvr_lock(qdev))) {
3678 if ((err = ql_adapter_initialize(qdev))) {
3679 printk(KERN_ERR PFX
3680 "%s: Unable to initialize adapter.\n",
3681 ndev->name);
3682 goto err_init;
3683 }
3684 printk(KERN_ERR PFX
3685 "%s: Releaseing driver lock.\n",ndev->name);
3686 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3687 } else {
3688 printk(KERN_ERR PFX
3689 "%s: Could not aquire driver lock.\n",
3690 ndev->name);
3691 goto err_lock;
3692 }
3693
3694 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3695
3696 set_bit(QL_ADAPTER_UP,&qdev->flags);
3697
3698 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3699
bea3348e 3700 napi_enable(&qdev->napi);
5a4faa87
RM		 3701 ql_enable_interrupts(qdev);
3702 return 0;
3703
3704err_init:
3705 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3706err_lock:
04f10773 3707 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87
RM		 3708 free_irq(qdev->pdev->irq, ndev);
3709err_irq:
3710 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3711 printk(KERN_INFO PFX
3712 "%s: calling pci_disable_msi().\n",
3713 qdev->ndev->name);
3714 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3715 pci_disable_msi(qdev->pdev);
3716 }
3717 return err;
3718}
3719
3720static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3721{
3722 if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3723 printk(KERN_ERR PFX
3724 "%s: Driver up/down cycle failed, "
3725 "closing device\n",qdev->ndev->name);
3726 dev_close(qdev->ndev);
3727 return -1;
3728 }
3729 return 0;
3730}
3731
3732static int ql3xxx_close(struct net_device *ndev)
3733{
3734 struct ql3_adapter *qdev = netdev_priv(ndev);
3735
3736 /*
3737 * Wait for device to recover from a reset.
3738 * (Rarely happens, but possible.)
3739 */
3740 while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3741 msleep(50);
3742
3743 ql_adapter_down(qdev,QL_DO_RESET);
3744 return 0;
3745}
3746
3747static int ql3xxx_open(struct net_device *ndev)
3748{
3749 struct ql3_adapter *qdev = netdev_priv(ndev);
3750 return (ql_adapter_up(qdev));
3751}
3752
5a4faa87
RM		 3753static void ql3xxx_set_multicast_list(struct net_device *ndev)
3754{
3755 /*
3756 * We are manually parsing the list in the net_device structure.
3757 */
3758 return;
3759}
3760
3761static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3762{
3763 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3764 struct ql3xxx_port_registers __iomem *port_regs =
3765 qdev->mem_map_registers;
3766 struct sockaddr *addr = p;
3767 unsigned long hw_flags;
3768
3769 if (netif_running(ndev))
3770 return -EBUSY;
3771
3772 if (!is_valid_ether_addr(addr->sa_data))
3773 return -EADDRNOTAVAIL;
3774
3775 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3776
3777 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3778 /* Program lower 32 bits of the MAC address */
3779 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3780 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3781 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3782 ((ndev->dev_addr[2] << 24) | (ndev->
3783 dev_addr[3] << 16) |
3784 (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3785
3786 /* Program top 16 bits of the MAC address */
3787 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3788 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3789 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3790 ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3791 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3792
3793 return 0;
3794}
3795
3796static void ql3xxx_tx_timeout(struct net_device *ndev)
3797{
3798 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3799
3800 printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3801 /*
3802 * Stop the queues, we've got a problem.
3803 */
3804 netif_stop_queue(ndev);
3805
3806 /*
3807 * Wake up the worker to process this event.
3808 */
c4028958 3809 queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
5a4faa87
RM		 3810}
3811
c4028958 3812static void ql_reset_work(struct work_struct *work)
5a4faa87 3813{
c4028958
DH		 3814 struct ql3_adapter *qdev =
3815 container_of(work, struct ql3_adapter, reset_work.work);
5a4faa87
RM		 3816 struct net_device *ndev = qdev->ndev;
3817 u32 value;
3818 struct ql_tx_buf_cb *tx_cb;
3819 int max_wait_time, i;
3820 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3821 unsigned long hw_flags;
3822
3823 if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3824 clear_bit(QL_LINK_MASTER,&qdev->flags);
3825
3826 /*
3827 * Loop through the active list and return the skb.
3828 */
3829 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
bd36b0ac 3830 int j;
5a4faa87
RM		 3831 tx_cb = &qdev->tx_buf[i];
3832 if (tx_cb->skb) {
5a4faa87
RM		 3833 printk(KERN_DEBUG PFX
3834 "%s: Freeing lost SKB.\n",
3835 qdev->ndev->name);
3836 pci_unmap_single(qdev->pdev,
bd36b0ac
RM		 3837 pci_unmap_addr(&tx_cb->map[0], mapaddr),
3838 pci_unmap_len(&tx_cb->map[0], maplen),
3839 PCI_DMA_TODEVICE);
3840 for(j=1;j<tx_cb->seg_count;j++) {
3841 pci_unmap_page(qdev->pdev,
3842 pci_unmap_addr(&tx_cb->map[j],mapaddr),
3843 pci_unmap_len(&tx_cb->map[j],maplen),
3844 PCI_DMA_TODEVICE);
3845 }
5a4faa87
RM		 3846 dev_kfree_skb(tx_cb->skb);
3847 tx_cb->skb = NULL;
3848 }
3849 }
3850
3851 printk(KERN_ERR PFX
3852 "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3853 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3854 ql_write_common_reg(qdev,
3855 &port_regs->CommonRegs.
3856 ispControlStatus,
3857 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3858 /*
3859 * Wait the for Soft Reset to Complete.
3860 */
3861 max_wait_time = 10;
3862 do {
3863 value = ql_read_common_reg(qdev,
3864 &port_regs->CommonRegs.
3865
3866 ispControlStatus);
3867 if ((value & ISP_CONTROL_SR) == 0) {
3868 printk(KERN_DEBUG PFX
3869 "%s: reset completed.\n",
3870 qdev->ndev->name);
3871 break;
3872 }
3873
3874 if (value & ISP_CONTROL_RI) {
3875 printk(KERN_DEBUG PFX
3876 "%s: clearing NRI after reset.\n",
3877 qdev->ndev->name);
3878 ql_write_common_reg(qdev,
ee111d11 3879 &port_regs->
5a4faa87
RM		 3880 CommonRegs.
3881 ispControlStatus,
3882 ((ISP_CONTROL_RI <<
3883 16) | ISP_CONTROL_RI));
3884 }
3885
3886 ssleep(1);
3887 } while (--max_wait_time);
3888 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3889
3890 if (value & ISP_CONTROL_SR) {
3891
3892 /*
3893 * Set the reset flags and clear the board again.
3894 * Nothing else to do...
3895 */
3896 printk(KERN_ERR PFX
3897 "%s: Timed out waiting for reset to "
3898 "complete.\n", ndev->name);
3899 printk(KERN_ERR PFX
3900 "%s: Do a reset.\n", ndev->name);
3901 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3902 clear_bit(QL_RESET_START,&qdev->flags);
3903 ql_cycle_adapter(qdev,QL_DO_RESET);
3904 return;
3905 }
3906
3907 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3908 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3909 clear_bit(QL_RESET_START,&qdev->flags);
3910 ql_cycle_adapter(qdev,QL_NO_RESET);
3911 }
3912}
3913
c4028958 3914static void ql_tx_timeout_work(struct work_struct *work)
5a4faa87 3915{
c4028958
DH		 3916 struct ql3_adapter *qdev =
3917 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3918
3919 ql_cycle_adapter(qdev, QL_DO_RESET);
5a4faa87
RM		 3920}
3921
3922static void ql_get_board_info(struct ql3_adapter *qdev)
3923{
3924 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3925 u32 value;
3926
3927 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3928
3929 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3930 if (value & PORT_STATUS_64)
3931 qdev->pci_width = 64;
3932 else
3933 qdev->pci_width = 32;
3934 if (value & PORT_STATUS_X)
3935 qdev->pci_x = 1;
3936 else
3937 qdev->pci_x = 0;
3938 qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3939}
3940
3941static void ql3xxx_timer(unsigned long ptr)
3942{
3943 struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3944
3945 if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
3946 printk(KERN_DEBUG PFX
3947 "%s: Reset in progress.\n",
3948 qdev->ndev->name);
3949 goto end;
3950 }
3951
3952 ql_link_state_machine(qdev);
3953
3954 /* Restart timer on 2 second interval. */
3955end:
3956 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3957}
3958
3959static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3960 const struct pci_device_id *pci_entry)
3961{
3962 struct net_device *ndev = NULL;
3963 struct ql3_adapter *qdev = NULL;
3964 static int cards_found = 0;
3965 int pci_using_dac, err;
3966
3967 err = pci_enable_device(pdev);
3968 if (err) {
3969 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3970 pci_name(pdev));
3971 goto err_out;
3972 }
3973
3974 err = pci_request_regions(pdev, DRV_NAME);
3975 if (err) {
3976 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3977 pci_name(pdev));
3978 goto err_out_disable_pdev;
3979 }
3980
3981 pci_set_master(pdev);
3982
3983 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3984 pci_using_dac = 1;
3985 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3986 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3987 pci_using_dac = 0;
3988 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3989 }
3990
3991 if (err) {
3992 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3993 pci_name(pdev));
3994 goto err_out_free_regions;
3995 }
3996
3997 ndev = alloc_etherdev(sizeof(struct ql3_adapter));
546faf07
BL		 3998 if (!ndev) {
3999 printk(KERN_ERR PFX "%s could not alloc etherdev\n",
4000 pci_name(pdev));
4001 err = -ENOMEM;
5a4faa87 4002 goto err_out_free_regions;
546faf07 4003 }
5a4faa87 4004
5a4faa87
RM		 4005 SET_NETDEV_DEV(ndev, &pdev->dev);
4006
5a4faa87
RM		 4007 pci_set_drvdata(pdev, ndev);
4008
4009 qdev = netdev_priv(ndev);
4010 qdev->index = cards_found;
4011 qdev->ndev = ndev;
4012 qdev->pdev = pdev;
bd36b0ac 4013 qdev->device_id = pci_entry->device;
5a4faa87
RM		 4014 qdev->port_link_state = LS_DOWN;
4015 if (msi)
4016 qdev->msi = 1;
4017
4018 qdev->msg_enable = netif_msg_init(debug, default_msg);
4019
bd36b0ac
RM		 4020 if (pci_using_dac)
4021 ndev->features |= NETIF_F_HIGHDMA;
4022 if (qdev->device_id == QL3032_DEVICE_ID)
e68a8c10 4023 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
bd36b0ac 4024
5a4faa87
RM		 4025 qdev->mem_map_registers =
4026 ioremap_nocache(pci_resource_start(pdev, 1),
4027 pci_resource_len(qdev->pdev, 1));
4028 if (!qdev->mem_map_registers) {
4029 printk(KERN_ERR PFX "%s: cannot map device registers\n",
4030 pci_name(pdev));
546faf07 4031 err = -EIO;
5a4faa87
RM		 4032 goto err_out_free_ndev;
4033 }
4034
4035 spin_lock_init(&qdev->adapter_lock);
4036 spin_lock_init(&qdev->hw_lock);
4037
4038 /* Set driver entry points */
4039 ndev->open = ql3xxx_open;
4040 ndev->hard_start_xmit = ql3xxx_send;
4041 ndev->stop = ql3xxx_close;
5a4faa87
RM		 4042 ndev->set_multicast_list = ql3xxx_set_multicast_list;
4043 SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
4044 ndev->set_mac_address = ql3xxx_set_mac_address;
4045 ndev->tx_timeout = ql3xxx_tx_timeout;
4046 ndev->watchdog_timeo = 5 * HZ;
4047
bea3348e 4048 netif_napi_add(ndev, &qdev->napi, ql_poll, 64);
5a4faa87
RM		 4049
4050 ndev->irq = pdev->irq;
4051
4052 /* make sure the EEPROM is good */
4053 if (ql_get_nvram_params(qdev)) {
4054 printk(KERN_ALERT PFX
4055 "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
4056 qdev->index);
546faf07 4057 err = -EIO;
5a4faa87
RM		 4058 goto err_out_iounmap;
4059 }
4060
4061 ql_set_mac_info(qdev);
4062
4063 /* Validate and set parameters */
4064 if (qdev->mac_index) {
cb8bac12 4065 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
5a4faa87
RM		 4066 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn2.macAddress,
4067 ETH_ALEN);
4068 } else {
cb8bac12 4069 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
5a4faa87
RM		 4070 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn0.macAddress,
4071 ETH_ALEN);
4072 }
4073 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
4074
4075 ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
4076
4077 /* Turn off support for multicasting */
4078 ndev->flags &= ~IFF_MULTICAST;
4079
4080 /* Record PCI bus information. */
4081 ql_get_board_info(qdev);
4082
4083 /*
4084 * Set the Maximum Memory Read Byte Count value. We do this to handle
4085 * jumbo frames.
4086 */
4087 if (qdev->pci_x) {
4088 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
4089 }
4090
4091 err = register_netdev(ndev);
4092 if (err) {
4093 printk(KERN_ERR PFX "%s: cannot register net device\n",
4094 pci_name(pdev));
4095 goto err_out_iounmap;
4096 }
4097
4098 /* we're going to reset, so assume we have no link for now */
4099
4100 netif_carrier_off(ndev);
4101 netif_stop_queue(ndev);
4102
4103 qdev->workqueue = create_singlethread_workqueue(ndev->name);
c4028958
DH		 4104 INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
4105 INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
5a4faa87
RM		 4106
4107 init_timer(&qdev->adapter_timer);
4108 qdev->adapter_timer.function = ql3xxx_timer;
4109 qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
4110 qdev->adapter_timer.data = (unsigned long)qdev;
4111
4112 if(!cards_found) {
4113 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
4114 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
4115 DRV_NAME, DRV_VERSION);
4116 }
4117 ql_display_dev_info(ndev);
4118
4119 cards_found++;
4120 return 0;
4121
4122err_out_iounmap:
4123 iounmap(qdev->mem_map_registers);
4124err_out_free_ndev:
4125 free_netdev(ndev);
4126err_out_free_regions:
4127 pci_release_regions(pdev);
4128err_out_disable_pdev:
4129 pci_disable_device(pdev);
4130 pci_set_drvdata(pdev, NULL);
4131err_out:
4132 return err;
4133}
4134
4135static void __devexit ql3xxx_remove(struct pci_dev *pdev)
4136{
4137 struct net_device *ndev = pci_get_drvdata(pdev);
4138 struct ql3_adapter *qdev = netdev_priv(ndev);
4139
4140 unregister_netdev(ndev);
4141 qdev = netdev_priv(ndev);
4142
4143 ql_disable_interrupts(qdev);
4144
4145 if (qdev->workqueue) {
4146 cancel_delayed_work(&qdev->reset_work);
4147 cancel_delayed_work(&qdev->tx_timeout_work);
4148 destroy_workqueue(qdev->workqueue);
4149 qdev->workqueue = NULL;
4150 }
4151
855fc73b 4152 iounmap(qdev->mem_map_registers);
5a4faa87
RM		 4153 pci_release_regions(pdev);
4154 pci_set_drvdata(pdev, NULL);
4155 free_netdev(ndev);
4156}
4157
4158static struct pci_driver ql3xxx_driver = {
4159
4160 .name = DRV_NAME,
4161 .id_table = ql3xxx_pci_tbl,
4162 .probe = ql3xxx_probe,
4163 .remove = __devexit_p(ql3xxx_remove),
4164};
4165
4166static int __init ql3xxx_init_module(void)
4167{
4168 return pci_register_driver(&ql3xxx_driver);
4169}
4170
4171static void __exit ql3xxx_exit(void)
4172{
4173 pci_unregister_driver(&ql3xxx_driver);
4174}
4175
4176module_init(ql3xxx_init_module);
4177module_exit(ql3xxx_exit);
Linux kernel - Deliverables
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