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af19b491 AKS |
1 | /* |
2 | * Copyright (C) 2009 - QLogic Corporation. | |
3 | * All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
19 | * | |
20 | * The full GNU General Public License is included in this distribution | |
21 | * in the file called "COPYING". | |
22 | * | |
23 | */ | |
24 | ||
25 | #ifndef _QLCNIC_H_ | |
26 | #define _QLCNIC_H_ | |
27 | ||
28 | #include <linux/module.h> | |
29 | #include <linux/kernel.h> | |
30 | #include <linux/types.h> | |
31 | #include <linux/ioport.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/in.h> | |
37 | #include <linux/tcp.h> | |
38 | #include <linux/skbuff.h> | |
39 | #include <linux/firmware.h> | |
40 | ||
41 | #include <linux/ethtool.h> | |
42 | #include <linux/mii.h> | |
43 | #include <linux/timer.h> | |
44 | ||
45 | #include <linux/vmalloc.h> | |
46 | ||
47 | #include <linux/io.h> | |
48 | #include <asm/byteorder.h> | |
49 | ||
50 | #include "qlcnic_hdr.h" | |
51 | ||
52 | #define _QLCNIC_LINUX_MAJOR 5 | |
53 | #define _QLCNIC_LINUX_MINOR 0 | |
cea8975e AC |
54 | #define _QLCNIC_LINUX_SUBVERSION 7 |
55 | #define QLCNIC_LINUX_VERSIONID "5.0.7" | |
96f8118c | 56 | #define QLCNIC_DRV_IDC_VER 0x01 |
af19b491 AKS |
57 | |
58 | #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) | |
59 | #define _major(v) (((v) >> 24) & 0xff) | |
60 | #define _minor(v) (((v) >> 16) & 0xff) | |
61 | #define _build(v) ((v) & 0xffff) | |
62 | ||
63 | /* version in image has weird encoding: | |
64 | * 7:0 - major | |
65 | * 15:8 - minor | |
66 | * 31:16 - build (little endian) | |
67 | */ | |
68 | #define QLCNIC_DECODE_VERSION(v) \ | |
69 | QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) | |
70 | ||
8f891387 | 71 | #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2) |
af19b491 AKS |
72 | #define QLCNIC_NUM_FLASH_SECTORS (64) |
73 | #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024) | |
74 | #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \ | |
75 | * QLCNIC_FLASH_SECTOR_SIZE) | |
76 | ||
77 | #define RCV_DESC_RINGSIZE(rds_ring) \ | |
78 | (sizeof(struct rcv_desc) * (rds_ring)->num_desc) | |
79 | #define RCV_BUFF_RINGSIZE(rds_ring) \ | |
80 | (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc) | |
81 | #define STATUS_DESC_RINGSIZE(sds_ring) \ | |
82 | (sizeof(struct status_desc) * (sds_ring)->num_desc) | |
83 | #define TX_BUFF_RINGSIZE(tx_ring) \ | |
84 | (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc) | |
85 | #define TX_DESC_RINGSIZE(tx_ring) \ | |
86 | (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) | |
87 | ||
88 | #define QLCNIC_P3P_A0 0x50 | |
89 | ||
90 | #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0) | |
91 | ||
92 | #define FIRST_PAGE_GROUP_START 0 | |
93 | #define FIRST_PAGE_GROUP_END 0x100000 | |
94 | ||
95 | #define P3_MAX_MTU (9600) | |
96 | #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */ | |
97 | ||
98 | #define QLCNIC_P3_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN) | |
99 | #define QLCNIC_P3_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3_MAX_MTU) | |
100 | #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 | |
101 | #define QLCNIC_LRO_BUFFER_EXTRA 2048 | |
102 | ||
af19b491 AKS |
103 | /* Opcodes to be used with the commands */ |
104 | #define TX_ETHER_PKT 0x01 | |
105 | #define TX_TCP_PKT 0x02 | |
106 | #define TX_UDP_PKT 0x03 | |
107 | #define TX_IP_PKT 0x04 | |
108 | #define TX_TCP_LSO 0x05 | |
109 | #define TX_TCP_LSO6 0x06 | |
110 | #define TX_IPSEC 0x07 | |
111 | #define TX_IPSEC_CMD 0x0a | |
112 | #define TX_TCPV6_PKT 0x0b | |
113 | #define TX_UDPV6_PKT 0x0c | |
114 | ||
115 | /* Tx defines */ | |
ef71ff83 RB |
116 | #define MAX_TSO_HEADER_DESC 2 |
117 | #define MGMT_CMD_DESC_RESV 4 | |
118 | #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \ | |
119 | + MGMT_CMD_DESC_RESV) | |
af19b491 AKS |
120 | #define QLCNIC_MAX_TX_TIMEOUTS 2 |
121 | ||
122 | /* | |
123 | * Following are the states of the Phantom. Phantom will set them and | |
124 | * Host will read to check if the fields are correct. | |
125 | */ | |
126 | #define PHAN_INITIALIZE_FAILED 0xffff | |
127 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | |
128 | ||
129 | /* Host writes the following to notify that it has done the init-handshake */ | |
130 | #define PHAN_INITIALIZE_ACK 0xf00f | |
131 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | |
132 | ||
133 | #define NUM_RCV_DESC_RINGS 3 | |
134 | #define NUM_STS_DESC_RINGS 4 | |
135 | ||
136 | #define RCV_RING_NORMAL 0 | |
137 | #define RCV_RING_JUMBO 1 | |
af19b491 AKS |
138 | |
139 | #define MIN_CMD_DESCRIPTORS 64 | |
140 | #define MIN_RCV_DESCRIPTORS 64 | |
141 | #define MIN_JUMBO_DESCRIPTORS 32 | |
142 | ||
143 | #define MAX_CMD_DESCRIPTORS 1024 | |
144 | #define MAX_RCV_DESCRIPTORS_1G 4096 | |
145 | #define MAX_RCV_DESCRIPTORS_10G 8192 | |
146 | #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 | |
147 | #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 | |
af19b491 AKS |
148 | |
149 | #define DEFAULT_RCV_DESCRIPTORS_1G 2048 | |
150 | #define DEFAULT_RCV_DESCRIPTORS_10G 4096 | |
251b036a | 151 | #define MAX_RDS_RINGS 2 |
af19b491 AKS |
152 | |
153 | #define get_next_index(index, length) \ | |
154 | (((index) + 1) & ((length) - 1)) | |
155 | ||
af19b491 AKS |
156 | /* |
157 | * Following data structures describe the descriptors that will be used. | |
158 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when | |
159 | * we are doing LSO (above the 1500 size packet) only. | |
160 | */ | |
161 | ||
162 | #define FLAGS_VLAN_TAGGED 0x10 | |
163 | #define FLAGS_VLAN_OOB 0x40 | |
164 | ||
165 | #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \ | |
166 | (cmd_desc)->vlan_TCI = cpu_to_le16(v); | |
167 | #define qlcnic_set_cmd_desc_port(cmd_desc, var) \ | |
168 | ((cmd_desc)->port_ctxid |= ((var) & 0x0F)) | |
169 | #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \ | |
170 | ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0)) | |
171 | ||
172 | #define qlcnic_set_tx_port(_desc, _port) \ | |
173 | ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)) | |
174 | ||
175 | #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \ | |
176 | ((_desc)->flags_opcode = \ | |
177 | cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))) | |
178 | ||
179 | #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \ | |
180 | ((_desc)->nfrags__length = \ | |
181 | cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))) | |
182 | ||
183 | struct cmd_desc_type0 { | |
184 | u8 tcp_hdr_offset; /* For LSO only */ | |
185 | u8 ip_hdr_offset; /* For LSO only */ | |
186 | __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ | |
187 | __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ | |
188 | ||
189 | __le64 addr_buffer2; | |
190 | ||
191 | __le16 reference_handle; | |
192 | __le16 mss; | |
193 | u8 port_ctxid; /* 7:4 ctxid 3:0 port */ | |
194 | u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ | |
195 | __le16 conn_id; /* IPSec offoad only */ | |
196 | ||
197 | __le64 addr_buffer3; | |
198 | __le64 addr_buffer1; | |
199 | ||
200 | __le16 buffer_length[4]; | |
201 | ||
202 | __le64 addr_buffer4; | |
203 | ||
2e9d722d | 204 | u8 eth_addr[ETH_ALEN]; |
af19b491 AKS |
205 | __le16 vlan_TCI; |
206 | ||
207 | } __attribute__ ((aligned(64))); | |
208 | ||
209 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ | |
210 | struct rcv_desc { | |
211 | __le16 reference_handle; | |
212 | __le16 reserved; | |
213 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ | |
214 | __le64 addr_buffer; | |
215 | }; | |
216 | ||
217 | /* opcode field in status_desc */ | |
218 | #define QLCNIC_SYN_OFFLOAD 0x03 | |
219 | #define QLCNIC_RXPKT_DESC 0x04 | |
220 | #define QLCNIC_OLD_RXPKT_DESC 0x3f | |
221 | #define QLCNIC_RESPONSE_DESC 0x05 | |
222 | #define QLCNIC_LRO_DESC 0x12 | |
223 | ||
224 | /* for status field in status_desc */ | |
225 | #define STATUS_CKSUM_OK (2) | |
226 | ||
227 | /* owner bits of status_desc */ | |
228 | #define STATUS_OWNER_HOST (0x1ULL << 56) | |
229 | #define STATUS_OWNER_PHANTOM (0x2ULL << 56) | |
230 | ||
231 | /* Status descriptor: | |
232 | 0-3 port, 4-7 status, 8-11 type, 12-27 total_length | |
233 | 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset | |
234 | 53-55 desc_cnt, 56-57 owner, 58-63 opcode | |
235 | */ | |
236 | #define qlcnic_get_sts_port(sts_data) \ | |
237 | ((sts_data) & 0x0F) | |
238 | #define qlcnic_get_sts_status(sts_data) \ | |
239 | (((sts_data) >> 4) & 0x0F) | |
240 | #define qlcnic_get_sts_type(sts_data) \ | |
241 | (((sts_data) >> 8) & 0x0F) | |
242 | #define qlcnic_get_sts_totallength(sts_data) \ | |
243 | (((sts_data) >> 12) & 0xFFFF) | |
244 | #define qlcnic_get_sts_refhandle(sts_data) \ | |
245 | (((sts_data) >> 28) & 0xFFFF) | |
246 | #define qlcnic_get_sts_prot(sts_data) \ | |
247 | (((sts_data) >> 44) & 0x0F) | |
248 | #define qlcnic_get_sts_pkt_offset(sts_data) \ | |
249 | (((sts_data) >> 48) & 0x1F) | |
250 | #define qlcnic_get_sts_desc_cnt(sts_data) \ | |
251 | (((sts_data) >> 53) & 0x7) | |
252 | #define qlcnic_get_sts_opcode(sts_data) \ | |
253 | (((sts_data) >> 58) & 0x03F) | |
254 | ||
255 | #define qlcnic_get_lro_sts_refhandle(sts_data) \ | |
256 | ((sts_data) & 0x0FFFF) | |
257 | #define qlcnic_get_lro_sts_length(sts_data) \ | |
258 | (((sts_data) >> 16) & 0x0FFFF) | |
259 | #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \ | |
260 | (((sts_data) >> 32) & 0x0FF) | |
261 | #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \ | |
262 | (((sts_data) >> 40) & 0x0FF) | |
263 | #define qlcnic_get_lro_sts_timestamp(sts_data) \ | |
264 | (((sts_data) >> 48) & 0x1) | |
265 | #define qlcnic_get_lro_sts_type(sts_data) \ | |
266 | (((sts_data) >> 49) & 0x7) | |
267 | #define qlcnic_get_lro_sts_push_flag(sts_data) \ | |
268 | (((sts_data) >> 52) & 0x1) | |
269 | #define qlcnic_get_lro_sts_seq_number(sts_data) \ | |
270 | ((sts_data) & 0x0FFFFFFFF) | |
271 | ||
272 | ||
273 | struct status_desc { | |
274 | __le64 status_desc_data[2]; | |
275 | } __attribute__ ((aligned(16))); | |
276 | ||
277 | /* UNIFIED ROMIMAGE */ | |
278 | #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000 | |
279 | #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0 | |
280 | #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6 | |
281 | #define QLCNIC_UNI_DIR_SECT_FW 0x7 | |
282 | ||
283 | /*Offsets */ | |
284 | #define QLCNIC_UNI_CHIP_REV_OFF 10 | |
285 | #define QLCNIC_UNI_FLAGS_OFF 11 | |
286 | #define QLCNIC_UNI_BIOS_VERSION_OFF 12 | |
287 | #define QLCNIC_UNI_BOOTLD_IDX_OFF 27 | |
288 | #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29 | |
289 | ||
290 | struct uni_table_desc{ | |
291 | u32 findex; | |
292 | u32 num_entries; | |
293 | u32 entry_size; | |
294 | u32 reserved[5]; | |
295 | }; | |
296 | ||
297 | struct uni_data_desc{ | |
298 | u32 findex; | |
299 | u32 size; | |
300 | u32 reserved[5]; | |
301 | }; | |
302 | ||
303 | /* Magic number to let user know flash is programmed */ | |
304 | #define QLCNIC_BDINFO_MAGIC 0x12345678 | |
305 | ||
306 | #define QLCNIC_BRDTYPE_P3_REF_QG 0x0021 | |
307 | #define QLCNIC_BRDTYPE_P3_HMEZ 0x0022 | |
308 | #define QLCNIC_BRDTYPE_P3_10G_CX4_LP 0x0023 | |
309 | #define QLCNIC_BRDTYPE_P3_4_GB 0x0024 | |
310 | #define QLCNIC_BRDTYPE_P3_IMEZ 0x0025 | |
311 | #define QLCNIC_BRDTYPE_P3_10G_SFP_PLUS 0x0026 | |
312 | #define QLCNIC_BRDTYPE_P3_10000_BASE_T 0x0027 | |
313 | #define QLCNIC_BRDTYPE_P3_XG_LOM 0x0028 | |
314 | #define QLCNIC_BRDTYPE_P3_4_GB_MM 0x0029 | |
315 | #define QLCNIC_BRDTYPE_P3_10G_SFP_CT 0x002a | |
316 | #define QLCNIC_BRDTYPE_P3_10G_SFP_QT 0x002b | |
317 | #define QLCNIC_BRDTYPE_P3_10G_CX4 0x0031 | |
318 | #define QLCNIC_BRDTYPE_P3_10G_XFP 0x0032 | |
319 | #define QLCNIC_BRDTYPE_P3_10G_TP 0x0080 | |
320 | ||
2e9d722d AC |
321 | #define QLCNIC_MSIX_TABLE_OFFSET 0x44 |
322 | ||
af19b491 AKS |
323 | /* Flash memory map */ |
324 | #define QLCNIC_BRDCFG_START 0x4000 /* board config */ | |
325 | #define QLCNIC_BOOTLD_START 0x10000 /* bootld */ | |
326 | #define QLCNIC_IMAGE_START 0x43000 /* compressed image */ | |
327 | #define QLCNIC_USER_START 0x3E8000 /* Firmare info */ | |
328 | ||
329 | #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408) | |
330 | #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c) | |
331 | #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c) | |
332 | #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c) | |
333 | ||
334 | #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8) | |
335 | #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128) | |
336 | ||
337 | #define QLCNIC_FW_MIN_SIZE (0x3fffff) | |
338 | #define QLCNIC_UNIFIED_ROMIMAGE 0 | |
339 | #define QLCNIC_FLASH_ROMIMAGE 1 | |
340 | #define QLCNIC_UNKNOWN_ROMIMAGE 0xff | |
341 | ||
342 | #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin" | |
343 | #define QLCNIC_FLASH_ROMIMAGE_NAME "flash" | |
344 | ||
345 | extern char qlcnic_driver_name[]; | |
346 | ||
347 | /* Number of status descriptors to handle per interrupt */ | |
348 | #define MAX_STATUS_HANDLE (64) | |
349 | ||
350 | /* | |
351 | * qlcnic_skb_frag{} is to contain mapping info for each SG list. This | |
352 | * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}. | |
353 | */ | |
354 | struct qlcnic_skb_frag { | |
355 | u64 dma; | |
356 | u64 length; | |
357 | }; | |
358 | ||
359 | struct qlcnic_recv_crb { | |
360 | u32 crb_rcv_producer[NUM_RCV_DESC_RINGS]; | |
361 | u32 crb_sts_consumer[NUM_STS_DESC_RINGS]; | |
362 | u32 sw_int_mask[NUM_STS_DESC_RINGS]; | |
363 | }; | |
364 | ||
365 | /* Following defines are for the state of the buffers */ | |
366 | #define QLCNIC_BUFFER_FREE 0 | |
367 | #define QLCNIC_BUFFER_BUSY 1 | |
368 | ||
369 | /* | |
370 | * There will be one qlcnic_buffer per skb packet. These will be | |
371 | * used to save the dma info for pci_unmap_page() | |
372 | */ | |
373 | struct qlcnic_cmd_buffer { | |
374 | struct sk_buff *skb; | |
ef71ff83 | 375 | struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1]; |
af19b491 AKS |
376 | u32 frag_count; |
377 | }; | |
378 | ||
379 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ | |
380 | struct qlcnic_rx_buffer { | |
381 | struct list_head list; | |
382 | struct sk_buff *skb; | |
383 | u64 dma; | |
384 | u16 ref_handle; | |
af19b491 AKS |
385 | }; |
386 | ||
387 | /* Board types */ | |
388 | #define QLCNIC_GBE 0x01 | |
389 | #define QLCNIC_XGBE 0x02 | |
390 | ||
391 | /* | |
392 | * One hardware_context{} per adapter | |
393 | * contains interrupt info as well shared hardware info. | |
394 | */ | |
395 | struct qlcnic_hardware_context { | |
396 | void __iomem *pci_base0; | |
397 | void __iomem *ocm_win_crb; | |
398 | ||
399 | unsigned long pci_len0; | |
400 | ||
af19b491 AKS |
401 | rwlock_t crb_lock; |
402 | struct mutex mem_lock; | |
403 | ||
af19b491 AKS |
404 | u8 revision_id; |
405 | u8 pci_func; | |
406 | u8 linkup; | |
407 | u16 port_type; | |
408 | u16 board_type; | |
409 | }; | |
410 | ||
411 | struct qlcnic_adapter_stats { | |
412 | u64 xmitcalled; | |
413 | u64 xmitfinished; | |
414 | u64 rxdropped; | |
415 | u64 txdropped; | |
416 | u64 csummed; | |
417 | u64 rx_pkts; | |
418 | u64 lro_pkts; | |
419 | u64 rxbytes; | |
420 | u64 txbytes; | |
8bfe8b91 SC |
421 | u64 lrobytes; |
422 | u64 lso_frames; | |
423 | u64 xmit_on; | |
424 | u64 xmit_off; | |
425 | u64 skb_alloc_failure; | |
8ae6df97 AKS |
426 | u64 null_rxbuf; |
427 | u64 rx_dma_map_error; | |
428 | u64 tx_dma_map_error; | |
af19b491 AKS |
429 | }; |
430 | ||
431 | /* | |
432 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may | |
433 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. | |
434 | */ | |
435 | struct qlcnic_host_rds_ring { | |
436 | u32 producer; | |
437 | u32 num_desc; | |
438 | u32 dma_size; | |
439 | u32 skb_size; | |
440 | u32 flags; | |
441 | void __iomem *crb_rcv_producer; | |
442 | struct rcv_desc *desc_head; | |
443 | struct qlcnic_rx_buffer *rx_buf_arr; | |
444 | struct list_head free_list; | |
445 | spinlock_t lock; | |
446 | dma_addr_t phys_addr; | |
447 | }; | |
448 | ||
449 | struct qlcnic_host_sds_ring { | |
450 | u32 consumer; | |
451 | u32 num_desc; | |
452 | void __iomem *crb_sts_consumer; | |
453 | void __iomem *crb_intr_mask; | |
454 | ||
455 | struct status_desc *desc_head; | |
456 | struct qlcnic_adapter *adapter; | |
457 | struct napi_struct napi; | |
458 | struct list_head free_list[NUM_RCV_DESC_RINGS]; | |
459 | ||
460 | int irq; | |
461 | ||
462 | dma_addr_t phys_addr; | |
463 | char name[IFNAMSIZ+4]; | |
464 | }; | |
465 | ||
466 | struct qlcnic_host_tx_ring { | |
467 | u32 producer; | |
468 | __le32 *hw_consumer; | |
469 | u32 sw_consumer; | |
470 | void __iomem *crb_cmd_producer; | |
471 | u32 num_desc; | |
472 | ||
473 | struct netdev_queue *txq; | |
474 | ||
475 | struct qlcnic_cmd_buffer *cmd_buf_arr; | |
476 | struct cmd_desc_type0 *desc_head; | |
477 | dma_addr_t phys_addr; | |
478 | dma_addr_t hw_cons_phys_addr; | |
479 | }; | |
480 | ||
481 | /* | |
482 | * Receive context. There is one such structure per instance of the | |
483 | * receive processing. Any state information that is relevant to | |
484 | * the receive, and is must be in this structure. The global data may be | |
485 | * present elsewhere. | |
486 | */ | |
487 | struct qlcnic_recv_context { | |
488 | u32 state; | |
489 | u16 context_id; | |
490 | u16 virt_port; | |
491 | ||
492 | struct qlcnic_host_rds_ring *rds_rings; | |
493 | struct qlcnic_host_sds_ring *sds_rings; | |
494 | }; | |
495 | ||
496 | /* HW context creation */ | |
497 | ||
498 | #define QLCNIC_OS_CRB_RETRY_COUNT 4000 | |
499 | #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \ | |
500 | (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16)) | |
501 | ||
502 | #define QLCNIC_CDRP_CMD_BIT 0x80000000 | |
503 | ||
504 | /* | |
505 | * All responses must have the QLCNIC_CDRP_CMD_BIT cleared | |
506 | * in the crb QLCNIC_CDRP_CRB_OFFSET. | |
507 | */ | |
508 | #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp) | |
509 | #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0) | |
510 | ||
511 | #define QLCNIC_CDRP_RSP_OK 0x00000001 | |
512 | #define QLCNIC_CDRP_RSP_FAIL 0x00000002 | |
513 | #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003 | |
514 | ||
515 | /* | |
516 | * All commands must have the QLCNIC_CDRP_CMD_BIT set in | |
517 | * the crb QLCNIC_CDRP_CRB_OFFSET. | |
518 | */ | |
519 | #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd)) | |
520 | #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0) | |
521 | ||
522 | #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001 | |
523 | #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002 | |
524 | #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003 | |
525 | #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004 | |
526 | #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005 | |
527 | #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006 | |
528 | #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007 | |
529 | #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008 | |
530 | #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009 | |
531 | #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a | |
532 | #define QLCNIC_CDRP_CMD_SETUP_STATISTICS 0x0000000e | |
533 | #define QLCNIC_CDRP_CMD_GET_STATISTICS 0x0000000f | |
534 | #define QLCNIC_CDRP_CMD_DELETE_STATISTICS 0x00000010 | |
535 | #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012 | |
536 | #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013 | |
537 | #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014 | |
538 | #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015 | |
539 | #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016 | |
540 | #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017 | |
541 | #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018 | |
542 | #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019 | |
543 | #define QLCNIC_CDRP_CMD_CONFIGURE_TOE 0x0000001a | |
544 | #define QLCNIC_CDRP_CMD_FUNC_ATTRIB 0x0000001b | |
545 | #define QLCNIC_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c | |
546 | #define QLCNIC_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d | |
547 | #define QLCNIC_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e | |
2e9d722d AC |
548 | #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f |
549 | ||
550 | #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020 | |
551 | #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021 | |
552 | #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022 | |
553 | #define QLCNIC_CDRP_CMD_RESET_NPAR 0x00000023 | |
554 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024 | |
555 | #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025 | |
556 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026 | |
557 | #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027 | |
558 | #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028 | |
4e8acb01 | 559 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029 |
b6021212 | 560 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a |
af19b491 AKS |
561 | |
562 | #define QLCNIC_RCODE_SUCCESS 0 | |
563 | #define QLCNIC_RCODE_TIMEOUT 17 | |
564 | #define QLCNIC_DESTROY_CTX_RESET 0 | |
565 | ||
566 | /* | |
567 | * Capabilities Announced | |
568 | */ | |
569 | #define QLCNIC_CAP0_LEGACY_CONTEXT (1) | |
570 | #define QLCNIC_CAP0_LEGACY_MN (1 << 2) | |
571 | #define QLCNIC_CAP0_LSO (1 << 6) | |
572 | #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7) | |
573 | #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8) | |
8f891387 | 574 | #define QLCNIC_CAP0_VALIDOFF (1 << 11) |
af19b491 AKS |
575 | |
576 | /* | |
577 | * Context state | |
578 | */ | |
d626ad4d | 579 | #define QLCNIC_HOST_CTX_STATE_FREED 0 |
af19b491 AKS |
580 | #define QLCNIC_HOST_CTX_STATE_ACTIVE 2 |
581 | ||
582 | /* | |
583 | * Rx context | |
584 | */ | |
585 | ||
586 | struct qlcnic_hostrq_sds_ring { | |
587 | __le64 host_phys_addr; /* Ring base addr */ | |
588 | __le32 ring_size; /* Ring entries */ | |
589 | __le16 msi_index; | |
590 | __le16 rsvd; /* Padding */ | |
591 | }; | |
592 | ||
593 | struct qlcnic_hostrq_rds_ring { | |
594 | __le64 host_phys_addr; /* Ring base addr */ | |
595 | __le64 buff_size; /* Packet buffer size */ | |
596 | __le32 ring_size; /* Ring entries */ | |
597 | __le32 ring_kind; /* Class of ring */ | |
598 | }; | |
599 | ||
600 | struct qlcnic_hostrq_rx_ctx { | |
601 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
602 | __le32 capabilities[4]; /* Flag bit vector */ | |
603 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
604 | __le32 host_rds_crb_mode; /* RDS crb usage */ | |
605 | /* These ring offsets are relative to data[0] below */ | |
606 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
607 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
608 | __le16 num_rds_rings; /* Count of RDS rings */ | |
609 | __le16 num_sds_rings; /* Count of SDS rings */ | |
8f891387 | 610 | __le16 valid_field_offset; |
611 | u8 txrx_sds_binding; | |
612 | u8 msix_handler; | |
613 | u8 reserved[128]; /* reserve space for future expansion*/ | |
af19b491 AKS |
614 | /* MUST BE 64-bit aligned. |
615 | The following is packed: | |
616 | - N hostrq_rds_rings | |
617 | - N hostrq_sds_rings */ | |
618 | char data[0]; | |
619 | }; | |
620 | ||
621 | struct qlcnic_cardrsp_rds_ring{ | |
622 | __le32 host_producer_crb; /* Crb to use */ | |
623 | __le32 rsvd1; /* Padding */ | |
624 | }; | |
625 | ||
626 | struct qlcnic_cardrsp_sds_ring { | |
627 | __le32 host_consumer_crb; /* Crb to use */ | |
628 | __le32 interrupt_crb; /* Crb to use */ | |
629 | }; | |
630 | ||
631 | struct qlcnic_cardrsp_rx_ctx { | |
632 | /* These ring offsets are relative to data[0] below */ | |
633 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
634 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
635 | __le32 host_ctx_state; /* Starting State */ | |
636 | __le32 num_fn_per_port; /* How many PCI fn share the port */ | |
637 | __le16 num_rds_rings; /* Count of RDS rings */ | |
638 | __le16 num_sds_rings; /* Count of SDS rings */ | |
639 | __le16 context_id; /* Handle for context */ | |
640 | u8 phys_port; /* Physical id of port */ | |
641 | u8 virt_port; /* Virtual/Logical id of port */ | |
642 | u8 reserved[128]; /* save space for future expansion */ | |
643 | /* MUST BE 64-bit aligned. | |
644 | The following is packed: | |
645 | - N cardrsp_rds_rings | |
646 | - N cardrs_sds_rings */ | |
647 | char data[0]; | |
648 | }; | |
649 | ||
650 | #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ | |
651 | (sizeof(HOSTRQ_RX) + \ | |
652 | (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \ | |
653 | (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring))) | |
654 | ||
655 | #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ | |
656 | (sizeof(CARDRSP_RX) + \ | |
657 | (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \ | |
658 | (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring))) | |
659 | ||
660 | /* | |
661 | * Tx context | |
662 | */ | |
663 | ||
664 | struct qlcnic_hostrq_cds_ring { | |
665 | __le64 host_phys_addr; /* Ring base addr */ | |
666 | __le32 ring_size; /* Ring entries */ | |
667 | __le32 rsvd; /* Padding */ | |
668 | }; | |
669 | ||
670 | struct qlcnic_hostrq_tx_ctx { | |
671 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
672 | __le64 cmd_cons_dma_addr; /* */ | |
673 | __le64 dummy_dma_addr; /* */ | |
674 | __le32 capabilities[4]; /* Flag bit vector */ | |
675 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
676 | __le32 rsvd1; /* Padding */ | |
677 | __le16 rsvd2; /* Padding */ | |
678 | __le16 interrupt_ctl; | |
679 | __le16 msi_index; | |
680 | __le16 rsvd3; /* Padding */ | |
681 | struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */ | |
682 | u8 reserved[128]; /* future expansion */ | |
683 | }; | |
684 | ||
685 | struct qlcnic_cardrsp_cds_ring { | |
686 | __le32 host_producer_crb; /* Crb to use */ | |
687 | __le32 interrupt_crb; /* Crb to use */ | |
688 | }; | |
689 | ||
690 | struct qlcnic_cardrsp_tx_ctx { | |
691 | __le32 host_ctx_state; /* Starting state */ | |
692 | __le16 context_id; /* Handle for context */ | |
693 | u8 phys_port; /* Physical id of port */ | |
694 | u8 virt_port; /* Virtual/Logical id of port */ | |
695 | struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */ | |
696 | u8 reserved[128]; /* future expansion */ | |
697 | }; | |
698 | ||
699 | #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) | |
700 | #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) | |
701 | ||
702 | /* CRB */ | |
703 | ||
704 | #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0 | |
705 | #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1 | |
706 | #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2 | |
707 | #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3 | |
708 | ||
709 | #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0 | |
710 | #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1 | |
711 | #define QLCNIC_HOST_INT_CRB_MODE_NORX 2 | |
712 | #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3 | |
713 | #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4 | |
714 | ||
715 | ||
716 | /* MAC */ | |
717 | ||
718 | #define MC_COUNT_P3 38 | |
719 | ||
720 | #define QLCNIC_MAC_NOOP 0 | |
721 | #define QLCNIC_MAC_ADD 1 | |
722 | #define QLCNIC_MAC_DEL 2 | |
723 | ||
724 | struct qlcnic_mac_list_s { | |
725 | struct list_head list; | |
726 | uint8_t mac_addr[ETH_ALEN+2]; | |
727 | }; | |
728 | ||
729 | /* | |
730 | * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is | |
731 | * adjusted based on configured MTU. | |
732 | */ | |
733 | #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3 | |
734 | #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256 | |
735 | #define QLCNIC_DEFAULT_INTR_COALESCE_TX_PACKETS 64 | |
736 | #define QLCNIC_DEFAULT_INTR_COALESCE_TX_TIME_US 4 | |
737 | ||
738 | #define QLCNIC_INTR_DEFAULT 0x04 | |
739 | ||
740 | union qlcnic_nic_intr_coalesce_data { | |
741 | struct { | |
742 | u16 rx_packets; | |
743 | u16 rx_time_us; | |
744 | u16 tx_packets; | |
745 | u16 tx_time_us; | |
746 | } data; | |
747 | u64 word; | |
748 | }; | |
749 | ||
750 | struct qlcnic_nic_intr_coalesce { | |
751 | u16 stats_time_us; | |
752 | u16 rate_sample_time; | |
753 | u16 flags; | |
754 | u16 rsvd_1; | |
755 | u32 low_threshold; | |
756 | u32 high_threshold; | |
757 | union qlcnic_nic_intr_coalesce_data normal; | |
758 | union qlcnic_nic_intr_coalesce_data low; | |
759 | union qlcnic_nic_intr_coalesce_data high; | |
760 | union qlcnic_nic_intr_coalesce_data irq; | |
761 | }; | |
762 | ||
763 | #define QLCNIC_HOST_REQUEST 0x13 | |
764 | #define QLCNIC_REQUEST 0x14 | |
765 | ||
766 | #define QLCNIC_MAC_EVENT 0x1 | |
767 | ||
768 | #define QLCNIC_IP_UP 2 | |
769 | #define QLCNIC_IP_DOWN 3 | |
770 | ||
771 | /* | |
772 | * Driver --> Firmware | |
773 | */ | |
774 | #define QLCNIC_H2C_OPCODE_START 0 | |
775 | #define QLCNIC_H2C_OPCODE_CONFIG_RSS 1 | |
776 | #define QLCNIC_H2C_OPCODE_CONFIG_RSS_TBL 2 | |
777 | #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3 | |
778 | #define QLCNIC_H2C_OPCODE_CONFIG_LED 4 | |
779 | #define QLCNIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5 | |
780 | #define QLCNIC_H2C_OPCODE_CONFIG_L2_MAC 6 | |
781 | #define QLCNIC_H2C_OPCODE_LRO_REQUEST 7 | |
782 | #define QLCNIC_H2C_OPCODE_GET_SNMP_STATS 8 | |
783 | #define QLCNIC_H2C_OPCODE_PROXY_START_REQUEST 9 | |
784 | #define QLCNIC_H2C_OPCODE_PROXY_STOP_REQUEST 10 | |
785 | #define QLCNIC_H2C_OPCODE_PROXY_SET_MTU 11 | |
786 | #define QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12 | |
787 | #define QLCNIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13 | |
788 | #define QLCNIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14 | |
789 | #define QLCNIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15 | |
790 | #define QLCNIC_H2C_OPCODE_GET_NET_STATS 16 | |
791 | #define QLCNIC_H2C_OPCODE_PROXY_UPDATE_P2V 17 | |
792 | #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 18 | |
793 | #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 19 | |
794 | #define QLCNIC_H2C_OPCODE_PROXY_STOP_DONE 20 | |
795 | #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 21 | |
796 | #define QLCNIC_C2C_OPCODE 22 | |
797 | #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 23 | |
798 | #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 24 | |
799 | #define QLCNIC_H2C_OPCODE_LAST 25 | |
800 | /* | |
801 | * Firmware --> Driver | |
802 | */ | |
803 | ||
804 | #define QLCNIC_C2H_OPCODE_START 128 | |
805 | #define QLCNIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129 | |
806 | #define QLCNIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130 | |
807 | #define QLCNIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131 | |
808 | #define QLCNIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132 | |
809 | #define QLCNIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133 | |
810 | #define QLCNIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134 | |
811 | #define QLCNIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135 | |
812 | #define QLCNIC_C2H_OPCODE_GET_SNMP_STATS 136 | |
813 | #define QLCNIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137 | |
814 | #define QLCNIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138 | |
815 | #define QLCNIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139 | |
816 | #define QLCNIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140 | |
817 | #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141 | |
818 | #define QLCNIC_C2H_OPCODE_LAST 142 | |
819 | ||
820 | #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ | |
821 | #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ | |
822 | #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ | |
823 | ||
824 | #define QLCNIC_LRO_REQUEST_CLEANUP 4 | |
825 | ||
826 | /* Capabilites received */ | |
ac8d0c4f AC |
827 | #define QLCNIC_FW_CAPABILITY_TSO BIT_1 |
828 | #define QLCNIC_FW_CAPABILITY_BDG BIT_8 | |
829 | #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9 | |
830 | #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10 | |
af19b491 AKS |
831 | |
832 | /* module types */ | |
833 | #define LINKEVENT_MODULE_NOT_PRESENT 1 | |
834 | #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 | |
835 | #define LINKEVENT_MODULE_OPTICAL_SRLR 3 | |
836 | #define LINKEVENT_MODULE_OPTICAL_LRM 4 | |
837 | #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 | |
838 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 | |
839 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 | |
840 | #define LINKEVENT_MODULE_TWINAX 8 | |
841 | ||
842 | #define LINKSPEED_10GBPS 10000 | |
843 | #define LINKSPEED_1GBPS 1000 | |
844 | #define LINKSPEED_100MBPS 100 | |
845 | #define LINKSPEED_10MBPS 10 | |
846 | ||
847 | #define LINKSPEED_ENCODED_10MBPS 0 | |
848 | #define LINKSPEED_ENCODED_100MBPS 1 | |
849 | #define LINKSPEED_ENCODED_1GBPS 2 | |
850 | ||
851 | #define LINKEVENT_AUTONEG_DISABLED 0 | |
852 | #define LINKEVENT_AUTONEG_ENABLED 1 | |
853 | ||
854 | #define LINKEVENT_HALF_DUPLEX 0 | |
855 | #define LINKEVENT_FULL_DUPLEX 1 | |
856 | ||
857 | #define LINKEVENT_LINKSPEED_MBPS 0 | |
858 | #define LINKEVENT_LINKSPEED_ENCODED 1 | |
859 | ||
860 | #define AUTO_FW_RESET_ENABLED 0x01 | |
861 | /* firmware response header: | |
862 | * 63:58 - message type | |
863 | * 57:56 - owner | |
864 | * 55:53 - desc count | |
865 | * 52:48 - reserved | |
866 | * 47:40 - completion id | |
867 | * 39:32 - opcode | |
868 | * 31:16 - error code | |
869 | * 15:00 - reserved | |
870 | */ | |
871 | #define qlcnic_get_nic_msg_opcode(msg_hdr) \ | |
872 | ((msg_hdr >> 32) & 0xFF) | |
873 | ||
874 | struct qlcnic_fw_msg { | |
875 | union { | |
876 | struct { | |
877 | u64 hdr; | |
878 | u64 body[7]; | |
879 | }; | |
880 | u64 words[8]; | |
881 | }; | |
882 | }; | |
883 | ||
884 | struct qlcnic_nic_req { | |
885 | __le64 qhdr; | |
886 | __le64 req_hdr; | |
887 | __le64 words[6]; | |
888 | }; | |
889 | ||
890 | struct qlcnic_mac_req { | |
891 | u8 op; | |
892 | u8 tag; | |
893 | u8 mac_addr[6]; | |
894 | }; | |
895 | ||
896 | #define QLCNIC_MSI_ENABLED 0x02 | |
897 | #define QLCNIC_MSIX_ENABLED 0x04 | |
898 | #define QLCNIC_LRO_ENABLED 0x08 | |
24763d80 | 899 | #define QLCNIC_LRO_DISABLED 0x00 |
af19b491 AKS |
900 | #define QLCNIC_BRIDGE_ENABLED 0X10 |
901 | #define QLCNIC_DIAG_ENABLED 0x20 | |
0e33c664 | 902 | #define QLCNIC_ESWITCH_ENABLED 0x40 |
af19b491 AKS |
903 | #define QLCNIC_IS_MSI_FAMILY(adapter) \ |
904 | ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED)) | |
905 | ||
906 | #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS | |
907 | #define QLCNIC_MSIX_TBL_SPACE 8192 | |
908 | #define QLCNIC_PCI_REG_MSIX_TBL 0x44 | |
2e9d722d | 909 | #define QLCNIC_MSIX_TBL_PGSIZE 4096 |
af19b491 AKS |
910 | |
911 | #define QLCNIC_NETDEV_WEIGHT 128 | |
912 | #define QLCNIC_ADAPTER_UP_MAGIC 777 | |
913 | ||
914 | #define __QLCNIC_FW_ATTACHED 0 | |
915 | #define __QLCNIC_DEV_UP 1 | |
916 | #define __QLCNIC_RESETTING 2 | |
917 | #define __QLCNIC_START_FW 4 | |
451724c8 | 918 | #define __QLCNIC_AER 5 |
af19b491 | 919 | |
7eb9855d | 920 | #define QLCNIC_INTERRUPT_TEST 1 |
cdaff185 | 921 | #define QLCNIC_LOOPBACK_TEST 2 |
7eb9855d | 922 | |
af19b491 AKS |
923 | struct qlcnic_adapter { |
924 | struct qlcnic_hardware_context ahw; | |
925 | ||
926 | struct net_device *netdev; | |
927 | struct pci_dev *pdev; | |
928 | struct list_head mac_list; | |
929 | ||
930 | spinlock_t tx_clean_lock; | |
931 | ||
932 | u16 num_txd; | |
933 | u16 num_rxd; | |
934 | u16 num_jumbo_rxd; | |
af19b491 AKS |
935 | |
936 | u8 max_rds_rings; | |
937 | u8 max_sds_rings; | |
af19b491 AKS |
938 | u8 msix_supported; |
939 | u8 rx_csum; | |
af19b491 AKS |
940 | u8 portnum; |
941 | u8 physical_port; | |
68bf1c68 | 942 | u8 reset_context; |
af19b491 AKS |
943 | |
944 | u8 mc_enabled; | |
945 | u8 max_mc_count; | |
946 | u8 rss_supported; | |
af19b491 AKS |
947 | u8 fw_wait_cnt; |
948 | u8 fw_fail_cnt; | |
949 | u8 tx_timeo_cnt; | |
950 | u8 need_fw_reset; | |
951 | ||
952 | u8 has_link_events; | |
953 | u8 fw_type; | |
954 | u16 tx_context_id; | |
af19b491 AKS |
955 | u16 is_up; |
956 | ||
957 | u16 link_speed; | |
958 | u16 link_duplex; | |
959 | u16 link_autoneg; | |
960 | u16 module_type; | |
961 | ||
2e9d722d AC |
962 | u16 op_mode; |
963 | u16 switch_mode; | |
964 | u16 max_tx_ques; | |
965 | u16 max_rx_ques; | |
2e9d722d AC |
966 | u16 max_mtu; |
967 | ||
968 | u32 fw_hal_version; | |
af19b491 AKS |
969 | u32 capabilities; |
970 | u32 flags; | |
971 | u32 irq; | |
972 | u32 temp; | |
973 | ||
974 | u32 int_vec_bit; | |
975 | u32 heartbit; | |
976 | ||
2e9d722d | 977 | u8 max_mac_filters; |
af19b491 | 978 | u8 dev_state; |
7eb9855d AKS |
979 | u8 diag_test; |
980 | u8 diag_cnt; | |
aa5e18c0 SC |
981 | u8 reset_ack_timeo; |
982 | u8 dev_init_timeo; | |
65b5b420 | 983 | u16 msg_enable; |
af19b491 AKS |
984 | |
985 | u8 mac_addr[ETH_ALEN]; | |
986 | ||
6df900e9 SC |
987 | u64 dev_rst_time; |
988 | ||
346fe763 | 989 | struct qlcnic_npar_info *npars; |
2e9d722d AC |
990 | struct qlcnic_eswitch *eswitch; |
991 | struct qlcnic_nic_template *nic_ops; | |
992 | ||
af19b491 AKS |
993 | struct qlcnic_adapter_stats stats; |
994 | ||
995 | struct qlcnic_recv_context recv_ctx; | |
996 | struct qlcnic_host_tx_ring *tx_ring; | |
997 | ||
998 | void __iomem *tgt_mask_reg; | |
999 | void __iomem *tgt_status_reg; | |
1000 | void __iomem *crb_int_state_reg; | |
1001 | void __iomem *isr_int_vec; | |
1002 | ||
1003 | struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER]; | |
1004 | ||
1005 | struct delayed_work fw_work; | |
1006 | ||
af19b491 AKS |
1007 | struct qlcnic_nic_intr_coalesce coal; |
1008 | ||
1009 | unsigned long state; | |
1010 | __le32 file_prd_off; /*File fw product offset*/ | |
1011 | u32 fw_version; | |
1012 | const struct firmware *fw; | |
1013 | }; | |
1014 | ||
2e9d722d AC |
1015 | struct qlcnic_info { |
1016 | __le16 pci_func; | |
1017 | __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */ | |
1018 | __le16 phys_port; | |
1019 | __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */ | |
1020 | ||
1021 | __le32 capabilities; | |
1022 | u8 max_mac_filters; | |
1023 | u8 reserved1; | |
1024 | __le16 max_mtu; | |
1025 | ||
1026 | __le16 max_tx_ques; | |
1027 | __le16 max_rx_ques; | |
1028 | __le16 min_tx_bw; | |
1029 | __le16 max_tx_bw; | |
1030 | u8 reserved2[104]; | |
1031 | }; | |
1032 | ||
1033 | struct qlcnic_pci_info { | |
1034 | __le16 id; /* pci function id */ | |
1035 | __le16 active; /* 1 = Enabled */ | |
1036 | __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */ | |
1037 | __le16 default_port; /* default port number */ | |
1038 | ||
1039 | __le16 tx_min_bw; /* Multiple of 100mbpc */ | |
1040 | __le16 tx_max_bw; | |
1041 | __le16 reserved1[2]; | |
1042 | ||
1043 | u8 mac[ETH_ALEN]; | |
1044 | u8 reserved2[106]; | |
1045 | }; | |
1046 | ||
346fe763 | 1047 | struct qlcnic_npar_info { |
4e8acb01 | 1048 | u16 pvid; |
cea8975e AC |
1049 | u16 min_bw; |
1050 | u16 max_bw; | |
346fe763 RB |
1051 | u8 phy_port; |
1052 | u8 type; | |
1053 | u8 active; | |
1054 | u8 enable_pm; | |
1055 | u8 dest_npar; | |
346fe763 RB |
1056 | u8 discard_tagged; |
1057 | u8 mac_learning; | |
4e8acb01 RB |
1058 | u8 mac_anti_spoof; |
1059 | u8 promisc_mode; | |
1060 | u8 offload_flags; | |
346fe763 | 1061 | }; |
4e8acb01 | 1062 | |
2e9d722d AC |
1063 | struct qlcnic_eswitch { |
1064 | u8 port; | |
1065 | u8 active_vports; | |
1066 | u8 active_vlans; | |
1067 | u8 active_ucast_filters; | |
1068 | u8 max_ucast_filters; | |
1069 | u8 max_active_vlans; | |
1070 | ||
1071 | u32 flags; | |
1072 | #define QLCNIC_SWITCH_ENABLE BIT_1 | |
1073 | #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2 | |
1074 | #define QLCNIC_SWITCH_PROMISC_MODE BIT_3 | |
1075 | #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4 | |
1076 | }; | |
1077 | ||
346fe763 RB |
1078 | |
1079 | /* Return codes for Error handling */ | |
1080 | #define QL_STATUS_INVALID_PARAM -1 | |
1081 | ||
9963a8bd RB |
1082 | #define MAX_BW 100 |
1083 | #define MIN_BW 1 | |
346fe763 RB |
1084 | #define MAX_VLAN_ID 4095 |
1085 | #define MIN_VLAN_ID 2 | |
1086 | #define MAX_TX_QUEUES 1 | |
1087 | #define MAX_RX_QUEUES 4 | |
1088 | #define DEFAULT_MAC_LEARN 1 | |
1089 | ||
1090 | #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan <= MAX_VLAN_ID) | |
9963a8bd | 1091 | #define IS_VALID_BW(bw) (bw >= MIN_BW && bw <= MAX_BW) |
346fe763 RB |
1092 | #define IS_VALID_TX_QUEUES(que) (que > 0 && que <= MAX_TX_QUEUES) |
1093 | #define IS_VALID_RX_QUEUES(que) (que > 0 && que <= MAX_RX_QUEUES) | |
346fe763 RB |
1094 | |
1095 | struct qlcnic_pci_func_cfg { | |
1096 | u16 func_type; | |
1097 | u16 min_bw; | |
1098 | u16 max_bw; | |
1099 | u16 port_num; | |
1100 | u8 pci_func; | |
1101 | u8 func_state; | |
1102 | u8 def_mac_addr[6]; | |
1103 | }; | |
1104 | ||
1105 | struct qlcnic_npar_func_cfg { | |
1106 | u32 fw_capab; | |
1107 | u16 port_num; | |
1108 | u16 min_bw; | |
1109 | u16 max_bw; | |
1110 | u16 max_tx_queues; | |
1111 | u16 max_rx_queues; | |
1112 | u8 pci_func; | |
1113 | u8 op_mode; | |
1114 | }; | |
1115 | ||
1116 | struct qlcnic_pm_func_cfg { | |
1117 | u8 pci_func; | |
1118 | u8 action; | |
1119 | u8 dest_npar; | |
1120 | u8 reserved[5]; | |
1121 | }; | |
1122 | ||
1123 | struct qlcnic_esw_func_cfg { | |
1124 | u16 vlan_id; | |
4e8acb01 RB |
1125 | u8 op_mode; |
1126 | u8 op_type; | |
346fe763 RB |
1127 | u8 pci_func; |
1128 | u8 host_vlan_tag; | |
1129 | u8 promisc_mode; | |
1130 | u8 discard_tagged; | |
1131 | u8 mac_learning; | |
4e8acb01 RB |
1132 | u8 mac_anti_spoof; |
1133 | u8 offload_flags; | |
1134 | u8 reserved[5]; | |
346fe763 RB |
1135 | }; |
1136 | ||
b6021212 AKS |
1137 | #define QLCNIC_STATS_VERSION 1 |
1138 | #define QLCNIC_STATS_PORT 1 | |
1139 | #define QLCNIC_STATS_ESWITCH 2 | |
1140 | #define QLCNIC_QUERY_RX_COUNTER 0 | |
1141 | #define QLCNIC_QUERY_TX_COUNTER 1 | |
1142 | struct __qlcnic_esw_statistics { | |
1143 | __le16 context_id; | |
1144 | __le16 version; | |
1145 | __le16 size; | |
1146 | __le16 unused; | |
1147 | __le64 unicast_frames; | |
1148 | __le64 multicast_frames; | |
1149 | __le64 broadcast_frames; | |
1150 | __le64 dropped_frames; | |
1151 | __le64 errors; | |
1152 | __le64 local_frames; | |
1153 | __le64 numbytes; | |
1154 | __le64 rsvd[3]; | |
1155 | }; | |
1156 | ||
1157 | struct qlcnic_esw_statistics { | |
1158 | struct __qlcnic_esw_statistics rx; | |
1159 | struct __qlcnic_esw_statistics tx; | |
1160 | }; | |
1161 | ||
af19b491 AKS |
1162 | int qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val); |
1163 | int qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val); | |
1164 | ||
1165 | u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off); | |
1166 | int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data); | |
1167 | int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data); | |
1168 | int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data); | |
897e8c7c DP |
1169 | void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *); |
1170 | void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64); | |
1171 | ||
1172 | #define ADDR_IN_RANGE(addr, low, high) \ | |
1173 | (((addr) < (high)) && ((addr) >= (low))) | |
af19b491 AKS |
1174 | |
1175 | #define QLCRD32(adapter, off) \ | |
1176 | (qlcnic_hw_read_wx_2M(adapter, off)) | |
1177 | #define QLCWR32(adapter, off, val) \ | |
1178 | (qlcnic_hw_write_wx_2M(adapter, off, val)) | |
1179 | ||
1180 | int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32); | |
1181 | void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int); | |
1182 | ||
1183 | #define qlcnic_rom_lock(a) \ | |
1184 | qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID) | |
1185 | #define qlcnic_rom_unlock(a) \ | |
1186 | qlcnic_pcie_sem_unlock((a), 2) | |
1187 | #define qlcnic_phy_lock(a) \ | |
1188 | qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID) | |
1189 | #define qlcnic_phy_unlock(a) \ | |
1190 | qlcnic_pcie_sem_unlock((a), 3) | |
1191 | #define qlcnic_api_lock(a) \ | |
1192 | qlcnic_pcie_sem_lock((a), 5, 0) | |
1193 | #define qlcnic_api_unlock(a) \ | |
1194 | qlcnic_pcie_sem_unlock((a), 5) | |
1195 | #define qlcnic_sw_lock(a) \ | |
1196 | qlcnic_pcie_sem_lock((a), 6, 0) | |
1197 | #define qlcnic_sw_unlock(a) \ | |
1198 | qlcnic_pcie_sem_unlock((a), 6) | |
1199 | #define crb_win_lock(a) \ | |
1200 | qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID) | |
1201 | #define crb_win_unlock(a) \ | |
1202 | qlcnic_pcie_sem_unlock((a), 7) | |
1203 | ||
1204 | int qlcnic_get_board_info(struct qlcnic_adapter *adapter); | |
1205 | int qlcnic_wol_supported(struct qlcnic_adapter *adapter); | |
897d3596 | 1206 | int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate); |
af19b491 AKS |
1207 | |
1208 | /* Functions from qlcnic_init.c */ | |
af19b491 AKS |
1209 | int qlcnic_load_firmware(struct qlcnic_adapter *adapter); |
1210 | int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter); | |
1211 | void qlcnic_request_firmware(struct qlcnic_adapter *adapter); | |
1212 | void qlcnic_release_firmware(struct qlcnic_adapter *adapter); | |
1213 | int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter); | |
b3a24649 | 1214 | int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); |
8f891387 | 1215 | int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter); |
af19b491 AKS |
1216 | |
1217 | int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp); | |
1218 | int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, | |
1219 | u8 *bytes, size_t size); | |
1220 | int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); | |
1221 | void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter); | |
1222 | ||
1223 | void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32); | |
1224 | ||
1225 | int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter); | |
1226 | void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter); | |
1227 | ||
8a15ad1f AKS |
1228 | int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter); |
1229 | void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter); | |
1230 | ||
1231 | void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter); | |
af19b491 AKS |
1232 | void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter); |
1233 | void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter); | |
1234 | ||
1235 | int qlcnic_init_firmware(struct qlcnic_adapter *adapter); | |
1236 | void qlcnic_watchdog_task(struct work_struct *work); | |
1237 | void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, u32 ringid, | |
1238 | struct qlcnic_host_rds_ring *rds_ring); | |
1239 | int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max); | |
1240 | void qlcnic_set_multi(struct net_device *netdev); | |
1241 | void qlcnic_free_mac_list(struct qlcnic_adapter *adapter); | |
1242 | int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32); | |
1243 | int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter); | |
1244 | int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable); | |
1245 | int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd); | |
1246 | int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable); | |
1247 | void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup); | |
1248 | ||
1249 | int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu); | |
1250 | int qlcnic_change_mtu(struct net_device *netdev, int new_mtu); | |
1251 | int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable); | |
2e9d722d | 1252 | int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable); |
af19b491 AKS |
1253 | int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter); |
1254 | void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter, | |
1255 | struct qlcnic_host_tx_ring *tx_ring); | |
2e9d722d | 1256 | int qlcnic_get_mac_addr(struct qlcnic_adapter *adapter, u8 *mac); |
cdaff185 AKS |
1257 | void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter); |
1258 | int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter); | |
2e9d722d | 1259 | void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *); |
af19b491 AKS |
1260 | |
1261 | /* Functions from qlcnic_main.c */ | |
1262 | int qlcnic_reset_context(struct qlcnic_adapter *); | |
7eb9855d AKS |
1263 | u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter, |
1264 | u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd); | |
1265 | void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings); | |
1266 | int qlcnic_diag_alloc_res(struct net_device *netdev, int test); | |
cdaff185 AKS |
1267 | int qlcnic_check_loopback_buff(unsigned char *data); |
1268 | netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev); | |
1269 | void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring); | |
af19b491 | 1270 | |
2e9d722d AC |
1271 | /* Management functions */ |
1272 | int qlcnic_set_mac_address(struct qlcnic_adapter *, u8*); | |
1273 | int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*); | |
346fe763 | 1274 | int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8); |
2e9d722d | 1275 | int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *); |
346fe763 | 1276 | int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*); |
2e9d722d AC |
1277 | int qlcnic_reset_partition(struct qlcnic_adapter *, u8); |
1278 | ||
1279 | /* eSwitch management functions */ | |
1280 | int qlcnic_get_eswitch_capabilities(struct qlcnic_adapter *, u8, | |
1281 | struct qlcnic_eswitch *); | |
1282 | int qlcnic_get_eswitch_status(struct qlcnic_adapter *, u8, | |
1283 | struct qlcnic_eswitch *); | |
1284 | int qlcnic_toggle_eswitch(struct qlcnic_adapter *, u8, u8); | |
4e8acb01 RB |
1285 | int qlcnic_config_switch_port(struct qlcnic_adapter *, |
1286 | struct qlcnic_esw_func_cfg *); | |
1287 | int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *, | |
1288 | struct qlcnic_esw_func_cfg *); | |
2e9d722d | 1289 | int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8); |
b6021212 AKS |
1290 | int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8, |
1291 | struct __qlcnic_esw_statistics *); | |
1292 | int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8, | |
1293 | struct __qlcnic_esw_statistics *); | |
1294 | int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8); | |
2e9d722d AC |
1295 | extern int qlcnic_config_tso; |
1296 | ||
af19b491 AKS |
1297 | /* |
1298 | * QLOGIC Board information | |
1299 | */ | |
1300 | ||
02420be6 | 1301 | #define QLCNIC_MAX_BOARD_NAME_LEN 100 |
af19b491 AKS |
1302 | struct qlcnic_brdinfo { |
1303 | unsigned short vendor; | |
1304 | unsigned short device; | |
1305 | unsigned short sub_vendor; | |
1306 | unsigned short sub_device; | |
1307 | char short_name[QLCNIC_MAX_BOARD_NAME_LEN]; | |
1308 | }; | |
1309 | ||
1310 | static const struct qlcnic_brdinfo qlcnic_boards[] = { | |
02420be6 | 1311 | {0x1077, 0x8020, 0x1077, 0x203, |
1515faf2 AKS |
1312 | "8200 Series Single Port 10GbE Converged Network Adapter " |
1313 | "(TCP/IP Networking)"}, | |
02420be6 | 1314 | {0x1077, 0x8020, 0x1077, 0x207, |
1515faf2 AKS |
1315 | "8200 Series Dual Port 10GbE Converged Network Adapter " |
1316 | "(TCP/IP Networking)"}, | |
af19b491 AKS |
1317 | {0x1077, 0x8020, 0x1077, 0x20b, |
1318 | "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"}, | |
1319 | {0x1077, 0x8020, 0x1077, 0x20c, | |
1320 | "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"}, | |
1321 | {0x1077, 0x8020, 0x1077, 0x20f, | |
1322 | "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"}, | |
1323 | {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"}, | |
1324 | }; | |
1325 | ||
1326 | #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards) | |
1327 | ||
1328 | static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring) | |
1329 | { | |
1330 | smp_mb(); | |
1331 | if (tx_ring->producer < tx_ring->sw_consumer) | |
1332 | return tx_ring->sw_consumer - tx_ring->producer; | |
1333 | else | |
1334 | return tx_ring->sw_consumer + tx_ring->num_desc - | |
1335 | tx_ring->producer; | |
1336 | } | |
1337 | ||
1338 | extern const struct ethtool_ops qlcnic_ethtool_ops; | |
1339 | ||
2e9d722d AC |
1340 | struct qlcnic_nic_template { |
1341 | int (*get_mac_addr) (struct qlcnic_adapter *, u8*); | |
1342 | int (*config_bridged_mode) (struct qlcnic_adapter *, u32); | |
1343 | int (*config_led) (struct qlcnic_adapter *, u32, u32); | |
9f26f547 | 1344 | int (*start_firmware) (struct qlcnic_adapter *); |
2e9d722d AC |
1345 | }; |
1346 | ||
65b5b420 AKS |
1347 | #define QLCDB(adapter, lvl, _fmt, _args...) do { \ |
1348 | if (NETIF_MSG_##lvl & adapter->msg_enable) \ | |
1349 | printk(KERN_INFO "%s: %s: " _fmt, \ | |
1350 | dev_name(&adapter->pdev->dev), \ | |
1351 | __func__, ##_args); \ | |
1352 | } while (0) | |
1353 | ||
af19b491 | 1354 | #endif /* __QLCNIC_H_ */ |