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qlcnic: updated supported cards information
[deliverable/linux.git] / drivers / net / qlcnic / qlcnic_hw.c
CommitLineData
af19b491 1/*
40839129
SV		 2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2010 QLogic Corporation
af19b491 4 *
40839129 5 * See LICENSE.qlcnic for copyright and licensing details.
af19b491
AKS		 6 */
7
8#include "qlcnic.h"
9
5a0e3ad6 10#include <linux/slab.h>
af19b491 11#include <net/ip.h>
18f2f616 12#include <linux/bitops.h>
af19b491
AKS		 13
14#define MASK(n) ((1ULL<<(n))-1)
15#define OCM_WIN_P3P(addr) (addr & 0xffc0000)
16
17#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
18
19#define CRB_BLK(off) ((off >> 20) & 0x3f)
20#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
21#define CRB_WINDOW_2M (0x130060)
22#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
23#define CRB_INDIRECT_2M (0x1e0000UL)
24
25
26#ifndef readq
27static inline u64 readq(void __iomem *addr)
28{
29 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
30}
31#endif
32
33#ifndef writeq
34static inline void writeq(u64 val, void __iomem *addr)
35{
36 writel(((u32) (val)), (addr));
37 writel(((u32) (val >> 32)), (addr + 4));
38}
39#endif
40
af19b491
AKS		 41static const struct crb_128M_2M_block_map
42crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
43 {{{0, 0, 0, 0} } }, /* 0: PCI */
44 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
45 {1, 0x0110000, 0x0120000, 0x130000},
46 {1, 0x0120000, 0x0122000, 0x124000},
47 {1, 0x0130000, 0x0132000, 0x126000},
48 {1, 0x0140000, 0x0142000, 0x128000},
49 {1, 0x0150000, 0x0152000, 0x12a000},
50 {1, 0x0160000, 0x0170000, 0x110000},
51 {1, 0x0170000, 0x0172000, 0x12e000},
52 {0, 0x0000000, 0x0000000, 0x000000},
53 {0, 0x0000000, 0x0000000, 0x000000},
54 {0, 0x0000000, 0x0000000, 0x000000},
55 {0, 0x0000000, 0x0000000, 0x000000},
56 {0, 0x0000000, 0x0000000, 0x000000},
57 {0, 0x0000000, 0x0000000, 0x000000},
58 {1, 0x01e0000, 0x01e0800, 0x122000},
59 {0, 0x0000000, 0x0000000, 0x000000} } },
60 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
61 {{{0, 0, 0, 0} } }, /* 3: */
62 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
63 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
64 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
65 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
66 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {0, 0x0000000, 0x0000000, 0x000000},
72 {0, 0x0000000, 0x0000000, 0x000000},
73 {0, 0x0000000, 0x0000000, 0x000000},
74 {0, 0x0000000, 0x0000000, 0x000000},
75 {0, 0x0000000, 0x0000000, 0x000000},
76 {0, 0x0000000, 0x0000000, 0x000000},
77 {0, 0x0000000, 0x0000000, 0x000000},
78 {0, 0x0000000, 0x0000000, 0x000000},
79 {0, 0x0000000, 0x0000000, 0x000000},
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {1, 0x08f0000, 0x08f2000, 0x172000} } },
82 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {1, 0x09f0000, 0x09f2000, 0x176000} } },
98 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
114 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
130 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
131 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
132 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
133 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
134 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
135 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
136 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
137 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
138 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
139 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
140 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
141 {{{0, 0, 0, 0} } }, /* 23: */
142 {{{0, 0, 0, 0} } }, /* 24: */
143 {{{0, 0, 0, 0} } }, /* 25: */
144 {{{0, 0, 0, 0} } }, /* 26: */
145 {{{0, 0, 0, 0} } }, /* 27: */
146 {{{0, 0, 0, 0} } }, /* 28: */
147 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
148 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
149 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
150 {{{0} } }, /* 32: PCI */
151 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
152 {1, 0x2110000, 0x2120000, 0x130000},
153 {1, 0x2120000, 0x2122000, 0x124000},
154 {1, 0x2130000, 0x2132000, 0x126000},
155 {1, 0x2140000, 0x2142000, 0x128000},
156 {1, 0x2150000, 0x2152000, 0x12a000},
157 {1, 0x2160000, 0x2170000, 0x110000},
158 {1, 0x2170000, 0x2172000, 0x12e000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000} } },
167 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
168 {{{0} } }, /* 35: */
169 {{{0} } }, /* 36: */
170 {{{0} } }, /* 37: */
171 {{{0} } }, /* 38: */
172 {{{0} } }, /* 39: */
173 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
174 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
175 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
176 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
177 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
178 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
179 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
180 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
181 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
182 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
183 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
184 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
185 {{{0} } }, /* 52: */
186 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
187 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
188 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
189 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
190 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
191 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
192 {{{0} } }, /* 59: I2C0 */
193 {{{0} } }, /* 60: I2C1 */
194 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
195 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
196 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
197};
198
199/*
200 * top 12 bits of crb internal address (hub, agent)
201 */
202static const unsigned crb_hub_agt[64] = {
203 0,
204 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
205 QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
206 QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
207 0,
208 QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
209 QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
210 QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
211 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
212 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
213 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
214 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
215 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
216 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
217 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
218 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
219 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
220 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
221 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
222 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
223 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
224 QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
225 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
226 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
227 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
228 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
229 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
230 0,
231 QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
232 QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
233 0,
234 QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
235 0,
236 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
237 QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
238 0,
239 0,
240 0,
241 0,
242 0,
243 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
244 0,
245 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
246 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
247 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
248 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
249 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
250 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
251 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
252 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
253 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
254 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
255 0,
256 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
257 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
258 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
259 QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
260 0,
261 QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
262 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
263 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
264 0,
265 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
266 0,
267};
268
269/* PCI Windowing for DDR regions. */
270
271#define QLCNIC_PCIE_SEM_TIMEOUT 10000
272
273int
274qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
275{
276 int done = 0, timeout = 0;
277
278 while (!done) {
279 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
280 if (done == 1)
281 break;
65b5b420
AKS		 282 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
283 dev_err(&adapter->pdev->dev,
091754a1
SC		 284 "Failed to acquire sem=%d lock; holdby=%d\n",
285 sem, id_reg ? QLCRD32(adapter, id_reg) : -1);
af19b491 286 return -EIO;
65b5b420 287 }
af19b491
AKS		 288 msleep(1);
289 }
290
291 if (id_reg)
292 QLCWR32(adapter, id_reg, adapter->portnum);
293
294 return 0;
295}
296
297void
298qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
299{
300 QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
301}
302
303static int
304qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
305 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
306{
307 u32 i, producer, consumer;
308 struct qlcnic_cmd_buffer *pbuf;
309 struct cmd_desc_type0 *cmd_desc;
310 struct qlcnic_host_tx_ring *tx_ring;
311
312 i = 0;
313
8a15ad1f 314 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
af19b491
AKS		 315 return -EIO;
316
317 tx_ring = adapter->tx_ring;
318 __netif_tx_lock_bh(tx_ring->txq);
319
320 producer = tx_ring->producer;
321 consumer = tx_ring->sw_consumer;
322
323 if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
324 netif_tx_stop_queue(tx_ring->txq);
ef71ff83
RB		 325 smp_mb();
326 if (qlcnic_tx_avail(tx_ring) > nr_desc) {
327 if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
328 netif_tx_wake_queue(tx_ring->txq);
329 } else {
330 adapter->stats.xmit_off++;
331 __netif_tx_unlock_bh(tx_ring->txq);
332 return -EBUSY;
333 }
af19b491
AKS		 334 }
335
336 do {
337 cmd_desc = &cmd_desc_arr[i];
338
339 pbuf = &tx_ring->cmd_buf_arr[producer];
340 pbuf->skb = NULL;
341 pbuf->frag_count = 0;
342
343 memcpy(&tx_ring->desc_head[producer],
344 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
345
346 producer = get_next_index(producer, tx_ring->num_desc);
347 i++;
348
349 } while (i != nr_desc);
350
351 tx_ring->producer = producer;
352
353 qlcnic_update_cmd_producer(adapter, tx_ring);
354
355 __netif_tx_unlock_bh(tx_ring->txq);
356
357 return 0;
358}
359
360static int
361qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
7e56cac4 362 __le16 vlan_id, unsigned op)
af19b491
AKS		 363{
364 struct qlcnic_nic_req req;
365 struct qlcnic_mac_req *mac_req;
7e56cac4 366 struct qlcnic_vlan_req *vlan_req;
af19b491
AKS		 367 u64 word;
368
369 memset(&req, 0, sizeof(struct qlcnic_nic_req));
370 req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
371
372 word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
373 req.req_hdr = cpu_to_le64(word);
374
375 mac_req = (struct qlcnic_mac_req *)&req.words[0];
376 mac_req->op = op;
377 memcpy(mac_req->mac_addr, addr, 6);
378
7e56cac4
SC		 379 vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
380 vlan_req->vlan_id = vlan_id;
03c5d770 381
af19b491
AKS		 382 return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
383}
384
215faf9c 385static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr)
af19b491
AKS		 386{
387 struct list_head *head;
388 struct qlcnic_mac_list_s *cur;
389
390 /* look up if already exists */
9ab17b39 391 list_for_each(head, &adapter->mac_list) {
af19b491 392 cur = list_entry(head, struct qlcnic_mac_list_s, list);
9ab17b39 393 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
af19b491 394 return 0;
af19b491
AKS		 395 }
396
397 cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
398 if (cur == NULL) {
399 dev_err(&adapter->netdev->dev,
400 "failed to add mac address filter\n");
401 return -ENOMEM;
402 }
403 memcpy(cur->mac_addr, addr, ETH_ALEN);
af19b491 404
42f65cba 405 if (qlcnic_sre_macaddr_change(adapter,
03c5d770 406 cur->mac_addr, 0, QLCNIC_MAC_ADD)) {
42f65cba
AKS		 407 kfree(cur);
408 return -EIO;
409 }
410
411 list_add_tail(&cur->list, &adapter->mac_list);
412 return 0;
af19b491
AKS		 413}
414
415void qlcnic_set_multi(struct net_device *netdev)
416{
417 struct qlcnic_adapter *adapter = netdev_priv(netdev);
22bedad3 418 struct netdev_hw_addr *ha;
215faf9c
JP		 419 static const u8 bcast_addr[ETH_ALEN] = {
420 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
421 };
af19b491 422 u32 mode = VPORT_MISS_MODE_DROP;
af19b491 423
8a15ad1f 424 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
a55cb185
AKS		 425 return;
426
9ab17b39
SC		 427 qlcnic_nic_add_mac(adapter, adapter->mac_addr);
428 qlcnic_nic_add_mac(adapter, bcast_addr);
af19b491
AKS		 429
430 if (netdev->flags & IFF_PROMISC) {
ee07c1a7
RB		 431 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
432 mode = VPORT_MISS_MODE_ACCEPT_ALL;
af19b491
AKS		 433 goto send_fw_cmd;
434 }
435
436 if ((netdev->flags & IFF_ALLMULTI) ||
4cd24eaf 437 (netdev_mc_count(netdev) > adapter->max_mc_count)) {
af19b491
AKS		 438 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
439 goto send_fw_cmd;
440 }
441
4cd24eaf 442 if (!netdev_mc_empty(netdev)) {
22bedad3
JP		 443 netdev_for_each_mc_addr(ha, netdev) {
444 qlcnic_nic_add_mac(adapter, ha->addr);
af19b491
AKS		 445 }
446 }
447
448send_fw_cmd:
449 qlcnic_nic_set_promisc(adapter, mode);
af19b491
AKS		 450}
451
452int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
453{
454 struct qlcnic_nic_req req;
455 u64 word;
456
457 memset(&req, 0, sizeof(struct qlcnic_nic_req));
458
459 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
460
b1fc6d3c 461 word = QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE |
af19b491
AKS		 462 ((u64)adapter->portnum << 16);
463 req.req_hdr = cpu_to_le64(word);
464
465 req.words[0] = cpu_to_le64(mode);
466
467 return qlcnic_send_cmd_descs(adapter,
468 (struct cmd_desc_type0 *)&req, 1);
469}
470
471void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
472{
473 struct qlcnic_mac_list_s *cur;
474 struct list_head *head = &adapter->mac_list;
475
476 while (!list_empty(head)) {
477 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
478 qlcnic_sre_macaddr_change(adapter,
03c5d770 479 cur->mac_addr, 0, QLCNIC_MAC_DEL);
af19b491
AKS		 480 list_del(&cur->list);
481 kfree(cur);
482 }
483}
484
b5e5492c
AKS		 485void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
486{
487 struct qlcnic_filter *tmp_fil;
488 struct hlist_node *tmp_hnode, *n;
489 struct hlist_head *head;
490 int i;
491
492 for (i = 0; i < adapter->fhash.fmax; i++) {
493 head = &(adapter->fhash.fhead[i]);
494
495 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode)
496 {
497 if (jiffies >
498 (QLCNIC_FILTER_AGE * HZ + tmp_fil->ftime)) {
499 qlcnic_sre_macaddr_change(adapter,
03c5d770
AKS		 500 tmp_fil->faddr, tmp_fil->vlan_id,
501 tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
502 QLCNIC_MAC_DEL);
b5e5492c
AKS		 503 spin_lock_bh(&adapter->mac_learn_lock);
504 adapter->fhash.fnum--;
505 hlist_del(&tmp_fil->fnode);
506 spin_unlock_bh(&adapter->mac_learn_lock);
507 kfree(tmp_fil);
508 }
509 }
510 }
511}
512
513void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
514{
515 struct qlcnic_filter *tmp_fil;
516 struct hlist_node *tmp_hnode, *n;
517 struct hlist_head *head;
518 int i;
519
520 for (i = 0; i < adapter->fhash.fmax; i++) {
521 head = &(adapter->fhash.fhead[i]);
522
523 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode) {
03c5d770
AKS		 524 qlcnic_sre_macaddr_change(adapter, tmp_fil->faddr,
525 tmp_fil->vlan_id, tmp_fil->vlan_id ?
526 QLCNIC_MAC_VLAN_DEL : QLCNIC_MAC_DEL);
b5e5492c
AKS		 527 spin_lock_bh(&adapter->mac_learn_lock);
528 adapter->fhash.fnum--;
529 hlist_del(&tmp_fil->fnode);
530 spin_unlock_bh(&adapter->mac_learn_lock);
531 kfree(tmp_fil);
532 }
533 }
534}
535
22c8c934
SC		 536int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag)
537{
538 struct qlcnic_nic_req req;
539 int rv;
540
541 memset(&req, 0, sizeof(struct qlcnic_nic_req));
542
543 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
544 req.req_hdr = cpu_to_le64(QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
545 ((u64) adapter->portnum << 16) | ((u64) 0x1 << 32));
546
547 req.words[0] = cpu_to_le64(flag);
548
549 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
550 if (rv != 0)
551 dev_err(&adapter->pdev->dev, "%sting loopback mode failed\n",
552 flag ? "Set" : "Reset");
553 return rv;
554}
555
556int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
557{
558 if (qlcnic_set_fw_loopback(adapter, mode))
559 return -EIO;
560
561 if (qlcnic_nic_set_promisc(adapter, VPORT_MISS_MODE_ACCEPT_ALL)) {
562 qlcnic_set_fw_loopback(adapter, mode);
563 return -EIO;
564 }
565
566 msleep(1000);
567 return 0;
568}
569
570void qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter)
571{
572 int mode = VPORT_MISS_MODE_DROP;
573 struct net_device *netdev = adapter->netdev;
574
575 qlcnic_set_fw_loopback(adapter, 0);
576
577 if (netdev->flags & IFF_PROMISC)
578 mode = VPORT_MISS_MODE_ACCEPT_ALL;
579 else if (netdev->flags & IFF_ALLMULTI)
580 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
581
582 qlcnic_nic_set_promisc(adapter, mode);
583 msleep(1000);
584}
585
af19b491
AKS		 586/*
587 * Send the interrupt coalescing parameter set by ethtool to the card.
588 */
589int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
590{
591 struct qlcnic_nic_req req;
8816d009 592 int rv;
af19b491
AKS		 593
594 memset(&req, 0, sizeof(struct qlcnic_nic_req));
595
596 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
597
8816d009
AC		 598 req.req_hdr = cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE |
599 ((u64) adapter->portnum << 16));
af19b491 600
8816d009
AC		 601 req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32);
602 req.words[2] = cpu_to_le64(adapter->ahw->coal.rx_packets |
603 ((u64) adapter->ahw->coal.rx_time_us) << 16);
604 req.words[5] = cpu_to_le64(adapter->ahw->coal.timer_out |
605 ((u64) adapter->ahw->coal.type) << 32 |
606 ((u64) adapter->ahw->coal.sts_ring_mask) << 40);
af19b491
AKS		 607 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
608 if (rv != 0)
609 dev_err(&adapter->netdev->dev,
610 "Could not send interrupt coalescing parameters\n");
af19b491
AKS		 611 return rv;
612}
613
614int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
615{
616 struct qlcnic_nic_req req;
617 u64 word;
618 int rv;
619
b56421d0
RB		 620 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
621 return 0;
622
af19b491
AKS		 623 memset(&req, 0, sizeof(struct qlcnic_nic_req));
624
625 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
626
627 word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
628 req.req_hdr = cpu_to_le64(word);
629
630 req.words[0] = cpu_to_le64(enable);
631
632 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
633 if (rv != 0)
634 dev_err(&adapter->netdev->dev,
635 "Could not send configure hw lro request\n");
636
af19b491
AKS		 637 return rv;
638}
639
2e9d722d 640int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
af19b491
AKS		 641{
642 struct qlcnic_nic_req req;
643 u64 word;
644 int rv;
645
646 if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
647 return 0;
648
649 memset(&req, 0, sizeof(struct qlcnic_nic_req));
650
651 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
652
653 word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
654 ((u64)adapter->portnum << 16);
655 req.req_hdr = cpu_to_le64(word);
656
657 req.words[0] = cpu_to_le64(enable);
658
659 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
660 if (rv != 0)
661 dev_err(&adapter->netdev->dev,
662 "Could not send configure bridge mode request\n");
663
664 adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
665
666 return rv;
667}
668
669
670#define RSS_HASHTYPE_IP_TCP 0x3
671
672int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
673{
674 struct qlcnic_nic_req req;
675 u64 word;
676 int i, rv;
677
215faf9c
JP		 678 static const u64 key[] = {
679 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
680 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
681 0x255b0ec26d5a56daULL
682 };
af19b491
AKS		 683
684 memset(&req, 0, sizeof(struct qlcnic_nic_req));
685 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
686
687 word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
688 req.req_hdr = cpu_to_le64(word);
689
690 /*
691 * RSS request:
692 * bits 3-0: hash_method
693 * 5-4: hash_type_ipv4
694 * 7-6: hash_type_ipv6
695 * 8: enable
696 * 9: use indirection table
697 * 47-10: reserved
698 * 63-48: indirection table mask
699 */
700 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
701 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
702 ((u64)(enable & 0x1) << 8) |
703 ((0x7ULL) << 48);
704 req.words[0] = cpu_to_le64(word);
705 for (i = 0; i < 5; i++)
706 req.words[i+1] = cpu_to_le64(key[i]);
707
708 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
709 if (rv != 0)
710 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
711
712 return rv;
713}
714
b501595c 715int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd)
af19b491
AKS		 716{
717 struct qlcnic_nic_req req;
b501595c 718 struct qlcnic_ipaddr *ipa;
af19b491
AKS		 719 u64 word;
720 int rv;
721
722 memset(&req, 0, sizeof(struct qlcnic_nic_req));
723 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
724
725 word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
726 req.req_hdr = cpu_to_le64(word);
727
728 req.words[0] = cpu_to_le64(cmd);
b501595c
SC		 729 ipa = (struct qlcnic_ipaddr *)&req.words[1];
730 ipa->ipv4 = ip;
af19b491
AKS		 731
732 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
733 if (rv != 0)
734 dev_err(&adapter->netdev->dev,
735 "could not notify %s IP 0x%x reuqest\n",
736 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
737
738 return rv;
739}
740
741int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
742{
743 struct qlcnic_nic_req req;
744 u64 word;
745 int rv;
746
747 memset(&req, 0, sizeof(struct qlcnic_nic_req));
748 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
749
750 word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
751 req.req_hdr = cpu_to_le64(word);
752 req.words[0] = cpu_to_le64(enable | (enable << 8));
753
754 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
755 if (rv != 0)
756 dev_err(&adapter->netdev->dev,
757 "could not configure link notification\n");
758
759 return rv;
760}
761
762int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
763{
764 struct qlcnic_nic_req req;
765 u64 word;
766 int rv;
767
b56421d0
RB		 768 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
769 return 0;
770
af19b491
AKS		 771 memset(&req, 0, sizeof(struct qlcnic_nic_req));
772 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
773
774 word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
775 ((u64)adapter->portnum << 16) |
776 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
777
778 req.req_hdr = cpu_to_le64(word);
779
780 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
781 if (rv != 0)
782 dev_err(&adapter->netdev->dev,
783 "could not cleanup lro flows\n");
784
785 return rv;
786}
787
788/*
789 * qlcnic_change_mtu - Change the Maximum Transfer Unit
790 * @returns 0 on success, negative on failure
791 */
792
793int qlcnic_change_mtu(struct net_device *netdev, int mtu)
794{
795 struct qlcnic_adapter *adapter = netdev_priv(netdev);
796 int rc = 0;
797
ff1b1bf8 798 if (mtu < P3P_MIN_MTU || mtu > P3P_MAX_MTU) {
0bd9e6a9 799 dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes"
ff1b1bf8 800 " not supported\n", P3P_MAX_MTU, P3P_MIN_MTU);
af19b491
AKS		 801 return -EINVAL;
802 }
803
804 rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
805
806 if (!rc)
807 netdev->mtu = mtu;
808
809 return rc;
810}
811
135d84a9
MM		 812
813u32 qlcnic_fix_features(struct net_device *netdev, u32 features)
814{
815 struct qlcnic_adapter *adapter = netdev_priv(netdev);
816
817 if ((adapter->flags & QLCNIC_ESWITCH_ENABLED)) {
818 u32 changed = features ^ netdev->features;
819 features ^= changed & (NETIF_F_ALL_CSUM | NETIF_F_RXCSUM);
820 }
821
822 if (!(features & NETIF_F_RXCSUM))
823 features &= ~NETIF_F_LRO;
824
825 return features;
826}
827
828
829int qlcnic_set_features(struct net_device *netdev, u32 features)
830{
831 struct qlcnic_adapter *adapter = netdev_priv(netdev);
832 u32 changed = netdev->features ^ features;
833 int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0;
834
835 if (!(changed & NETIF_F_LRO))
836 return 0;
837
838 netdev->features = features ^ NETIF_F_LRO;
839
840 if (qlcnic_config_hw_lro(adapter, hw_lro))
841 return -EIO;
842
843 if ((hw_lro == 0) && qlcnic_send_lro_cleanup(adapter))
844 return -EIO;
845
846 return 0;
847}
848
af19b491
AKS		 849/*
850 * Changes the CRB window to the specified window.
851 */
852 /* Returns < 0 if off is not valid,
853 * 1 if window access is needed. 'off' is set to offset from
854 * CRB space in 128M pci map
855 * 0 if no window access is needed. 'off' is set to 2M addr
856 * In: 'off' is offset from base in 128M pci map
857 */
858static int
859qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter *adapter,
860 ulong off, void __iomem **addr)
861{
862 const struct crb_128M_2M_sub_block_map *m;
863
864 if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
865 return -EINVAL;
866
867 off -= QLCNIC_PCI_CRBSPACE;
868
869 /*
870 * Try direct map
871 */
872 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
873
874 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
b1fc6d3c 875 *addr = adapter->ahw->pci_base0 + m->start_2M +
af19b491
AKS		 876 (off - m->start_128M);
877 return 0;
878 }
879
880 /*
881 * Not in direct map, use crb window
882 */
b1fc6d3c 883 *addr = adapter->ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
af19b491
AKS		 884 return 1;
885}
886
887/*
888 * In: 'off' is offset from CRB space in 128M pci map
889 * Out: 'off' is 2M pci map addr
890 * side effect: lock crb window
891 */
4de57826 892static int
af19b491
AKS		 893qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
894{
895 u32 window;
b1fc6d3c 896 void __iomem *addr = adapter->ahw->pci_base0 + CRB_WINDOW_2M;
af19b491
AKS		 897
898 off -= QLCNIC_PCI_CRBSPACE;
899
900 window = CRB_HI(off);
4de57826
AKS		 901 if (window == 0) {
902 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
903 return -EIO;
904 }
af19b491 905
af19b491
AKS		 906 writel(window, addr);
907 if (readl(addr) != window) {
908 if (printk_ratelimit())
909 dev_warn(&adapter->pdev->dev,
910 "failed to set CRB window to %d off 0x%lx\n",
911 window, off);
4de57826 912 return -EIO;
af19b491 913 }
4de57826 914 return 0;
af19b491
AKS		 915}
916
917int
918qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
919{
920 unsigned long flags;
921 int rv;
922 void __iomem *addr = NULL;
923
924 rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
925
926 if (rv == 0) {
927 writel(data, addr);
928 return 0;
929 }
930
931 if (rv > 0) {
932 /* indirect access */
b1fc6d3c 933 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
af19b491 934 crb_win_lock(adapter);
4de57826
AKS		 935 rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
936 if (!rv)
937 writel(data, addr);
af19b491 938 crb_win_unlock(adapter);
b1fc6d3c 939 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
4de57826 940 return rv;
af19b491
AKS		 941 }
942
943 dev_err(&adapter->pdev->dev,
944 "%s: invalid offset: 0x%016lx\n", __func__, off);
945 dump_stack();
946 return -EIO;
947}
948
949u32
950qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
951{
952 unsigned long flags;
953 int rv;
4de57826 954 u32 data = -1;
af19b491
AKS		 955 void __iomem *addr = NULL;
956
957 rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
958
959 if (rv == 0)
960 return readl(addr);
961
962 if (rv > 0) {
963 /* indirect access */
b1fc6d3c 964 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
af19b491 965 crb_win_lock(adapter);
4de57826
AKS		 966 if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
967 data = readl(addr);
af19b491 968 crb_win_unlock(adapter);
b1fc6d3c 969 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
af19b491
AKS		 970 return data;
971 }
972
973 dev_err(&adapter->pdev->dev,
974 "%s: invalid offset: 0x%016lx\n", __func__, off);
975 dump_stack();
976 return -1;
977}
978
979
980void __iomem *
981qlcnic_get_ioaddr(struct qlcnic_adapter *adapter, u32 offset)
982{
983 void __iomem *addr = NULL;
984
985 WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter, offset, &addr));
986
987 return addr;
988}
989
990
991static int
992qlcnic_pci_set_window_2M(struct qlcnic_adapter *adapter,
993 u64 addr, u32 *start)
994{
995 u32 window;
af19b491
AKS		 996
997 window = OCM_WIN_P3P(addr);
998
b1fc6d3c 999 writel(window, adapter->ahw->ocm_win_crb);
af19b491 1000 /* read back to flush */
b1fc6d3c 1001 readl(adapter->ahw->ocm_win_crb);
af19b491 1002
af19b491
AKS		 1003 *start = QLCNIC_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
1004 return 0;
1005}
1006
1007static int
1008qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, u64 off,
1009 u64 *data, int op)
1010{
0c39aa48 1011 void __iomem *addr;
af19b491
AKS		 1012 int ret;
1013 u32 start;
1014
b1fc6d3c 1015 mutex_lock(&adapter->ahw->mem_lock);
af19b491
AKS		 1016
1017 ret = qlcnic_pci_set_window_2M(adapter, off, &start);
1018 if (ret != 0)
1019 goto unlock;
1020
b1fc6d3c 1021 addr = adapter->ahw->pci_base0 + start;
af19b491 1022
af19b491
AKS		 1023 if (op == 0) /* read */
1024 *data = readq(addr);
1025 else /* write */
1026 writeq(*data, addr);
1027
1028unlock:
b1fc6d3c 1029 mutex_unlock(&adapter->ahw->mem_lock);
af19b491 1030
af19b491
AKS		 1031 return ret;
1032}
1033
897e8c7c
DP		 1034void
1035qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1036{
b1fc6d3c 1037 void __iomem *addr = adapter->ahw->pci_base0 +
897e8c7c
DP		 1038 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1039
b1fc6d3c 1040 mutex_lock(&adapter->ahw->mem_lock);
897e8c7c 1041 *data = readq(addr);
b1fc6d3c 1042 mutex_unlock(&adapter->ahw->mem_lock);
897e8c7c
DP		 1043}
1044
1045void
1046qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1047{
b1fc6d3c 1048 void __iomem *addr = adapter->ahw->pci_base0 +
897e8c7c
DP		 1049 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1050
b1fc6d3c 1051 mutex_lock(&adapter->ahw->mem_lock);
897e8c7c 1052 writeq(data, addr);
b1fc6d3c 1053 mutex_unlock(&adapter->ahw->mem_lock);
897e8c7c
DP		 1054}
1055
af19b491
AKS		 1056#define MAX_CTL_CHECK 1000
1057
1058int
1059qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
1060 u64 off, u64 data)
1061{
1062 int i, j, ret;
1063 u32 temp, off8;
af19b491
AKS		 1064 void __iomem *mem_crb;
1065
1066 /* Only 64-bit aligned access */
1067 if (off & 7)
1068 return -EIO;
1069
1070 /* P3 onward, test agent base for MIU and SIU is same */
1071 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
b47acacd 1072 QLCNIC_ADDR_QDR_NET_MAX)) {
af19b491
AKS		 1073 mem_crb = qlcnic_get_ioaddr(adapter,
1074 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1075 goto correct;
1076 }
1077
1078 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1079 mem_crb = qlcnic_get_ioaddr(adapter,
1080 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1081 goto correct;
1082 }
1083
1084 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1085 return qlcnic_pci_mem_access_direct(adapter, off, &data, 1);
1086
1087 return -EIO;
1088
1089correct:
b47acacd 1090 off8 = off & ~0xf;
af19b491 1091
b1fc6d3c 1092 mutex_lock(&adapter->ahw->mem_lock);
af19b491
AKS		 1093
1094 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1095 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1096
1097 i = 0;
b47acacd
DP		 1098 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1099 writel((TA_CTL_START | TA_CTL_ENABLE),
1100 (mem_crb + TEST_AGT_CTRL));
af19b491 1101
b47acacd
DP		 1102 for (j = 0; j < MAX_CTL_CHECK; j++) {
1103 temp = readl(mem_crb + TEST_AGT_CTRL);
1104 if ((temp & TA_CTL_BUSY) == 0)
1105 break;
1106 }
af19b491 1107
b47acacd
DP		 1108 if (j >= MAX_CTL_CHECK) {
1109 ret = -EIO;
1110 goto done;
af19b491
AKS		 1111 }
1112
b47acacd
DP		 1113 i = (off & 0xf) ? 0 : 2;
1114 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
1115 mem_crb + MIU_TEST_AGT_WRDATA(i));
1116 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
1117 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1118 i = (off & 0xf) ? 2 : 0;
1119
af19b491
AKS		 1120 writel(data & 0xffffffff,
1121 mem_crb + MIU_TEST_AGT_WRDATA(i));
1122 writel((data >> 32) & 0xffffffff,
1123 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1124
1125 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1126 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1127 (mem_crb + TEST_AGT_CTRL));
1128
1129 for (j = 0; j < MAX_CTL_CHECK; j++) {
1130 temp = readl(mem_crb + TEST_AGT_CTRL);
1131 if ((temp & TA_CTL_BUSY) == 0)
1132 break;
1133 }
1134
1135 if (j >= MAX_CTL_CHECK) {
1136 if (printk_ratelimit())
1137 dev_err(&adapter->pdev->dev,
1138 "failed to write through agent\n");
1139 ret = -EIO;
1140 } else
1141 ret = 0;
1142
1143done:
b1fc6d3c 1144 mutex_unlock(&adapter->ahw->mem_lock);
af19b491
AKS		 1145
1146 return ret;
1147}
1148
1149int
1150qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
1151 u64 off, u64 *data)
1152{
1153 int j, ret;
1154 u32 temp, off8;
b47acacd 1155 u64 val;
af19b491
AKS		 1156 void __iomem *mem_crb;
1157
1158 /* Only 64-bit aligned access */
1159 if (off & 7)
1160 return -EIO;
1161
1162 /* P3 onward, test agent base for MIU and SIU is same */
1163 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
b47acacd 1164 QLCNIC_ADDR_QDR_NET_MAX)) {
af19b491
AKS		 1165 mem_crb = qlcnic_get_ioaddr(adapter,
1166 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1167 goto correct;
1168 }
1169
1170 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1171 mem_crb = qlcnic_get_ioaddr(adapter,
1172 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1173 goto correct;
1174 }
1175
1176 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) {
1177 return qlcnic_pci_mem_access_direct(adapter,
1178 off, data, 0);
1179 }
1180
1181 return -EIO;
1182
1183correct:
b47acacd 1184 off8 = off & ~0xf;
af19b491 1185
b1fc6d3c 1186 mutex_lock(&adapter->ahw->mem_lock);
af19b491
AKS		 1187
1188 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1189 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1190 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1191 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1192
1193 for (j = 0; j < MAX_CTL_CHECK; j++) {
1194 temp = readl(mem_crb + TEST_AGT_CTRL);
1195 if ((temp & TA_CTL_BUSY) == 0)
1196 break;
1197 }
1198
1199 if (j >= MAX_CTL_CHECK) {
1200 if (printk_ratelimit())
1201 dev_err(&adapter->pdev->dev,
1202 "failed to read through agent\n");
1203 ret = -EIO;
1204 } else {
1205 off8 = MIU_TEST_AGT_RDDATA_LO;
b47acacd 1206 if (off & 0xf)
af19b491
AKS		 1207 off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1208
1209 temp = readl(mem_crb + off8 + 4);
1210 val = (u64)temp << 32;
1211 val |= readl(mem_crb + off8);
1212 *data = val;
1213 ret = 0;
1214 }
1215
b1fc6d3c 1216 mutex_unlock(&adapter->ahw->mem_lock);
af19b491
AKS		 1217
1218 return ret;
1219}
1220
1221int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1222{
1223 int offset, board_type, magic;
1224 struct pci_dev *pdev = adapter->pdev;
1225
1226 offset = QLCNIC_FW_MAGIC_OFFSET;
1227 if (qlcnic_rom_fast_read(adapter, offset, &magic))
1228 return -EIO;
1229
1230 if (magic != QLCNIC_BDINFO_MAGIC) {
1231 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1232 magic);
1233 return -EIO;
1234 }
1235
1236 offset = QLCNIC_BRDTYPE_OFFSET;
1237 if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1238 return -EIO;
1239
b1fc6d3c 1240 adapter->ahw->board_type = board_type;
af19b491 1241
ff1b1bf8 1242 if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) {
af19b491
AKS		 1243 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1244 if ((gpio & 0x8000) == 0)
ff1b1bf8 1245 board_type = QLCNIC_BRDTYPE_P3P_10G_TP;
af19b491
AKS		 1246 }
1247
1248 switch (board_type) {
ff1b1bf8
SV		 1249 case QLCNIC_BRDTYPE_P3P_HMEZ:
1250 case QLCNIC_BRDTYPE_P3P_XG_LOM:
1251 case QLCNIC_BRDTYPE_P3P_10G_CX4:
1252 case QLCNIC_BRDTYPE_P3P_10G_CX4_LP:
1253 case QLCNIC_BRDTYPE_P3P_IMEZ:
1254 case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS:
1255 case QLCNIC_BRDTYPE_P3P_10G_SFP_CT:
1256 case QLCNIC_BRDTYPE_P3P_10G_SFP_QT:
1257 case QLCNIC_BRDTYPE_P3P_10G_XFP:
1258 case QLCNIC_BRDTYPE_P3P_10000_BASE_T:
b1fc6d3c 1259 adapter->ahw->port_type = QLCNIC_XGBE;
af19b491 1260 break;
ff1b1bf8
SV		 1261 case QLCNIC_BRDTYPE_P3P_REF_QG:
1262 case QLCNIC_BRDTYPE_P3P_4_GB:
1263 case QLCNIC_BRDTYPE_P3P_4_GB_MM:
b1fc6d3c 1264 adapter->ahw->port_type = QLCNIC_GBE;
af19b491 1265 break;
ff1b1bf8 1266 case QLCNIC_BRDTYPE_P3P_10G_TP:
b1fc6d3c 1267 adapter->ahw->port_type = (adapter->portnum < 2) ?
af19b491
AKS		 1268 QLCNIC_XGBE : QLCNIC_GBE;
1269 break;
1270 default:
1271 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
b1fc6d3c 1272 adapter->ahw->port_type = QLCNIC_XGBE;
af19b491
AKS		 1273 break;
1274 }
1275
1276 return 0;
1277}
1278
1279int
1280qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1281{
1282 u32 wol_cfg;
1283
1284 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1285 if (wol_cfg & (1UL << adapter->portnum)) {
1286 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1287 if (wol_cfg & (1 << adapter->portnum))
1288 return 1;
1289 }
1290
1291 return 0;
1292}
897d3596
SC		 1293
1294int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1295{
1296 struct qlcnic_nic_req req;
1297 int rv;
1298 u64 word;
1299
1300 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1301 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1302
1303 word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1304 req.req_hdr = cpu_to_le64(word);
1305
1306 req.words[0] = cpu_to_le64((u64)rate << 32);
1307 req.words[1] = cpu_to_le64(state);
1308
1309 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1310 if (rv)
1311 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1312
1313 return rv;
1314}
18f2f616
AC		 1315
1316/* FW dump related functions */
1317static u32
1318qlcnic_dump_crb(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
1319 u32 *buffer)
1320{
1321 int i;
1322 u32 addr, data;
1323 struct __crb *crb = &entry->region.crb;
1324 void __iomem *base = adapter->ahw->pci_base0;
1325
1326 addr = crb->addr;
1327
1328 for (i = 0; i < crb->no_ops; i++) {
1329 QLCNIC_RD_DUMP_REG(addr, base, &data);
1330 *buffer++ = cpu_to_le32(addr);
1331 *buffer++ = cpu_to_le32(data);
1332 addr += crb->stride;
1333 }
1334 return crb->no_ops * 2 * sizeof(u32);
1335}
1336
1337static u32
1338qlcnic_dump_ctrl(struct qlcnic_adapter *adapter,
1339 struct qlcnic_dump_entry *entry, u32 *buffer)
1340{
1341 int i, k, timeout = 0;
1342 void __iomem *base = adapter->ahw->pci_base0;
1343 u32 addr, data;
1344 u8 opcode, no_ops;
1345 struct __ctrl *ctr = &entry->region.ctrl;
1346 struct qlcnic_dump_template_hdr *t_hdr = adapter->ahw->fw_dump.tmpl_hdr;
1347
1348 addr = ctr->addr;
1349 no_ops = ctr->no_ops;
1350
1351 for (i = 0; i < no_ops; i++) {
1352 k = 0;
1353 opcode = 0;
1354 for (k = 0; k < 8; k++) {
1355 if (!(ctr->opcode & (1 << k)))
1356 continue;
1357 switch (1 << k) {
1358 case QLCNIC_DUMP_WCRB:
1359 QLCNIC_WR_DUMP_REG(addr, base, ctr->val1);
1360 break;
1361 case QLCNIC_DUMP_RWCRB:
1362 QLCNIC_RD_DUMP_REG(addr, base, &data);
1363 QLCNIC_WR_DUMP_REG(addr, base, data);
1364 break;
1365 case QLCNIC_DUMP_ANDCRB:
1366 QLCNIC_RD_DUMP_REG(addr, base, &data);
1367 QLCNIC_WR_DUMP_REG(addr, base,
1368 (data & ctr->val2));
1369 break;
1370 case QLCNIC_DUMP_ORCRB:
1371 QLCNIC_RD_DUMP_REG(addr, base, &data);
1372 QLCNIC_WR_DUMP_REG(addr, base,
1373 (data | ctr->val3));
1374 break;
1375 case QLCNIC_DUMP_POLLCRB:
1376 while (timeout <= ctr->timeout) {
1377 QLCNIC_RD_DUMP_REG(addr, base, &data);
1378 if ((data & ctr->val2) == ctr->val1)
1379 break;
1380 msleep(1);
1381 timeout++;
1382 }
1383 if (timeout > ctr->timeout) {
1384 dev_info(&adapter->pdev->dev,
1385 "Timed out, aborting poll CRB\n");
1386 return -EINVAL;
1387 }
1388 break;
1389 case QLCNIC_DUMP_RD_SAVE:
1390 if (ctr->index_a)
1391 addr = t_hdr->saved_state[ctr->index_a];
1392 QLCNIC_RD_DUMP_REG(addr, base, &data);
1393 t_hdr->saved_state[ctr->index_v] = data;
1394 break;
1395 case QLCNIC_DUMP_WRT_SAVED:
1396 if (ctr->index_v)
1397 data = t_hdr->saved_state[ctr->index_v];
1398 else
1399 data = ctr->val1;
1400 if (ctr->index_a)
1401 addr = t_hdr->saved_state[ctr->index_a];
1402 QLCNIC_WR_DUMP_REG(addr, base, data);
1403 break;
1404 case QLCNIC_DUMP_MOD_SAVE_ST:
1405 data = t_hdr->saved_state[ctr->index_v];
1406 data <<= ctr->shl_val;
1407 data >>= ctr->shr_val;
1408 if (ctr->val2)
1409 data &= ctr->val2;
1410 data |= ctr->val3;
1411 data += ctr->val1;
1412 t_hdr->saved_state[ctr->index_v] = data;
1413 break;
1414 default:
1415 dev_info(&adapter->pdev->dev,
1416 "Unknown opcode\n");
1417 break;
1418 }
1419 }
1420 addr += ctr->stride;
1421 }
1422 return 0;
1423}
1424
1425static u32
1426qlcnic_dump_mux(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
1427 u32 *buffer)
1428{
1429 int loop;
1430 u32 val, data = 0;
1431 struct __mux *mux = &entry->region.mux;
1432 void __iomem *base = adapter->ahw->pci_base0;
1433
1434 val = mux->val;
1435 for (loop = 0; loop < mux->no_ops; loop++) {
1436 QLCNIC_WR_DUMP_REG(mux->addr, base, val);
1437 QLCNIC_RD_DUMP_REG(mux->read_addr, base, &data);
1438 *buffer++ = cpu_to_le32(val);
1439 *buffer++ = cpu_to_le32(data);
1440 val += mux->val_stride;
1441 }
1442 return 2 * mux->no_ops * sizeof(u32);
1443}
1444
1445static u32
1446qlcnic_dump_que(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
1447 u32 *buffer)
1448{
1449 int i, loop;
1450 u32 cnt, addr, data, que_id = 0;
1451 void __iomem *base = adapter->ahw->pci_base0;
1452 struct __queue *que = &entry->region.que;
1453
1454 addr = que->read_addr;
1455 cnt = que->read_addr_cnt;
1456
1457 for (loop = 0; loop < que->no_ops; loop++) {
1458 QLCNIC_WR_DUMP_REG(que->sel_addr, base, que_id);
54ff502c 1459 addr = que->read_addr;
18f2f616
AC		 1460 for (i = 0; i < cnt; i++) {
1461 QLCNIC_RD_DUMP_REG(addr, base, &data);
1462 *buffer++ = cpu_to_le32(data);
1463 addr += que->read_addr_stride;
1464 }
1465 que_id += que->stride;
1466 }
1467 return que->no_ops * cnt * sizeof(u32);
1468}
1469
1470static u32
1471qlcnic_dump_ocm(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
1472 u32 *buffer)
1473{
1474 int i;
1475 u32 data;
1476 void __iomem *addr;
1477 struct __ocm *ocm = &entry->region.ocm;
1478
1479 addr = adapter->ahw->pci_base0 + ocm->read_addr;
1480 for (i = 0; i < ocm->no_ops; i++) {
1481 data = readl(addr);
1482 *buffer++ = cpu_to_le32(data);
1483 addr += ocm->read_addr_stride;
1484 }
1485 return ocm->no_ops * sizeof(u32);
1486}
1487
1488static u32
1489qlcnic_read_rom(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
1490 u32 *buffer)
1491{
1492 int i, count = 0;
1493 u32 fl_addr, size, val, lck_val, addr;
1494 struct __mem *rom = &entry->region.mem;
1495 void __iomem *base = adapter->ahw->pci_base0;
1496
1497 fl_addr = rom->addr;
1498 size = rom->size/4;
1499lock_try:
1500 lck_val = readl(base + QLCNIC_FLASH_SEM2_LK);
1501 if (!lck_val && count < MAX_CTL_CHECK) {
1502 msleep(10);
1503 count++;
1504 goto lock_try;
1505 }
1506 writel(adapter->ahw->pci_func, (base + QLCNIC_FLASH_LOCK_ID));
1507 for (i = 0; i < size; i++) {
1508 addr = fl_addr & 0xFFFF0000;
1509 QLCNIC_WR_DUMP_REG(FLASH_ROM_WINDOW, base, addr);
1510 addr = LSW(fl_addr) + FLASH_ROM_DATA;
1511 QLCNIC_RD_DUMP_REG(addr, base, &val);
1512 fl_addr += 4;
1513 *buffer++ = cpu_to_le32(val);
1514 }
1515 readl(base + QLCNIC_FLASH_SEM2_ULK);
1516 return rom->size;
1517}
1518
1519static u32
1520qlcnic_dump_l1_cache(struct qlcnic_adapter *adapter,
1521 struct qlcnic_dump_entry *entry, u32 *buffer)
1522{
1523 int i;
1524 u32 cnt, val, data, addr;
1525 void __iomem *base = adapter->ahw->pci_base0;
1526 struct __cache *l1 = &entry->region.cache;
1527
1528 val = l1->init_tag_val;
1529
1530 for (i = 0; i < l1->no_ops; i++) {
1531 QLCNIC_WR_DUMP_REG(l1->addr, base, val);
1532 QLCNIC_WR_DUMP_REG(l1->ctrl_addr, base, LSW(l1->ctrl_val));
1533 addr = l1->read_addr;
1534 cnt = l1->read_addr_num;
1535 while (cnt) {
1536 QLCNIC_RD_DUMP_REG(addr, base, &data);
1537 *buffer++ = cpu_to_le32(data);
1538 addr += l1->read_addr_stride;
1539 cnt--;
1540 }
1541 val += l1->stride;
1542 }
1543 return l1->no_ops * l1->read_addr_num * sizeof(u32);
1544}
1545
1546static u32
1547qlcnic_dump_l2_cache(struct qlcnic_adapter *adapter,
1548 struct qlcnic_dump_entry *entry, u32 *buffer)
1549{
1550 int i;
1551 u32 cnt, val, data, addr;
1552 u8 poll_mask, poll_to, time_out = 0;
1553 void __iomem *base = adapter->ahw->pci_base0;
1554 struct __cache *l2 = &entry->region.cache;
1555
1556 val = l2->init_tag_val;
1557 poll_mask = LSB(MSW(l2->ctrl_val));
1558 poll_to = MSB(MSW(l2->ctrl_val));
1559
1560 for (i = 0; i < l2->no_ops; i++) {
1561 QLCNIC_WR_DUMP_REG(l2->addr, base, val);
c40f4ef7 1562 if (LSW(l2->ctrl_val))
18f2f616
AC		 1563 QLCNIC_WR_DUMP_REG(l2->ctrl_addr, base,
1564 LSW(l2->ctrl_val));
c40f4ef7
AC		 1565 if (!poll_mask)
1566 goto skip_poll;
1567 do {
18f2f616
AC		 1568 QLCNIC_RD_DUMP_REG(l2->ctrl_addr, base, &data);
1569 if (!(data & poll_mask))
1570 break;
1571 msleep(1);
1572 time_out++;
1573 } while (time_out <= poll_to);
18f2f616 1574
c40f4ef7
AC		 1575 if (time_out > poll_to) {
1576 dev_err(&adapter->pdev->dev,
1577 "Timeout exceeded in %s, aborting dump\n",
1578 __func__);
1579 return -EINVAL;
1580 }
1581skip_poll:
18f2f616
AC		 1582 addr = l2->read_addr;
1583 cnt = l2->read_addr_num;
1584 while (cnt) {
1585 QLCNIC_RD_DUMP_REG(addr, base, &data);
1586 *buffer++ = cpu_to_le32(data);
1587 addr += l2->read_addr_stride;
1588 cnt--;
1589 }
1590 val += l2->stride;
1591 }
1592 return l2->no_ops * l2->read_addr_num * sizeof(u32);
1593}
1594
1595static u32
1596qlcnic_read_memory(struct qlcnic_adapter *adapter,
1597 struct qlcnic_dump_entry *entry, u32 *buffer)
1598{
1599 u32 addr, data, test, ret = 0;
1600 int i, reg_read;
1601 struct __mem *mem = &entry->region.mem;
1602 void __iomem *base = adapter->ahw->pci_base0;
1603
1604 reg_read = mem->size;
1605 addr = mem->addr;
1606 /* check for data size of multiple of 16 and 16 byte alignment */
1607 if ((addr & 0xf) || (reg_read%16)) {
1608 dev_info(&adapter->pdev->dev,
1609 "Unaligned memory addr:0x%x size:0x%x\n",
1610 addr, reg_read);
1611 return -EINVAL;
1612 }
1613
1614 mutex_lock(&adapter->ahw->mem_lock);
1615
1616 while (reg_read != 0) {
1617 QLCNIC_WR_DUMP_REG(MIU_TEST_ADDR_LO, base, addr);
1618 QLCNIC_WR_DUMP_REG(MIU_TEST_ADDR_HI, base, 0);
1619 QLCNIC_WR_DUMP_REG(MIU_TEST_CTR, base,
1620 TA_CTL_ENABLE | TA_CTL_START);
1621
1622 for (i = 0; i < MAX_CTL_CHECK; i++) {
1623 QLCNIC_RD_DUMP_REG(MIU_TEST_CTR, base, &test);
1624 if (!(test & TA_CTL_BUSY))
1625 break;
1626 }
1627 if (i == MAX_CTL_CHECK) {
1628 if (printk_ratelimit()) {
1629 dev_err(&adapter->pdev->dev,
1630 "failed to read through agent\n");
1631 ret = -EINVAL;
1632 goto out;
1633 }
1634 }
1635 for (i = 0; i < 4; i++) {
1636 QLCNIC_RD_DUMP_REG(MIU_TEST_READ_DATA[i], base, &data);
1637 *buffer++ = cpu_to_le32(data);
1638 }
1639 addr += 16;
1640 reg_read -= 16;
1641 ret += 16;
1642 }
1643out:
1644 mutex_unlock(&adapter->ahw->mem_lock);
1645 return mem->size;
1646}
1647
1648static u32
1649qlcnic_dump_nop(struct qlcnic_adapter *adapter,
1650 struct qlcnic_dump_entry *entry, u32 *buffer)
1651{
1652 entry->hdr.flags |= QLCNIC_DUMP_SKIP;
1653 return 0;
1654}
1655
1656struct qlcnic_dump_operations fw_dump_ops[] = {
1657 { QLCNIC_DUMP_NOP, qlcnic_dump_nop },
1658 { QLCNIC_DUMP_READ_CRB, qlcnic_dump_crb },
1659 { QLCNIC_DUMP_READ_MUX, qlcnic_dump_mux },
1660 { QLCNIC_DUMP_QUEUE, qlcnic_dump_que },
1661 { QLCNIC_DUMP_BRD_CONFIG, qlcnic_read_rom },
1662 { QLCNIC_DUMP_READ_OCM, qlcnic_dump_ocm },
1663 { QLCNIC_DUMP_PEG_REG, qlcnic_dump_ctrl },
1664 { QLCNIC_DUMP_L1_DTAG, qlcnic_dump_l1_cache },
1665 { QLCNIC_DUMP_L1_ITAG, qlcnic_dump_l1_cache },
1666 { QLCNIC_DUMP_L1_DATA, qlcnic_dump_l1_cache },
1667 { QLCNIC_DUMP_L1_INST, qlcnic_dump_l1_cache },
1668 { QLCNIC_DUMP_L2_DTAG, qlcnic_dump_l2_cache },
1669 { QLCNIC_DUMP_L2_ITAG, qlcnic_dump_l2_cache },
1670 { QLCNIC_DUMP_L2_DATA, qlcnic_dump_l2_cache },
1671 { QLCNIC_DUMP_L2_INST, qlcnic_dump_l2_cache },
1672 { QLCNIC_DUMP_READ_ROM, qlcnic_read_rom },
1673 { QLCNIC_DUMP_READ_MEM, qlcnic_read_memory },
1674 { QLCNIC_DUMP_READ_CTRL, qlcnic_dump_ctrl },
1675 { QLCNIC_DUMP_TLHDR, qlcnic_dump_nop },
1676 { QLCNIC_DUMP_RDEND, qlcnic_dump_nop },
1677};
1678
1679/* Walk the template and collect dump for each entry in the dump template */
1680static int
1681qlcnic_valid_dump_entry(struct device *dev, struct qlcnic_dump_entry *entry,
1682 u32 size)
1683{
1684 int ret = 1;
1685 if (size != entry->hdr.cap_size) {
1686 dev_info(dev,
1687 "Invalidate dump, Type:%d\tMask:%d\tSize:%dCap_size:%d\n",
1688 entry->hdr.type, entry->hdr.mask, size, entry->hdr.cap_size);
1689 dev_info(dev, "Aborting further dump capture\n");
1690 ret = 0;
1691 }
1692 return ret;
1693}
1694
1695int qlcnic_dump_fw(struct qlcnic_adapter *adapter)
1696{
1697 u32 *buffer;
1698 char mesg[64];
1699 char *msg[] = {mesg, NULL};
1700 int i, k, ops_cnt, ops_index, dump_size = 0;
1701 u32 entry_offset, dump, no_entries, buf_offset = 0;
1702 struct qlcnic_dump_entry *entry;
1703 struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump;
1704 struct qlcnic_dump_template_hdr *tmpl_hdr = fw_dump->tmpl_hdr;
1705
1706 if (fw_dump->clr) {
1707 dev_info(&adapter->pdev->dev,
1708 "Previous dump not cleared, not capturing dump\n");
1709 return -EIO;
1710 }
1711 /* Calculate the size for dump data area only */
1712 for (i = 2, k = 1; (i & QLCNIC_DUMP_MASK_MAX); i <<= 1, k++)
1713 if (i & tmpl_hdr->drv_cap_mask)
1714 dump_size += tmpl_hdr->cap_sizes[k];
1715 if (!dump_size)
1716 return -EIO;
1717
1718 fw_dump->data = vzalloc(dump_size);
1719 if (!fw_dump->data) {
1720 dev_info(&adapter->pdev->dev,
1721 "Unable to allocate (%d KB) for fw dump\n",
1722 dump_size/1024);
1723 return -ENOMEM;
1724 }
1725 buffer = fw_dump->data;
1726 fw_dump->size = dump_size;
1727 no_entries = tmpl_hdr->num_entries;
1728 ops_cnt = ARRAY_SIZE(fw_dump_ops);
1729 entry_offset = tmpl_hdr->offset;
1730 tmpl_hdr->sys_info[0] = QLCNIC_DRIVER_VERSION;
1731 tmpl_hdr->sys_info[1] = adapter->fw_version;
1732
1733 for (i = 0; i < no_entries; i++) {
43d620c8 1734 entry = (void *)tmpl_hdr + entry_offset;
18f2f616
AC		 1735 if (!(entry->hdr.mask & tmpl_hdr->drv_cap_mask)) {
1736 entry->hdr.flags |= QLCNIC_DUMP_SKIP;
1737 entry_offset += entry->hdr.offset;
1738 continue;
1739 }
1740 /* Find the handler for this entry */
1741 ops_index = 0;
1742 while (ops_index < ops_cnt) {
1743 if (entry->hdr.type == fw_dump_ops[ops_index].opcode)
1744 break;
1745 ops_index++;
1746 }
1747 if (ops_index == ops_cnt) {
1748 dev_info(&adapter->pdev->dev,
1749 "Invalid entry type %d, exiting dump\n",
1750 entry->hdr.type);
1751 goto error;
1752 }
1753 /* Collect dump for this entry */
1754 dump = fw_dump_ops[ops_index].handler(adapter, entry, buffer);
1755 if (dump && !qlcnic_valid_dump_entry(&adapter->pdev->dev, entry,
1756 dump))
1757 entry->hdr.flags |= QLCNIC_DUMP_SKIP;
1758 buf_offset += entry->hdr.cap_size;
1759 entry_offset += entry->hdr.offset;
1760 buffer = fw_dump->data + buf_offset;
1761 }
1762 if (dump_size != buf_offset) {
1763 dev_info(&adapter->pdev->dev,
1764 "Captured(%d) and expected size(%d) do not match\n",
1765 buf_offset, dump_size);
1766 goto error;
1767 } else {
1768 fw_dump->clr = 1;
1769 snprintf(mesg, sizeof(mesg), "FW dump for device: %d\n",
1770 adapter->pdev->devfn);
1771 dev_info(&adapter->pdev->dev, "Dump data, %d bytes captured\n",
1772 fw_dump->size);
1773 /* Send a udev event to notify availability of FW dump */
1774 kobject_uevent_env(&adapter->pdev->dev.kobj, KOBJ_CHANGE, msg);
1775 return 0;
1776 }
1777error:
1778 vfree(fw_dump->data);
1779 return -EINVAL;
1780}
Linux kernel - Deliverables
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