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qlge: Move firmware event handler.
[deliverable/linux.git] / drivers / net / qlge / qlge.h
CommitLineData
c4e84bde
RM		 1/*
2 * QLogic QLA41xx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qlge for copyright and licensing details.
6 */
7#ifndef _QLGE_H_
8#define _QLGE_H_
9
10#include <linux/pci.h>
11#include <linux/netdevice.h>
12
13/*
14 * General definitions...
15 */
16#define DRV_NAME "qlge"
17#define DRV_STRING "QLogic 10 Gigabit PCI-E Ethernet Driver "
18#define DRV_VERSION "v1.00.00-b3"
19
20#define PFX "qlge: "
21#define QPRINTK(qdev, nlevel, klevel, fmt, args...) \
22 do { \
23 if (!((qdev)->msg_enable & NETIF_MSG_##nlevel)) \
24 ; \
25 else \
26 dev_printk(KERN_##klevel, &((qdev)->pdev->dev), \
27 "%s: " fmt, __func__, ##args); \
28 } while (0)
29
30#define QLGE_VENDOR_ID 0x1077
697cdc46 31#define QLGE_DEVICE_ID 0x8012
c4e84bde 32
683d46a9
RM		 33#define MAX_CPUS 8
34#define MAX_TX_RINGS MAX_CPUS
35#define MAX_RX_RINGS ((MAX_CPUS * 2) + 1)
c4e84bde
RM		 36
37#define NUM_TX_RING_ENTRIES 256
38#define NUM_RX_RING_ENTRIES 256
39
40#define NUM_SMALL_BUFFERS 512
41#define NUM_LARGE_BUFFERS 512
42
43#define SMALL_BUFFER_SIZE 256
44#define LARGE_BUFFER_SIZE PAGE_SIZE
45#define MAX_SPLIT_SIZE 1023
46#define QLGE_SB_PAD 32
47
683d46a9 48#define MAX_CQ 128
c4e84bde
RM		 49#define DFLT_COALESCE_WAIT 100 /* 100 usec wait for coalescing */
50#define MAX_INTER_FRAME_WAIT 10 /* 10 usec max interframe-wait for coalescing */
51#define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2)
52#define UDELAY_COUNT 3
53#define UDELAY_DELAY 10
54
55
56#define TX_DESC_PER_IOCB 8
57/* The maximum number of frags we handle is based
58 * on PAGE_SIZE...
59 */
60#if (PAGE_SHIFT == 12) || (PAGE_SHIFT == 13) /* 4k & 8k pages */
61#define TX_DESC_PER_OAL ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2)
48501371 62#else /* all other page sizes */
c4e84bde
RM		 63#define TX_DESC_PER_OAL 0
64#endif
65
66#define DB_PAGE_SIZE 4096
67
68/*
69 * Processor Address Register (PROC_ADDR) bit definitions.
70 */
71enum {
72
73 /* Misc. stuff */
74 MAILBOX_COUNT = 16,
75
76 PROC_ADDR_RDY = (1 << 31),
77 PROC_ADDR_R = (1 << 30),
78 PROC_ADDR_ERR = (1 << 29),
79 PROC_ADDR_DA = (1 << 28),
80 PROC_ADDR_FUNC0_MBI = 0x00001180,
81 PROC_ADDR_FUNC0_MBO = (PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT),
82 PROC_ADDR_FUNC0_CTL = 0x000011a1,
83 PROC_ADDR_FUNC2_MBI = 0x00001280,
84 PROC_ADDR_FUNC2_MBO = (PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT),
85 PROC_ADDR_FUNC2_CTL = 0x000012a1,
86 PROC_ADDR_MPI_RISC = 0x00000000,
87 PROC_ADDR_MDE = 0x00010000,
88 PROC_ADDR_REGBLOCK = 0x00020000,
89 PROC_ADDR_RISC_REG = 0x00030000,
90};
91
92/*
93 * System Register (SYS) bit definitions.
94 */
95enum {
96 SYS_EFE = (1 << 0),
97 SYS_FAE = (1 << 1),
98 SYS_MDC = (1 << 2),
99 SYS_DST = (1 << 3),
100 SYS_DWC = (1 << 4),
101 SYS_EVW = (1 << 5),
102 SYS_OMP_DLY_MASK = 0x3f000000,
103 /*
104 * There are no values defined as of edit #15.
105 */
106 SYS_ODI = (1 << 14),
107};
108
109/*
110 * Reset/Failover Register (RST_FO) bit definitions.
111 */
112enum {
113 RST_FO_TFO = (1 << 0),
114 RST_FO_RR_MASK = 0x00060000,
115 RST_FO_RR_CQ_CAM = 0x00000000,
116 RST_FO_RR_DROP = 0x00000001,
117 RST_FO_RR_DQ = 0x00000002,
118 RST_FO_RR_RCV_FUNC_CQ = 0x00000003,
119 RST_FO_FRB = (1 << 12),
120 RST_FO_MOP = (1 << 13),
121 RST_FO_REG = (1 << 14),
122 RST_FO_FR = (1 << 15),
123};
124
125/*
126 * Function Specific Control Register (FSC) bit definitions.
127 */
128enum {
129 FSC_DBRST_MASK = 0x00070000,
130 FSC_DBRST_256 = 0x00000000,
131 FSC_DBRST_512 = 0x00000001,
132 FSC_DBRST_768 = 0x00000002,
133 FSC_DBRST_1024 = 0x00000003,
134 FSC_DBL_MASK = 0x00180000,
135 FSC_DBL_DBRST = 0x00000000,
136 FSC_DBL_MAX_PLD = 0x00000008,
137 FSC_DBL_MAX_BRST = 0x00000010,
138 FSC_DBL_128_BYTES = 0x00000018,
139 FSC_EC = (1 << 5),
140 FSC_EPC_MASK = 0x00c00000,
141 FSC_EPC_INBOUND = (1 << 6),
142 FSC_EPC_OUTBOUND = (1 << 7),
143 FSC_VM_PAGESIZE_MASK = 0x07000000,
144 FSC_VM_PAGE_2K = 0x00000100,
145 FSC_VM_PAGE_4K = 0x00000200,
146 FSC_VM_PAGE_8K = 0x00000300,
147 FSC_VM_PAGE_64K = 0x00000600,
148 FSC_SH = (1 << 11),
149 FSC_DSB = (1 << 12),
150 FSC_STE = (1 << 13),
151 FSC_FE = (1 << 15),
152};
153
154/*
155 * Host Command Status Register (CSR) bit definitions.
156 */
157enum {
158 CSR_ERR_STS_MASK = 0x0000003f,
159 /*
160 * There are no valued defined as of edit #15.
161 */
162 CSR_RR = (1 << 8),
163 CSR_HRI = (1 << 9),
164 CSR_RP = (1 << 10),
165 CSR_CMD_PARM_SHIFT = 22,
166 CSR_CMD_NOP = 0x00000000,
b82808b7 167 CSR_CMD_SET_RST = 0x10000000,
c4e84bde
RM		 168 CSR_CMD_CLR_RST = 0x20000000,
169 CSR_CMD_SET_PAUSE = 0x30000000,
170 CSR_CMD_CLR_PAUSE = 0x40000000,
171 CSR_CMD_SET_H2R_INT = 0x50000000,
172 CSR_CMD_CLR_H2R_INT = 0x60000000,
173 CSR_CMD_PAR_EN = 0x70000000,
174 CSR_CMD_SET_BAD_PAR = 0x80000000,
175 CSR_CMD_CLR_BAD_PAR = 0x90000000,
176 CSR_CMD_CLR_R2PCI_INT = 0xa0000000,
177};
178
179/*
180 * Configuration Register (CFG) bit definitions.
181 */
182enum {
183 CFG_LRQ = (1 << 0),
184 CFG_DRQ = (1 << 1),
185 CFG_LR = (1 << 2),
186 CFG_DR = (1 << 3),
187 CFG_LE = (1 << 5),
188 CFG_LCQ = (1 << 6),
189 CFG_DCQ = (1 << 7),
190 CFG_Q_SHIFT = 8,
191 CFG_Q_MASK = 0x7f000000,
192};
193
194/*
195 * Status Register (STS) bit definitions.
196 */
197enum {
198 STS_FE = (1 << 0),
199 STS_PI = (1 << 1),
200 STS_PL0 = (1 << 2),
201 STS_PL1 = (1 << 3),
202 STS_PI0 = (1 << 4),
203 STS_PI1 = (1 << 5),
204 STS_FUNC_ID_MASK = 0x000000c0,
205 STS_FUNC_ID_SHIFT = 6,
206 STS_F0E = (1 << 8),
207 STS_F1E = (1 << 9),
208 STS_F2E = (1 << 10),
209 STS_F3E = (1 << 11),
210 STS_NFE = (1 << 12),
211};
212
213/*
214 * Interrupt Enable Register (INTR_EN) bit definitions.
215 */
216enum {
217 INTR_EN_INTR_MASK = 0x007f0000,
218 INTR_EN_TYPE_MASK = 0x03000000,
219 INTR_EN_TYPE_ENABLE = 0x00000100,
220 INTR_EN_TYPE_DISABLE = 0x00000200,
221 INTR_EN_TYPE_READ = 0x00000300,
222 INTR_EN_IHD = (1 << 13),
223 INTR_EN_IHD_MASK = (INTR_EN_IHD << 16),
224 INTR_EN_EI = (1 << 14),
225 INTR_EN_EN = (1 << 15),
226};
227
228/*
229 * Interrupt Mask Register (INTR_MASK) bit definitions.
230 */
231enum {
232 INTR_MASK_PI = (1 << 0),
233 INTR_MASK_HL0 = (1 << 1),
234 INTR_MASK_LH0 = (1 << 2),
235 INTR_MASK_HL1 = (1 << 3),
236 INTR_MASK_LH1 = (1 << 4),
237 INTR_MASK_SE = (1 << 5),
238 INTR_MASK_LSC = (1 << 6),
239 INTR_MASK_MC = (1 << 7),
240 INTR_MASK_LINK_IRQS = INTR_MASK_LSC | INTR_MASK_SE | INTR_MASK_MC,
241};
242
243/*
244 * Register (REV_ID) bit definitions.
245 */
246enum {
247 REV_ID_MASK = 0x0000000f,
248 REV_ID_NICROLL_SHIFT = 0,
249 REV_ID_NICREV_SHIFT = 4,
250 REV_ID_XGROLL_SHIFT = 8,
251 REV_ID_XGREV_SHIFT = 12,
252 REV_ID_CHIPREV_SHIFT = 28,
253};
254
255/*
256 * Force ECC Error Register (FRC_ECC_ERR) bit definitions.
257 */
258enum {
259 FRC_ECC_ERR_VW = (1 << 12),
260 FRC_ECC_ERR_VB = (1 << 13),
261 FRC_ECC_ERR_NI = (1 << 14),
262 FRC_ECC_ERR_NO = (1 << 15),
263 FRC_ECC_PFE_SHIFT = 16,
264 FRC_ECC_ERR_DO = (1 << 18),
265 FRC_ECC_P14 = (1 << 19),
266};
267
268/*
269 * Error Status Register (ERR_STS) bit definitions.
270 */
271enum {
272 ERR_STS_NOF = (1 << 0),
273 ERR_STS_NIF = (1 << 1),
274 ERR_STS_DRP = (1 << 2),
275 ERR_STS_XGP = (1 << 3),
276 ERR_STS_FOU = (1 << 4),
277 ERR_STS_FOC = (1 << 5),
278 ERR_STS_FOF = (1 << 6),
279 ERR_STS_FIU = (1 << 7),
280 ERR_STS_FIC = (1 << 8),
281 ERR_STS_FIF = (1 << 9),
282 ERR_STS_MOF = (1 << 10),
283 ERR_STS_TA = (1 << 11),
284 ERR_STS_MA = (1 << 12),
285 ERR_STS_MPE = (1 << 13),
286 ERR_STS_SCE = (1 << 14),
287 ERR_STS_STE = (1 << 15),
288 ERR_STS_FOW = (1 << 16),
289 ERR_STS_UE = (1 << 17),
290 ERR_STS_MCH = (1 << 26),
291 ERR_STS_LOC_SHIFT = 27,
292};
293
294/*
295 * RAM Debug Address Register (RAM_DBG_ADDR) bit definitions.
296 */
297enum {
298 RAM_DBG_ADDR_FW = (1 << 30),
299 RAM_DBG_ADDR_FR = (1 << 31),
300};
301
302/*
303 * Semaphore Register (SEM) bit definitions.
304 */
305enum {
306 /*
307 * Example:
308 * reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT)
309 */
310 SEM_CLEAR = 0,
311 SEM_SET = 1,
312 SEM_FORCE = 3,
313 SEM_XGMAC0_SHIFT = 0,
314 SEM_XGMAC1_SHIFT = 2,
315 SEM_ICB_SHIFT = 4,
316 SEM_MAC_ADDR_SHIFT = 6,
317 SEM_FLASH_SHIFT = 8,
318 SEM_PROBE_SHIFT = 10,
319 SEM_RT_IDX_SHIFT = 12,
320 SEM_PROC_REG_SHIFT = 14,
321 SEM_XGMAC0_MASK = 0x00030000,
322 SEM_XGMAC1_MASK = 0x000c0000,
323 SEM_ICB_MASK = 0x00300000,
324 SEM_MAC_ADDR_MASK = 0x00c00000,
325 SEM_FLASH_MASK = 0x03000000,
326 SEM_PROBE_MASK = 0x0c000000,
327 SEM_RT_IDX_MASK = 0x30000000,
328 SEM_PROC_REG_MASK = 0xc0000000,
329};
330
331/*
332 * 10G MAC Address Register (XGMAC_ADDR) bit definitions.
333 */
334enum {
335 XGMAC_ADDR_RDY = (1 << 31),
336 XGMAC_ADDR_R = (1 << 30),
337 XGMAC_ADDR_XME = (1 << 29),
338
339 /* XGMAC control registers */
340 PAUSE_SRC_LO = 0x00000100,
341 PAUSE_SRC_HI = 0x00000104,
342 GLOBAL_CFG = 0x00000108,
343 GLOBAL_CFG_RESET = (1 << 0),
344 GLOBAL_CFG_JUMBO = (1 << 6),
345 GLOBAL_CFG_TX_STAT_EN = (1 << 10),
346 GLOBAL_CFG_RX_STAT_EN = (1 << 11),
347 TX_CFG = 0x0000010c,
348 TX_CFG_RESET = (1 << 0),
349 TX_CFG_EN = (1 << 1),
350 TX_CFG_PREAM = (1 << 2),
351 RX_CFG = 0x00000110,
352 RX_CFG_RESET = (1 << 0),
353 RX_CFG_EN = (1 << 1),
354 RX_CFG_PREAM = (1 << 2),
355 FLOW_CTL = 0x0000011c,
356 PAUSE_OPCODE = 0x00000120,
357 PAUSE_TIMER = 0x00000124,
358 PAUSE_FRM_DEST_LO = 0x00000128,
359 PAUSE_FRM_DEST_HI = 0x0000012c,
360 MAC_TX_PARAMS = 0x00000134,
361 MAC_TX_PARAMS_JUMBO = (1 << 31),
362 MAC_TX_PARAMS_SIZE_SHIFT = 16,
363 MAC_RX_PARAMS = 0x00000138,
364 MAC_SYS_INT = 0x00000144,
365 MAC_SYS_INT_MASK = 0x00000148,
366 MAC_MGMT_INT = 0x0000014c,
367 MAC_MGMT_IN_MASK = 0x00000150,
368 EXT_ARB_MODE = 0x000001fc,
369
370 /* XGMAC TX statistics registers */
371 TX_PKTS = 0x00000200,
372 TX_BYTES = 0x00000208,
373 TX_MCAST_PKTS = 0x00000210,
374 TX_BCAST_PKTS = 0x00000218,
375 TX_UCAST_PKTS = 0x00000220,
376 TX_CTL_PKTS = 0x00000228,
377 TX_PAUSE_PKTS = 0x00000230,
378 TX_64_PKT = 0x00000238,
379 TX_65_TO_127_PKT = 0x00000240,
380 TX_128_TO_255_PKT = 0x00000248,
381 TX_256_511_PKT = 0x00000250,
382 TX_512_TO_1023_PKT = 0x00000258,
383 TX_1024_TO_1518_PKT = 0x00000260,
384 TX_1519_TO_MAX_PKT = 0x00000268,
385 TX_UNDERSIZE_PKT = 0x00000270,
386 TX_OVERSIZE_PKT = 0x00000278,
387
388 /* XGMAC statistics control registers */
389 RX_HALF_FULL_DET = 0x000002a0,
390 TX_HALF_FULL_DET = 0x000002a4,
391 RX_OVERFLOW_DET = 0x000002a8,
392 TX_OVERFLOW_DET = 0x000002ac,
393 RX_HALF_FULL_MASK = 0x000002b0,
394 TX_HALF_FULL_MASK = 0x000002b4,
395 RX_OVERFLOW_MASK = 0x000002b8,
396 TX_OVERFLOW_MASK = 0x000002bc,
397 STAT_CNT_CTL = 0x000002c0,
398 STAT_CNT_CTL_CLEAR_TX = (1 << 0),
399 STAT_CNT_CTL_CLEAR_RX = (1 << 1),
400 AUX_RX_HALF_FULL_DET = 0x000002d0,
401 AUX_TX_HALF_FULL_DET = 0x000002d4,
402 AUX_RX_OVERFLOW_DET = 0x000002d8,
403 AUX_TX_OVERFLOW_DET = 0x000002dc,
404 AUX_RX_HALF_FULL_MASK = 0x000002f0,
405 AUX_TX_HALF_FULL_MASK = 0x000002f4,
406 AUX_RX_OVERFLOW_MASK = 0x000002f8,
407 AUX_TX_OVERFLOW_MASK = 0x000002fc,
408
409 /* XGMAC RX statistics registers */
410 RX_BYTES = 0x00000300,
411 RX_BYTES_OK = 0x00000308,
412 RX_PKTS = 0x00000310,
413 RX_PKTS_OK = 0x00000318,
414 RX_BCAST_PKTS = 0x00000320,
415 RX_MCAST_PKTS = 0x00000328,
416 RX_UCAST_PKTS = 0x00000330,
417 RX_UNDERSIZE_PKTS = 0x00000338,
418 RX_OVERSIZE_PKTS = 0x00000340,
419 RX_JABBER_PKTS = 0x00000348,
420 RX_UNDERSIZE_FCERR_PKTS = 0x00000350,
421 RX_DROP_EVENTS = 0x00000358,
422 RX_FCERR_PKTS = 0x00000360,
423 RX_ALIGN_ERR = 0x00000368,
424 RX_SYMBOL_ERR = 0x00000370,
425 RX_MAC_ERR = 0x00000378,
426 RX_CTL_PKTS = 0x00000380,
b82808b7 427 RX_PAUSE_PKTS = 0x00000388,
c4e84bde
RM		 428 RX_64_PKTS = 0x00000390,
429 RX_65_TO_127_PKTS = 0x00000398,
430 RX_128_255_PKTS = 0x000003a0,
431 RX_256_511_PKTS = 0x000003a8,
432 RX_512_TO_1023_PKTS = 0x000003b0,
433 RX_1024_TO_1518_PKTS = 0x000003b8,
434 RX_1519_TO_MAX_PKTS = 0x000003c0,
435 RX_LEN_ERR_PKTS = 0x000003c8,
436
437 /* XGMAC MDIO control registers */
438 MDIO_TX_DATA = 0x00000400,
439 MDIO_RX_DATA = 0x00000410,
440 MDIO_CMD = 0x00000420,
441 MDIO_PHY_ADDR = 0x00000430,
442 MDIO_PORT = 0x00000440,
443 MDIO_STATUS = 0x00000450,
444
445 /* XGMAC AUX statistics registers */
446};
447
448/*
449 * Enhanced Transmission Schedule Registers (NIC_ETS,CNA_ETS) bit definitions.
450 */
451enum {
452 ETS_QUEUE_SHIFT = 29,
453 ETS_REF = (1 << 26),
454 ETS_RS = (1 << 27),
455 ETS_P = (1 << 28),
456 ETS_FC_COS_SHIFT = 23,
457};
458
459/*
460 * Flash Address Register (FLASH_ADDR) bit definitions.
461 */
462enum {
463 FLASH_ADDR_RDY = (1 << 31),
464 FLASH_ADDR_R = (1 << 30),
465 FLASH_ADDR_ERR = (1 << 29),
466};
467
468/*
469 * Stop CQ Processing Register (CQ_STOP) bit definitions.
470 */
471enum {
472 CQ_STOP_QUEUE_MASK = (0x007f0000),
473 CQ_STOP_TYPE_MASK = (0x03000000),
474 CQ_STOP_TYPE_START = 0x00000100,
475 CQ_STOP_TYPE_STOP = 0x00000200,
476 CQ_STOP_TYPE_READ = 0x00000300,
477 CQ_STOP_EN = (1 << 15),
478};
479
480/*
481 * MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions.
482 */
483enum {
484 MAC_ADDR_IDX_SHIFT = 4,
485 MAC_ADDR_TYPE_SHIFT = 16,
486 MAC_ADDR_TYPE_MASK = 0x000f0000,
487 MAC_ADDR_TYPE_CAM_MAC = 0x00000000,
488 MAC_ADDR_TYPE_MULTI_MAC = 0x00010000,
489 MAC_ADDR_TYPE_VLAN = 0x00020000,
490 MAC_ADDR_TYPE_MULTI_FLTR = 0x00030000,
491 MAC_ADDR_TYPE_FC_MAC = 0x00040000,
492 MAC_ADDR_TYPE_MGMT_MAC = 0x00050000,
493 MAC_ADDR_TYPE_MGMT_VLAN = 0x00060000,
494 MAC_ADDR_TYPE_MGMT_V4 = 0x00070000,
495 MAC_ADDR_TYPE_MGMT_V6 = 0x00080000,
496 MAC_ADDR_TYPE_MGMT_TU_DP = 0x00090000,
497 MAC_ADDR_ADR = (1 << 25),
498 MAC_ADDR_RS = (1 << 26),
499 MAC_ADDR_E = (1 << 27),
500 MAC_ADDR_MR = (1 << 30),
501 MAC_ADDR_MW = (1 << 31),
502 MAX_MULTICAST_ENTRIES = 32,
503};
504
505/*
506 * MAC Protocol Address Index Register (SPLT_HDR) bit definitions.
507 */
508enum {
509 SPLT_HDR_EP = (1 << 31),
510};
511
512/*
513 * FCoE Receive Configuration Register (FC_RCV_CFG) bit definitions.
514 */
515enum {
516 FC_RCV_CFG_ECT = (1 << 15),
517 FC_RCV_CFG_DFH = (1 << 20),
518 FC_RCV_CFG_DVF = (1 << 21),
519 FC_RCV_CFG_RCE = (1 << 27),
520 FC_RCV_CFG_RFE = (1 << 28),
521 FC_RCV_CFG_TEE = (1 << 29),
522 FC_RCV_CFG_TCE = (1 << 30),
523 FC_RCV_CFG_TFE = (1 << 31),
524};
525
526/*
527 * NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions.
528 */
529enum {
530 NIC_RCV_CFG_PPE = (1 << 0),
531 NIC_RCV_CFG_VLAN_MASK = 0x00060000,
532 NIC_RCV_CFG_VLAN_ALL = 0x00000000,
533 NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002,
534 NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004,
535 NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006,
536 NIC_RCV_CFG_RV = (1 << 3),
537 NIC_RCV_CFG_DFQ_MASK = (0x7f000000),
538 NIC_RCV_CFG_DFQ_SHIFT = 8,
539 NIC_RCV_CFG_DFQ = 0, /* HARDCODE default queue to 0. */
540};
541
542/*
543 * Mgmt Receive Configuration Register (MGMT_RCV_CFG) bit definitions.
544 */
545enum {
546 MGMT_RCV_CFG_ARP = (1 << 0),
547 MGMT_RCV_CFG_DHC = (1 << 1),
548 MGMT_RCV_CFG_DHS = (1 << 2),
549 MGMT_RCV_CFG_NP = (1 << 3),
550 MGMT_RCV_CFG_I6N = (1 << 4),
551 MGMT_RCV_CFG_I6R = (1 << 5),
552 MGMT_RCV_CFG_DH6 = (1 << 6),
553 MGMT_RCV_CFG_UD1 = (1 << 7),
554 MGMT_RCV_CFG_UD0 = (1 << 8),
555 MGMT_RCV_CFG_BCT = (1 << 9),
556 MGMT_RCV_CFG_MCT = (1 << 10),
557 MGMT_RCV_CFG_DM = (1 << 11),
558 MGMT_RCV_CFG_RM = (1 << 12),
559 MGMT_RCV_CFG_STL = (1 << 13),
560 MGMT_RCV_CFG_VLAN_MASK = 0xc0000000,
561 MGMT_RCV_CFG_VLAN_ALL = 0x00000000,
562 MGMT_RCV_CFG_VLAN_MATCH_ONLY = 0x00004000,
563 MGMT_RCV_CFG_VLAN_MATCH_AND_NON = 0x00008000,
564 MGMT_RCV_CFG_VLAN_NONE_AND_NON = 0x0000c000,
565};
566
567/*
568 * Routing Index Register (RT_IDX) bit definitions.
569 */
570enum {
571 RT_IDX_IDX_SHIFT = 8,
572 RT_IDX_TYPE_MASK = 0x000f0000,
573 RT_IDX_TYPE_RT = 0x00000000,
574 RT_IDX_TYPE_RT_INV = 0x00010000,
575 RT_IDX_TYPE_NICQ = 0x00020000,
576 RT_IDX_TYPE_NICQ_INV = 0x00030000,
577 RT_IDX_DST_MASK = 0x00700000,
578 RT_IDX_DST_RSS = 0x00000000,
579 RT_IDX_DST_CAM_Q = 0x00100000,
580 RT_IDX_DST_COS_Q = 0x00200000,
581 RT_IDX_DST_DFLT_Q = 0x00300000,
582 RT_IDX_DST_DEST_Q = 0x00400000,
583 RT_IDX_RS = (1 << 26),
584 RT_IDX_E = (1 << 27),
585 RT_IDX_MR = (1 << 30),
586 RT_IDX_MW = (1 << 31),
587
588 /* Nic Queue format - type 2 bits */
589 RT_IDX_BCAST = (1 << 0),
590 RT_IDX_MCAST = (1 << 1),
591 RT_IDX_MCAST_MATCH = (1 << 2),
592 RT_IDX_MCAST_REG_MATCH = (1 << 3),
593 RT_IDX_MCAST_HASH_MATCH = (1 << 4),
594 RT_IDX_FC_MACH = (1 << 5),
595 RT_IDX_ETH_FCOE = (1 << 6),
596 RT_IDX_CAM_HIT = (1 << 7),
597 RT_IDX_CAM_BIT0 = (1 << 8),
598 RT_IDX_CAM_BIT1 = (1 << 9),
599 RT_IDX_VLAN_TAG = (1 << 10),
600 RT_IDX_VLAN_MATCH = (1 << 11),
601 RT_IDX_VLAN_FILTER = (1 << 12),
602 RT_IDX_ETH_SKIP1 = (1 << 13),
603 RT_IDX_ETH_SKIP2 = (1 << 14),
604 RT_IDX_BCAST_MCAST_MATCH = (1 << 15),
605 RT_IDX_802_3 = (1 << 16),
606 RT_IDX_LLDP = (1 << 17),
607 RT_IDX_UNUSED018 = (1 << 18),
608 RT_IDX_UNUSED019 = (1 << 19),
609 RT_IDX_UNUSED20 = (1 << 20),
610 RT_IDX_UNUSED21 = (1 << 21),
611 RT_IDX_ERR = (1 << 22),
612 RT_IDX_VALID = (1 << 23),
613 RT_IDX_TU_CSUM_ERR = (1 << 24),
614 RT_IDX_IP_CSUM_ERR = (1 << 25),
615 RT_IDX_MAC_ERR = (1 << 26),
616 RT_IDX_RSS_TCP6 = (1 << 27),
617 RT_IDX_RSS_TCP4 = (1 << 28),
618 RT_IDX_RSS_IPV6 = (1 << 29),
619 RT_IDX_RSS_IPV4 = (1 << 30),
620 RT_IDX_RSS_MATCH = (1 << 31),
621
622 /* Hierarchy for the NIC Queue Mask */
623 RT_IDX_ALL_ERR_SLOT = 0,
624 RT_IDX_MAC_ERR_SLOT = 0,
625 RT_IDX_IP_CSUM_ERR_SLOT = 1,
626 RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2,
627 RT_IDX_BCAST_SLOT = 3,
628 RT_IDX_MCAST_MATCH_SLOT = 4,
629 RT_IDX_ALLMULTI_SLOT = 5,
630 RT_IDX_UNUSED6_SLOT = 6,
631 RT_IDX_UNUSED7_SLOT = 7,
632 RT_IDX_RSS_MATCH_SLOT = 8,
633 RT_IDX_RSS_IPV4_SLOT = 8,
634 RT_IDX_RSS_IPV6_SLOT = 9,
635 RT_IDX_RSS_TCP4_SLOT = 10,
636 RT_IDX_RSS_TCP6_SLOT = 11,
637 RT_IDX_CAM_HIT_SLOT = 12,
638 RT_IDX_UNUSED013 = 13,
639 RT_IDX_UNUSED014 = 14,
640 RT_IDX_PROMISCUOUS_SLOT = 15,
641 RT_IDX_MAX_SLOTS = 16,
642};
643
644/*
645 * Control Register Set Map
646 */
647enum {
648 PROC_ADDR = 0, /* Use semaphore */
649 PROC_DATA = 0x04, /* Use semaphore */
650 SYS = 0x08,
651 RST_FO = 0x0c,
652 FSC = 0x10,
653 CSR = 0x14,
654 LED = 0x18,
655 ICB_RID = 0x1c, /* Use semaphore */
656 ICB_L = 0x20, /* Use semaphore */
657 ICB_H = 0x24, /* Use semaphore */
658 CFG = 0x28,
659 BIOS_ADDR = 0x2c,
660 STS = 0x30,
661 INTR_EN = 0x34,
662 INTR_MASK = 0x38,
663 ISR1 = 0x3c,
664 ISR2 = 0x40,
665 ISR3 = 0x44,
666 ISR4 = 0x48,
667 REV_ID = 0x4c,
668 FRC_ECC_ERR = 0x50,
669 ERR_STS = 0x54,
670 RAM_DBG_ADDR = 0x58,
671 RAM_DBG_DATA = 0x5c,
672 ECC_ERR_CNT = 0x60,
673 SEM = 0x64,
674 GPIO_1 = 0x68, /* Use semaphore */
675 GPIO_2 = 0x6c, /* Use semaphore */
676 GPIO_3 = 0x70, /* Use semaphore */
677 RSVD2 = 0x74,
678 XGMAC_ADDR = 0x78, /* Use semaphore */
679 XGMAC_DATA = 0x7c, /* Use semaphore */
680 NIC_ETS = 0x80,
681 CNA_ETS = 0x84,
682 FLASH_ADDR = 0x88, /* Use semaphore */
683 FLASH_DATA = 0x8c, /* Use semaphore */
684 CQ_STOP = 0x90,
685 PAGE_TBL_RID = 0x94,
686 WQ_PAGE_TBL_LO = 0x98,
687 WQ_PAGE_TBL_HI = 0x9c,
688 CQ_PAGE_TBL_LO = 0xa0,
689 CQ_PAGE_TBL_HI = 0xa4,
690 MAC_ADDR_IDX = 0xa8, /* Use semaphore */
691 MAC_ADDR_DATA = 0xac, /* Use semaphore */
692 COS_DFLT_CQ1 = 0xb0,
693 COS_DFLT_CQ2 = 0xb4,
694 ETYPE_SKIP1 = 0xb8,
695 ETYPE_SKIP2 = 0xbc,
696 SPLT_HDR = 0xc0,
697 FC_PAUSE_THRES = 0xc4,
698 NIC_PAUSE_THRES = 0xc8,
699 FC_ETHERTYPE = 0xcc,
700 FC_RCV_CFG = 0xd0,
701 NIC_RCV_CFG = 0xd4,
702 FC_COS_TAGS = 0xd8,
703 NIC_COS_TAGS = 0xdc,
704 MGMT_RCV_CFG = 0xe0,
705 RT_IDX = 0xe4,
706 RT_DATA = 0xe8,
707 RSVD7 = 0xec,
708 XG_SERDES_ADDR = 0xf0,
709 XG_SERDES_DATA = 0xf4,
710 PRB_MX_ADDR = 0xf8, /* Use semaphore */
711 PRB_MX_DATA = 0xfc, /* Use semaphore */
712};
713
714/*
715 * CAM output format.
716 */
717enum {
718 CAM_OUT_ROUTE_FC = 0,
719 CAM_OUT_ROUTE_NIC = 1,
720 CAM_OUT_FUNC_SHIFT = 2,
721 CAM_OUT_RV = (1 << 4),
722 CAM_OUT_SH = (1 << 15),
723 CAM_OUT_CQ_ID_SHIFT = 5,
724};
725
726/*
727 * Mailbox definitions
728 */
729enum {
730 /* Asynchronous Event Notifications */
731 AEN_SYS_ERR = 0x00008002,
732 AEN_LINK_UP = 0x00008011,
733 AEN_LINK_DOWN = 0x00008012,
734 AEN_IDC_CMPLT = 0x00008100,
735 AEN_IDC_REQ = 0x00008101,
b82808b7
RM		 736 AEN_IDC_EXT = 0x00008102,
737 AEN_DCBX_CHG = 0x00008110,
738 AEN_AEN_LOST = 0x00008120,
739 AEN_AEN_SFP_IN = 0x00008130,
740 AEN_AEN_SFP_OUT = 0x00008131,
c4e84bde
RM		 741 AEN_FW_INIT_DONE = 0x00008400,
742 AEN_FW_INIT_FAIL = 0x00008401,
743
744 /* Mailbox Command Opcodes. */
745 MB_CMD_NOP = 0x00000000,
746 MB_CMD_EX_FW = 0x00000002,
747 MB_CMD_MB_TEST = 0x00000006,
748 MB_CMD_CSUM_TEST = 0x00000007, /* Verify Checksum */
749 MB_CMD_ABOUT_FW = 0x00000008,
b82808b7 750 MB_CMD_COPY_RISC_RAM = 0x0000000a,
c4e84bde
RM		 751 MB_CMD_LOAD_RISC_RAM = 0x0000000b,
752 MB_CMD_DUMP_RISC_RAM = 0x0000000c,
753 MB_CMD_WRITE_RAM = 0x0000000d,
b82808b7 754 MB_CMD_INIT_RISC_RAM = 0x0000000e,
c4e84bde
RM		 755 MB_CMD_READ_RAM = 0x0000000f,
756 MB_CMD_STOP_FW = 0x00000014,
757 MB_CMD_MAKE_SYS_ERR = 0x0000002a,
b82808b7
RM		 758 MB_CMD_WRITE_SFP = 0x00000030,
759 MB_CMD_READ_SFP = 0x00000031,
c4e84bde 760 MB_CMD_INIT_FW = 0x00000060,
b82808b7 761 MB_CMD_GET_IFCB = 0x00000061,
c4e84bde
RM		 762 MB_CMD_GET_FW_STATE = 0x00000069,
763 MB_CMD_IDC_REQ = 0x00000100, /* Inter-Driver Communication */
764 MB_CMD_IDC_ACK = 0x00000101, /* Inter-Driver Communication */
765 MB_CMD_SET_WOL_MODE = 0x00000110, /* Wake On Lan */
b82808b7
RM		 766 MB_WOL_DISABLE = 0,
767 MB_WOL_MAGIC_PKT = (1 << 1),
768 MB_WOL_FLTR = (1 << 2),
769 MB_WOL_UCAST = (1 << 3),
770 MB_WOL_MCAST = (1 << 4),
771 MB_WOL_BCAST = (1 << 5),
772 MB_WOL_LINK_UP = (1 << 6),
773 MB_WOL_LINK_DOWN = (1 << 7),
c4e84bde 774 MB_CMD_SET_WOL_FLTR = 0x00000111, /* Wake On Lan Filter */
b82808b7 775 MB_CMD_CLEAR_WOL_FLTR = 0x00000112, /* Wake On Lan Filter */
c4e84bde 776 MB_CMD_SET_WOL_MAGIC = 0x00000113, /* Wake On Lan Magic Packet */
b82808b7
RM		 777 MB_CMD_CLEAR_WOL_MAGIC = 0x00000114,/* Wake On Lan Magic Packet */
778 MB_CMD_SET_WOL_IMMED = 0x00000115,
c4e84bde
RM		 779 MB_CMD_PORT_RESET = 0x00000120,
780 MB_CMD_SET_PORT_CFG = 0x00000122,
781 MB_CMD_GET_PORT_CFG = 0x00000123,
b82808b7 782 MB_CMD_GET_LINK_STS = 0x00000124,
c4e84bde
RM		 783
784 /* Mailbox Command Status. */
785 MB_CMD_STS_GOOD = 0x00004000, /* Success. */
786 MB_CMD_STS_INTRMDT = 0x00001000, /* Intermediate Complete. */
b82808b7
RM		 787 MB_CMD_STS_INVLD_CMD = 0x00004001, /* Invalid. */
788 MB_CMD_STS_XFC_ERR = 0x00004002, /* Interface Error. */
789 MB_CMD_STS_CSUM_ERR = 0x00004003, /* Csum Error. */
790 MB_CMD_STS_ERR = 0x00004005, /* System Error. */
791 MB_CMD_STS_PARAM_ERR = 0x00004006, /* Parameter Error. */
c4e84bde
RM		 792};
793
794struct mbox_params {
795 u32 mbox_in[MAILBOX_COUNT];
796 u32 mbox_out[MAILBOX_COUNT];
797 int in_count;
798 int out_count;
799};
800
801struct flash_params {
802 u8 dev_id_str[4];
26351479
RM		 803 __le16 size;
804 __le16 csum;
805 __le16 ver;
806 __le16 sub_dev_id;
c4e84bde 807 u8 mac_addr[6];
26351479 808 __le16 res;
c4e84bde
RM		 809};
810
811
812/*
813 * doorbell space for the rx ring context
814 */
815struct rx_doorbell_context {
816 u32 cnsmr_idx; /* 0x00 */
817 u32 valid; /* 0x04 */
818 u32 reserved[4]; /* 0x08-0x14 */
819 u32 lbq_prod_idx; /* 0x18 */
820 u32 sbq_prod_idx; /* 0x1c */
821};
822
823/*
824 * doorbell space for the tx ring context
825 */
826struct tx_doorbell_context {
827 u32 prod_idx; /* 0x00 */
828 u32 valid; /* 0x04 */
829 u32 reserved[4]; /* 0x08-0x14 */
830 u32 lbq_prod_idx; /* 0x18 */
831 u32 sbq_prod_idx; /* 0x1c */
832};
833
834/* DATA STRUCTURES SHARED WITH HARDWARE. */
c4e84bde
RM		 835struct tx_buf_desc {
836 __le64 addr;
837 __le32 len;
838#define TX_DESC_LEN_MASK 0x000fffff
839#define TX_DESC_C 0x40000000
840#define TX_DESC_E 0x80000000
841} __attribute((packed));
842
843/*
844 * IOCB Definitions...
845 */
846
847#define OPCODE_OB_MAC_IOCB 0x01
848#define OPCODE_OB_MAC_TSO_IOCB 0x02
849#define OPCODE_IB_MAC_IOCB 0x20
850#define OPCODE_IB_MPI_IOCB 0x21
851#define OPCODE_IB_AE_IOCB 0x3f
852
853struct ob_mac_iocb_req {
854 u8 opcode;
855 u8 flags1;
856#define OB_MAC_IOCB_REQ_OI 0x01
857#define OB_MAC_IOCB_REQ_I 0x02
858#define OB_MAC_IOCB_REQ_D 0x08
859#define OB_MAC_IOCB_REQ_F 0x10
860 u8 flags2;
861 u8 flags3;
862#define OB_MAC_IOCB_DFP 0x02
863#define OB_MAC_IOCB_V 0x04
864 __le32 reserved1[2];
865 __le16 frame_len;
866#define OB_MAC_IOCB_LEN_MASK 0x3ffff
867 __le16 reserved2;
3537d54c
RM		 868 u32 tid;
869 u32 txq_idx;
c4e84bde
RM		 870 __le32 reserved3;
871 __le16 vlan_tci;
872 __le16 reserved4;
873 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
874} __attribute((packed));
875
876struct ob_mac_iocb_rsp {
877 u8 opcode; /* */
878 u8 flags1; /* */
879#define OB_MAC_IOCB_RSP_OI 0x01 /* */
880#define OB_MAC_IOCB_RSP_I 0x02 /* */
881#define OB_MAC_IOCB_RSP_E 0x08 /* */
882#define OB_MAC_IOCB_RSP_S 0x10 /* too Short */
883#define OB_MAC_IOCB_RSP_L 0x20 /* too Large */
884#define OB_MAC_IOCB_RSP_P 0x40 /* Padded */
885 u8 flags2; /* */
886 u8 flags3; /* */
887#define OB_MAC_IOCB_RSP_B 0x80 /* */
3537d54c
RM		 888 u32 tid;
889 u32 txq_idx;
c4e84bde
RM		 890 __le32 reserved[13];
891} __attribute((packed));
892
893struct ob_mac_tso_iocb_req {
894 u8 opcode;
895 u8 flags1;
896#define OB_MAC_TSO_IOCB_OI 0x01
897#define OB_MAC_TSO_IOCB_I 0x02
898#define OB_MAC_TSO_IOCB_D 0x08
899#define OB_MAC_TSO_IOCB_IP4 0x40
900#define OB_MAC_TSO_IOCB_IP6 0x80
901 u8 flags2;
902#define OB_MAC_TSO_IOCB_LSO 0x20
903#define OB_MAC_TSO_IOCB_UC 0x40
904#define OB_MAC_TSO_IOCB_TC 0x80
905 u8 flags3;
906#define OB_MAC_TSO_IOCB_IC 0x01
907#define OB_MAC_TSO_IOCB_DFP 0x02
908#define OB_MAC_TSO_IOCB_V 0x04
909 __le32 reserved1[2];
910 __le32 frame_len;
3537d54c
RM		 911 u32 tid;
912 u32 txq_idx;
c4e84bde
RM		 913 __le16 total_hdrs_len;
914 __le16 net_trans_offset;
915#define OB_MAC_TRANSPORT_HDR_SHIFT 6
916 __le16 vlan_tci;
917 __le16 mss;
918 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
919} __attribute((packed));
920
921struct ob_mac_tso_iocb_rsp {
922 u8 opcode;
923 u8 flags1;
924#define OB_MAC_TSO_IOCB_RSP_OI 0x01
925#define OB_MAC_TSO_IOCB_RSP_I 0x02
926#define OB_MAC_TSO_IOCB_RSP_E 0x08
927#define OB_MAC_TSO_IOCB_RSP_S 0x10
928#define OB_MAC_TSO_IOCB_RSP_L 0x20
929#define OB_MAC_TSO_IOCB_RSP_P 0x40
930 u8 flags2; /* */
931 u8 flags3; /* */
932#define OB_MAC_TSO_IOCB_RSP_B 0x8000
3537d54c
RM		 933 u32 tid;
934 u32 txq_idx;
c4e84bde
RM		 935 __le32 reserved2[13];
936} __attribute((packed));
937
938struct ib_mac_iocb_rsp {
939 u8 opcode; /* 0x20 */
940 u8 flags1;
941#define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */
942#define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */
943#define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */
944#define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */
945#define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */
946#define IB_MAC_IOCB_RSP_M_MASK 0x60 /* Multicast info */
947#define IB_MAC_IOCB_RSP_M_NONE 0x00 /* Not mcast frame */
948#define IB_MAC_IOCB_RSP_M_HASH 0x20 /* HASH mcast frame */
949#define IB_MAC_IOCB_RSP_M_REG 0x40 /* Registered mcast frame */
950#define IB_MAC_IOCB_RSP_M_PROM 0x60 /* Promiscuous mcast frame */
951#define IB_MAC_IOCB_RSP_B 0x80 /* Broadcast frame */
952 u8 flags2;
953#define IB_MAC_IOCB_RSP_P 0x01 /* Promiscuous frame */
954#define IB_MAC_IOCB_RSP_V 0x02 /* Vlan tag present */
955#define IB_MAC_IOCB_RSP_ERR_MASK 0x1c /* */
956#define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04
957#define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08
958#define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10
959#define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14
960#define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18
961#define IB_MAC_IOCB_RSP_ERR_CRC 0x1c
962#define IB_MAC_IOCB_RSP_U 0x20 /* UDP packet */
963#define IB_MAC_IOCB_RSP_T 0x40 /* TCP packet */
964#define IB_MAC_IOCB_RSP_FO 0x80 /* Failover port */
965 u8 flags3;
966#define IB_MAC_IOCB_RSP_RSS_MASK 0x07 /* RSS mask */
967#define IB_MAC_IOCB_RSP_M_NONE 0x00 /* No RSS match */
968#define IB_MAC_IOCB_RSP_M_IPV4 0x04 /* IPv4 RSS match */
969#define IB_MAC_IOCB_RSP_M_IPV6 0x02 /* IPv6 RSS match */
970#define IB_MAC_IOCB_RSP_M_TCP_V4 0x05 /* TCP with IPv4 */
971#define IB_MAC_IOCB_RSP_M_TCP_V6 0x03 /* TCP with IPv6 */
972#define IB_MAC_IOCB_RSP_V4 0x08 /* IPV4 */
973#define IB_MAC_IOCB_RSP_V6 0x10 /* IPV6 */
974#define IB_MAC_IOCB_RSP_IH 0x20 /* Split after IP header */
975#define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */
976#define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */
977 __le32 data_len; /* */
97345524 978 __le64 data_addr; /* */
c4e84bde
RM		 979 __le32 rss; /* */
980 __le16 vlan_id; /* 12 bits */
981#define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */
982#define IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */
b82808b7 983#define IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff
c4e84bde
RM		 984
985 __le16 reserved1;
986 __le32 reserved2[6];
a303ce09
RM		 987 u8 reserved3[3];
988 u8 flags4;
989#define IB_MAC_IOCB_RSP_HV 0x20
990#define IB_MAC_IOCB_RSP_HS 0x40
991#define IB_MAC_IOCB_RSP_HL 0x80
c4e84bde 992 __le32 hdr_len; /* */
97345524 993 __le64 hdr_addr; /* */
c4e84bde
RM		 994} __attribute((packed));
995
996struct ib_ae_iocb_rsp {
997 u8 opcode;
998 u8 flags1;
999#define IB_AE_IOCB_RSP_OI 0x01
1000#define IB_AE_IOCB_RSP_I 0x02
1001 u8 event;
1002#define LINK_UP_EVENT 0x00
1003#define LINK_DOWN_EVENT 0x01
1004#define CAM_LOOKUP_ERR_EVENT 0x06
1005#define SOFT_ECC_ERROR_EVENT 0x07
1006#define MGMT_ERR_EVENT 0x08
1007#define TEN_GIG_MAC_EVENT 0x09
1008#define GPI0_H2L_EVENT 0x10
1009#define GPI0_L2H_EVENT 0x20
1010#define GPI1_H2L_EVENT 0x11
1011#define GPI1_L2H_EVENT 0x21
1012#define PCI_ERR_ANON_BUF_RD 0x40
1013 u8 q_id;
1014 __le32 reserved[15];
1015} __attribute((packed));
1016
1017/*
1018 * These three structures are for generic
1019 * handling of ib and ob iocbs.
1020 */
1021struct ql_net_rsp_iocb {
1022 u8 opcode;
1023 u8 flags0;
1024 __le16 length;
1025 __le32 tid;
1026 __le32 reserved[14];
1027} __attribute((packed));
1028
1029struct net_req_iocb {
1030 u8 opcode;
1031 u8 flags0;
1032 __le16 flags1;
1033 __le32 tid;
1034 __le32 reserved1[30];
1035} __attribute((packed));
1036
1037/*
1038 * tx ring initialization control block for chip.
1039 * It is defined as:
1040 * "Work Queue Initialization Control Block"
1041 */
1042struct wqicb {
1043 __le16 len;
1044#define Q_LEN_V (1 << 4)
1045#define Q_LEN_CPP_CONT 0x0000
1046#define Q_LEN_CPP_16 0x0001
1047#define Q_LEN_CPP_32 0x0002
1048#define Q_LEN_CPP_64 0x0003
b82808b7 1049#define Q_LEN_CPP_512 0x0006
c4e84bde
RM		 1050 __le16 flags;
1051#define Q_PRI_SHIFT 1
1052#define Q_FLAGS_LC 0x1000
1053#define Q_FLAGS_LB 0x2000
1054#define Q_FLAGS_LI 0x4000
1055#define Q_FLAGS_LO 0x8000
1056 __le16 cq_id_rss;
1057#define Q_CQ_ID_RSS_RV 0x8000
1058 __le16 rid;
97345524
RM		 1059 __le64 addr;
1060 __le64 cnsmr_idx_addr;
c4e84bde
RM		 1061} __attribute((packed));
1062
1063/*
1064 * rx ring initialization control block for chip.
1065 * It is defined as:
1066 * "Completion Queue Initialization Control Block"
1067 */
1068struct cqicb {
1069 u8 msix_vect;
1070 u8 reserved1;
1071 u8 reserved2;
1072 u8 flags;
1073#define FLAGS_LV 0x08
1074#define FLAGS_LS 0x10
1075#define FLAGS_LL 0x20
1076#define FLAGS_LI 0x40
1077#define FLAGS_LC 0x80
1078 __le16 len;
1079#define LEN_V (1 << 4)
1080#define LEN_CPP_CONT 0x0000
1081#define LEN_CPP_32 0x0001
1082#define LEN_CPP_64 0x0002
1083#define LEN_CPP_128 0x0003
1084 __le16 rid;
97345524
RM		 1085 __le64 addr;
1086 __le64 prod_idx_addr;
c4e84bde
RM		 1087 __le16 pkt_delay;
1088 __le16 irq_delay;
97345524 1089 __le64 lbq_addr;
c4e84bde
RM		 1090 __le16 lbq_buf_size;
1091 __le16 lbq_len; /* entry count */
97345524 1092 __le64 sbq_addr;
c4e84bde
RM		 1093 __le16 sbq_buf_size;
1094 __le16 sbq_len; /* entry count */
1095} __attribute((packed));
1096
1097struct ricb {
1098 u8 base_cq;
1099#define RSS_L4K 0x80
1100 u8 flags;
1101#define RSS_L6K 0x01
1102#define RSS_LI 0x02
1103#define RSS_LB 0x04
1104#define RSS_LM 0x08
1105#define RSS_RI4 0x10
1106#define RSS_RT4 0x20
1107#define RSS_RI6 0x40
1108#define RSS_RT6 0x80
1109 __le16 mask;
1110 __le32 hash_cq_id[256];
1111 __le32 ipv6_hash_key[10];
1112 __le32 ipv4_hash_key[4];
1113} __attribute((packed));
1114
1115/* SOFTWARE/DRIVER DATA STRUCTURES. */
1116
1117struct oal {
1118 struct tx_buf_desc oal[TX_DESC_PER_OAL];
1119};
1120
1121struct map_list {
1122 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1123 DECLARE_PCI_UNMAP_LEN(maplen);
1124};
1125
1126struct tx_ring_desc {
1127 struct sk_buff *skb;
1128 struct ob_mac_iocb_req *queue_entry;
3537d54c 1129 u32 index;
c4e84bde
RM		 1130 struct oal oal;
1131 struct map_list map[MAX_SKB_FRAGS + 1];
1132 int map_cnt;
1133 struct tx_ring_desc *next;
1134};
1135
1136struct bq_desc {
1137 union {
1138 struct page *lbq_page;
1139 struct sk_buff *skb;
1140 } p;
2c9a0d41 1141 __le64 *addr;
3537d54c 1142 u32 index;
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RM		 1143 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1144 DECLARE_PCI_UNMAP_LEN(maplen);
1145};
1146
1147#define QL_TXQ_IDX(qdev, skb) (smp_processor_id()%(qdev->tx_ring_count))
1148
1149struct tx_ring {
1150 /*
1151 * queue info.
1152 */
1153 struct wqicb wqicb; /* structure used to inform chip of new queue */
1154 void *wq_base; /* pci_alloc:virtual addr for tx */
1155 dma_addr_t wq_base_dma; /* pci_alloc:dma addr for tx */
ba7cd3ba 1156 __le32 *cnsmr_idx_sh_reg; /* shadow copy of consumer idx */
c4e84bde
RM		 1157 dma_addr_t cnsmr_idx_sh_reg_dma; /* dma-shadow copy of consumer */
1158 u32 wq_size; /* size in bytes of queue area */
1159 u32 wq_len; /* number of entries in queue */
1160 void __iomem *prod_idx_db_reg; /* doorbell area index reg at offset 0x00 */
1161 void __iomem *valid_db_reg; /* doorbell area valid reg at offset 0x04 */
1162 u16 prod_idx; /* current value for prod idx */
1163 u16 cq_id; /* completion (rx) queue for tx completions */
1164 u8 wq_id; /* queue id for this entry */
1165 u8 reserved1[3];
1166 struct tx_ring_desc *q; /* descriptor list for the queue */
1167 spinlock_t lock;
1168 atomic_t tx_count; /* counts down for every outstanding IO */
1169 atomic_t queue_stopped; /* Turns queue off when full. */
1170 struct delayed_work tx_work;
1171 struct ql_adapter *qdev;
1172};
1173
1174/*
1175 * Type of inbound queue.
1176 */
1177enum {
1178 DEFAULT_Q = 2, /* Handles slow queue and chip/MPI events. */
1179 TX_Q = 3, /* Handles outbound completions. */
1180 RX_Q = 4, /* Handles inbound completions. */
1181};
1182
1183struct rx_ring {
1184 struct cqicb cqicb; /* The chip's completion queue init control block. */
1185
1186 /* Completion queue elements. */
1187 void *cq_base;
1188 dma_addr_t cq_base_dma;
1189 u32 cq_size;
1190 u32 cq_len;
1191 u16 cq_id;
ba7cd3ba 1192 __le32 *prod_idx_sh_reg; /* Shadowed producer register. */
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RM		 1193 dma_addr_t prod_idx_sh_reg_dma;
1194 void __iomem *cnsmr_idx_db_reg; /* PCI doorbell mem area + 0 */
1195 u32 cnsmr_idx; /* current sw idx */
1196 struct ql_net_rsp_iocb *curr_entry; /* next entry on queue */
1197 void __iomem *valid_db_reg; /* PCI doorbell mem area + 0x04 */
1198
1199 /* Large buffer queue elements. */
1200 u32 lbq_len; /* entry count */
1201 u32 lbq_size; /* size in bytes of queue */
1202 u32 lbq_buf_size;
1203 void *lbq_base;
1204 dma_addr_t lbq_base_dma;
1205 void *lbq_base_indirect;
1206 dma_addr_t lbq_base_indirect_dma;
1207 struct bq_desc *lbq; /* array of control blocks */
1208 void __iomem *lbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x18 */
1209 u32 lbq_prod_idx; /* current sw prod idx */
1210 u32 lbq_curr_idx; /* next entry we expect */
1211 u32 lbq_clean_idx; /* beginning of new descs */
1212 u32 lbq_free_cnt; /* free buffer desc cnt */
1213
1214 /* Small buffer queue elements. */
1215 u32 sbq_len; /* entry count */
1216 u32 sbq_size; /* size in bytes of queue */
1217 u32 sbq_buf_size;
1218 void *sbq_base;
1219 dma_addr_t sbq_base_dma;
1220 void *sbq_base_indirect;
1221 dma_addr_t sbq_base_indirect_dma;
1222 struct bq_desc *sbq; /* array of control blocks */
1223 void __iomem *sbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x1c */
1224 u32 sbq_prod_idx; /* current sw prod idx */
1225 u32 sbq_curr_idx; /* next entry we expect */
1226 u32 sbq_clean_idx; /* beginning of new descs */
1227 u32 sbq_free_cnt; /* free buffer desc cnt */
1228
1229 /* Misc. handler elements. */
1230 u32 type; /* Type of queue, tx, rx, or default. */
1231 u32 irq; /* Which vector this ring is assigned. */
1232 u32 cpu; /* Which CPU this should run on. */
1233 char name[IFNAMSIZ + 5];
1234 struct napi_struct napi;
1235 struct delayed_work rx_work;
1236 u8 reserved;
1237 struct ql_adapter *qdev;
1238};
1239
1240/*
1241 * RSS Initialization Control Block
1242 */
1243struct hash_id {
1244 u8 value[4];
1245};
1246
1247struct nic_stats {
1248 /*
1249 * These stats come from offset 200h to 278h
1250 * in the XGMAC register.
1251 */
1252 u64 tx_pkts;
1253 u64 tx_bytes;
1254 u64 tx_mcast_pkts;
1255 u64 tx_bcast_pkts;
1256 u64 tx_ucast_pkts;
1257 u64 tx_ctl_pkts;
1258 u64 tx_pause_pkts;
1259 u64 tx_64_pkt;
1260 u64 tx_65_to_127_pkt;
1261 u64 tx_128_to_255_pkt;
1262 u64 tx_256_511_pkt;
1263 u64 tx_512_to_1023_pkt;
1264 u64 tx_1024_to_1518_pkt;
1265 u64 tx_1519_to_max_pkt;
1266 u64 tx_undersize_pkt;
1267 u64 tx_oversize_pkt;
1268
1269 /*
1270 * These stats come from offset 300h to 3C8h
1271 * in the XGMAC register.
1272 */
1273 u64 rx_bytes;
1274 u64 rx_bytes_ok;
1275 u64 rx_pkts;
1276 u64 rx_pkts_ok;
1277 u64 rx_bcast_pkts;
1278 u64 rx_mcast_pkts;
1279 u64 rx_ucast_pkts;
1280 u64 rx_undersize_pkts;
1281 u64 rx_oversize_pkts;
1282 u64 rx_jabber_pkts;
1283 u64 rx_undersize_fcerr_pkts;
1284 u64 rx_drop_events;
1285 u64 rx_fcerr_pkts;
1286 u64 rx_align_err;
1287 u64 rx_symbol_err;
1288 u64 rx_mac_err;
1289 u64 rx_ctl_pkts;
1290 u64 rx_pause_pkts;
1291 u64 rx_64_pkts;
1292 u64 rx_65_to_127_pkts;
1293 u64 rx_128_255_pkts;
1294 u64 rx_256_511_pkts;
1295 u64 rx_512_to_1023_pkts;
1296 u64 rx_1024_to_1518_pkts;
1297 u64 rx_1519_to_max_pkts;
1298 u64 rx_len_err_pkts;
1299};
1300
1301/*
1302 * intr_context structure is used during initialization
1303 * to hook the interrupts. It is also used in a single
1304 * irq environment as a context to the ISR.
1305 */
1306struct intr_context {
1307 struct ql_adapter *qdev;
1308 u32 intr;
1309 u32 hooked;
1310 u32 intr_en_mask; /* value/mask used to enable this intr */
1311 u32 intr_dis_mask; /* value/mask used to disable this intr */
1312 u32 intr_read_mask; /* value/mask used to read this intr */
1313 char name[IFNAMSIZ * 2];
1314 atomic_t irq_cnt; /* irq_cnt is used in single vector
1315 * environment. It's incremented for each
1316 * irq handler that is scheduled. When each
1317 * handler finishes it decrements irq_cnt and
1318 * enables interrupts if it's zero. */
1319 irq_handler_t handler;
1320};
1321
1322/* adapter flags definitions. */
1323enum {
1324 QL_ADAPTER_UP = (1 << 0), /* Adapter has been brought up. */
1325 QL_LEGACY_ENABLED = (1 << 3),
1326 QL_MSI_ENABLED = (1 << 3),
1327 QL_MSIX_ENABLED = (1 << 4),
1328 QL_DMA64 = (1 << 5),
1329 QL_PROMISCUOUS = (1 << 6),
1330 QL_ALLMULTI = (1 << 7),
b82808b7
RM		 1331 QL_PORT_CFG = (1 << 8),
1332 QL_CAM_RT_SET = (1 << 9),
c4e84bde
RM		 1333};
1334
1335/* link_status bit definitions */
1336enum {
b82808b7
RM		 1337 STS_LOOPBACK_MASK = 0x00000700,
1338 STS_LOOPBACK_PCS = 0x00000100,
1339 STS_LOOPBACK_HSS = 0x00000200,
1340 STS_LOOPBACK_EXT = 0x00000300,
1341 STS_PAUSE_MASK = 0x000000c0,
1342 STS_PAUSE_STD = 0x00000040,
1343 STS_PAUSE_PRI = 0x00000080,
1344 STS_SPEED_MASK = 0x00000038,
1345 STS_SPEED_100Mb = 0x00000000,
1346 STS_SPEED_1Gb = 0x00000008,
1347 STS_SPEED_10Gb = 0x00000010,
1348 STS_LINK_TYPE_MASK = 0x00000007,
1349 STS_LINK_TYPE_XFI = 0x00000001,
1350 STS_LINK_TYPE_XAUI = 0x00000002,
1351 STS_LINK_TYPE_XFI_BP = 0x00000003,
1352 STS_LINK_TYPE_XAUI_BP = 0x00000004,
1353 STS_LINK_TYPE_10GBASET = 0x00000005,
1354};
1355
1356/* link_config bit definitions */
1357enum {
1358 CFG_JUMBO_FRAME_SIZE = 0x00010000,
1359 CFG_PAUSE_MASK = 0x00000060,
1360 CFG_PAUSE_STD = 0x00000020,
1361 CFG_PAUSE_PRI = 0x00000040,
1362 CFG_DCBX = 0x00000010,
1363 CFG_LOOPBACK_MASK = 0x00000007,
1364 CFG_LOOPBACK_PCS = 0x00000002,
1365 CFG_LOOPBACK_HSS = 0x00000004,
1366 CFG_LOOPBACK_EXT = 0x00000006,
1367 CFG_DEFAULT_MAX_FRAME_SIZE = 0x00002580,
c4e84bde
RM		 1368};
1369
1370/*
1371 * The main Adapter structure definition.
1372 * This structure has all fields relevant to the hardware.
1373 */
1374struct ql_adapter {
1375 struct ricb ricb;
1376 unsigned long flags;
1377 u32 wol;
1378
1379 struct nic_stats nic_stats;
1380
1381 struct vlan_group *vlgrp;
1382
1383 /* PCI Configuration information for this device */
1384 struct pci_dev *pdev;
1385 struct net_device *ndev; /* Parent NET device */
1386
1387 /* Hardware information */
1388 u32 chip_rev_id;
1389 u32 func; /* PCI function for this adapter */
1390
1391 spinlock_t adapter_lock;
1392 spinlock_t hw_lock;
1393 spinlock_t stats_lock;
c4e84bde
RM		 1394
1395 /* PCI Bus Relative Register Addresses */
1396 void __iomem *reg_base;
1397 void __iomem *doorbell_area;
1398 u32 doorbell_area_size;
1399
1400 u32 msg_enable;
1401
1402 /* Page for Shadow Registers */
1403 void *rx_ring_shadow_reg_area;
1404 dma_addr_t rx_ring_shadow_reg_dma;
1405 void *tx_ring_shadow_reg_area;
1406 dma_addr_t tx_ring_shadow_reg_dma;
1407
1408 u32 mailbox_in;
1409 u32 mailbox_out;
125844ea 1410 struct mutex mpi_mutex;
c4e84bde
RM		 1411
1412 int tx_ring_size;
1413 int rx_ring_size;
1414 u32 intr_count;
1415 struct msix_entry *msi_x_entry;
1416 struct intr_context intr_context[MAX_RX_RINGS];
1417
c4e84bde
RM		 1418 int tx_ring_count; /* One per online CPU. */
1419 u32 rss_ring_first_cq_id;/* index of first inbound (rss) rx_ring */
1420 u32 rss_ring_count; /* One per online CPU. */
1421 /*
1422 * rx_ring_count =
1423 * one default queue +
1424 * (CPU count * outbound completion rx_ring) +
1425 * (CPU count * inbound (RSS) completion rx_ring)
1426 */
1427 int rx_ring_count;
1428 int ring_mem_size;
1429 void *ring_mem;
683d46a9
RM		 1430
1431 struct rx_ring rx_ring[MAX_RX_RINGS];
1432 struct tx_ring tx_ring[MAX_TX_RINGS];
1433
c4e84bde 1434 int rx_csum;
c4e84bde
RM		 1435 u32 default_rx_queue;
1436
1437 u16 rx_coalesce_usecs; /* cqicb->int_delay */
1438 u16 rx_max_coalesced_frames; /* cqicb->pkt_int_delay */
1439 u16 tx_coalesce_usecs; /* cqicb->int_delay */
1440 u16 tx_max_coalesced_frames; /* cqicb->pkt_int_delay */
1441
1442 u32 xg_sem_mask;
1443 u32 port_link_up;
1444 u32 port_init;
1445 u32 link_status;
1446
1447 struct flash_params flash;
1448
1449 struct net_device_stats stats;
1450 struct workqueue_struct *q_workqueue;
1451 struct workqueue_struct *workqueue;
1452 struct delayed_work asic_reset_work;
1453 struct delayed_work mpi_reset_work;
1454 struct delayed_work mpi_work;
1455};
1456
1457/*
1458 * Typical Register accessor for memory mapped device.
1459 */
1460static inline u32 ql_read32(const struct ql_adapter *qdev, int reg)
1461{
1462 return readl(qdev->reg_base + reg);
1463}
1464
1465/*
1466 * Typical Register accessor for memory mapped device.
1467 */
1468static inline void ql_write32(const struct ql_adapter *qdev, int reg, u32 val)
1469{
1470 writel(val, qdev->reg_base + reg);
1471}
1472
1473/*
1474 * Doorbell Registers:
1475 * Doorbell registers are virtual registers in the PCI memory space.
1476 * The space is allocated by the chip during PCI initialization. The
1477 * device driver finds the doorbell address in BAR 3 in PCI config space.
1478 * The registers are used to control outbound and inbound queues. For
1479 * example, the producer index for an outbound queue. Each queue uses
1480 * 1 4k chunk of memory. The lower half of the space is for outbound
1481 * queues. The upper half is for inbound queues.
1482 */
1483static inline void ql_write_db_reg(u32 val, void __iomem *addr)
1484{
1485 writel(val, addr);
1486 mmiowb();
1487}
1488
ba7cd3ba
RM		 1489/*
1490 * Shadow Registers:
1491 * Outbound queues have a consumer index that is maintained by the chip.
1492 * Inbound queues have a producer index that is maintained by the chip.
1493 * For lower overhead, these registers are "shadowed" to host memory
1494 * which allows the device driver to track the queue progress without
1495 * PCI reads. When an entry is placed on an inbound queue, the chip will
1496 * update the relevant index register and then copy the value to the
1497 * shadow register in host memory.
1498 */
1499static inline u32 ql_read_sh_reg(__le32 *addr)
1500{
1501 u32 reg;
1502 reg = le32_to_cpu(*addr);
1503 rmb();
1504 return reg;
1505}
1506
c4e84bde
RM		 1507extern char qlge_driver_name[];
1508extern const char qlge_driver_version[];
1509extern const struct ethtool_ops qlge_ethtool_ops;
1510
1511extern int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask);
1512extern void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask);
1513extern int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
1514extern int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
1515 u32 *value);
1516extern int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value);
1517extern int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
1518 u16 q_id);
1519void ql_queue_fw_error(struct ql_adapter *qdev);
1520void ql_mpi_work(struct work_struct *work);
1521void ql_mpi_reset_work(struct work_struct *work);
1522int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 ebit);
1523void ql_queue_asic_error(struct ql_adapter *qdev);
bb0d215c 1524u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr);
c4e84bde
RM		 1525void ql_set_ethtool_ops(struct net_device *ndev);
1526int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data);
1527
1528#if 1
1529#define QL_ALL_DUMP
1530#define QL_REG_DUMP
1531#define QL_DEV_DUMP
1532#define QL_CB_DUMP
1533/* #define QL_IB_DUMP */
1534/* #define QL_OB_DUMP */
1535#endif
1536
1537#ifdef QL_REG_DUMP
1538extern void ql_dump_xgmac_control_regs(struct ql_adapter *qdev);
1539extern void ql_dump_routing_entries(struct ql_adapter *qdev);
1540extern void ql_dump_regs(struct ql_adapter *qdev);
1541#define QL_DUMP_REGS(qdev) ql_dump_regs(qdev)
1542#define QL_DUMP_ROUTE(qdev) ql_dump_routing_entries(qdev)
1543#define QL_DUMP_XGMAC_CONTROL_REGS(qdev) ql_dump_xgmac_control_regs(qdev)
1544#else
1545#define QL_DUMP_REGS(qdev)
1546#define QL_DUMP_ROUTE(qdev)
1547#define QL_DUMP_XGMAC_CONTROL_REGS(qdev)
1548#endif
1549
1550#ifdef QL_STAT_DUMP
1551extern void ql_dump_stat(struct ql_adapter *qdev);
1552#define QL_DUMP_STAT(qdev) ql_dump_stat(qdev)
1553#else
1554#define QL_DUMP_STAT(qdev)
1555#endif
1556
1557#ifdef QL_DEV_DUMP
1558extern void ql_dump_qdev(struct ql_adapter *qdev);
1559#define QL_DUMP_QDEV(qdev) ql_dump_qdev(qdev)
1560#else
1561#define QL_DUMP_QDEV(qdev)
1562#endif
1563
1564#ifdef QL_CB_DUMP
1565extern void ql_dump_wqicb(struct wqicb *wqicb);
1566extern void ql_dump_tx_ring(struct tx_ring *tx_ring);
1567extern void ql_dump_ricb(struct ricb *ricb);
1568extern void ql_dump_cqicb(struct cqicb *cqicb);
1569extern void ql_dump_rx_ring(struct rx_ring *rx_ring);
1570extern void ql_dump_hw_cb(struct ql_adapter *qdev, int size, u32 bit, u16 q_id);
1571#define QL_DUMP_RICB(ricb) ql_dump_ricb(ricb)
1572#define QL_DUMP_WQICB(wqicb) ql_dump_wqicb(wqicb)
1573#define QL_DUMP_TX_RING(tx_ring) ql_dump_tx_ring(tx_ring)
1574#define QL_DUMP_CQICB(cqicb) ql_dump_cqicb(cqicb)
1575#define QL_DUMP_RX_RING(rx_ring) ql_dump_rx_ring(rx_ring)
1576#define QL_DUMP_HW_CB(qdev, size, bit, q_id) \
1577 ql_dump_hw_cb(qdev, size, bit, q_id)
1578#else
1579#define QL_DUMP_RICB(ricb)
1580#define QL_DUMP_WQICB(wqicb)
1581#define QL_DUMP_TX_RING(tx_ring)
1582#define QL_DUMP_CQICB(cqicb)
1583#define QL_DUMP_RX_RING(rx_ring)
1584#define QL_DUMP_HW_CB(qdev, size, bit, q_id)
1585#endif
1586
1587#ifdef QL_OB_DUMP
1588extern void ql_dump_tx_desc(struct tx_buf_desc *tbd);
1589extern void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req *ob_mac_iocb);
1590extern void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp *ob_mac_rsp);
1591#define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb) ql_dump_ob_mac_iocb(ob_mac_iocb)
1592#define QL_DUMP_OB_MAC_RSP(ob_mac_rsp) ql_dump_ob_mac_rsp(ob_mac_rsp)
1593#else
1594#define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb)
1595#define QL_DUMP_OB_MAC_RSP(ob_mac_rsp)
1596#endif
1597
1598#ifdef QL_IB_DUMP
1599extern void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp);
1600#define QL_DUMP_IB_MAC_RSP(ib_mac_rsp) ql_dump_ib_mac_rsp(ib_mac_rsp)
1601#else
1602#define QL_DUMP_IB_MAC_RSP(ib_mac_rsp)
1603#endif
1604
1605#ifdef QL_ALL_DUMP
1606extern void ql_dump_all(struct ql_adapter *qdev);
1607#define QL_DUMP_ALL(qdev) ql_dump_all(qdev)
1608#else
1609#define QL_DUMP_ALL(qdev)
1610#endif
1611
1612#endif /* _QLGE_H_ */
Linux kernel - Deliverables
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