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c4e84bde RM |
1 | /* |
2 | * QLogic QLA41xx NIC HBA Driver | |
3 | * Copyright (c) 2003-2006 QLogic Corporation | |
4 | * | |
5 | * See LICENSE.qlge for copyright and licensing details. | |
6 | */ | |
7 | #ifndef _QLGE_H_ | |
8 | #define _QLGE_H_ | |
9 | ||
a6b7a407 | 10 | #include <linux/interrupt.h> |
c4e84bde RM |
11 | #include <linux/pci.h> |
12 | #include <linux/netdevice.h> | |
86aaf9ad | 13 | #include <linux/rtnetlink.h> |
18c49b91 | 14 | #include <linux/if_vlan.h> |
c4e84bde RM |
15 | |
16 | /* | |
17 | * General definitions... | |
18 | */ | |
19 | #define DRV_NAME "qlge" | |
20 | #define DRV_STRING "QLogic 10 Gigabit PCI-E Ethernet Driver " | |
b4e4fe84 | 21 | #define DRV_VERSION "v1.00.00.29.00.00-01" |
c4e84bde | 22 | |
88c55e3c RM |
23 | #define WQ_ADDR_ALIGN 0x3 /* 4 byte alignment */ |
24 | ||
c4e84bde | 25 | #define QLGE_VENDOR_ID 0x1077 |
b0c2aadf | 26 | #define QLGE_DEVICE_ID_8012 0x8012 |
cdca8d02 | 27 | #define QLGE_DEVICE_ID_8000 0x8000 |
683d46a9 RM |
28 | #define MAX_CPUS 8 |
29 | #define MAX_TX_RINGS MAX_CPUS | |
30 | #define MAX_RX_RINGS ((MAX_CPUS * 2) + 1) | |
c4e84bde RM |
31 | |
32 | #define NUM_TX_RING_ENTRIES 256 | |
33 | #define NUM_RX_RING_ENTRIES 256 | |
34 | ||
35 | #define NUM_SMALL_BUFFERS 512 | |
36 | #define NUM_LARGE_BUFFERS 512 | |
b8facca0 RM |
37 | #define DB_PAGE_SIZE 4096 |
38 | ||
39 | /* Calculate the number of (4k) pages required to | |
40 | * contain a buffer queue of the given length. | |
41 | */ | |
42 | #define MAX_DB_PAGES_PER_BQ(x) \ | |
43 | (((x * sizeof(u64)) / DB_PAGE_SIZE) + \ | |
44 | (((x * sizeof(u64)) % DB_PAGE_SIZE) ? 1 : 0)) | |
c4e84bde | 45 | |
b8facca0 RM |
46 | #define RX_RING_SHADOW_SPACE (sizeof(u64) + \ |
47 | MAX_DB_PAGES_PER_BQ(NUM_SMALL_BUFFERS) * sizeof(u64) + \ | |
48 | MAX_DB_PAGES_PER_BQ(NUM_LARGE_BUFFERS) * sizeof(u64)) | |
7c734359 RM |
49 | #define LARGE_BUFFER_MAX_SIZE 8192 |
50 | #define LARGE_BUFFER_MIN_SIZE 2048 | |
c4e84bde | 51 | |
683d46a9 | 52 | #define MAX_CQ 128 |
c4e84bde RM |
53 | #define DFLT_COALESCE_WAIT 100 /* 100 usec wait for coalescing */ |
54 | #define MAX_INTER_FRAME_WAIT 10 /* 10 usec max interframe-wait for coalescing */ | |
55 | #define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2) | |
56 | #define UDELAY_COUNT 3 | |
d2ba4986 | 57 | #define UDELAY_DELAY 100 |
c4e84bde RM |
58 | |
59 | ||
60 | #define TX_DESC_PER_IOCB 8 | |
61 | /* The maximum number of frags we handle is based | |
62 | * on PAGE_SIZE... | |
63 | */ | |
64 | #if (PAGE_SHIFT == 12) || (PAGE_SHIFT == 13) /* 4k & 8k pages */ | |
65 | #define TX_DESC_PER_OAL ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2) | |
48501371 | 66 | #else /* all other page sizes */ |
c4e84bde RM |
67 | #define TX_DESC_PER_OAL 0 |
68 | #endif | |
69 | ||
b87babeb RM |
70 | /* Word shifting for converting 64-bit |
71 | * address to a series of 16-bit words. | |
72 | * This is used for some MPI firmware | |
73 | * mailbox commands. | |
74 | */ | |
75 | #define LSW(x) ((u16)(x)) | |
76 | #define MSW(x) ((u16)((u32)(x) >> 16)) | |
77 | #define LSD(x) ((u32)((u64)(x))) | |
78 | #define MSD(x) ((u32)((((u64)(x)) >> 32))) | |
79 | ||
e4552f51 RM |
80 | /* MPI test register definitions. This register |
81 | * is used for determining alternate NIC function's | |
82 | * PCI->func number. | |
83 | */ | |
84 | enum { | |
85 | MPI_TEST_FUNC_PORT_CFG = 0x1002, | |
b87babeb RM |
86 | MPI_TEST_FUNC_PRB_CTL = 0x100e, |
87 | MPI_TEST_FUNC_PRB_EN = 0x18a20000, | |
88 | MPI_TEST_FUNC_RST_STS = 0x100a, | |
89 | MPI_TEST_FUNC_RST_FRC = 0x00000003, | |
90 | MPI_TEST_NIC_FUNC_MASK = 0x00000007, | |
91 | MPI_TEST_NIC1_FUNCTION_ENABLE = (1 << 0), | |
92 | MPI_TEST_NIC1_FUNCTION_MASK = 0x0000000e, | |
e4552f51 | 93 | MPI_TEST_NIC1_FUNC_SHIFT = 1, |
b87babeb RM |
94 | MPI_TEST_NIC2_FUNCTION_ENABLE = (1 << 4), |
95 | MPI_TEST_NIC2_FUNCTION_MASK = 0x000000e0, | |
e4552f51 | 96 | MPI_TEST_NIC2_FUNC_SHIFT = 5, |
b87babeb RM |
97 | MPI_TEST_FC1_FUNCTION_ENABLE = (1 << 8), |
98 | MPI_TEST_FC1_FUNCTION_MASK = 0x00000e00, | |
99 | MPI_TEST_FC1_FUNCTION_SHIFT = 9, | |
100 | MPI_TEST_FC2_FUNCTION_ENABLE = (1 << 12), | |
101 | MPI_TEST_FC2_FUNCTION_MASK = 0x0000e000, | |
102 | MPI_TEST_FC2_FUNCTION_SHIFT = 13, | |
103 | ||
104 | MPI_NIC_READ = 0x00000000, | |
105 | MPI_NIC_REG_BLOCK = 0x00020000, | |
106 | MPI_NIC_FUNCTION_SHIFT = 6, | |
e4552f51 RM |
107 | }; |
108 | ||
c4e84bde RM |
109 | /* |
110 | * Processor Address Register (PROC_ADDR) bit definitions. | |
111 | */ | |
112 | enum { | |
113 | ||
114 | /* Misc. stuff */ | |
115 | MAILBOX_COUNT = 16, | |
da039451 | 116 | MAILBOX_TIMEOUT = 5, |
c4e84bde RM |
117 | |
118 | PROC_ADDR_RDY = (1 << 31), | |
119 | PROC_ADDR_R = (1 << 30), | |
120 | PROC_ADDR_ERR = (1 << 29), | |
121 | PROC_ADDR_DA = (1 << 28), | |
122 | PROC_ADDR_FUNC0_MBI = 0x00001180, | |
123 | PROC_ADDR_FUNC0_MBO = (PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT), | |
124 | PROC_ADDR_FUNC0_CTL = 0x000011a1, | |
125 | PROC_ADDR_FUNC2_MBI = 0x00001280, | |
126 | PROC_ADDR_FUNC2_MBO = (PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT), | |
127 | PROC_ADDR_FUNC2_CTL = 0x000012a1, | |
128 | PROC_ADDR_MPI_RISC = 0x00000000, | |
129 | PROC_ADDR_MDE = 0x00010000, | |
130 | PROC_ADDR_REGBLOCK = 0x00020000, | |
131 | PROC_ADDR_RISC_REG = 0x00030000, | |
132 | }; | |
133 | ||
134 | /* | |
135 | * System Register (SYS) bit definitions. | |
136 | */ | |
137 | enum { | |
138 | SYS_EFE = (1 << 0), | |
139 | SYS_FAE = (1 << 1), | |
140 | SYS_MDC = (1 << 2), | |
141 | SYS_DST = (1 << 3), | |
142 | SYS_DWC = (1 << 4), | |
143 | SYS_EVW = (1 << 5), | |
144 | SYS_OMP_DLY_MASK = 0x3f000000, | |
145 | /* | |
146 | * There are no values defined as of edit #15. | |
147 | */ | |
148 | SYS_ODI = (1 << 14), | |
149 | }; | |
150 | ||
151 | /* | |
152 | * Reset/Failover Register (RST_FO) bit definitions. | |
153 | */ | |
154 | enum { | |
155 | RST_FO_TFO = (1 << 0), | |
156 | RST_FO_RR_MASK = 0x00060000, | |
157 | RST_FO_RR_CQ_CAM = 0x00000000, | |
d799bbfb RM |
158 | RST_FO_RR_DROP = 0x00000002, |
159 | RST_FO_RR_DQ = 0x00000004, | |
160 | RST_FO_RR_RCV_FUNC_CQ = 0x00000006, | |
c4e84bde RM |
161 | RST_FO_FRB = (1 << 12), |
162 | RST_FO_MOP = (1 << 13), | |
163 | RST_FO_REG = (1 << 14), | |
164 | RST_FO_FR = (1 << 15), | |
165 | }; | |
166 | ||
167 | /* | |
168 | * Function Specific Control Register (FSC) bit definitions. | |
169 | */ | |
170 | enum { | |
171 | FSC_DBRST_MASK = 0x00070000, | |
172 | FSC_DBRST_256 = 0x00000000, | |
173 | FSC_DBRST_512 = 0x00000001, | |
174 | FSC_DBRST_768 = 0x00000002, | |
175 | FSC_DBRST_1024 = 0x00000003, | |
176 | FSC_DBL_MASK = 0x00180000, | |
177 | FSC_DBL_DBRST = 0x00000000, | |
178 | FSC_DBL_MAX_PLD = 0x00000008, | |
179 | FSC_DBL_MAX_BRST = 0x00000010, | |
180 | FSC_DBL_128_BYTES = 0x00000018, | |
181 | FSC_EC = (1 << 5), | |
182 | FSC_EPC_MASK = 0x00c00000, | |
183 | FSC_EPC_INBOUND = (1 << 6), | |
184 | FSC_EPC_OUTBOUND = (1 << 7), | |
185 | FSC_VM_PAGESIZE_MASK = 0x07000000, | |
186 | FSC_VM_PAGE_2K = 0x00000100, | |
187 | FSC_VM_PAGE_4K = 0x00000200, | |
188 | FSC_VM_PAGE_8K = 0x00000300, | |
189 | FSC_VM_PAGE_64K = 0x00000600, | |
190 | FSC_SH = (1 << 11), | |
191 | FSC_DSB = (1 << 12), | |
192 | FSC_STE = (1 << 13), | |
193 | FSC_FE = (1 << 15), | |
194 | }; | |
195 | ||
196 | /* | |
197 | * Host Command Status Register (CSR) bit definitions. | |
198 | */ | |
199 | enum { | |
200 | CSR_ERR_STS_MASK = 0x0000003f, | |
201 | /* | |
202 | * There are no valued defined as of edit #15. | |
203 | */ | |
204 | CSR_RR = (1 << 8), | |
205 | CSR_HRI = (1 << 9), | |
206 | CSR_RP = (1 << 10), | |
207 | CSR_CMD_PARM_SHIFT = 22, | |
208 | CSR_CMD_NOP = 0x00000000, | |
b82808b7 | 209 | CSR_CMD_SET_RST = 0x10000000, |
c4e84bde RM |
210 | CSR_CMD_CLR_RST = 0x20000000, |
211 | CSR_CMD_SET_PAUSE = 0x30000000, | |
212 | CSR_CMD_CLR_PAUSE = 0x40000000, | |
213 | CSR_CMD_SET_H2R_INT = 0x50000000, | |
214 | CSR_CMD_CLR_H2R_INT = 0x60000000, | |
215 | CSR_CMD_PAR_EN = 0x70000000, | |
216 | CSR_CMD_SET_BAD_PAR = 0x80000000, | |
217 | CSR_CMD_CLR_BAD_PAR = 0x90000000, | |
218 | CSR_CMD_CLR_R2PCI_INT = 0xa0000000, | |
219 | }; | |
220 | ||
221 | /* | |
222 | * Configuration Register (CFG) bit definitions. | |
223 | */ | |
224 | enum { | |
225 | CFG_LRQ = (1 << 0), | |
226 | CFG_DRQ = (1 << 1), | |
227 | CFG_LR = (1 << 2), | |
228 | CFG_DR = (1 << 3), | |
229 | CFG_LE = (1 << 5), | |
230 | CFG_LCQ = (1 << 6), | |
231 | CFG_DCQ = (1 << 7), | |
232 | CFG_Q_SHIFT = 8, | |
233 | CFG_Q_MASK = 0x7f000000, | |
234 | }; | |
235 | ||
236 | /* | |
237 | * Status Register (STS) bit definitions. | |
238 | */ | |
239 | enum { | |
240 | STS_FE = (1 << 0), | |
241 | STS_PI = (1 << 1), | |
242 | STS_PL0 = (1 << 2), | |
243 | STS_PL1 = (1 << 3), | |
244 | STS_PI0 = (1 << 4), | |
245 | STS_PI1 = (1 << 5), | |
246 | STS_FUNC_ID_MASK = 0x000000c0, | |
247 | STS_FUNC_ID_SHIFT = 6, | |
248 | STS_F0E = (1 << 8), | |
249 | STS_F1E = (1 << 9), | |
250 | STS_F2E = (1 << 10), | |
251 | STS_F3E = (1 << 11), | |
252 | STS_NFE = (1 << 12), | |
253 | }; | |
254 | ||
255 | /* | |
256 | * Interrupt Enable Register (INTR_EN) bit definitions. | |
257 | */ | |
258 | enum { | |
259 | INTR_EN_INTR_MASK = 0x007f0000, | |
260 | INTR_EN_TYPE_MASK = 0x03000000, | |
261 | INTR_EN_TYPE_ENABLE = 0x00000100, | |
262 | INTR_EN_TYPE_DISABLE = 0x00000200, | |
263 | INTR_EN_TYPE_READ = 0x00000300, | |
264 | INTR_EN_IHD = (1 << 13), | |
265 | INTR_EN_IHD_MASK = (INTR_EN_IHD << 16), | |
266 | INTR_EN_EI = (1 << 14), | |
267 | INTR_EN_EN = (1 << 15), | |
268 | }; | |
269 | ||
270 | /* | |
271 | * Interrupt Mask Register (INTR_MASK) bit definitions. | |
272 | */ | |
273 | enum { | |
274 | INTR_MASK_PI = (1 << 0), | |
275 | INTR_MASK_HL0 = (1 << 1), | |
276 | INTR_MASK_LH0 = (1 << 2), | |
277 | INTR_MASK_HL1 = (1 << 3), | |
278 | INTR_MASK_LH1 = (1 << 4), | |
279 | INTR_MASK_SE = (1 << 5), | |
280 | INTR_MASK_LSC = (1 << 6), | |
281 | INTR_MASK_MC = (1 << 7), | |
282 | INTR_MASK_LINK_IRQS = INTR_MASK_LSC | INTR_MASK_SE | INTR_MASK_MC, | |
283 | }; | |
284 | ||
285 | /* | |
286 | * Register (REV_ID) bit definitions. | |
287 | */ | |
288 | enum { | |
289 | REV_ID_MASK = 0x0000000f, | |
290 | REV_ID_NICROLL_SHIFT = 0, | |
291 | REV_ID_NICREV_SHIFT = 4, | |
292 | REV_ID_XGROLL_SHIFT = 8, | |
293 | REV_ID_XGREV_SHIFT = 12, | |
294 | REV_ID_CHIPREV_SHIFT = 28, | |
295 | }; | |
296 | ||
297 | /* | |
298 | * Force ECC Error Register (FRC_ECC_ERR) bit definitions. | |
299 | */ | |
300 | enum { | |
301 | FRC_ECC_ERR_VW = (1 << 12), | |
302 | FRC_ECC_ERR_VB = (1 << 13), | |
303 | FRC_ECC_ERR_NI = (1 << 14), | |
304 | FRC_ECC_ERR_NO = (1 << 15), | |
305 | FRC_ECC_PFE_SHIFT = 16, | |
306 | FRC_ECC_ERR_DO = (1 << 18), | |
307 | FRC_ECC_P14 = (1 << 19), | |
308 | }; | |
309 | ||
310 | /* | |
311 | * Error Status Register (ERR_STS) bit definitions. | |
312 | */ | |
313 | enum { | |
314 | ERR_STS_NOF = (1 << 0), | |
315 | ERR_STS_NIF = (1 << 1), | |
316 | ERR_STS_DRP = (1 << 2), | |
317 | ERR_STS_XGP = (1 << 3), | |
318 | ERR_STS_FOU = (1 << 4), | |
319 | ERR_STS_FOC = (1 << 5), | |
320 | ERR_STS_FOF = (1 << 6), | |
321 | ERR_STS_FIU = (1 << 7), | |
322 | ERR_STS_FIC = (1 << 8), | |
323 | ERR_STS_FIF = (1 << 9), | |
324 | ERR_STS_MOF = (1 << 10), | |
325 | ERR_STS_TA = (1 << 11), | |
326 | ERR_STS_MA = (1 << 12), | |
327 | ERR_STS_MPE = (1 << 13), | |
328 | ERR_STS_SCE = (1 << 14), | |
329 | ERR_STS_STE = (1 << 15), | |
330 | ERR_STS_FOW = (1 << 16), | |
331 | ERR_STS_UE = (1 << 17), | |
332 | ERR_STS_MCH = (1 << 26), | |
333 | ERR_STS_LOC_SHIFT = 27, | |
334 | }; | |
335 | ||
336 | /* | |
337 | * RAM Debug Address Register (RAM_DBG_ADDR) bit definitions. | |
338 | */ | |
339 | enum { | |
340 | RAM_DBG_ADDR_FW = (1 << 30), | |
341 | RAM_DBG_ADDR_FR = (1 << 31), | |
342 | }; | |
343 | ||
344 | /* | |
345 | * Semaphore Register (SEM) bit definitions. | |
346 | */ | |
347 | enum { | |
348 | /* | |
349 | * Example: | |
350 | * reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT) | |
351 | */ | |
352 | SEM_CLEAR = 0, | |
353 | SEM_SET = 1, | |
354 | SEM_FORCE = 3, | |
355 | SEM_XGMAC0_SHIFT = 0, | |
356 | SEM_XGMAC1_SHIFT = 2, | |
357 | SEM_ICB_SHIFT = 4, | |
358 | SEM_MAC_ADDR_SHIFT = 6, | |
359 | SEM_FLASH_SHIFT = 8, | |
360 | SEM_PROBE_SHIFT = 10, | |
361 | SEM_RT_IDX_SHIFT = 12, | |
362 | SEM_PROC_REG_SHIFT = 14, | |
363 | SEM_XGMAC0_MASK = 0x00030000, | |
364 | SEM_XGMAC1_MASK = 0x000c0000, | |
365 | SEM_ICB_MASK = 0x00300000, | |
366 | SEM_MAC_ADDR_MASK = 0x00c00000, | |
367 | SEM_FLASH_MASK = 0x03000000, | |
368 | SEM_PROBE_MASK = 0x0c000000, | |
369 | SEM_RT_IDX_MASK = 0x30000000, | |
370 | SEM_PROC_REG_MASK = 0xc0000000, | |
371 | }; | |
372 | ||
373 | /* | |
374 | * 10G MAC Address Register (XGMAC_ADDR) bit definitions. | |
375 | */ | |
376 | enum { | |
377 | XGMAC_ADDR_RDY = (1 << 31), | |
378 | XGMAC_ADDR_R = (1 << 30), | |
379 | XGMAC_ADDR_XME = (1 << 29), | |
380 | ||
381 | /* XGMAC control registers */ | |
382 | PAUSE_SRC_LO = 0x00000100, | |
383 | PAUSE_SRC_HI = 0x00000104, | |
384 | GLOBAL_CFG = 0x00000108, | |
385 | GLOBAL_CFG_RESET = (1 << 0), | |
386 | GLOBAL_CFG_JUMBO = (1 << 6), | |
387 | GLOBAL_CFG_TX_STAT_EN = (1 << 10), | |
388 | GLOBAL_CFG_RX_STAT_EN = (1 << 11), | |
389 | TX_CFG = 0x0000010c, | |
390 | TX_CFG_RESET = (1 << 0), | |
391 | TX_CFG_EN = (1 << 1), | |
392 | TX_CFG_PREAM = (1 << 2), | |
393 | RX_CFG = 0x00000110, | |
394 | RX_CFG_RESET = (1 << 0), | |
395 | RX_CFG_EN = (1 << 1), | |
396 | RX_CFG_PREAM = (1 << 2), | |
397 | FLOW_CTL = 0x0000011c, | |
398 | PAUSE_OPCODE = 0x00000120, | |
399 | PAUSE_TIMER = 0x00000124, | |
400 | PAUSE_FRM_DEST_LO = 0x00000128, | |
401 | PAUSE_FRM_DEST_HI = 0x0000012c, | |
402 | MAC_TX_PARAMS = 0x00000134, | |
403 | MAC_TX_PARAMS_JUMBO = (1 << 31), | |
404 | MAC_TX_PARAMS_SIZE_SHIFT = 16, | |
405 | MAC_RX_PARAMS = 0x00000138, | |
406 | MAC_SYS_INT = 0x00000144, | |
407 | MAC_SYS_INT_MASK = 0x00000148, | |
408 | MAC_MGMT_INT = 0x0000014c, | |
409 | MAC_MGMT_IN_MASK = 0x00000150, | |
410 | EXT_ARB_MODE = 0x000001fc, | |
411 | ||
412 | /* XGMAC TX statistics registers */ | |
413 | TX_PKTS = 0x00000200, | |
414 | TX_BYTES = 0x00000208, | |
415 | TX_MCAST_PKTS = 0x00000210, | |
416 | TX_BCAST_PKTS = 0x00000218, | |
417 | TX_UCAST_PKTS = 0x00000220, | |
418 | TX_CTL_PKTS = 0x00000228, | |
419 | TX_PAUSE_PKTS = 0x00000230, | |
420 | TX_64_PKT = 0x00000238, | |
421 | TX_65_TO_127_PKT = 0x00000240, | |
422 | TX_128_TO_255_PKT = 0x00000248, | |
423 | TX_256_511_PKT = 0x00000250, | |
424 | TX_512_TO_1023_PKT = 0x00000258, | |
425 | TX_1024_TO_1518_PKT = 0x00000260, | |
426 | TX_1519_TO_MAX_PKT = 0x00000268, | |
427 | TX_UNDERSIZE_PKT = 0x00000270, | |
428 | TX_OVERSIZE_PKT = 0x00000278, | |
429 | ||
430 | /* XGMAC statistics control registers */ | |
431 | RX_HALF_FULL_DET = 0x000002a0, | |
432 | TX_HALF_FULL_DET = 0x000002a4, | |
433 | RX_OVERFLOW_DET = 0x000002a8, | |
434 | TX_OVERFLOW_DET = 0x000002ac, | |
435 | RX_HALF_FULL_MASK = 0x000002b0, | |
436 | TX_HALF_FULL_MASK = 0x000002b4, | |
437 | RX_OVERFLOW_MASK = 0x000002b8, | |
438 | TX_OVERFLOW_MASK = 0x000002bc, | |
439 | STAT_CNT_CTL = 0x000002c0, | |
440 | STAT_CNT_CTL_CLEAR_TX = (1 << 0), | |
441 | STAT_CNT_CTL_CLEAR_RX = (1 << 1), | |
442 | AUX_RX_HALF_FULL_DET = 0x000002d0, | |
443 | AUX_TX_HALF_FULL_DET = 0x000002d4, | |
444 | AUX_RX_OVERFLOW_DET = 0x000002d8, | |
445 | AUX_TX_OVERFLOW_DET = 0x000002dc, | |
446 | AUX_RX_HALF_FULL_MASK = 0x000002f0, | |
447 | AUX_TX_HALF_FULL_MASK = 0x000002f4, | |
448 | AUX_RX_OVERFLOW_MASK = 0x000002f8, | |
449 | AUX_TX_OVERFLOW_MASK = 0x000002fc, | |
450 | ||
451 | /* XGMAC RX statistics registers */ | |
452 | RX_BYTES = 0x00000300, | |
453 | RX_BYTES_OK = 0x00000308, | |
454 | RX_PKTS = 0x00000310, | |
455 | RX_PKTS_OK = 0x00000318, | |
456 | RX_BCAST_PKTS = 0x00000320, | |
457 | RX_MCAST_PKTS = 0x00000328, | |
458 | RX_UCAST_PKTS = 0x00000330, | |
459 | RX_UNDERSIZE_PKTS = 0x00000338, | |
460 | RX_OVERSIZE_PKTS = 0x00000340, | |
461 | RX_JABBER_PKTS = 0x00000348, | |
462 | RX_UNDERSIZE_FCERR_PKTS = 0x00000350, | |
463 | RX_DROP_EVENTS = 0x00000358, | |
464 | RX_FCERR_PKTS = 0x00000360, | |
465 | RX_ALIGN_ERR = 0x00000368, | |
466 | RX_SYMBOL_ERR = 0x00000370, | |
467 | RX_MAC_ERR = 0x00000378, | |
468 | RX_CTL_PKTS = 0x00000380, | |
b82808b7 | 469 | RX_PAUSE_PKTS = 0x00000388, |
c4e84bde RM |
470 | RX_64_PKTS = 0x00000390, |
471 | RX_65_TO_127_PKTS = 0x00000398, | |
472 | RX_128_255_PKTS = 0x000003a0, | |
473 | RX_256_511_PKTS = 0x000003a8, | |
474 | RX_512_TO_1023_PKTS = 0x000003b0, | |
475 | RX_1024_TO_1518_PKTS = 0x000003b8, | |
476 | RX_1519_TO_MAX_PKTS = 0x000003c0, | |
477 | RX_LEN_ERR_PKTS = 0x000003c8, | |
478 | ||
479 | /* XGMAC MDIO control registers */ | |
480 | MDIO_TX_DATA = 0x00000400, | |
481 | MDIO_RX_DATA = 0x00000410, | |
482 | MDIO_CMD = 0x00000420, | |
483 | MDIO_PHY_ADDR = 0x00000430, | |
484 | MDIO_PORT = 0x00000440, | |
485 | MDIO_STATUS = 0x00000450, | |
486 | ||
b87babeb | 487 | XGMAC_REGISTER_END = 0x00000740, |
c4e84bde RM |
488 | }; |
489 | ||
490 | /* | |
491 | * Enhanced Transmission Schedule Registers (NIC_ETS,CNA_ETS) bit definitions. | |
492 | */ | |
493 | enum { | |
494 | ETS_QUEUE_SHIFT = 29, | |
495 | ETS_REF = (1 << 26), | |
496 | ETS_RS = (1 << 27), | |
497 | ETS_P = (1 << 28), | |
498 | ETS_FC_COS_SHIFT = 23, | |
499 | }; | |
500 | ||
501 | /* | |
502 | * Flash Address Register (FLASH_ADDR) bit definitions. | |
503 | */ | |
504 | enum { | |
505 | FLASH_ADDR_RDY = (1 << 31), | |
506 | FLASH_ADDR_R = (1 << 30), | |
507 | FLASH_ADDR_ERR = (1 << 29), | |
508 | }; | |
509 | ||
510 | /* | |
511 | * Stop CQ Processing Register (CQ_STOP) bit definitions. | |
512 | */ | |
513 | enum { | |
514 | CQ_STOP_QUEUE_MASK = (0x007f0000), | |
515 | CQ_STOP_TYPE_MASK = (0x03000000), | |
516 | CQ_STOP_TYPE_START = 0x00000100, | |
517 | CQ_STOP_TYPE_STOP = 0x00000200, | |
518 | CQ_STOP_TYPE_READ = 0x00000300, | |
519 | CQ_STOP_EN = (1 << 15), | |
520 | }; | |
521 | ||
522 | /* | |
523 | * MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions. | |
524 | */ | |
525 | enum { | |
526 | MAC_ADDR_IDX_SHIFT = 4, | |
527 | MAC_ADDR_TYPE_SHIFT = 16, | |
b87babeb | 528 | MAC_ADDR_TYPE_COUNT = 10, |
c4e84bde RM |
529 | MAC_ADDR_TYPE_MASK = 0x000f0000, |
530 | MAC_ADDR_TYPE_CAM_MAC = 0x00000000, | |
531 | MAC_ADDR_TYPE_MULTI_MAC = 0x00010000, | |
532 | MAC_ADDR_TYPE_VLAN = 0x00020000, | |
533 | MAC_ADDR_TYPE_MULTI_FLTR = 0x00030000, | |
534 | MAC_ADDR_TYPE_FC_MAC = 0x00040000, | |
535 | MAC_ADDR_TYPE_MGMT_MAC = 0x00050000, | |
536 | MAC_ADDR_TYPE_MGMT_VLAN = 0x00060000, | |
537 | MAC_ADDR_TYPE_MGMT_V4 = 0x00070000, | |
538 | MAC_ADDR_TYPE_MGMT_V6 = 0x00080000, | |
539 | MAC_ADDR_TYPE_MGMT_TU_DP = 0x00090000, | |
540 | MAC_ADDR_ADR = (1 << 25), | |
541 | MAC_ADDR_RS = (1 << 26), | |
542 | MAC_ADDR_E = (1 << 27), | |
543 | MAC_ADDR_MR = (1 << 30), | |
544 | MAC_ADDR_MW = (1 << 31), | |
545 | MAX_MULTICAST_ENTRIES = 32, | |
b87babeb RM |
546 | |
547 | /* Entry count and words per entry | |
548 | * for each address type in the filter. | |
549 | */ | |
550 | MAC_ADDR_MAX_CAM_ENTRIES = 512, | |
551 | MAC_ADDR_MAX_CAM_WCOUNT = 3, | |
552 | MAC_ADDR_MAX_MULTICAST_ENTRIES = 32, | |
553 | MAC_ADDR_MAX_MULTICAST_WCOUNT = 2, | |
554 | MAC_ADDR_MAX_VLAN_ENTRIES = 4096, | |
555 | MAC_ADDR_MAX_VLAN_WCOUNT = 1, | |
556 | MAC_ADDR_MAX_MCAST_FLTR_ENTRIES = 4096, | |
557 | MAC_ADDR_MAX_MCAST_FLTR_WCOUNT = 1, | |
558 | MAC_ADDR_MAX_FC_MAC_ENTRIES = 4, | |
559 | MAC_ADDR_MAX_FC_MAC_WCOUNT = 2, | |
560 | MAC_ADDR_MAX_MGMT_MAC_ENTRIES = 8, | |
561 | MAC_ADDR_MAX_MGMT_MAC_WCOUNT = 2, | |
562 | MAC_ADDR_MAX_MGMT_VLAN_ENTRIES = 16, | |
563 | MAC_ADDR_MAX_MGMT_VLAN_WCOUNT = 1, | |
564 | MAC_ADDR_MAX_MGMT_V4_ENTRIES = 4, | |
565 | MAC_ADDR_MAX_MGMT_V4_WCOUNT = 1, | |
566 | MAC_ADDR_MAX_MGMT_V6_ENTRIES = 4, | |
567 | MAC_ADDR_MAX_MGMT_V6_WCOUNT = 4, | |
568 | MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES = 4, | |
569 | MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT = 1, | |
c4e84bde RM |
570 | }; |
571 | ||
572 | /* | |
573 | * MAC Protocol Address Index Register (SPLT_HDR) bit definitions. | |
574 | */ | |
575 | enum { | |
576 | SPLT_HDR_EP = (1 << 31), | |
577 | }; | |
578 | ||
579 | /* | |
580 | * FCoE Receive Configuration Register (FC_RCV_CFG) bit definitions. | |
581 | */ | |
582 | enum { | |
583 | FC_RCV_CFG_ECT = (1 << 15), | |
584 | FC_RCV_CFG_DFH = (1 << 20), | |
585 | FC_RCV_CFG_DVF = (1 << 21), | |
586 | FC_RCV_CFG_RCE = (1 << 27), | |
587 | FC_RCV_CFG_RFE = (1 << 28), | |
588 | FC_RCV_CFG_TEE = (1 << 29), | |
589 | FC_RCV_CFG_TCE = (1 << 30), | |
590 | FC_RCV_CFG_TFE = (1 << 31), | |
591 | }; | |
592 | ||
593 | /* | |
594 | * NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions. | |
595 | */ | |
596 | enum { | |
597 | NIC_RCV_CFG_PPE = (1 << 0), | |
598 | NIC_RCV_CFG_VLAN_MASK = 0x00060000, | |
599 | NIC_RCV_CFG_VLAN_ALL = 0x00000000, | |
600 | NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002, | |
601 | NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004, | |
602 | NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006, | |
603 | NIC_RCV_CFG_RV = (1 << 3), | |
604 | NIC_RCV_CFG_DFQ_MASK = (0x7f000000), | |
605 | NIC_RCV_CFG_DFQ_SHIFT = 8, | |
606 | NIC_RCV_CFG_DFQ = 0, /* HARDCODE default queue to 0. */ | |
607 | }; | |
608 | ||
609 | /* | |
610 | * Mgmt Receive Configuration Register (MGMT_RCV_CFG) bit definitions. | |
611 | */ | |
612 | enum { | |
613 | MGMT_RCV_CFG_ARP = (1 << 0), | |
614 | MGMT_RCV_CFG_DHC = (1 << 1), | |
615 | MGMT_RCV_CFG_DHS = (1 << 2), | |
616 | MGMT_RCV_CFG_NP = (1 << 3), | |
617 | MGMT_RCV_CFG_I6N = (1 << 4), | |
618 | MGMT_RCV_CFG_I6R = (1 << 5), | |
619 | MGMT_RCV_CFG_DH6 = (1 << 6), | |
620 | MGMT_RCV_CFG_UD1 = (1 << 7), | |
621 | MGMT_RCV_CFG_UD0 = (1 << 8), | |
622 | MGMT_RCV_CFG_BCT = (1 << 9), | |
623 | MGMT_RCV_CFG_MCT = (1 << 10), | |
624 | MGMT_RCV_CFG_DM = (1 << 11), | |
625 | MGMT_RCV_CFG_RM = (1 << 12), | |
626 | MGMT_RCV_CFG_STL = (1 << 13), | |
627 | MGMT_RCV_CFG_VLAN_MASK = 0xc0000000, | |
628 | MGMT_RCV_CFG_VLAN_ALL = 0x00000000, | |
629 | MGMT_RCV_CFG_VLAN_MATCH_ONLY = 0x00004000, | |
630 | MGMT_RCV_CFG_VLAN_MATCH_AND_NON = 0x00008000, | |
631 | MGMT_RCV_CFG_VLAN_NONE_AND_NON = 0x0000c000, | |
632 | }; | |
633 | ||
634 | /* | |
635 | * Routing Index Register (RT_IDX) bit definitions. | |
636 | */ | |
637 | enum { | |
638 | RT_IDX_IDX_SHIFT = 8, | |
639 | RT_IDX_TYPE_MASK = 0x000f0000, | |
b87babeb | 640 | RT_IDX_TYPE_SHIFT = 16, |
c4e84bde RM |
641 | RT_IDX_TYPE_RT = 0x00000000, |
642 | RT_IDX_TYPE_RT_INV = 0x00010000, | |
643 | RT_IDX_TYPE_NICQ = 0x00020000, | |
644 | RT_IDX_TYPE_NICQ_INV = 0x00030000, | |
645 | RT_IDX_DST_MASK = 0x00700000, | |
646 | RT_IDX_DST_RSS = 0x00000000, | |
647 | RT_IDX_DST_CAM_Q = 0x00100000, | |
648 | RT_IDX_DST_COS_Q = 0x00200000, | |
649 | RT_IDX_DST_DFLT_Q = 0x00300000, | |
650 | RT_IDX_DST_DEST_Q = 0x00400000, | |
651 | RT_IDX_RS = (1 << 26), | |
652 | RT_IDX_E = (1 << 27), | |
653 | RT_IDX_MR = (1 << 30), | |
654 | RT_IDX_MW = (1 << 31), | |
655 | ||
656 | /* Nic Queue format - type 2 bits */ | |
657 | RT_IDX_BCAST = (1 << 0), | |
658 | RT_IDX_MCAST = (1 << 1), | |
659 | RT_IDX_MCAST_MATCH = (1 << 2), | |
660 | RT_IDX_MCAST_REG_MATCH = (1 << 3), | |
661 | RT_IDX_MCAST_HASH_MATCH = (1 << 4), | |
662 | RT_IDX_FC_MACH = (1 << 5), | |
663 | RT_IDX_ETH_FCOE = (1 << 6), | |
664 | RT_IDX_CAM_HIT = (1 << 7), | |
665 | RT_IDX_CAM_BIT0 = (1 << 8), | |
666 | RT_IDX_CAM_BIT1 = (1 << 9), | |
667 | RT_IDX_VLAN_TAG = (1 << 10), | |
668 | RT_IDX_VLAN_MATCH = (1 << 11), | |
669 | RT_IDX_VLAN_FILTER = (1 << 12), | |
670 | RT_IDX_ETH_SKIP1 = (1 << 13), | |
671 | RT_IDX_ETH_SKIP2 = (1 << 14), | |
672 | RT_IDX_BCAST_MCAST_MATCH = (1 << 15), | |
673 | RT_IDX_802_3 = (1 << 16), | |
674 | RT_IDX_LLDP = (1 << 17), | |
675 | RT_IDX_UNUSED018 = (1 << 18), | |
676 | RT_IDX_UNUSED019 = (1 << 19), | |
677 | RT_IDX_UNUSED20 = (1 << 20), | |
678 | RT_IDX_UNUSED21 = (1 << 21), | |
679 | RT_IDX_ERR = (1 << 22), | |
680 | RT_IDX_VALID = (1 << 23), | |
681 | RT_IDX_TU_CSUM_ERR = (1 << 24), | |
682 | RT_IDX_IP_CSUM_ERR = (1 << 25), | |
683 | RT_IDX_MAC_ERR = (1 << 26), | |
684 | RT_IDX_RSS_TCP6 = (1 << 27), | |
685 | RT_IDX_RSS_TCP4 = (1 << 28), | |
686 | RT_IDX_RSS_IPV6 = (1 << 29), | |
687 | RT_IDX_RSS_IPV4 = (1 << 30), | |
688 | RT_IDX_RSS_MATCH = (1 << 31), | |
689 | ||
690 | /* Hierarchy for the NIC Queue Mask */ | |
691 | RT_IDX_ALL_ERR_SLOT = 0, | |
692 | RT_IDX_MAC_ERR_SLOT = 0, | |
693 | RT_IDX_IP_CSUM_ERR_SLOT = 1, | |
694 | RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2, | |
695 | RT_IDX_BCAST_SLOT = 3, | |
696 | RT_IDX_MCAST_MATCH_SLOT = 4, | |
697 | RT_IDX_ALLMULTI_SLOT = 5, | |
698 | RT_IDX_UNUSED6_SLOT = 6, | |
699 | RT_IDX_UNUSED7_SLOT = 7, | |
700 | RT_IDX_RSS_MATCH_SLOT = 8, | |
701 | RT_IDX_RSS_IPV4_SLOT = 8, | |
702 | RT_IDX_RSS_IPV6_SLOT = 9, | |
703 | RT_IDX_RSS_TCP4_SLOT = 10, | |
704 | RT_IDX_RSS_TCP6_SLOT = 11, | |
705 | RT_IDX_CAM_HIT_SLOT = 12, | |
706 | RT_IDX_UNUSED013 = 13, | |
707 | RT_IDX_UNUSED014 = 14, | |
708 | RT_IDX_PROMISCUOUS_SLOT = 15, | |
b87babeb RM |
709 | RT_IDX_MAX_RT_SLOTS = 8, |
710 | RT_IDX_MAX_NIC_SLOTS = 16, | |
711 | }; | |
712 | ||
713 | /* | |
714 | * Serdes Address Register (XG_SERDES_ADDR) bit definitions. | |
715 | */ | |
716 | enum { | |
717 | XG_SERDES_ADDR_RDY = (1 << 31), | |
718 | XG_SERDES_ADDR_R = (1 << 30), | |
719 | ||
720 | XG_SERDES_ADDR_STS = 0x00001E06, | |
721 | XG_SERDES_ADDR_XFI1_PWR_UP = 0x00000005, | |
722 | XG_SERDES_ADDR_XFI2_PWR_UP = 0x0000000a, | |
723 | XG_SERDES_ADDR_XAUI_PWR_DOWN = 0x00000001, | |
724 | ||
725 | /* Serdes coredump definitions. */ | |
726 | XG_SERDES_XAUI_AN_START = 0x00000000, | |
727 | XG_SERDES_XAUI_AN_END = 0x00000034, | |
728 | XG_SERDES_XAUI_HSS_PCS_START = 0x00000800, | |
729 | XG_SERDES_XAUI_HSS_PCS_END = 0x0000880, | |
730 | XG_SERDES_XFI_AN_START = 0x00001000, | |
731 | XG_SERDES_XFI_AN_END = 0x00001034, | |
732 | XG_SERDES_XFI_TRAIN_START = 0x10001050, | |
733 | XG_SERDES_XFI_TRAIN_END = 0x1000107C, | |
734 | XG_SERDES_XFI_HSS_PCS_START = 0x00001800, | |
735 | XG_SERDES_XFI_HSS_PCS_END = 0x00001838, | |
736 | XG_SERDES_XFI_HSS_TX_START = 0x00001c00, | |
737 | XG_SERDES_XFI_HSS_TX_END = 0x00001c1f, | |
738 | XG_SERDES_XFI_HSS_RX_START = 0x00001c40, | |
739 | XG_SERDES_XFI_HSS_RX_END = 0x00001c5f, | |
740 | XG_SERDES_XFI_HSS_PLL_START = 0x00001e00, | |
741 | XG_SERDES_XFI_HSS_PLL_END = 0x00001e1f, | |
742 | }; | |
743 | ||
744 | /* | |
745 | * NIC Probe Mux Address Register (PRB_MX_ADDR) bit definitions. | |
746 | */ | |
747 | enum { | |
748 | PRB_MX_ADDR_ARE = (1 << 16), | |
749 | PRB_MX_ADDR_UP = (1 << 15), | |
750 | PRB_MX_ADDR_SWP = (1 << 14), | |
751 | ||
752 | /* Module select values. */ | |
753 | PRB_MX_ADDR_MAX_MODS = 21, | |
754 | PRB_MX_ADDR_MOD_SEL_SHIFT = 9, | |
755 | PRB_MX_ADDR_MOD_SEL_TBD = 0, | |
756 | PRB_MX_ADDR_MOD_SEL_IDE1 = 1, | |
757 | PRB_MX_ADDR_MOD_SEL_IDE2 = 2, | |
758 | PRB_MX_ADDR_MOD_SEL_FRB = 3, | |
759 | PRB_MX_ADDR_MOD_SEL_ODE1 = 4, | |
760 | PRB_MX_ADDR_MOD_SEL_ODE2 = 5, | |
761 | PRB_MX_ADDR_MOD_SEL_DA1 = 6, | |
762 | PRB_MX_ADDR_MOD_SEL_DA2 = 7, | |
763 | PRB_MX_ADDR_MOD_SEL_IMP1 = 8, | |
764 | PRB_MX_ADDR_MOD_SEL_IMP2 = 9, | |
765 | PRB_MX_ADDR_MOD_SEL_OMP1 = 10, | |
766 | PRB_MX_ADDR_MOD_SEL_OMP2 = 11, | |
767 | PRB_MX_ADDR_MOD_SEL_ORS1 = 12, | |
768 | PRB_MX_ADDR_MOD_SEL_ORS2 = 13, | |
769 | PRB_MX_ADDR_MOD_SEL_REG = 14, | |
770 | PRB_MX_ADDR_MOD_SEL_MAC1 = 16, | |
771 | PRB_MX_ADDR_MOD_SEL_MAC2 = 17, | |
772 | PRB_MX_ADDR_MOD_SEL_VQM1 = 18, | |
773 | PRB_MX_ADDR_MOD_SEL_VQM2 = 19, | |
774 | PRB_MX_ADDR_MOD_SEL_MOP = 20, | |
775 | /* Bit fields indicating which modules | |
776 | * are valid for each clock domain. | |
777 | */ | |
778 | PRB_MX_ADDR_VALID_SYS_MOD = 0x000f7ff7, | |
779 | PRB_MX_ADDR_VALID_PCI_MOD = 0x000040c1, | |
780 | PRB_MX_ADDR_VALID_XGM_MOD = 0x00037309, | |
781 | PRB_MX_ADDR_VALID_FC_MOD = 0x00003001, | |
782 | PRB_MX_ADDR_VALID_TOTAL = 34, | |
783 | ||
784 | /* Clock domain values. */ | |
785 | PRB_MX_ADDR_CLOCK_SHIFT = 6, | |
786 | PRB_MX_ADDR_SYS_CLOCK = 0, | |
787 | PRB_MX_ADDR_PCI_CLOCK = 2, | |
788 | PRB_MX_ADDR_FC_CLOCK = 5, | |
789 | PRB_MX_ADDR_XGM_CLOCK = 6, | |
790 | ||
791 | PRB_MX_ADDR_MAX_MUX = 64, | |
c4e84bde RM |
792 | }; |
793 | ||
794 | /* | |
795 | * Control Register Set Map | |
796 | */ | |
797 | enum { | |
798 | PROC_ADDR = 0, /* Use semaphore */ | |
799 | PROC_DATA = 0x04, /* Use semaphore */ | |
800 | SYS = 0x08, | |
801 | RST_FO = 0x0c, | |
802 | FSC = 0x10, | |
803 | CSR = 0x14, | |
804 | LED = 0x18, | |
805 | ICB_RID = 0x1c, /* Use semaphore */ | |
806 | ICB_L = 0x20, /* Use semaphore */ | |
807 | ICB_H = 0x24, /* Use semaphore */ | |
808 | CFG = 0x28, | |
809 | BIOS_ADDR = 0x2c, | |
810 | STS = 0x30, | |
811 | INTR_EN = 0x34, | |
812 | INTR_MASK = 0x38, | |
813 | ISR1 = 0x3c, | |
814 | ISR2 = 0x40, | |
815 | ISR3 = 0x44, | |
816 | ISR4 = 0x48, | |
817 | REV_ID = 0x4c, | |
818 | FRC_ECC_ERR = 0x50, | |
819 | ERR_STS = 0x54, | |
820 | RAM_DBG_ADDR = 0x58, | |
821 | RAM_DBG_DATA = 0x5c, | |
822 | ECC_ERR_CNT = 0x60, | |
823 | SEM = 0x64, | |
824 | GPIO_1 = 0x68, /* Use semaphore */ | |
825 | GPIO_2 = 0x6c, /* Use semaphore */ | |
826 | GPIO_3 = 0x70, /* Use semaphore */ | |
827 | RSVD2 = 0x74, | |
828 | XGMAC_ADDR = 0x78, /* Use semaphore */ | |
829 | XGMAC_DATA = 0x7c, /* Use semaphore */ | |
830 | NIC_ETS = 0x80, | |
831 | CNA_ETS = 0x84, | |
832 | FLASH_ADDR = 0x88, /* Use semaphore */ | |
833 | FLASH_DATA = 0x8c, /* Use semaphore */ | |
834 | CQ_STOP = 0x90, | |
835 | PAGE_TBL_RID = 0x94, | |
836 | WQ_PAGE_TBL_LO = 0x98, | |
837 | WQ_PAGE_TBL_HI = 0x9c, | |
838 | CQ_PAGE_TBL_LO = 0xa0, | |
839 | CQ_PAGE_TBL_HI = 0xa4, | |
840 | MAC_ADDR_IDX = 0xa8, /* Use semaphore */ | |
841 | MAC_ADDR_DATA = 0xac, /* Use semaphore */ | |
842 | COS_DFLT_CQ1 = 0xb0, | |
843 | COS_DFLT_CQ2 = 0xb4, | |
844 | ETYPE_SKIP1 = 0xb8, | |
845 | ETYPE_SKIP2 = 0xbc, | |
846 | SPLT_HDR = 0xc0, | |
847 | FC_PAUSE_THRES = 0xc4, | |
848 | NIC_PAUSE_THRES = 0xc8, | |
849 | FC_ETHERTYPE = 0xcc, | |
850 | FC_RCV_CFG = 0xd0, | |
851 | NIC_RCV_CFG = 0xd4, | |
852 | FC_COS_TAGS = 0xd8, | |
853 | NIC_COS_TAGS = 0xdc, | |
854 | MGMT_RCV_CFG = 0xe0, | |
855 | RT_IDX = 0xe4, | |
856 | RT_DATA = 0xe8, | |
857 | RSVD7 = 0xec, | |
858 | XG_SERDES_ADDR = 0xf0, | |
859 | XG_SERDES_DATA = 0xf4, | |
860 | PRB_MX_ADDR = 0xf8, /* Use semaphore */ | |
861 | PRB_MX_DATA = 0xfc, /* Use semaphore */ | |
862 | }; | |
863 | ||
572c526f RM |
864 | #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
865 | #define SMALL_BUFFER_SIZE 256 | |
866 | #define SMALL_BUF_MAP_SIZE SMALL_BUFFER_SIZE | |
867 | #define SPLT_SETTING FSC_DBRST_1024 | |
868 | #define SPLT_LEN 0 | |
869 | #define QLGE_SB_PAD 0 | |
870 | #else | |
871 | #define SMALL_BUFFER_SIZE 512 | |
872 | #define SMALL_BUF_MAP_SIZE (SMALL_BUFFER_SIZE / 2) | |
873 | #define SPLT_SETTING FSC_SH | |
874 | #define SPLT_LEN (SPLT_HDR_EP | \ | |
875 | min(SMALL_BUF_MAP_SIZE, 1023)) | |
876 | #define QLGE_SB_PAD 32 | |
877 | #endif | |
878 | ||
c4e84bde RM |
879 | /* |
880 | * CAM output format. | |
881 | */ | |
882 | enum { | |
883 | CAM_OUT_ROUTE_FC = 0, | |
884 | CAM_OUT_ROUTE_NIC = 1, | |
885 | CAM_OUT_FUNC_SHIFT = 2, | |
886 | CAM_OUT_RV = (1 << 4), | |
887 | CAM_OUT_SH = (1 << 15), | |
888 | CAM_OUT_CQ_ID_SHIFT = 5, | |
889 | }; | |
890 | ||
891 | /* | |
892 | * Mailbox definitions | |
893 | */ | |
894 | enum { | |
895 | /* Asynchronous Event Notifications */ | |
896 | AEN_SYS_ERR = 0x00008002, | |
897 | AEN_LINK_UP = 0x00008011, | |
898 | AEN_LINK_DOWN = 0x00008012, | |
899 | AEN_IDC_CMPLT = 0x00008100, | |
900 | AEN_IDC_REQ = 0x00008101, | |
b82808b7 RM |
901 | AEN_IDC_EXT = 0x00008102, |
902 | AEN_DCBX_CHG = 0x00008110, | |
903 | AEN_AEN_LOST = 0x00008120, | |
904 | AEN_AEN_SFP_IN = 0x00008130, | |
905 | AEN_AEN_SFP_OUT = 0x00008131, | |
c4e84bde RM |
906 | AEN_FW_INIT_DONE = 0x00008400, |
907 | AEN_FW_INIT_FAIL = 0x00008401, | |
908 | ||
909 | /* Mailbox Command Opcodes. */ | |
910 | MB_CMD_NOP = 0x00000000, | |
911 | MB_CMD_EX_FW = 0x00000002, | |
912 | MB_CMD_MB_TEST = 0x00000006, | |
913 | MB_CMD_CSUM_TEST = 0x00000007, /* Verify Checksum */ | |
914 | MB_CMD_ABOUT_FW = 0x00000008, | |
b82808b7 | 915 | MB_CMD_COPY_RISC_RAM = 0x0000000a, |
c4e84bde RM |
916 | MB_CMD_LOAD_RISC_RAM = 0x0000000b, |
917 | MB_CMD_DUMP_RISC_RAM = 0x0000000c, | |
918 | MB_CMD_WRITE_RAM = 0x0000000d, | |
b82808b7 | 919 | MB_CMD_INIT_RISC_RAM = 0x0000000e, |
c4e84bde RM |
920 | MB_CMD_READ_RAM = 0x0000000f, |
921 | MB_CMD_STOP_FW = 0x00000014, | |
922 | MB_CMD_MAKE_SYS_ERR = 0x0000002a, | |
b82808b7 RM |
923 | MB_CMD_WRITE_SFP = 0x00000030, |
924 | MB_CMD_READ_SFP = 0x00000031, | |
c4e84bde | 925 | MB_CMD_INIT_FW = 0x00000060, |
b82808b7 | 926 | MB_CMD_GET_IFCB = 0x00000061, |
c4e84bde RM |
927 | MB_CMD_GET_FW_STATE = 0x00000069, |
928 | MB_CMD_IDC_REQ = 0x00000100, /* Inter-Driver Communication */ | |
929 | MB_CMD_IDC_ACK = 0x00000101, /* Inter-Driver Communication */ | |
930 | MB_CMD_SET_WOL_MODE = 0x00000110, /* Wake On Lan */ | |
b82808b7 RM |
931 | MB_WOL_DISABLE = 0, |
932 | MB_WOL_MAGIC_PKT = (1 << 1), | |
933 | MB_WOL_FLTR = (1 << 2), | |
934 | MB_WOL_UCAST = (1 << 3), | |
935 | MB_WOL_MCAST = (1 << 4), | |
936 | MB_WOL_BCAST = (1 << 5), | |
937 | MB_WOL_LINK_UP = (1 << 6), | |
938 | MB_WOL_LINK_DOWN = (1 << 7), | |
bc083ce9 | 939 | MB_WOL_MODE_ON = (1 << 16), /* Wake on Lan Mode on */ |
c4e84bde | 940 | MB_CMD_SET_WOL_FLTR = 0x00000111, /* Wake On Lan Filter */ |
b82808b7 | 941 | MB_CMD_CLEAR_WOL_FLTR = 0x00000112, /* Wake On Lan Filter */ |
c4e84bde | 942 | MB_CMD_SET_WOL_MAGIC = 0x00000113, /* Wake On Lan Magic Packet */ |
b82808b7 RM |
943 | MB_CMD_CLEAR_WOL_MAGIC = 0x00000114,/* Wake On Lan Magic Packet */ |
944 | MB_CMD_SET_WOL_IMMED = 0x00000115, | |
c4e84bde RM |
945 | MB_CMD_PORT_RESET = 0x00000120, |
946 | MB_CMD_SET_PORT_CFG = 0x00000122, | |
947 | MB_CMD_GET_PORT_CFG = 0x00000123, | |
b82808b7 | 948 | MB_CMD_GET_LINK_STS = 0x00000124, |
d8eb59dc RM |
949 | MB_CMD_SET_LED_CFG = 0x00000125, /* Set LED Configuration Register */ |
950 | QL_LED_BLINK = 0x03e803e8, | |
951 | MB_CMD_GET_LED_CFG = 0x00000126, /* Get LED Configuration Register */ | |
84087f4d RM |
952 | MB_CMD_SET_MGMNT_TFK_CTL = 0x00000160, /* Set Mgmnt Traffic Control */ |
953 | MB_SET_MPI_TFK_STOP = (1 << 0), | |
954 | MB_SET_MPI_TFK_RESUME = (1 << 1), | |
955 | MB_CMD_GET_MGMNT_TFK_CTL = 0x00000161, /* Get Mgmnt Traffic Control */ | |
956 | MB_GET_MPI_TFK_STOPPED = (1 << 0), | |
957 | MB_GET_MPI_TFK_FIFO_EMPTY = (1 << 1), | |
1e34e307 RM |
958 | /* Sub-commands for IDC request. |
959 | * This describes the reason for the | |
960 | * IDC request. | |
961 | */ | |
962 | MB_CMD_IOP_NONE = 0x0000, | |
963 | MB_CMD_IOP_PREP_UPDATE_MPI = 0x0001, | |
964 | MB_CMD_IOP_COMP_UPDATE_MPI = 0x0002, | |
965 | MB_CMD_IOP_PREP_LINK_DOWN = 0x0010, | |
966 | MB_CMD_IOP_DVR_START = 0x0100, | |
967 | MB_CMD_IOP_FLASH_ACC = 0x0101, | |
968 | MB_CMD_IOP_RESTART_MPI = 0x0102, | |
969 | MB_CMD_IOP_CORE_DUMP_MPI = 0x0103, | |
c4e84bde RM |
970 | |
971 | /* Mailbox Command Status. */ | |
972 | MB_CMD_STS_GOOD = 0x00004000, /* Success. */ | |
973 | MB_CMD_STS_INTRMDT = 0x00001000, /* Intermediate Complete. */ | |
b82808b7 RM |
974 | MB_CMD_STS_INVLD_CMD = 0x00004001, /* Invalid. */ |
975 | MB_CMD_STS_XFC_ERR = 0x00004002, /* Interface Error. */ | |
976 | MB_CMD_STS_CSUM_ERR = 0x00004003, /* Csum Error. */ | |
977 | MB_CMD_STS_ERR = 0x00004005, /* System Error. */ | |
978 | MB_CMD_STS_PARAM_ERR = 0x00004006, /* Parameter Error. */ | |
c4e84bde RM |
979 | }; |
980 | ||
981 | struct mbox_params { | |
982 | u32 mbox_in[MAILBOX_COUNT]; | |
983 | u32 mbox_out[MAILBOX_COUNT]; | |
984 | int in_count; | |
985 | int out_count; | |
986 | }; | |
987 | ||
b0c2aadf | 988 | struct flash_params_8012 { |
c4e84bde | 989 | u8 dev_id_str[4]; |
26351479 RM |
990 | __le16 size; |
991 | __le16 csum; | |
992 | __le16 ver; | |
993 | __le16 sub_dev_id; | |
c4e84bde | 994 | u8 mac_addr[6]; |
26351479 | 995 | __le16 res; |
c4e84bde RM |
996 | }; |
997 | ||
cdca8d02 RM |
998 | /* 8000 device's flash is a different structure |
999 | * at a different offset in flash. | |
1000 | */ | |
1001 | #define FUNC0_FLASH_OFFSET 0x140200 | |
1002 | #define FUNC1_FLASH_OFFSET 0x140600 | |
1003 | ||
1004 | /* Flash related data structures. */ | |
1005 | struct flash_params_8000 { | |
1006 | u8 dev_id_str[4]; /* "8000" */ | |
1007 | __le16 ver; | |
1008 | __le16 size; | |
1009 | __le16 csum; | |
1010 | __le16 reserved0; | |
1011 | __le16 total_size; | |
1012 | __le16 entry_count; | |
1013 | u8 data_type0; | |
1014 | u8 data_size0; | |
1015 | u8 mac_addr[6]; | |
1016 | u8 data_type1; | |
1017 | u8 data_size1; | |
1018 | u8 mac_addr1[6]; | |
1019 | u8 data_type2; | |
1020 | u8 data_size2; | |
1021 | __le16 vlan_id; | |
1022 | u8 data_type3; | |
1023 | u8 data_size3; | |
1024 | __le16 last; | |
1025 | u8 reserved1[464]; | |
1026 | __le16 subsys_ven_id; | |
1027 | __le16 subsys_dev_id; | |
1028 | u8 reserved2[4]; | |
1029 | }; | |
1030 | ||
b0c2aadf RM |
1031 | union flash_params { |
1032 | struct flash_params_8012 flash_params_8012; | |
cdca8d02 | 1033 | struct flash_params_8000 flash_params_8000; |
b0c2aadf | 1034 | }; |
c4e84bde RM |
1035 | |
1036 | /* | |
1037 | * doorbell space for the rx ring context | |
1038 | */ | |
1039 | struct rx_doorbell_context { | |
1040 | u32 cnsmr_idx; /* 0x00 */ | |
1041 | u32 valid; /* 0x04 */ | |
1042 | u32 reserved[4]; /* 0x08-0x14 */ | |
1043 | u32 lbq_prod_idx; /* 0x18 */ | |
1044 | u32 sbq_prod_idx; /* 0x1c */ | |
1045 | }; | |
1046 | ||
1047 | /* | |
1048 | * doorbell space for the tx ring context | |
1049 | */ | |
1050 | struct tx_doorbell_context { | |
1051 | u32 prod_idx; /* 0x00 */ | |
1052 | u32 valid; /* 0x04 */ | |
1053 | u32 reserved[4]; /* 0x08-0x14 */ | |
1054 | u32 lbq_prod_idx; /* 0x18 */ | |
1055 | u32 sbq_prod_idx; /* 0x1c */ | |
1056 | }; | |
1057 | ||
1058 | /* DATA STRUCTURES SHARED WITH HARDWARE. */ | |
c4e84bde RM |
1059 | struct tx_buf_desc { |
1060 | __le64 addr; | |
1061 | __le32 len; | |
1062 | #define TX_DESC_LEN_MASK 0x000fffff | |
1063 | #define TX_DESC_C 0x40000000 | |
1064 | #define TX_DESC_E 0x80000000 | |
ba2d3587 | 1065 | } __packed; |
c4e84bde RM |
1066 | |
1067 | /* | |
1068 | * IOCB Definitions... | |
1069 | */ | |
1070 | ||
1071 | #define OPCODE_OB_MAC_IOCB 0x01 | |
1072 | #define OPCODE_OB_MAC_TSO_IOCB 0x02 | |
1073 | #define OPCODE_IB_MAC_IOCB 0x20 | |
1074 | #define OPCODE_IB_MPI_IOCB 0x21 | |
1075 | #define OPCODE_IB_AE_IOCB 0x3f | |
1076 | ||
1077 | struct ob_mac_iocb_req { | |
1078 | u8 opcode; | |
1079 | u8 flags1; | |
1080 | #define OB_MAC_IOCB_REQ_OI 0x01 | |
1081 | #define OB_MAC_IOCB_REQ_I 0x02 | |
1082 | #define OB_MAC_IOCB_REQ_D 0x08 | |
1083 | #define OB_MAC_IOCB_REQ_F 0x10 | |
1084 | u8 flags2; | |
1085 | u8 flags3; | |
1086 | #define OB_MAC_IOCB_DFP 0x02 | |
1087 | #define OB_MAC_IOCB_V 0x04 | |
1088 | __le32 reserved1[2]; | |
1089 | __le16 frame_len; | |
1090 | #define OB_MAC_IOCB_LEN_MASK 0x3ffff | |
1091 | __le16 reserved2; | |
3537d54c RM |
1092 | u32 tid; |
1093 | u32 txq_idx; | |
c4e84bde RM |
1094 | __le32 reserved3; |
1095 | __le16 vlan_tci; | |
1096 | __le16 reserved4; | |
1097 | struct tx_buf_desc tbd[TX_DESC_PER_IOCB]; | |
ba2d3587 | 1098 | } __packed; |
c4e84bde RM |
1099 | |
1100 | struct ob_mac_iocb_rsp { | |
1101 | u8 opcode; /* */ | |
1102 | u8 flags1; /* */ | |
1103 | #define OB_MAC_IOCB_RSP_OI 0x01 /* */ | |
1104 | #define OB_MAC_IOCB_RSP_I 0x02 /* */ | |
1105 | #define OB_MAC_IOCB_RSP_E 0x08 /* */ | |
1106 | #define OB_MAC_IOCB_RSP_S 0x10 /* too Short */ | |
1107 | #define OB_MAC_IOCB_RSP_L 0x20 /* too Large */ | |
1108 | #define OB_MAC_IOCB_RSP_P 0x40 /* Padded */ | |
1109 | u8 flags2; /* */ | |
1110 | u8 flags3; /* */ | |
1111 | #define OB_MAC_IOCB_RSP_B 0x80 /* */ | |
3537d54c RM |
1112 | u32 tid; |
1113 | u32 txq_idx; | |
c4e84bde | 1114 | __le32 reserved[13]; |
ba2d3587 | 1115 | } __packed; |
c4e84bde RM |
1116 | |
1117 | struct ob_mac_tso_iocb_req { | |
1118 | u8 opcode; | |
1119 | u8 flags1; | |
1120 | #define OB_MAC_TSO_IOCB_OI 0x01 | |
1121 | #define OB_MAC_TSO_IOCB_I 0x02 | |
1122 | #define OB_MAC_TSO_IOCB_D 0x08 | |
1123 | #define OB_MAC_TSO_IOCB_IP4 0x40 | |
1124 | #define OB_MAC_TSO_IOCB_IP6 0x80 | |
1125 | u8 flags2; | |
1126 | #define OB_MAC_TSO_IOCB_LSO 0x20 | |
1127 | #define OB_MAC_TSO_IOCB_UC 0x40 | |
1128 | #define OB_MAC_TSO_IOCB_TC 0x80 | |
1129 | u8 flags3; | |
1130 | #define OB_MAC_TSO_IOCB_IC 0x01 | |
1131 | #define OB_MAC_TSO_IOCB_DFP 0x02 | |
1132 | #define OB_MAC_TSO_IOCB_V 0x04 | |
1133 | __le32 reserved1[2]; | |
1134 | __le32 frame_len; | |
3537d54c RM |
1135 | u32 tid; |
1136 | u32 txq_idx; | |
c4e84bde RM |
1137 | __le16 total_hdrs_len; |
1138 | __le16 net_trans_offset; | |
1139 | #define OB_MAC_TRANSPORT_HDR_SHIFT 6 | |
1140 | __le16 vlan_tci; | |
1141 | __le16 mss; | |
1142 | struct tx_buf_desc tbd[TX_DESC_PER_IOCB]; | |
ba2d3587 | 1143 | } __packed; |
c4e84bde RM |
1144 | |
1145 | struct ob_mac_tso_iocb_rsp { | |
1146 | u8 opcode; | |
1147 | u8 flags1; | |
1148 | #define OB_MAC_TSO_IOCB_RSP_OI 0x01 | |
1149 | #define OB_MAC_TSO_IOCB_RSP_I 0x02 | |
1150 | #define OB_MAC_TSO_IOCB_RSP_E 0x08 | |
1151 | #define OB_MAC_TSO_IOCB_RSP_S 0x10 | |
1152 | #define OB_MAC_TSO_IOCB_RSP_L 0x20 | |
1153 | #define OB_MAC_TSO_IOCB_RSP_P 0x40 | |
1154 | u8 flags2; /* */ | |
1155 | u8 flags3; /* */ | |
1156 | #define OB_MAC_TSO_IOCB_RSP_B 0x8000 | |
3537d54c RM |
1157 | u32 tid; |
1158 | u32 txq_idx; | |
c4e84bde | 1159 | __le32 reserved2[13]; |
ba2d3587 | 1160 | } __packed; |
c4e84bde RM |
1161 | |
1162 | struct ib_mac_iocb_rsp { | |
1163 | u8 opcode; /* 0x20 */ | |
1164 | u8 flags1; | |
1165 | #define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */ | |
1166 | #define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */ | |
d555f592 | 1167 | #define IB_MAC_CSUM_ERR_MASK 0x1c /* A mask to use for csum errs */ |
c4e84bde RM |
1168 | #define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */ |
1169 | #define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */ | |
1170 | #define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */ | |
1171 | #define IB_MAC_IOCB_RSP_M_MASK 0x60 /* Multicast info */ | |
1172 | #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* Not mcast frame */ | |
1173 | #define IB_MAC_IOCB_RSP_M_HASH 0x20 /* HASH mcast frame */ | |
1174 | #define IB_MAC_IOCB_RSP_M_REG 0x40 /* Registered mcast frame */ | |
1175 | #define IB_MAC_IOCB_RSP_M_PROM 0x60 /* Promiscuous mcast frame */ | |
1176 | #define IB_MAC_IOCB_RSP_B 0x80 /* Broadcast frame */ | |
1177 | u8 flags2; | |
1178 | #define IB_MAC_IOCB_RSP_P 0x01 /* Promiscuous frame */ | |
1179 | #define IB_MAC_IOCB_RSP_V 0x02 /* Vlan tag present */ | |
1180 | #define IB_MAC_IOCB_RSP_ERR_MASK 0x1c /* */ | |
1181 | #define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04 | |
1182 | #define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08 | |
1183 | #define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10 | |
1184 | #define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14 | |
1185 | #define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18 | |
1186 | #define IB_MAC_IOCB_RSP_ERR_CRC 0x1c | |
1187 | #define IB_MAC_IOCB_RSP_U 0x20 /* UDP packet */ | |
1188 | #define IB_MAC_IOCB_RSP_T 0x40 /* TCP packet */ | |
1189 | #define IB_MAC_IOCB_RSP_FO 0x80 /* Failover port */ | |
1190 | u8 flags3; | |
1191 | #define IB_MAC_IOCB_RSP_RSS_MASK 0x07 /* RSS mask */ | |
1192 | #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* No RSS match */ | |
1193 | #define IB_MAC_IOCB_RSP_M_IPV4 0x04 /* IPv4 RSS match */ | |
1194 | #define IB_MAC_IOCB_RSP_M_IPV6 0x02 /* IPv6 RSS match */ | |
1195 | #define IB_MAC_IOCB_RSP_M_TCP_V4 0x05 /* TCP with IPv4 */ | |
1196 | #define IB_MAC_IOCB_RSP_M_TCP_V6 0x03 /* TCP with IPv6 */ | |
1197 | #define IB_MAC_IOCB_RSP_V4 0x08 /* IPV4 */ | |
1198 | #define IB_MAC_IOCB_RSP_V6 0x10 /* IPV6 */ | |
1199 | #define IB_MAC_IOCB_RSP_IH 0x20 /* Split after IP header */ | |
1200 | #define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */ | |
1201 | #define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */ | |
1202 | __le32 data_len; /* */ | |
97345524 | 1203 | __le64 data_addr; /* */ |
c4e84bde RM |
1204 | __le32 rss; /* */ |
1205 | __le16 vlan_id; /* 12 bits */ | |
1206 | #define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */ | |
1207 | #define IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */ | |
b82808b7 | 1208 | #define IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff |
c4e84bde RM |
1209 | |
1210 | __le16 reserved1; | |
1211 | __le32 reserved2[6]; | |
a303ce09 RM |
1212 | u8 reserved3[3]; |
1213 | u8 flags4; | |
1214 | #define IB_MAC_IOCB_RSP_HV 0x20 | |
1215 | #define IB_MAC_IOCB_RSP_HS 0x40 | |
1216 | #define IB_MAC_IOCB_RSP_HL 0x80 | |
c4e84bde | 1217 | __le32 hdr_len; /* */ |
97345524 | 1218 | __le64 hdr_addr; /* */ |
ba2d3587 | 1219 | } __packed; |
c4e84bde RM |
1220 | |
1221 | struct ib_ae_iocb_rsp { | |
1222 | u8 opcode; | |
1223 | u8 flags1; | |
1224 | #define IB_AE_IOCB_RSP_OI 0x01 | |
1225 | #define IB_AE_IOCB_RSP_I 0x02 | |
1226 | u8 event; | |
1227 | #define LINK_UP_EVENT 0x00 | |
1228 | #define LINK_DOWN_EVENT 0x01 | |
1229 | #define CAM_LOOKUP_ERR_EVENT 0x06 | |
1230 | #define SOFT_ECC_ERROR_EVENT 0x07 | |
1231 | #define MGMT_ERR_EVENT 0x08 | |
1232 | #define TEN_GIG_MAC_EVENT 0x09 | |
1233 | #define GPI0_H2L_EVENT 0x10 | |
1234 | #define GPI0_L2H_EVENT 0x20 | |
1235 | #define GPI1_H2L_EVENT 0x11 | |
1236 | #define GPI1_L2H_EVENT 0x21 | |
1237 | #define PCI_ERR_ANON_BUF_RD 0x40 | |
1238 | u8 q_id; | |
1239 | __le32 reserved[15]; | |
ba2d3587 | 1240 | } __packed; |
c4e84bde RM |
1241 | |
1242 | /* | |
1243 | * These three structures are for generic | |
1244 | * handling of ib and ob iocbs. | |
1245 | */ | |
1246 | struct ql_net_rsp_iocb { | |
1247 | u8 opcode; | |
1248 | u8 flags0; | |
1249 | __le16 length; | |
1250 | __le32 tid; | |
1251 | __le32 reserved[14]; | |
ba2d3587 | 1252 | } __packed; |
c4e84bde RM |
1253 | |
1254 | struct net_req_iocb { | |
1255 | u8 opcode; | |
1256 | u8 flags0; | |
1257 | __le16 flags1; | |
1258 | __le32 tid; | |
1259 | __le32 reserved1[30]; | |
ba2d3587 | 1260 | } __packed; |
c4e84bde RM |
1261 | |
1262 | /* | |
1263 | * tx ring initialization control block for chip. | |
1264 | * It is defined as: | |
1265 | * "Work Queue Initialization Control Block" | |
1266 | */ | |
1267 | struct wqicb { | |
1268 | __le16 len; | |
1269 | #define Q_LEN_V (1 << 4) | |
1270 | #define Q_LEN_CPP_CONT 0x0000 | |
1271 | #define Q_LEN_CPP_16 0x0001 | |
1272 | #define Q_LEN_CPP_32 0x0002 | |
1273 | #define Q_LEN_CPP_64 0x0003 | |
b82808b7 | 1274 | #define Q_LEN_CPP_512 0x0006 |
c4e84bde RM |
1275 | __le16 flags; |
1276 | #define Q_PRI_SHIFT 1 | |
1277 | #define Q_FLAGS_LC 0x1000 | |
1278 | #define Q_FLAGS_LB 0x2000 | |
1279 | #define Q_FLAGS_LI 0x4000 | |
1280 | #define Q_FLAGS_LO 0x8000 | |
1281 | __le16 cq_id_rss; | |
1282 | #define Q_CQ_ID_RSS_RV 0x8000 | |
1283 | __le16 rid; | |
97345524 RM |
1284 | __le64 addr; |
1285 | __le64 cnsmr_idx_addr; | |
ba2d3587 | 1286 | } __packed; |
c4e84bde RM |
1287 | |
1288 | /* | |
1289 | * rx ring initialization control block for chip. | |
1290 | * It is defined as: | |
1291 | * "Completion Queue Initialization Control Block" | |
1292 | */ | |
1293 | struct cqicb { | |
1294 | u8 msix_vect; | |
1295 | u8 reserved1; | |
1296 | u8 reserved2; | |
1297 | u8 flags; | |
1298 | #define FLAGS_LV 0x08 | |
1299 | #define FLAGS_LS 0x10 | |
1300 | #define FLAGS_LL 0x20 | |
1301 | #define FLAGS_LI 0x40 | |
1302 | #define FLAGS_LC 0x80 | |
1303 | __le16 len; | |
1304 | #define LEN_V (1 << 4) | |
1305 | #define LEN_CPP_CONT 0x0000 | |
1306 | #define LEN_CPP_32 0x0001 | |
1307 | #define LEN_CPP_64 0x0002 | |
1308 | #define LEN_CPP_128 0x0003 | |
1309 | __le16 rid; | |
97345524 RM |
1310 | __le64 addr; |
1311 | __le64 prod_idx_addr; | |
c4e84bde RM |
1312 | __le16 pkt_delay; |
1313 | __le16 irq_delay; | |
97345524 | 1314 | __le64 lbq_addr; |
c4e84bde RM |
1315 | __le16 lbq_buf_size; |
1316 | __le16 lbq_len; /* entry count */ | |
97345524 | 1317 | __le64 sbq_addr; |
c4e84bde RM |
1318 | __le16 sbq_buf_size; |
1319 | __le16 sbq_len; /* entry count */ | |
ba2d3587 | 1320 | } __packed; |
c4e84bde RM |
1321 | |
1322 | struct ricb { | |
1323 | u8 base_cq; | |
1324 | #define RSS_L4K 0x80 | |
1325 | u8 flags; | |
1326 | #define RSS_L6K 0x01 | |
1327 | #define RSS_LI 0x02 | |
1328 | #define RSS_LB 0x04 | |
1329 | #define RSS_LM 0x08 | |
1330 | #define RSS_RI4 0x10 | |
1331 | #define RSS_RT4 0x20 | |
1332 | #define RSS_RI6 0x40 | |
1333 | #define RSS_RT6 0x80 | |
1334 | __le16 mask; | |
541ae28c | 1335 | u8 hash_cq_id[1024]; |
c4e84bde RM |
1336 | __le32 ipv6_hash_key[10]; |
1337 | __le32 ipv4_hash_key[4]; | |
ba2d3587 | 1338 | } __packed; |
c4e84bde RM |
1339 | |
1340 | /* SOFTWARE/DRIVER DATA STRUCTURES. */ | |
1341 | ||
1342 | struct oal { | |
1343 | struct tx_buf_desc oal[TX_DESC_PER_OAL]; | |
1344 | }; | |
1345 | ||
1346 | struct map_list { | |
64b9b41d FT |
1347 | DEFINE_DMA_UNMAP_ADDR(mapaddr); |
1348 | DEFINE_DMA_UNMAP_LEN(maplen); | |
c4e84bde RM |
1349 | }; |
1350 | ||
1351 | struct tx_ring_desc { | |
1352 | struct sk_buff *skb; | |
1353 | struct ob_mac_iocb_req *queue_entry; | |
3537d54c | 1354 | u32 index; |
c4e84bde RM |
1355 | struct oal oal; |
1356 | struct map_list map[MAX_SKB_FRAGS + 1]; | |
1357 | int map_cnt; | |
1358 | struct tx_ring_desc *next; | |
1359 | }; | |
1360 | ||
7c734359 RM |
1361 | struct page_chunk { |
1362 | struct page *page; /* master page */ | |
1363 | char *va; /* virt addr for this chunk */ | |
1364 | u64 map; /* mapping for master */ | |
1365 | unsigned int offset; /* offset for this chunk */ | |
1366 | unsigned int last_flag; /* flag set for last chunk in page */ | |
1367 | }; | |
1368 | ||
c4e84bde RM |
1369 | struct bq_desc { |
1370 | union { | |
7c734359 | 1371 | struct page_chunk pg_chunk; |
c4e84bde RM |
1372 | struct sk_buff *skb; |
1373 | } p; | |
2c9a0d41 | 1374 | __le64 *addr; |
3537d54c | 1375 | u32 index; |
64b9b41d FT |
1376 | DEFINE_DMA_UNMAP_ADDR(mapaddr); |
1377 | DEFINE_DMA_UNMAP_LEN(maplen); | |
c4e84bde RM |
1378 | }; |
1379 | ||
1380 | #define QL_TXQ_IDX(qdev, skb) (smp_processor_id()%(qdev->tx_ring_count)) | |
1381 | ||
1382 | struct tx_ring { | |
1383 | /* | |
1384 | * queue info. | |
1385 | */ | |
1386 | struct wqicb wqicb; /* structure used to inform chip of new queue */ | |
1387 | void *wq_base; /* pci_alloc:virtual addr for tx */ | |
1388 | dma_addr_t wq_base_dma; /* pci_alloc:dma addr for tx */ | |
ba7cd3ba | 1389 | __le32 *cnsmr_idx_sh_reg; /* shadow copy of consumer idx */ |
c4e84bde RM |
1390 | dma_addr_t cnsmr_idx_sh_reg_dma; /* dma-shadow copy of consumer */ |
1391 | u32 wq_size; /* size in bytes of queue area */ | |
1392 | u32 wq_len; /* number of entries in queue */ | |
1393 | void __iomem *prod_idx_db_reg; /* doorbell area index reg at offset 0x00 */ | |
1394 | void __iomem *valid_db_reg; /* doorbell area valid reg at offset 0x04 */ | |
1395 | u16 prod_idx; /* current value for prod idx */ | |
1396 | u16 cq_id; /* completion (rx) queue for tx completions */ | |
1397 | u8 wq_id; /* queue id for this entry */ | |
1398 | u8 reserved1[3]; | |
1399 | struct tx_ring_desc *q; /* descriptor list for the queue */ | |
1400 | spinlock_t lock; | |
1401 | atomic_t tx_count; /* counts down for every outstanding IO */ | |
1402 | atomic_t queue_stopped; /* Turns queue off when full. */ | |
1403 | struct delayed_work tx_work; | |
1404 | struct ql_adapter *qdev; | |
885ee398 RM |
1405 | u64 tx_packets; |
1406 | u64 tx_bytes; | |
1407 | u64 tx_errors; | |
c4e84bde RM |
1408 | }; |
1409 | ||
1410 | /* | |
1411 | * Type of inbound queue. | |
1412 | */ | |
1413 | enum { | |
1414 | DEFAULT_Q = 2, /* Handles slow queue and chip/MPI events. */ | |
1415 | TX_Q = 3, /* Handles outbound completions. */ | |
1416 | RX_Q = 4, /* Handles inbound completions. */ | |
1417 | }; | |
1418 | ||
1419 | struct rx_ring { | |
1420 | struct cqicb cqicb; /* The chip's completion queue init control block. */ | |
1421 | ||
1422 | /* Completion queue elements. */ | |
1423 | void *cq_base; | |
1424 | dma_addr_t cq_base_dma; | |
1425 | u32 cq_size; | |
1426 | u32 cq_len; | |
1427 | u16 cq_id; | |
ba7cd3ba | 1428 | __le32 *prod_idx_sh_reg; /* Shadowed producer register. */ |
c4e84bde RM |
1429 | dma_addr_t prod_idx_sh_reg_dma; |
1430 | void __iomem *cnsmr_idx_db_reg; /* PCI doorbell mem area + 0 */ | |
1431 | u32 cnsmr_idx; /* current sw idx */ | |
1432 | struct ql_net_rsp_iocb *curr_entry; /* next entry on queue */ | |
1433 | void __iomem *valid_db_reg; /* PCI doorbell mem area + 0x04 */ | |
1434 | ||
1435 | /* Large buffer queue elements. */ | |
1436 | u32 lbq_len; /* entry count */ | |
1437 | u32 lbq_size; /* size in bytes of queue */ | |
1438 | u32 lbq_buf_size; | |
1439 | void *lbq_base; | |
1440 | dma_addr_t lbq_base_dma; | |
1441 | void *lbq_base_indirect; | |
1442 | dma_addr_t lbq_base_indirect_dma; | |
7c734359 | 1443 | struct page_chunk pg_chunk; /* current page for chunks */ |
c4e84bde RM |
1444 | struct bq_desc *lbq; /* array of control blocks */ |
1445 | void __iomem *lbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x18 */ | |
1446 | u32 lbq_prod_idx; /* current sw prod idx */ | |
1447 | u32 lbq_curr_idx; /* next entry we expect */ | |
1448 | u32 lbq_clean_idx; /* beginning of new descs */ | |
1449 | u32 lbq_free_cnt; /* free buffer desc cnt */ | |
1450 | ||
1451 | /* Small buffer queue elements. */ | |
1452 | u32 sbq_len; /* entry count */ | |
1453 | u32 sbq_size; /* size in bytes of queue */ | |
1454 | u32 sbq_buf_size; | |
1455 | void *sbq_base; | |
1456 | dma_addr_t sbq_base_dma; | |
1457 | void *sbq_base_indirect; | |
1458 | dma_addr_t sbq_base_indirect_dma; | |
1459 | struct bq_desc *sbq; /* array of control blocks */ | |
1460 | void __iomem *sbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x1c */ | |
1461 | u32 sbq_prod_idx; /* current sw prod idx */ | |
1462 | u32 sbq_curr_idx; /* next entry we expect */ | |
1463 | u32 sbq_clean_idx; /* beginning of new descs */ | |
1464 | u32 sbq_free_cnt; /* free buffer desc cnt */ | |
1465 | ||
1466 | /* Misc. handler elements. */ | |
b2014ff8 | 1467 | u32 type; /* Type of queue, tx, rx. */ |
c4e84bde RM |
1468 | u32 irq; /* Which vector this ring is assigned. */ |
1469 | u32 cpu; /* Which CPU this should run on. */ | |
1470 | char name[IFNAMSIZ + 5]; | |
1471 | struct napi_struct napi; | |
c4e84bde RM |
1472 | u8 reserved; |
1473 | struct ql_adapter *qdev; | |
885ee398 RM |
1474 | u64 rx_packets; |
1475 | u64 rx_multicast; | |
1476 | u64 rx_bytes; | |
1477 | u64 rx_dropped; | |
1478 | u64 rx_errors; | |
c4e84bde RM |
1479 | }; |
1480 | ||
1481 | /* | |
1482 | * RSS Initialization Control Block | |
1483 | */ | |
1484 | struct hash_id { | |
1485 | u8 value[4]; | |
1486 | }; | |
1487 | ||
1488 | struct nic_stats { | |
1489 | /* | |
1490 | * These stats come from offset 200h to 278h | |
1491 | * in the XGMAC register. | |
1492 | */ | |
1493 | u64 tx_pkts; | |
1494 | u64 tx_bytes; | |
1495 | u64 tx_mcast_pkts; | |
1496 | u64 tx_bcast_pkts; | |
1497 | u64 tx_ucast_pkts; | |
1498 | u64 tx_ctl_pkts; | |
1499 | u64 tx_pause_pkts; | |
1500 | u64 tx_64_pkt; | |
1501 | u64 tx_65_to_127_pkt; | |
1502 | u64 tx_128_to_255_pkt; | |
1503 | u64 tx_256_511_pkt; | |
1504 | u64 tx_512_to_1023_pkt; | |
1505 | u64 tx_1024_to_1518_pkt; | |
1506 | u64 tx_1519_to_max_pkt; | |
1507 | u64 tx_undersize_pkt; | |
1508 | u64 tx_oversize_pkt; | |
1509 | ||
1510 | /* | |
1511 | * These stats come from offset 300h to 3C8h | |
1512 | * in the XGMAC register. | |
1513 | */ | |
1514 | u64 rx_bytes; | |
1515 | u64 rx_bytes_ok; | |
1516 | u64 rx_pkts; | |
1517 | u64 rx_pkts_ok; | |
1518 | u64 rx_bcast_pkts; | |
1519 | u64 rx_mcast_pkts; | |
1520 | u64 rx_ucast_pkts; | |
1521 | u64 rx_undersize_pkts; | |
1522 | u64 rx_oversize_pkts; | |
1523 | u64 rx_jabber_pkts; | |
1524 | u64 rx_undersize_fcerr_pkts; | |
1525 | u64 rx_drop_events; | |
1526 | u64 rx_fcerr_pkts; | |
1527 | u64 rx_align_err; | |
1528 | u64 rx_symbol_err; | |
1529 | u64 rx_mac_err; | |
1530 | u64 rx_ctl_pkts; | |
1531 | u64 rx_pause_pkts; | |
1532 | u64 rx_64_pkts; | |
1533 | u64 rx_65_to_127_pkts; | |
1534 | u64 rx_128_255_pkts; | |
1535 | u64 rx_256_511_pkts; | |
1536 | u64 rx_512_to_1023_pkts; | |
1537 | u64 rx_1024_to_1518_pkts; | |
1538 | u64 rx_1519_to_max_pkts; | |
1539 | u64 rx_len_err_pkts; | |
6abd2346 RM |
1540 | /* |
1541 | * These stats come from offset 500h to 5C8h | |
1542 | * in the XGMAC register. | |
1543 | */ | |
1544 | u64 tx_cbfc_pause_frames0; | |
1545 | u64 tx_cbfc_pause_frames1; | |
1546 | u64 tx_cbfc_pause_frames2; | |
1547 | u64 tx_cbfc_pause_frames3; | |
1548 | u64 tx_cbfc_pause_frames4; | |
1549 | u64 tx_cbfc_pause_frames5; | |
1550 | u64 tx_cbfc_pause_frames6; | |
1551 | u64 tx_cbfc_pause_frames7; | |
1552 | u64 rx_cbfc_pause_frames0; | |
1553 | u64 rx_cbfc_pause_frames1; | |
1554 | u64 rx_cbfc_pause_frames2; | |
1555 | u64 rx_cbfc_pause_frames3; | |
1556 | u64 rx_cbfc_pause_frames4; | |
1557 | u64 rx_cbfc_pause_frames5; | |
1558 | u64 rx_cbfc_pause_frames6; | |
1559 | u64 rx_cbfc_pause_frames7; | |
1560 | u64 rx_nic_fifo_drop; | |
c4e84bde RM |
1561 | }; |
1562 | ||
b87babeb | 1563 | /* Firmware coredump internal register address/length pairs. */ |
a61f8026 RM |
1564 | enum { |
1565 | MPI_CORE_REGS_ADDR = 0x00030000, | |
1566 | MPI_CORE_REGS_CNT = 127, | |
1567 | MPI_CORE_SH_REGS_CNT = 16, | |
1568 | TEST_REGS_ADDR = 0x00001000, | |
1569 | TEST_REGS_CNT = 23, | |
1570 | RMII_REGS_ADDR = 0x00001040, | |
1571 | RMII_REGS_CNT = 64, | |
1572 | FCMAC1_REGS_ADDR = 0x00001080, | |
1573 | FCMAC2_REGS_ADDR = 0x000010c0, | |
1574 | FCMAC_REGS_CNT = 64, | |
1575 | FC1_MBX_REGS_ADDR = 0x00001100, | |
1576 | FC2_MBX_REGS_ADDR = 0x00001240, | |
1577 | FC_MBX_REGS_CNT = 64, | |
1578 | IDE_REGS_ADDR = 0x00001140, | |
1579 | IDE_REGS_CNT = 64, | |
1580 | NIC1_MBX_REGS_ADDR = 0x00001180, | |
1581 | NIC2_MBX_REGS_ADDR = 0x00001280, | |
1582 | NIC_MBX_REGS_CNT = 64, | |
1583 | SMBUS_REGS_ADDR = 0x00001200, | |
1584 | SMBUS_REGS_CNT = 64, | |
1585 | I2C_REGS_ADDR = 0x00001fc0, | |
1586 | I2C_REGS_CNT = 64, | |
1587 | MEMC_REGS_ADDR = 0x00003000, | |
1588 | MEMC_REGS_CNT = 256, | |
1589 | PBUS_REGS_ADDR = 0x00007c00, | |
1590 | PBUS_REGS_CNT = 256, | |
1591 | MDE_REGS_ADDR = 0x00010000, | |
1592 | MDE_REGS_CNT = 6, | |
1593 | CODE_RAM_ADDR = 0x00020000, | |
1594 | CODE_RAM_CNT = 0x2000, | |
1595 | MEMC_RAM_ADDR = 0x00100000, | |
1596 | MEMC_RAM_CNT = 0x2000, | |
1597 | }; | |
1598 | ||
1599 | #define MPI_COREDUMP_COOKIE 0x5555aaaa | |
1600 | struct mpi_coredump_global_header { | |
1601 | u32 cookie; | |
1602 | u8 idString[16]; | |
1603 | u32 timeLo; | |
1604 | u32 timeHi; | |
1605 | u32 imageSize; | |
1606 | u32 headerSize; | |
1607 | u8 info[220]; | |
1608 | }; | |
1609 | ||
1610 | struct mpi_coredump_segment_header { | |
1611 | u32 cookie; | |
1612 | u32 segNum; | |
1613 | u32 segSize; | |
1614 | u32 extra; | |
1615 | u8 description[16]; | |
1616 | }; | |
1617 | ||
b87babeb | 1618 | /* Firmware coredump header segment numbers. */ |
a61f8026 RM |
1619 | enum { |
1620 | CORE_SEG_NUM = 1, | |
1621 | TEST_LOGIC_SEG_NUM = 2, | |
1622 | RMII_SEG_NUM = 3, | |
1623 | FCMAC1_SEG_NUM = 4, | |
1624 | FCMAC2_SEG_NUM = 5, | |
1625 | FC1_MBOX_SEG_NUM = 6, | |
1626 | IDE_SEG_NUM = 7, | |
1627 | NIC1_MBOX_SEG_NUM = 8, | |
1628 | SMBUS_SEG_NUM = 9, | |
1629 | FC2_MBOX_SEG_NUM = 10, | |
1630 | NIC2_MBOX_SEG_NUM = 11, | |
1631 | I2C_SEG_NUM = 12, | |
1632 | MEMC_SEG_NUM = 13, | |
1633 | PBUS_SEG_NUM = 14, | |
1634 | MDE_SEG_NUM = 15, | |
1635 | NIC1_CONTROL_SEG_NUM = 16, | |
1636 | NIC2_CONTROL_SEG_NUM = 17, | |
1637 | NIC1_XGMAC_SEG_NUM = 18, | |
1638 | NIC2_XGMAC_SEG_NUM = 19, | |
1639 | WCS_RAM_SEG_NUM = 20, | |
1640 | MEMC_RAM_SEG_NUM = 21, | |
1641 | XAUI_AN_SEG_NUM = 22, | |
1642 | XAUI_HSS_PCS_SEG_NUM = 23, | |
1643 | XFI_AN_SEG_NUM = 24, | |
1644 | XFI_TRAIN_SEG_NUM = 25, | |
1645 | XFI_HSS_PCS_SEG_NUM = 26, | |
1646 | XFI_HSS_TX_SEG_NUM = 27, | |
1647 | XFI_HSS_RX_SEG_NUM = 28, | |
1648 | XFI_HSS_PLL_SEG_NUM = 29, | |
1649 | MISC_NIC_INFO_SEG_NUM = 30, | |
1650 | INTR_STATES_SEG_NUM = 31, | |
1651 | CAM_ENTRIES_SEG_NUM = 32, | |
1652 | ROUTING_WORDS_SEG_NUM = 33, | |
1653 | ETS_SEG_NUM = 34, | |
1654 | PROBE_DUMP_SEG_NUM = 35, | |
1655 | ROUTING_INDEX_SEG_NUM = 36, | |
1656 | MAC_PROTOCOL_SEG_NUM = 37, | |
1657 | XAUI2_AN_SEG_NUM = 38, | |
1658 | XAUI2_HSS_PCS_SEG_NUM = 39, | |
1659 | XFI2_AN_SEG_NUM = 40, | |
1660 | XFI2_TRAIN_SEG_NUM = 41, | |
1661 | XFI2_HSS_PCS_SEG_NUM = 42, | |
1662 | XFI2_HSS_TX_SEG_NUM = 43, | |
1663 | XFI2_HSS_RX_SEG_NUM = 44, | |
1664 | XFI2_HSS_PLL_SEG_NUM = 45, | |
1665 | SEM_REGS_SEG_NUM = 50 | |
1666 | ||
1667 | }; | |
1668 | ||
b87babeb RM |
1669 | /* There are 64 generic NIC registers. */ |
1670 | #define NIC_REGS_DUMP_WORD_COUNT 64 | |
1671 | /* XGMAC word count. */ | |
1672 | #define XGMAC_DUMP_WORD_COUNT (XGMAC_REGISTER_END / 4) | |
1673 | /* Word counts for the SERDES blocks. */ | |
1674 | #define XG_SERDES_XAUI_AN_COUNT 14 | |
1675 | #define XG_SERDES_XAUI_HSS_PCS_COUNT 33 | |
1676 | #define XG_SERDES_XFI_AN_COUNT 14 | |
1677 | #define XG_SERDES_XFI_TRAIN_COUNT 12 | |
1678 | #define XG_SERDES_XFI_HSS_PCS_COUNT 15 | |
1679 | #define XG_SERDES_XFI_HSS_TX_COUNT 32 | |
1680 | #define XG_SERDES_XFI_HSS_RX_COUNT 32 | |
1681 | #define XG_SERDES_XFI_HSS_PLL_COUNT 32 | |
1682 | ||
1683 | /* There are 2 CNA ETS and 8 NIC ETS registers. */ | |
1684 | #define ETS_REGS_DUMP_WORD_COUNT 10 | |
1685 | ||
1686 | /* Each probe mux entry stores the probe type plus 64 entries | |
1687 | * that are each each 64-bits in length. There are a total of | |
1688 | * 34 (PRB_MX_ADDR_VALID_TOTAL) valid probes. | |
1689 | */ | |
1690 | #define PRB_MX_ADDR_PRB_WORD_COUNT (1 + (PRB_MX_ADDR_MAX_MUX * 2)) | |
1691 | #define PRB_MX_DUMP_TOT_COUNT (PRB_MX_ADDR_PRB_WORD_COUNT * \ | |
1692 | PRB_MX_ADDR_VALID_TOTAL) | |
1693 | /* Each routing entry consists of 4 32-bit words. | |
1694 | * They are route type, index, index word, and result. | |
1695 | * There are 2 route blocks with 8 entries each and | |
1696 | * 2 NIC blocks with 16 entries each. | |
1697 | * The totol entries is 48 with 4 words each. | |
1698 | */ | |
1699 | #define RT_IDX_DUMP_ENTRIES 48 | |
1700 | #define RT_IDX_DUMP_WORDS_PER_ENTRY 4 | |
1701 | #define RT_IDX_DUMP_TOT_WORDS (RT_IDX_DUMP_ENTRIES * \ | |
1702 | RT_IDX_DUMP_WORDS_PER_ENTRY) | |
1703 | /* There are 10 address blocks in filter, each with | |
1704 | * different entry counts and different word-count-per-entry. | |
1705 | */ | |
1706 | #define MAC_ADDR_DUMP_ENTRIES \ | |
1707 | ((MAC_ADDR_MAX_CAM_ENTRIES * MAC_ADDR_MAX_CAM_WCOUNT) + \ | |
1708 | (MAC_ADDR_MAX_MULTICAST_ENTRIES * MAC_ADDR_MAX_MULTICAST_WCOUNT) + \ | |
1709 | (MAC_ADDR_MAX_VLAN_ENTRIES * MAC_ADDR_MAX_VLAN_WCOUNT) + \ | |
1710 | (MAC_ADDR_MAX_MCAST_FLTR_ENTRIES * MAC_ADDR_MAX_MCAST_FLTR_WCOUNT) + \ | |
1711 | (MAC_ADDR_MAX_FC_MAC_ENTRIES * MAC_ADDR_MAX_FC_MAC_WCOUNT) + \ | |
1712 | (MAC_ADDR_MAX_MGMT_MAC_ENTRIES * MAC_ADDR_MAX_MGMT_MAC_WCOUNT) + \ | |
1713 | (MAC_ADDR_MAX_MGMT_VLAN_ENTRIES * MAC_ADDR_MAX_MGMT_VLAN_WCOUNT) + \ | |
1714 | (MAC_ADDR_MAX_MGMT_V4_ENTRIES * MAC_ADDR_MAX_MGMT_V4_WCOUNT) + \ | |
1715 | (MAC_ADDR_MAX_MGMT_V6_ENTRIES * MAC_ADDR_MAX_MGMT_V6_WCOUNT) + \ | |
1716 | (MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES * MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT)) | |
1717 | #define MAC_ADDR_DUMP_WORDS_PER_ENTRY 2 | |
1718 | #define MAC_ADDR_DUMP_TOT_WORDS (MAC_ADDR_DUMP_ENTRIES * \ | |
1719 | MAC_ADDR_DUMP_WORDS_PER_ENTRY) | |
1720 | /* Maximum of 4 functions whose semaphore registeres are | |
1721 | * in the coredump. | |
1722 | */ | |
1723 | #define MAX_SEMAPHORE_FUNCTIONS 4 | |
1724 | /* Defines for access the MPI shadow registers. */ | |
1725 | #define RISC_124 0x0003007c | |
1726 | #define RISC_127 0x0003007f | |
1727 | #define SHADOW_OFFSET 0xb0000000 | |
1728 | #define SHADOW_REG_SHIFT 20 | |
1729 | ||
a61f8026 RM |
1730 | struct ql_nic_misc { |
1731 | u32 rx_ring_count; | |
1732 | u32 tx_ring_count; | |
1733 | u32 intr_count; | |
1734 | u32 function; | |
1735 | }; | |
1736 | ||
1737 | struct ql_reg_dump { | |
1738 | ||
1739 | /* segment 0 */ | |
1740 | struct mpi_coredump_global_header mpi_global_header; | |
1741 | ||
1742 | /* segment 16 */ | |
1743 | struct mpi_coredump_segment_header nic_regs_seg_hdr; | |
1744 | u32 nic_regs[64]; | |
1745 | ||
1746 | /* segment 30 */ | |
1747 | struct mpi_coredump_segment_header misc_nic_seg_hdr; | |
1748 | struct ql_nic_misc misc_nic_info; | |
1749 | ||
1750 | /* segment 31 */ | |
1751 | /* one interrupt state for each CQ */ | |
1752 | struct mpi_coredump_segment_header intr_states_seg_hdr; | |
1753 | u32 intr_states[MAX_CPUS]; | |
1754 | ||
1755 | /* segment 32 */ | |
1756 | /* 3 cam words each for 16 unicast, | |
1757 | * 2 cam words for each of 32 multicast. | |
1758 | */ | |
1759 | struct mpi_coredump_segment_header cam_entries_seg_hdr; | |
1760 | u32 cam_entries[(16 * 3) + (32 * 3)]; | |
1761 | ||
1762 | /* segment 33 */ | |
1763 | struct mpi_coredump_segment_header nic_routing_words_seg_hdr; | |
1764 | u32 nic_routing_words[16]; | |
1765 | ||
1766 | /* segment 34 */ | |
1767 | struct mpi_coredump_segment_header ets_seg_hdr; | |
1768 | u32 ets[8+2]; | |
1769 | }; | |
1770 | ||
b87babeb RM |
1771 | struct ql_mpi_coredump { |
1772 | /* segment 0 */ | |
1773 | struct mpi_coredump_global_header mpi_global_header; | |
1774 | ||
1775 | /* segment 1 */ | |
1776 | struct mpi_coredump_segment_header core_regs_seg_hdr; | |
1777 | u32 mpi_core_regs[MPI_CORE_REGS_CNT]; | |
1778 | u32 mpi_core_sh_regs[MPI_CORE_SH_REGS_CNT]; | |
1779 | ||
1780 | /* segment 2 */ | |
1781 | struct mpi_coredump_segment_header test_logic_regs_seg_hdr; | |
1782 | u32 test_logic_regs[TEST_REGS_CNT]; | |
1783 | ||
1784 | /* segment 3 */ | |
1785 | struct mpi_coredump_segment_header rmii_regs_seg_hdr; | |
1786 | u32 rmii_regs[RMII_REGS_CNT]; | |
1787 | ||
1788 | /* segment 4 */ | |
1789 | struct mpi_coredump_segment_header fcmac1_regs_seg_hdr; | |
1790 | u32 fcmac1_regs[FCMAC_REGS_CNT]; | |
1791 | ||
1792 | /* segment 5 */ | |
1793 | struct mpi_coredump_segment_header fcmac2_regs_seg_hdr; | |
1794 | u32 fcmac2_regs[FCMAC_REGS_CNT]; | |
1795 | ||
1796 | /* segment 6 */ | |
1797 | struct mpi_coredump_segment_header fc1_mbx_regs_seg_hdr; | |
1798 | u32 fc1_mbx_regs[FC_MBX_REGS_CNT]; | |
1799 | ||
1800 | /* segment 7 */ | |
1801 | struct mpi_coredump_segment_header ide_regs_seg_hdr; | |
1802 | u32 ide_regs[IDE_REGS_CNT]; | |
1803 | ||
1804 | /* segment 8 */ | |
1805 | struct mpi_coredump_segment_header nic1_mbx_regs_seg_hdr; | |
1806 | u32 nic1_mbx_regs[NIC_MBX_REGS_CNT]; | |
1807 | ||
1808 | /* segment 9 */ | |
1809 | struct mpi_coredump_segment_header smbus_regs_seg_hdr; | |
1810 | u32 smbus_regs[SMBUS_REGS_CNT]; | |
1811 | ||
1812 | /* segment 10 */ | |
1813 | struct mpi_coredump_segment_header fc2_mbx_regs_seg_hdr; | |
1814 | u32 fc2_mbx_regs[FC_MBX_REGS_CNT]; | |
1815 | ||
1816 | /* segment 11 */ | |
1817 | struct mpi_coredump_segment_header nic2_mbx_regs_seg_hdr; | |
1818 | u32 nic2_mbx_regs[NIC_MBX_REGS_CNT]; | |
1819 | ||
1820 | /* segment 12 */ | |
1821 | struct mpi_coredump_segment_header i2c_regs_seg_hdr; | |
1822 | u32 i2c_regs[I2C_REGS_CNT]; | |
1823 | /* segment 13 */ | |
1824 | struct mpi_coredump_segment_header memc_regs_seg_hdr; | |
1825 | u32 memc_regs[MEMC_REGS_CNT]; | |
1826 | ||
1827 | /* segment 14 */ | |
1828 | struct mpi_coredump_segment_header pbus_regs_seg_hdr; | |
1829 | u32 pbus_regs[PBUS_REGS_CNT]; | |
1830 | ||
1831 | /* segment 15 */ | |
1832 | struct mpi_coredump_segment_header mde_regs_seg_hdr; | |
1833 | u32 mde_regs[MDE_REGS_CNT]; | |
1834 | ||
1835 | /* segment 16 */ | |
1836 | struct mpi_coredump_segment_header nic_regs_seg_hdr; | |
1837 | u32 nic_regs[NIC_REGS_DUMP_WORD_COUNT]; | |
1838 | ||
1839 | /* segment 17 */ | |
1840 | struct mpi_coredump_segment_header nic2_regs_seg_hdr; | |
1841 | u32 nic2_regs[NIC_REGS_DUMP_WORD_COUNT]; | |
1842 | ||
1843 | /* segment 18 */ | |
1844 | struct mpi_coredump_segment_header xgmac1_seg_hdr; | |
1845 | u32 xgmac1[XGMAC_DUMP_WORD_COUNT]; | |
1846 | ||
1847 | /* segment 19 */ | |
1848 | struct mpi_coredump_segment_header xgmac2_seg_hdr; | |
1849 | u32 xgmac2[XGMAC_DUMP_WORD_COUNT]; | |
1850 | ||
1851 | /* segment 20 */ | |
1852 | struct mpi_coredump_segment_header code_ram_seg_hdr; | |
1853 | u32 code_ram[CODE_RAM_CNT]; | |
1854 | ||
1855 | /* segment 21 */ | |
1856 | struct mpi_coredump_segment_header memc_ram_seg_hdr; | |
1857 | u32 memc_ram[MEMC_RAM_CNT]; | |
1858 | ||
1859 | /* segment 22 */ | |
1860 | struct mpi_coredump_segment_header xaui_an_hdr; | |
1861 | u32 serdes_xaui_an[XG_SERDES_XAUI_AN_COUNT]; | |
1862 | ||
1863 | /* segment 23 */ | |
1864 | struct mpi_coredump_segment_header xaui_hss_pcs_hdr; | |
1865 | u32 serdes_xaui_hss_pcs[XG_SERDES_XAUI_HSS_PCS_COUNT]; | |
1866 | ||
1867 | /* segment 24 */ | |
1868 | struct mpi_coredump_segment_header xfi_an_hdr; | |
1869 | u32 serdes_xfi_an[XG_SERDES_XFI_AN_COUNT]; | |
1870 | ||
1871 | /* segment 25 */ | |
1872 | struct mpi_coredump_segment_header xfi_train_hdr; | |
1873 | u32 serdes_xfi_train[XG_SERDES_XFI_TRAIN_COUNT]; | |
1874 | ||
1875 | /* segment 26 */ | |
1876 | struct mpi_coredump_segment_header xfi_hss_pcs_hdr; | |
1877 | u32 serdes_xfi_hss_pcs[XG_SERDES_XFI_HSS_PCS_COUNT]; | |
1878 | ||
1879 | /* segment 27 */ | |
1880 | struct mpi_coredump_segment_header xfi_hss_tx_hdr; | |
1881 | u32 serdes_xfi_hss_tx[XG_SERDES_XFI_HSS_TX_COUNT]; | |
1882 | ||
1883 | /* segment 28 */ | |
1884 | struct mpi_coredump_segment_header xfi_hss_rx_hdr; | |
1885 | u32 serdes_xfi_hss_rx[XG_SERDES_XFI_HSS_RX_COUNT]; | |
1886 | ||
1887 | /* segment 29 */ | |
1888 | struct mpi_coredump_segment_header xfi_hss_pll_hdr; | |
1889 | u32 serdes_xfi_hss_pll[XG_SERDES_XFI_HSS_PLL_COUNT]; | |
1890 | ||
1891 | /* segment 30 */ | |
1892 | struct mpi_coredump_segment_header misc_nic_seg_hdr; | |
1893 | struct ql_nic_misc misc_nic_info; | |
1894 | ||
1895 | /* segment 31 */ | |
1896 | /* one interrupt state for each CQ */ | |
1897 | struct mpi_coredump_segment_header intr_states_seg_hdr; | |
1898 | u32 intr_states[MAX_RX_RINGS]; | |
1899 | ||
1900 | /* segment 32 */ | |
1901 | /* 3 cam words each for 16 unicast, | |
1902 | * 2 cam words for each of 32 multicast. | |
1903 | */ | |
1904 | struct mpi_coredump_segment_header cam_entries_seg_hdr; | |
1905 | u32 cam_entries[(16 * 3) + (32 * 3)]; | |
1906 | ||
1907 | /* segment 33 */ | |
1908 | struct mpi_coredump_segment_header nic_routing_words_seg_hdr; | |
1909 | u32 nic_routing_words[16]; | |
1910 | /* segment 34 */ | |
1911 | struct mpi_coredump_segment_header ets_seg_hdr; | |
1912 | u32 ets[ETS_REGS_DUMP_WORD_COUNT]; | |
1913 | ||
1914 | /* segment 35 */ | |
1915 | struct mpi_coredump_segment_header probe_dump_seg_hdr; | |
1916 | u32 probe_dump[PRB_MX_DUMP_TOT_COUNT]; | |
1917 | ||
1918 | /* segment 36 */ | |
1919 | struct mpi_coredump_segment_header routing_reg_seg_hdr; | |
1920 | u32 routing_regs[RT_IDX_DUMP_TOT_WORDS]; | |
1921 | ||
1922 | /* segment 37 */ | |
1923 | struct mpi_coredump_segment_header mac_prot_reg_seg_hdr; | |
1924 | u32 mac_prot_regs[MAC_ADDR_DUMP_TOT_WORDS]; | |
1925 | ||
1926 | /* segment 38 */ | |
1927 | struct mpi_coredump_segment_header xaui2_an_hdr; | |
1928 | u32 serdes2_xaui_an[XG_SERDES_XAUI_AN_COUNT]; | |
1929 | ||
1930 | /* segment 39 */ | |
1931 | struct mpi_coredump_segment_header xaui2_hss_pcs_hdr; | |
1932 | u32 serdes2_xaui_hss_pcs[XG_SERDES_XAUI_HSS_PCS_COUNT]; | |
1933 | ||
1934 | /* segment 40 */ | |
1935 | struct mpi_coredump_segment_header xfi2_an_hdr; | |
1936 | u32 serdes2_xfi_an[XG_SERDES_XFI_AN_COUNT]; | |
1937 | ||
1938 | /* segment 41 */ | |
1939 | struct mpi_coredump_segment_header xfi2_train_hdr; | |
1940 | u32 serdes2_xfi_train[XG_SERDES_XFI_TRAIN_COUNT]; | |
1941 | ||
1942 | /* segment 42 */ | |
1943 | struct mpi_coredump_segment_header xfi2_hss_pcs_hdr; | |
1944 | u32 serdes2_xfi_hss_pcs[XG_SERDES_XFI_HSS_PCS_COUNT]; | |
1945 | ||
1946 | /* segment 43 */ | |
1947 | struct mpi_coredump_segment_header xfi2_hss_tx_hdr; | |
1948 | u32 serdes2_xfi_hss_tx[XG_SERDES_XFI_HSS_TX_COUNT]; | |
1949 | ||
1950 | /* segment 44 */ | |
1951 | struct mpi_coredump_segment_header xfi2_hss_rx_hdr; | |
1952 | u32 serdes2_xfi_hss_rx[XG_SERDES_XFI_HSS_RX_COUNT]; | |
1953 | ||
1954 | /* segment 45 */ | |
1955 | struct mpi_coredump_segment_header xfi2_hss_pll_hdr; | |
1956 | u32 serdes2_xfi_hss_pll[XG_SERDES_XFI_HSS_PLL_COUNT]; | |
1957 | ||
1958 | /* segment 50 */ | |
1959 | /* semaphore register for all 5 functions */ | |
1960 | struct mpi_coredump_segment_header sem_regs_seg_hdr; | |
1961 | u32 sem_regs[MAX_SEMAPHORE_FUNCTIONS]; | |
1962 | }; | |
1963 | ||
c4e84bde RM |
1964 | /* |
1965 | * intr_context structure is used during initialization | |
1966 | * to hook the interrupts. It is also used in a single | |
1967 | * irq environment as a context to the ISR. | |
1968 | */ | |
1969 | struct intr_context { | |
1970 | struct ql_adapter *qdev; | |
1971 | u32 intr; | |
39aa8165 | 1972 | u32 irq_mask; /* Mask of which rings the vector services. */ |
c4e84bde RM |
1973 | u32 hooked; |
1974 | u32 intr_en_mask; /* value/mask used to enable this intr */ | |
1975 | u32 intr_dis_mask; /* value/mask used to disable this intr */ | |
1976 | u32 intr_read_mask; /* value/mask used to read this intr */ | |
1977 | char name[IFNAMSIZ * 2]; | |
1978 | atomic_t irq_cnt; /* irq_cnt is used in single vector | |
1979 | * environment. It's incremented for each | |
1980 | * irq handler that is scheduled. When each | |
1981 | * handler finishes it decrements irq_cnt and | |
1982 | * enables interrupts if it's zero. */ | |
1983 | irq_handler_t handler; | |
1984 | }; | |
1985 | ||
1986 | /* adapter flags definitions. */ | |
1987 | enum { | |
fbcbe56c RM |
1988 | QL_ADAPTER_UP = 0, /* Adapter has been brought up. */ |
1989 | QL_LEGACY_ENABLED = 1, | |
1990 | QL_MSI_ENABLED = 2, | |
1991 | QL_MSIX_ENABLED = 3, | |
1992 | QL_DMA64 = 4, | |
1993 | QL_PROMISCUOUS = 5, | |
1994 | QL_ALLMULTI = 6, | |
1995 | QL_PORT_CFG = 7, | |
1996 | QL_CAM_RT_SET = 8, | |
9dfbbaa6 RM |
1997 | QL_SELFTEST = 9, |
1998 | QL_LB_LINK_UP = 10, | |
d5c1da56 | 1999 | QL_FRC_COREDUMP = 11, |
4bbd1a19 | 2000 | QL_EEH_FATAL = 12, |
da92b393 | 2001 | QL_ASIC_RECOVERY = 14, /* We are in ascic recovery. */ |
c4e84bde RM |
2002 | }; |
2003 | ||
2004 | /* link_status bit definitions */ | |
2005 | enum { | |
b82808b7 RM |
2006 | STS_LOOPBACK_MASK = 0x00000700, |
2007 | STS_LOOPBACK_PCS = 0x00000100, | |
2008 | STS_LOOPBACK_HSS = 0x00000200, | |
2009 | STS_LOOPBACK_EXT = 0x00000300, | |
2010 | STS_PAUSE_MASK = 0x000000c0, | |
2011 | STS_PAUSE_STD = 0x00000040, | |
2012 | STS_PAUSE_PRI = 0x00000080, | |
2013 | STS_SPEED_MASK = 0x00000038, | |
2014 | STS_SPEED_100Mb = 0x00000000, | |
2015 | STS_SPEED_1Gb = 0x00000008, | |
2016 | STS_SPEED_10Gb = 0x00000010, | |
2017 | STS_LINK_TYPE_MASK = 0x00000007, | |
2018 | STS_LINK_TYPE_XFI = 0x00000001, | |
2019 | STS_LINK_TYPE_XAUI = 0x00000002, | |
2020 | STS_LINK_TYPE_XFI_BP = 0x00000003, | |
2021 | STS_LINK_TYPE_XAUI_BP = 0x00000004, | |
2022 | STS_LINK_TYPE_10GBASET = 0x00000005, | |
2023 | }; | |
2024 | ||
2025 | /* link_config bit definitions */ | |
2026 | enum { | |
2027 | CFG_JUMBO_FRAME_SIZE = 0x00010000, | |
2028 | CFG_PAUSE_MASK = 0x00000060, | |
2029 | CFG_PAUSE_STD = 0x00000020, | |
2030 | CFG_PAUSE_PRI = 0x00000040, | |
2031 | CFG_DCBX = 0x00000010, | |
2032 | CFG_LOOPBACK_MASK = 0x00000007, | |
2033 | CFG_LOOPBACK_PCS = 0x00000002, | |
2034 | CFG_LOOPBACK_HSS = 0x00000004, | |
2035 | CFG_LOOPBACK_EXT = 0x00000006, | |
2036 | CFG_DEFAULT_MAX_FRAME_SIZE = 0x00002580, | |
c4e84bde RM |
2037 | }; |
2038 | ||
b0c2aadf RM |
2039 | struct nic_operations { |
2040 | ||
2041 | int (*get_flash) (struct ql_adapter *); | |
2042 | int (*port_initialize) (struct ql_adapter *); | |
2043 | }; | |
2044 | ||
c4e84bde RM |
2045 | /* |
2046 | * The main Adapter structure definition. | |
2047 | * This structure has all fields relevant to the hardware. | |
2048 | */ | |
2049 | struct ql_adapter { | |
2050 | struct ricb ricb; | |
2051 | unsigned long flags; | |
2052 | u32 wol; | |
2053 | ||
2054 | struct nic_stats nic_stats; | |
2055 | ||
18c49b91 | 2056 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
c4e84bde RM |
2057 | |
2058 | /* PCI Configuration information for this device */ | |
2059 | struct pci_dev *pdev; | |
2060 | struct net_device *ndev; /* Parent NET device */ | |
2061 | ||
2062 | /* Hardware information */ | |
2063 | u32 chip_rev_id; | |
cfec0cbc | 2064 | u32 fw_rev_id; |
c4e84bde | 2065 | u32 func; /* PCI function for this adapter */ |
e4552f51 RM |
2066 | u32 alt_func; /* PCI function for alternate adapter */ |
2067 | u32 port; /* Port number this adapter */ | |
c4e84bde RM |
2068 | |
2069 | spinlock_t adapter_lock; | |
2070 | spinlock_t hw_lock; | |
2071 | spinlock_t stats_lock; | |
c4e84bde RM |
2072 | |
2073 | /* PCI Bus Relative Register Addresses */ | |
2074 | void __iomem *reg_base; | |
2075 | void __iomem *doorbell_area; | |
2076 | u32 doorbell_area_size; | |
2077 | ||
2078 | u32 msg_enable; | |
2079 | ||
2080 | /* Page for Shadow Registers */ | |
2081 | void *rx_ring_shadow_reg_area; | |
2082 | dma_addr_t rx_ring_shadow_reg_dma; | |
2083 | void *tx_ring_shadow_reg_area; | |
2084 | dma_addr_t tx_ring_shadow_reg_dma; | |
2085 | ||
2086 | u32 mailbox_in; | |
2087 | u32 mailbox_out; | |
bcc2cb3b | 2088 | struct mbox_params idc_mbc; |
4d7b6b5d | 2089 | struct mutex mpi_mutex; |
c4e84bde RM |
2090 | |
2091 | int tx_ring_size; | |
2092 | int rx_ring_size; | |
2093 | u32 intr_count; | |
2094 | struct msix_entry *msi_x_entry; | |
2095 | struct intr_context intr_context[MAX_RX_RINGS]; | |
2096 | ||
c4e84bde | 2097 | int tx_ring_count; /* One per online CPU. */ |
39aa8165 | 2098 | u32 rss_ring_count; /* One per irq vector. */ |
c4e84bde RM |
2099 | /* |
2100 | * rx_ring_count = | |
c4e84bde | 2101 | * (CPU count * outbound completion rx_ring) + |
39aa8165 | 2102 | * (irq_vector_cnt * inbound (RSS) completion rx_ring) |
c4e84bde RM |
2103 | */ |
2104 | int rx_ring_count; | |
2105 | int ring_mem_size; | |
2106 | void *ring_mem; | |
683d46a9 RM |
2107 | |
2108 | struct rx_ring rx_ring[MAX_RX_RINGS]; | |
2109 | struct tx_ring tx_ring[MAX_TX_RINGS]; | |
7c734359 | 2110 | unsigned int lbq_buf_order; |
683d46a9 | 2111 | |
c4e84bde | 2112 | int rx_csum; |
c4e84bde RM |
2113 | u32 default_rx_queue; |
2114 | ||
2115 | u16 rx_coalesce_usecs; /* cqicb->int_delay */ | |
2116 | u16 rx_max_coalesced_frames; /* cqicb->pkt_int_delay */ | |
2117 | u16 tx_coalesce_usecs; /* cqicb->int_delay */ | |
2118 | u16 tx_max_coalesced_frames; /* cqicb->pkt_int_delay */ | |
2119 | ||
2120 | u32 xg_sem_mask; | |
2121 | u32 port_link_up; | |
2122 | u32 port_init; | |
2123 | u32 link_status; | |
b87babeb RM |
2124 | struct ql_mpi_coredump *mpi_coredump; |
2125 | u32 core_is_dumped; | |
bcc2cb3b | 2126 | u32 link_config; |
d8eb59dc | 2127 | u32 led_config; |
bcc2cb3b | 2128 | u32 max_frame_size; |
c4e84bde | 2129 | |
b0c2aadf | 2130 | union flash_params flash; |
c4e84bde | 2131 | |
c4e84bde RM |
2132 | struct workqueue_struct *workqueue; |
2133 | struct delayed_work asic_reset_work; | |
2134 | struct delayed_work mpi_reset_work; | |
2135 | struct delayed_work mpi_work; | |
bcc2cb3b | 2136 | struct delayed_work mpi_port_cfg_work; |
2ee1e272 | 2137 | struct delayed_work mpi_idc_work; |
b87babeb | 2138 | struct delayed_work mpi_core_to_log; |
bcc2cb3b | 2139 | struct completion ide_completion; |
ef9c7ab4 | 2140 | const struct nic_operations *nic_ops; |
b0c2aadf | 2141 | u16 device_id; |
15c052fc | 2142 | struct timer_list timer; |
9dfbbaa6 | 2143 | atomic_t lb_count; |
801e9096 RM |
2144 | /* Keep local copy of current mac address. */ |
2145 | char current_mac_addr[6]; | |
c4e84bde RM |
2146 | }; |
2147 | ||
2148 | /* | |
2149 | * Typical Register accessor for memory mapped device. | |
2150 | */ | |
2151 | static inline u32 ql_read32(const struct ql_adapter *qdev, int reg) | |
2152 | { | |
2153 | return readl(qdev->reg_base + reg); | |
2154 | } | |
2155 | ||
2156 | /* | |
2157 | * Typical Register accessor for memory mapped device. | |
2158 | */ | |
2159 | static inline void ql_write32(const struct ql_adapter *qdev, int reg, u32 val) | |
2160 | { | |
2161 | writel(val, qdev->reg_base + reg); | |
2162 | } | |
2163 | ||
2164 | /* | |
2165 | * Doorbell Registers: | |
2166 | * Doorbell registers are virtual registers in the PCI memory space. | |
2167 | * The space is allocated by the chip during PCI initialization. The | |
2168 | * device driver finds the doorbell address in BAR 3 in PCI config space. | |
2169 | * The registers are used to control outbound and inbound queues. For | |
2170 | * example, the producer index for an outbound queue. Each queue uses | |
2171 | * 1 4k chunk of memory. The lower half of the space is for outbound | |
2172 | * queues. The upper half is for inbound queues. | |
2173 | */ | |
2174 | static inline void ql_write_db_reg(u32 val, void __iomem *addr) | |
2175 | { | |
2176 | writel(val, addr); | |
2177 | mmiowb(); | |
2178 | } | |
2179 | ||
ba7cd3ba RM |
2180 | /* |
2181 | * Shadow Registers: | |
2182 | * Outbound queues have a consumer index that is maintained by the chip. | |
2183 | * Inbound queues have a producer index that is maintained by the chip. | |
2184 | * For lower overhead, these registers are "shadowed" to host memory | |
2185 | * which allows the device driver to track the queue progress without | |
2186 | * PCI reads. When an entry is placed on an inbound queue, the chip will | |
2187 | * update the relevant index register and then copy the value to the | |
2188 | * shadow register in host memory. | |
2189 | */ | |
2190 | static inline u32 ql_read_sh_reg(__le32 *addr) | |
2191 | { | |
2192 | u32 reg; | |
2193 | reg = le32_to_cpu(*addr); | |
2194 | rmb(); | |
2195 | return reg; | |
2196 | } | |
2197 | ||
c4e84bde RM |
2198 | extern char qlge_driver_name[]; |
2199 | extern const char qlge_driver_version[]; | |
2200 | extern const struct ethtool_ops qlge_ethtool_ops; | |
2201 | ||
2202 | extern int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask); | |
2203 | extern void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask); | |
2204 | extern int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data); | |
2205 | extern int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index, | |
2206 | u32 *value); | |
2207 | extern int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value); | |
2208 | extern int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit, | |
2209 | u16 q_id); | |
2210 | void ql_queue_fw_error(struct ql_adapter *qdev); | |
2211 | void ql_mpi_work(struct work_struct *work); | |
2212 | void ql_mpi_reset_work(struct work_struct *work); | |
8aae2600 | 2213 | void ql_mpi_core_to_log(struct work_struct *work); |
c4e84bde RM |
2214 | int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 ebit); |
2215 | void ql_queue_asic_error(struct ql_adapter *qdev); | |
bb0d215c | 2216 | u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr); |
c4e84bde RM |
2217 | void ql_set_ethtool_ops(struct net_device *ndev); |
2218 | int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data); | |
2ee1e272 | 2219 | void ql_mpi_idc_work(struct work_struct *work); |
bcc2cb3b | 2220 | void ql_mpi_port_cfg_work(struct work_struct *work); |
cdca8d02 | 2221 | int ql_mb_get_fw_state(struct ql_adapter *qdev); |
2ee1e272 | 2222 | int ql_cam_route_initialize(struct ql_adapter *qdev); |
e4552f51 | 2223 | int ql_read_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 *data); |
8aae2600 RM |
2224 | int ql_write_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 data); |
2225 | int ql_unpause_mpi_risc(struct ql_adapter *qdev); | |
2226 | int ql_pause_mpi_risc(struct ql_adapter *qdev); | |
2c1f73c3 | 2227 | int ql_hard_reset_mpi_risc(struct ql_adapter *qdev); |
673483c7 | 2228 | int ql_soft_reset_mpi_risc(struct ql_adapter *qdev); |
2c1f73c3 RM |
2229 | int ql_dump_risc_ram_area(struct ql_adapter *qdev, void *buf, |
2230 | u32 ram_addr, int word_count); | |
8aae2600 RM |
2231 | int ql_core_dump(struct ql_adapter *qdev, |
2232 | struct ql_mpi_coredump *mpi_coredump); | |
cfec0cbc | 2233 | int ql_mb_about_fw(struct ql_adapter *qdev); |
bc083ce9 RM |
2234 | int ql_mb_wol_set_magic(struct ql_adapter *qdev, u32 enable_wol); |
2235 | int ql_mb_wol_mode(struct ql_adapter *qdev, u32 wol); | |
d8eb59dc RM |
2236 | int ql_mb_set_led_cfg(struct ql_adapter *qdev, u32 led_config); |
2237 | int ql_mb_get_led_cfg(struct ql_adapter *qdev); | |
6a473308 RM |
2238 | void ql_link_on(struct ql_adapter *qdev); |
2239 | void ql_link_off(struct ql_adapter *qdev); | |
84087f4d | 2240 | int ql_mb_set_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 control); |
1d30df24 RM |
2241 | int ql_mb_get_port_cfg(struct ql_adapter *qdev); |
2242 | int ql_mb_set_port_cfg(struct ql_adapter *qdev); | |
84087f4d | 2243 | int ql_wait_fifo_empty(struct ql_adapter *qdev); |
673483c7 | 2244 | void ql_get_dump(struct ql_adapter *qdev, void *buff); |
a61f8026 RM |
2245 | void ql_gen_reg_dump(struct ql_adapter *qdev, |
2246 | struct ql_reg_dump *mpi_coredump); | |
9dfbbaa6 RM |
2247 | netdev_tx_t ql_lb_send(struct sk_buff *skb, struct net_device *ndev); |
2248 | void ql_check_lb_frame(struct ql_adapter *, struct sk_buff *); | |
d5c1da56 | 2249 | int ql_own_firmware(struct ql_adapter *qdev); |
9dfbbaa6 | 2250 | int ql_clean_lb_rx_ring(struct rx_ring *rx_ring, int budget); |
c4e84bde | 2251 | |
fa274cb7 | 2252 | /* #define QL_ALL_DUMP */ |
2253 | /* #define QL_REG_DUMP */ | |
2254 | /* #define QL_DEV_DUMP */ | |
2255 | /* #define QL_CB_DUMP */ | |
c4e84bde RM |
2256 | /* #define QL_IB_DUMP */ |
2257 | /* #define QL_OB_DUMP */ | |
c4e84bde RM |
2258 | |
2259 | #ifdef QL_REG_DUMP | |
2260 | extern void ql_dump_xgmac_control_regs(struct ql_adapter *qdev); | |
2261 | extern void ql_dump_routing_entries(struct ql_adapter *qdev); | |
2262 | extern void ql_dump_regs(struct ql_adapter *qdev); | |
2263 | #define QL_DUMP_REGS(qdev) ql_dump_regs(qdev) | |
2264 | #define QL_DUMP_ROUTE(qdev) ql_dump_routing_entries(qdev) | |
2265 | #define QL_DUMP_XGMAC_CONTROL_REGS(qdev) ql_dump_xgmac_control_regs(qdev) | |
2266 | #else | |
2267 | #define QL_DUMP_REGS(qdev) | |
2268 | #define QL_DUMP_ROUTE(qdev) | |
2269 | #define QL_DUMP_XGMAC_CONTROL_REGS(qdev) | |
2270 | #endif | |
2271 | ||
2272 | #ifdef QL_STAT_DUMP | |
2273 | extern void ql_dump_stat(struct ql_adapter *qdev); | |
2274 | #define QL_DUMP_STAT(qdev) ql_dump_stat(qdev) | |
2275 | #else | |
2276 | #define QL_DUMP_STAT(qdev) | |
2277 | #endif | |
2278 | ||
2279 | #ifdef QL_DEV_DUMP | |
2280 | extern void ql_dump_qdev(struct ql_adapter *qdev); | |
2281 | #define QL_DUMP_QDEV(qdev) ql_dump_qdev(qdev) | |
2282 | #else | |
2283 | #define QL_DUMP_QDEV(qdev) | |
2284 | #endif | |
2285 | ||
2286 | #ifdef QL_CB_DUMP | |
2287 | extern void ql_dump_wqicb(struct wqicb *wqicb); | |
2288 | extern void ql_dump_tx_ring(struct tx_ring *tx_ring); | |
2289 | extern void ql_dump_ricb(struct ricb *ricb); | |
2290 | extern void ql_dump_cqicb(struct cqicb *cqicb); | |
2291 | extern void ql_dump_rx_ring(struct rx_ring *rx_ring); | |
2292 | extern void ql_dump_hw_cb(struct ql_adapter *qdev, int size, u32 bit, u16 q_id); | |
2293 | #define QL_DUMP_RICB(ricb) ql_dump_ricb(ricb) | |
2294 | #define QL_DUMP_WQICB(wqicb) ql_dump_wqicb(wqicb) | |
2295 | #define QL_DUMP_TX_RING(tx_ring) ql_dump_tx_ring(tx_ring) | |
2296 | #define QL_DUMP_CQICB(cqicb) ql_dump_cqicb(cqicb) | |
2297 | #define QL_DUMP_RX_RING(rx_ring) ql_dump_rx_ring(rx_ring) | |
2298 | #define QL_DUMP_HW_CB(qdev, size, bit, q_id) \ | |
2299 | ql_dump_hw_cb(qdev, size, bit, q_id) | |
2300 | #else | |
2301 | #define QL_DUMP_RICB(ricb) | |
2302 | #define QL_DUMP_WQICB(wqicb) | |
2303 | #define QL_DUMP_TX_RING(tx_ring) | |
2304 | #define QL_DUMP_CQICB(cqicb) | |
2305 | #define QL_DUMP_RX_RING(rx_ring) | |
2306 | #define QL_DUMP_HW_CB(qdev, size, bit, q_id) | |
2307 | #endif | |
2308 | ||
2309 | #ifdef QL_OB_DUMP | |
2310 | extern void ql_dump_tx_desc(struct tx_buf_desc *tbd); | |
2311 | extern void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req *ob_mac_iocb); | |
2312 | extern void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp *ob_mac_rsp); | |
2313 | #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb) ql_dump_ob_mac_iocb(ob_mac_iocb) | |
2314 | #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp) ql_dump_ob_mac_rsp(ob_mac_rsp) | |
2315 | #else | |
2316 | #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb) | |
2317 | #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp) | |
2318 | #endif | |
2319 | ||
2320 | #ifdef QL_IB_DUMP | |
2321 | extern void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp); | |
2322 | #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp) ql_dump_ib_mac_rsp(ib_mac_rsp) | |
2323 | #else | |
2324 | #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp) | |
2325 | #endif | |
2326 | ||
2327 | #ifdef QL_ALL_DUMP | |
2328 | extern void ql_dump_all(struct ql_adapter *qdev); | |
2329 | #define QL_DUMP_ALL(qdev) ql_dump_all(qdev) | |
2330 | #else | |
2331 | #define QL_DUMP_ALL(qdev) | |
2332 | #endif | |
2333 | ||
2334 | #endif /* _QLGE_H_ */ |