projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
qlge: Add RX frame handlers for non-split frames.
[deliverable/linux.git] / drivers / net / qlge / qlge_main.c
CommitLineData
c4e84bde
RM		 1/*
2 * QLogic qlge NIC HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 * See LICENSE.qlge for copyright and licensing details.
5 * Author: Linux qlge network device driver by
6 * Ron Mercer <ron.mercer@qlogic.com>
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/list.h>
13#include <linux/pci.h>
14#include <linux/dma-mapping.h>
15#include <linux/pagemap.h>
16#include <linux/sched.h>
17#include <linux/slab.h>
18#include <linux/dmapool.h>
19#include <linux/mempool.h>
20#include <linux/spinlock.h>
21#include <linux/kthread.h>
22#include <linux/interrupt.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/in.h>
26#include <linux/ip.h>
27#include <linux/ipv6.h>
28#include <net/ipv6.h>
29#include <linux/tcp.h>
30#include <linux/udp.h>
31#include <linux/if_arp.h>
32#include <linux/if_ether.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/skbuff.h>
c4e84bde 37#include <linux/if_vlan.h>
c4e84bde
RM		 38#include <linux/delay.h>
39#include <linux/mm.h>
40#include <linux/vmalloc.h>
b7c6bfb7 41#include <net/ip6_checksum.h>
c4e84bde
RM		 42
43#include "qlge.h"
44
45char qlge_driver_name[] = DRV_NAME;
46const char qlge_driver_version[] = DRV_VERSION;
47
48MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
49MODULE_DESCRIPTION(DRV_STRING " ");
50MODULE_LICENSE("GPL");
51MODULE_VERSION(DRV_VERSION);
52
53static const u32 default_msg =
54 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
55/* NETIF_MSG_TIMER | */
56 NETIF_MSG_IFDOWN |
57 NETIF_MSG_IFUP |
58 NETIF_MSG_RX_ERR |
59 NETIF_MSG_TX_ERR |
4974097a
RM		 60/* NETIF_MSG_TX_QUEUED | */
61/* NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
c4e84bde
RM		 62/* NETIF_MSG_PKTDATA | */
63 NETIF_MSG_HW | NETIF_MSG_WOL | 0;
64
65static int debug = 0x00007fff; /* defaults above */
66module_param(debug, int, 0);
67MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
68
69#define MSIX_IRQ 0
70#define MSI_IRQ 1
71#define LEG_IRQ 2
a5a62a1c
RM		 72static int qlge_irq_type = MSIX_IRQ;
73module_param(qlge_irq_type, int, MSIX_IRQ);
74MODULE_PARM_DESC(qlge_irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
c4e84bde
RM		 75
76static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
b0c2aadf 77 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
cdca8d02 78 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8000)},
c4e84bde
RM		 79 /* required last entry */
80 {0,}
81};
82
83MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
84
85/* This hardware semaphore causes exclusive access to
86 * resources shared between the NIC driver, MPI firmware,
87 * FCOE firmware and the FC driver.
88 */
89static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
90{
91 u32 sem_bits = 0;
92
93 switch (sem_mask) {
94 case SEM_XGMAC0_MASK:
95 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
96 break;
97 case SEM_XGMAC1_MASK:
98 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
99 break;
100 case SEM_ICB_MASK:
101 sem_bits = SEM_SET << SEM_ICB_SHIFT;
102 break;
103 case SEM_MAC_ADDR_MASK:
104 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
105 break;
106 case SEM_FLASH_MASK:
107 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
108 break;
109 case SEM_PROBE_MASK:
110 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
111 break;
112 case SEM_RT_IDX_MASK:
113 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
114 break;
115 case SEM_PROC_REG_MASK:
116 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
117 break;
118 default:
119 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
120 return -EINVAL;
121 }
122
123 ql_write32(qdev, SEM, sem_bits | sem_mask);
124 return !(ql_read32(qdev, SEM) & sem_bits);
125}
126
127int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
128{
0857e9d7 129 unsigned int wait_count = 30;
c4e84bde
RM		 130 do {
131 if (!ql_sem_trylock(qdev, sem_mask))
132 return 0;
0857e9d7
RM		 133 udelay(100);
134 } while (--wait_count);
c4e84bde
RM		 135 return -ETIMEDOUT;
136}
137
138void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
139{
140 ql_write32(qdev, SEM, sem_mask);
141 ql_read32(qdev, SEM); /* flush */
142}
143
144/* This function waits for a specific bit to come ready
145 * in a given register. It is used mostly by the initialize
146 * process, but is also used in kernel thread API such as
147 * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
148 */
149int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
150{
151 u32 temp;
152 int count = UDELAY_COUNT;
153
154 while (count) {
155 temp = ql_read32(qdev, reg);
156
157 /* check for errors */
158 if (temp & err_bit) {
159 QPRINTK(qdev, PROBE, ALERT,
160 "register 0x%.08x access error, value = 0x%.08x!.\n",
161 reg, temp);
162 return -EIO;
163 } else if (temp & bit)
164 return 0;
165 udelay(UDELAY_DELAY);
166 count--;
167 }
168 QPRINTK(qdev, PROBE, ALERT,
169 "Timed out waiting for reg %x to come ready.\n", reg);
170 return -ETIMEDOUT;
171}
172
173/* The CFG register is used to download TX and RX control blocks
174 * to the chip. This function waits for an operation to complete.
175 */
176static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
177{
178 int count = UDELAY_COUNT;
179 u32 temp;
180
181 while (count) {
182 temp = ql_read32(qdev, CFG);
183 if (temp & CFG_LE)
184 return -EIO;
185 if (!(temp & bit))
186 return 0;
187 udelay(UDELAY_DELAY);
188 count--;
189 }
190 return -ETIMEDOUT;
191}
192
193
194/* Used to issue init control blocks to hw. Maps control block,
195 * sets address, triggers download, waits for completion.
196 */
197int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
198 u16 q_id)
199{
200 u64 map;
201 int status = 0;
202 int direction;
203 u32 mask;
204 u32 value;
205
206 direction =
207 (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
208 PCI_DMA_FROMDEVICE;
209
210 map = pci_map_single(qdev->pdev, ptr, size, direction);
211 if (pci_dma_mapping_error(qdev->pdev, map)) {
212 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
213 return -ENOMEM;
214 }
215
4322c5be
RM		 216 status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
217 if (status)
218 return status;
219
c4e84bde
RM		 220 status = ql_wait_cfg(qdev, bit);
221 if (status) {
222 QPRINTK(qdev, IFUP, ERR,
223 "Timed out waiting for CFG to come ready.\n");
224 goto exit;
225 }
226
c4e84bde
RM		 227 ql_write32(qdev, ICB_L, (u32) map);
228 ql_write32(qdev, ICB_H, (u32) (map >> 32));
c4e84bde
RM		 229
230 mask = CFG_Q_MASK | (bit << 16);
231 value = bit | (q_id << CFG_Q_SHIFT);
232 ql_write32(qdev, CFG, (mask | value));
233
234 /*
235 * Wait for the bit to clear after signaling hw.
236 */
237 status = ql_wait_cfg(qdev, bit);
238exit:
4322c5be 239 ql_sem_unlock(qdev, SEM_ICB_MASK); /* does flush too */
c4e84bde
RM		 240 pci_unmap_single(qdev->pdev, map, size, direction);
241 return status;
242}
243
244/* Get a specific MAC address from the CAM. Used for debug and reg dump. */
245int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
246 u32 *value)
247{
248 u32 offset = 0;
249 int status;
250
c4e84bde
RM		 251 switch (type) {
252 case MAC_ADDR_TYPE_MULTI_MAC:
253 case MAC_ADDR_TYPE_CAM_MAC:
254 {
255 status =
256 ql_wait_reg_rdy(qdev,
939678f8 257 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 258 if (status)
259 goto exit;
260 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
261 (index << MAC_ADDR_IDX_SHIFT) | /* index */
262 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
263 status =
264 ql_wait_reg_rdy(qdev,
939678f8 265 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
c4e84bde
RM		 266 if (status)
267 goto exit;
268 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
269 status =
270 ql_wait_reg_rdy(qdev,
939678f8 271 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 272 if (status)
273 goto exit;
274 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
275 (index << MAC_ADDR_IDX_SHIFT) | /* index */
276 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
277 status =
278 ql_wait_reg_rdy(qdev,
939678f8 279 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
c4e84bde
RM		 280 if (status)
281 goto exit;
282 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
283 if (type == MAC_ADDR_TYPE_CAM_MAC) {
284 status =
285 ql_wait_reg_rdy(qdev,
939678f8 286 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 287 if (status)
288 goto exit;
289 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
290 (index << MAC_ADDR_IDX_SHIFT) | /* index */
291 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
292 status =
293 ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
939678f8 294 MAC_ADDR_MR, 0);
c4e84bde
RM		 295 if (status)
296 goto exit;
297 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
298 }
299 break;
300 }
301 case MAC_ADDR_TYPE_VLAN:
302 case MAC_ADDR_TYPE_MULTI_FLTR:
303 default:
304 QPRINTK(qdev, IFUP, CRIT,
305 "Address type %d not yet supported.\n", type);
306 status = -EPERM;
307 }
308exit:
c4e84bde
RM		 309 return status;
310}
311
312/* Set up a MAC, multicast or VLAN address for the
313 * inbound frame matching.
314 */
315static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
316 u16 index)
317{
318 u32 offset = 0;
319 int status = 0;
320
c4e84bde
RM		 321 switch (type) {
322 case MAC_ADDR_TYPE_MULTI_MAC:
76b26694
RM		 323 {
324 u32 upper = (addr[0] << 8) | addr[1];
325 u32 lower = (addr[2] << 24) | (addr[3] << 16) |
326 (addr[4] << 8) | (addr[5]);
327
328 status =
329 ql_wait_reg_rdy(qdev,
330 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
331 if (status)
332 goto exit;
333 ql_write32(qdev, MAC_ADDR_IDX, (offset++) |
334 (index << MAC_ADDR_IDX_SHIFT) |
335 type | MAC_ADDR_E);
336 ql_write32(qdev, MAC_ADDR_DATA, lower);
337 status =
338 ql_wait_reg_rdy(qdev,
339 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
340 if (status)
341 goto exit;
342 ql_write32(qdev, MAC_ADDR_IDX, (offset++) |
343 (index << MAC_ADDR_IDX_SHIFT) |
344 type | MAC_ADDR_E);
345
346 ql_write32(qdev, MAC_ADDR_DATA, upper);
347 status =
348 ql_wait_reg_rdy(qdev,
349 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
350 if (status)
351 goto exit;
352 break;
353 }
c4e84bde
RM		 354 case MAC_ADDR_TYPE_CAM_MAC:
355 {
356 u32 cam_output;
357 u32 upper = (addr[0] << 8) | addr[1];
358 u32 lower =
359 (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
360 (addr[5]);
361
4974097a 362 QPRINTK(qdev, IFUP, DEBUG,
7c510e4b 363 "Adding %s address %pM"
c4e84bde
RM		 364 " at index %d in the CAM.\n",
365 ((type ==
366 MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
7c510e4b 367 "UNICAST"), addr, index);
c4e84bde
RM		 368
369 status =
370 ql_wait_reg_rdy(qdev,
939678f8 371 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 372 if (status)
373 goto exit;
374 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
375 (index << MAC_ADDR_IDX_SHIFT) | /* index */
376 type); /* type */
377 ql_write32(qdev, MAC_ADDR_DATA, lower);
378 status =
379 ql_wait_reg_rdy(qdev,
939678f8 380 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 381 if (status)
382 goto exit;
383 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
384 (index << MAC_ADDR_IDX_SHIFT) | /* index */
385 type); /* type */
386 ql_write32(qdev, MAC_ADDR_DATA, upper);
387 status =
388 ql_wait_reg_rdy(qdev,
939678f8 389 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 390 if (status)
391 goto exit;
392 ql_write32(qdev, MAC_ADDR_IDX, (offset) | /* offset */
393 (index << MAC_ADDR_IDX_SHIFT) | /* index */
394 type); /* type */
395 /* This field should also include the queue id
396 and possibly the function id. Right now we hardcode
397 the route field to NIC core.
398 */
76b26694
RM		 399 cam_output = (CAM_OUT_ROUTE_NIC |
400 (qdev->
401 func << CAM_OUT_FUNC_SHIFT) |
402 (0 << CAM_OUT_CQ_ID_SHIFT));
403 if (qdev->vlgrp)
404 cam_output |= CAM_OUT_RV;
405 /* route to NIC core */
406 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
c4e84bde
RM		 407 break;
408 }
409 case MAC_ADDR_TYPE_VLAN:
410 {
411 u32 enable_bit = *((u32 *) &addr[0]);
412 /* For VLAN, the addr actually holds a bit that
413 * either enables or disables the vlan id we are
414 * addressing. It's either MAC_ADDR_E on or off.
415 * That's bit-27 we're talking about.
416 */
417 QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
418 (enable_bit ? "Adding" : "Removing"),
419 index, (enable_bit ? "to" : "from"));
420
421 status =
422 ql_wait_reg_rdy(qdev,
939678f8 423 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 424 if (status)
425 goto exit;
426 ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
427 (index << MAC_ADDR_IDX_SHIFT) | /* index */
428 type | /* type */
429 enable_bit); /* enable/disable */
430 break;
431 }
432 case MAC_ADDR_TYPE_MULTI_FLTR:
433 default:
434 QPRINTK(qdev, IFUP, CRIT,
435 "Address type %d not yet supported.\n", type);
436 status = -EPERM;
437 }
438exit:
c4e84bde
RM		 439 return status;
440}
441
7fab3bfe
RM		 442/* Set or clear MAC address in hardware. We sometimes
443 * have to clear it to prevent wrong frame routing
444 * especially in a bonding environment.
445 */
446static int ql_set_mac_addr(struct ql_adapter *qdev, int set)
447{
448 int status;
449 char zero_mac_addr[ETH_ALEN];
450 char *addr;
451
452 if (set) {
453 addr = &qdev->ndev->dev_addr[0];
454 QPRINTK(qdev, IFUP, DEBUG,
455 "Set Mac addr %02x:%02x:%02x:%02x:%02x:%02x\n",
456 addr[0], addr[1], addr[2], addr[3],
457 addr[4], addr[5]);
458 } else {
459 memset(zero_mac_addr, 0, ETH_ALEN);
460 addr = &zero_mac_addr[0];
461 QPRINTK(qdev, IFUP, DEBUG,
462 "Clearing MAC address on %s\n",
463 qdev->ndev->name);
464 }
465 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
466 if (status)
467 return status;
468 status = ql_set_mac_addr_reg(qdev, (u8 *) addr,
469 MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
470 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
471 if (status)
472 QPRINTK(qdev, IFUP, ERR, "Failed to init mac "
473 "address.\n");
474 return status;
475}
476
6a473308
RM		 477void ql_link_on(struct ql_adapter *qdev)
478{
479 QPRINTK(qdev, LINK, ERR, "%s: Link is up.\n",
480 qdev->ndev->name);
481 netif_carrier_on(qdev->ndev);
482 ql_set_mac_addr(qdev, 1);
483}
484
485void ql_link_off(struct ql_adapter *qdev)
486{
487 QPRINTK(qdev, LINK, ERR, "%s: Link is down.\n",
488 qdev->ndev->name);
489 netif_carrier_off(qdev->ndev);
490 ql_set_mac_addr(qdev, 0);
491}
492
c4e84bde
RM		 493/* Get a specific frame routing value from the CAM.
494 * Used for debug and reg dump.
495 */
496int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
497{
498 int status = 0;
499
939678f8 500 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
c4e84bde
RM		 501 if (status)
502 goto exit;
503
504 ql_write32(qdev, RT_IDX,
505 RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
939678f8 506 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
c4e84bde
RM		 507 if (status)
508 goto exit;
509 *value = ql_read32(qdev, RT_DATA);
510exit:
c4e84bde
RM		 511 return status;
512}
513
514/* The NIC function for this chip has 16 routing indexes. Each one can be used
515 * to route different frame types to various inbound queues. We send broadcast/
516 * multicast/error frames to the default queue for slow handling,
517 * and CAM hit/RSS frames to the fast handling queues.
518 */
519static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
520 int enable)
521{
8587ea35 522 int status = -EINVAL; /* Return error if no mask match. */
c4e84bde
RM		 523 u32 value = 0;
524
c4e84bde
RM		 525 QPRINTK(qdev, IFUP, DEBUG,
526 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
527 (enable ? "Adding" : "Removing"),
528 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
529 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
530 ((index ==
531 RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
532 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
533 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
534 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
535 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
536 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
537 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
538 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
539 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
540 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
541 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
542 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
543 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
544 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
545 (enable ? "to" : "from"));
546
547 switch (mask) {
548 case RT_IDX_CAM_HIT:
549 {
550 value = RT_IDX_DST_CAM_Q | /* dest */
551 RT_IDX_TYPE_NICQ | /* type */
552 (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
553 break;
554 }
555 case RT_IDX_VALID: /* Promiscuous Mode frames. */
556 {
557 value = RT_IDX_DST_DFLT_Q | /* dest */
558 RT_IDX_TYPE_NICQ | /* type */
559 (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
560 break;
561 }
562 case RT_IDX_ERR: /* Pass up MAC,IP,TCP/UDP error frames. */
563 {
564 value = RT_IDX_DST_DFLT_Q | /* dest */
565 RT_IDX_TYPE_NICQ | /* type */
566 (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
567 break;
568 }
569 case RT_IDX_BCAST: /* Pass up Broadcast frames to default Q. */
570 {
571 value = RT_IDX_DST_DFLT_Q | /* dest */
572 RT_IDX_TYPE_NICQ | /* type */
573 (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
574 break;
575 }
576 case RT_IDX_MCAST: /* Pass up All Multicast frames. */
577 {
e163d7f2 578 value = RT_IDX_DST_DFLT_Q | /* dest */
c4e84bde
RM		 579 RT_IDX_TYPE_NICQ | /* type */
580 (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
581 break;
582 }
583 case RT_IDX_MCAST_MATCH: /* Pass up matched Multicast frames. */
584 {
e163d7f2 585 value = RT_IDX_DST_DFLT_Q | /* dest */
c4e84bde
RM		 586 RT_IDX_TYPE_NICQ | /* type */
587 (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
588 break;
589 }
590 case RT_IDX_RSS_MATCH: /* Pass up matched RSS frames. */
591 {
592 value = RT_IDX_DST_RSS | /* dest */
593 RT_IDX_TYPE_NICQ | /* type */
594 (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
595 break;
596 }
597 case 0: /* Clear the E-bit on an entry. */
598 {
599 value = RT_IDX_DST_DFLT_Q | /* dest */
600 RT_IDX_TYPE_NICQ | /* type */
601 (index << RT_IDX_IDX_SHIFT);/* index */
602 break;
603 }
604 default:
605 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
606 mask);
607 status = -EPERM;
608 goto exit;
609 }
610
611 if (value) {
612 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
613 if (status)
614 goto exit;
615 value |= (enable ? RT_IDX_E : 0);
616 ql_write32(qdev, RT_IDX, value);
617 ql_write32(qdev, RT_DATA, enable ? mask : 0);
618 }
619exit:
c4e84bde
RM		 620 return status;
621}
622
623static void ql_enable_interrupts(struct ql_adapter *qdev)
624{
625 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
626}
627
628static void ql_disable_interrupts(struct ql_adapter *qdev)
629{
630 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
631}
632
633/* If we're running with multiple MSI-X vectors then we enable on the fly.
634 * Otherwise, we may have multiple outstanding workers and don't want to
635 * enable until the last one finishes. In this case, the irq_cnt gets
636 * incremented everytime we queue a worker and decremented everytime
637 * a worker finishes. Once it hits zero we enable the interrupt.
638 */
bb0d215c 639u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
c4e84bde 640{
bb0d215c
RM		 641 u32 var = 0;
642 unsigned long hw_flags = 0;
643 struct intr_context *ctx = qdev->intr_context + intr;
644
645 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
646 /* Always enable if we're MSIX multi interrupts and
647 * it's not the default (zeroeth) interrupt.
648 */
c4e84bde 649 ql_write32(qdev, INTR_EN,
bb0d215c
RM		 650 ctx->intr_en_mask);
651 var = ql_read32(qdev, STS);
652 return var;
c4e84bde 653 }
bb0d215c
RM		 654
655 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
656 if (atomic_dec_and_test(&ctx->irq_cnt)) {
657 ql_write32(qdev, INTR_EN,
658 ctx->intr_en_mask);
659 var = ql_read32(qdev, STS);
660 }
661 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
662 return var;
c4e84bde
RM		 663}
664
665static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
666{
667 u32 var = 0;
bb0d215c 668 struct intr_context *ctx;
c4e84bde 669
bb0d215c
RM		 670 /* HW disables for us if we're MSIX multi interrupts and
671 * it's not the default (zeroeth) interrupt.
672 */
673 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
674 return 0;
675
676 ctx = qdev->intr_context + intr;
08b1bc8f 677 spin_lock(&qdev->hw_lock);
bb0d215c 678 if (!atomic_read(&ctx->irq_cnt)) {
c4e84bde 679 ql_write32(qdev, INTR_EN,
bb0d215c 680 ctx->intr_dis_mask);
c4e84bde
RM		 681 var = ql_read32(qdev, STS);
682 }
bb0d215c 683 atomic_inc(&ctx->irq_cnt);
08b1bc8f 684 spin_unlock(&qdev->hw_lock);
c4e84bde
RM		 685 return var;
686}
687
688static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
689{
690 int i;
691 for (i = 0; i < qdev->intr_count; i++) {
692 /* The enable call does a atomic_dec_and_test
693 * and enables only if the result is zero.
694 * So we precharge it here.
695 */
bb0d215c
RM		 696 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
697 i == 0))
698 atomic_set(&qdev->intr_context[i].irq_cnt, 1);
c4e84bde
RM		 699 ql_enable_completion_interrupt(qdev, i);
700 }
701
702}
703
b0c2aadf
RM		 704static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
705{
706 int status, i;
707 u16 csum = 0;
708 __le16 *flash = (__le16 *)&qdev->flash;
709
710 status = strncmp((char *)&qdev->flash, str, 4);
711 if (status) {
712 QPRINTK(qdev, IFUP, ERR, "Invalid flash signature.\n");
713 return status;
714 }
715
716 for (i = 0; i < size; i++)
717 csum += le16_to_cpu(*flash++);
718
719 if (csum)
720 QPRINTK(qdev, IFUP, ERR,
721 "Invalid flash checksum, csum = 0x%.04x.\n", csum);
722
723 return csum;
724}
725
26351479 726static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
c4e84bde
RM		 727{
728 int status = 0;
729 /* wait for reg to come ready */
730 status = ql_wait_reg_rdy(qdev,
731 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
732 if (status)
733 goto exit;
734 /* set up for reg read */
735 ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
736 /* wait for reg to come ready */
737 status = ql_wait_reg_rdy(qdev,
738 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
739 if (status)
740 goto exit;
26351479
RM		 741 /* This data is stored on flash as an array of
742 * __le32. Since ql_read32() returns cpu endian
743 * we need to swap it back.
744 */
745 *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
c4e84bde
RM		 746exit:
747 return status;
748}
749
cdca8d02
RM		 750static int ql_get_8000_flash_params(struct ql_adapter *qdev)
751{
752 u32 i, size;
753 int status;
754 __le32 *p = (__le32 *)&qdev->flash;
755 u32 offset;
542512e4 756 u8 mac_addr[6];
cdca8d02
RM		 757
758 /* Get flash offset for function and adjust
759 * for dword access.
760 */
e4552f51 761 if (!qdev->port)
cdca8d02
RM		 762 offset = FUNC0_FLASH_OFFSET / sizeof(u32);
763 else
764 offset = FUNC1_FLASH_OFFSET / sizeof(u32);
765
766 if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
767 return -ETIMEDOUT;
768
769 size = sizeof(struct flash_params_8000) / sizeof(u32);
770 for (i = 0; i < size; i++, p++) {
771 status = ql_read_flash_word(qdev, i+offset, p);
772 if (status) {
773 QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
774 goto exit;
775 }
776 }
777
778 status = ql_validate_flash(qdev,
779 sizeof(struct flash_params_8000) / sizeof(u16),
780 "8000");
781 if (status) {
782 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
783 status = -EINVAL;
784 goto exit;
785 }
786
542512e4
RM		 787 /* Extract either manufacturer or BOFM modified
788 * MAC address.
789 */
790 if (qdev->flash.flash_params_8000.data_type1 == 2)
791 memcpy(mac_addr,
792 qdev->flash.flash_params_8000.mac_addr1,
793 qdev->ndev->addr_len);
794 else
795 memcpy(mac_addr,
796 qdev->flash.flash_params_8000.mac_addr,
797 qdev->ndev->addr_len);
798
799 if (!is_valid_ether_addr(mac_addr)) {
cdca8d02
RM		 800 QPRINTK(qdev, IFUP, ERR, "Invalid MAC address.\n");
801 status = -EINVAL;
802 goto exit;
803 }
804
805 memcpy(qdev->ndev->dev_addr,
542512e4 806 mac_addr,
cdca8d02
RM		 807 qdev->ndev->addr_len);
808
809exit:
810 ql_sem_unlock(qdev, SEM_FLASH_MASK);
811 return status;
812}
813
b0c2aadf 814static int ql_get_8012_flash_params(struct ql_adapter *qdev)
c4e84bde
RM		 815{
816 int i;
817 int status;
26351479 818 __le32 *p = (__le32 *)&qdev->flash;
e78f5fa7 819 u32 offset = 0;
b0c2aadf 820 u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
e78f5fa7
RM		 821
822 /* Second function's parameters follow the first
823 * function's.
824 */
e4552f51 825 if (qdev->port)
b0c2aadf 826 offset = size;
c4e84bde
RM		 827
828 if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
829 return -ETIMEDOUT;
830
b0c2aadf 831 for (i = 0; i < size; i++, p++) {
e78f5fa7 832 status = ql_read_flash_word(qdev, i+offset, p);
c4e84bde
RM		 833 if (status) {
834 QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
835 goto exit;
836 }
837
838 }
b0c2aadf
RM		 839
840 status = ql_validate_flash(qdev,
841 sizeof(struct flash_params_8012) / sizeof(u16),
842 "8012");
843 if (status) {
844 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
845 status = -EINVAL;
846 goto exit;
847 }
848
849 if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
850 status = -EINVAL;
851 goto exit;
852 }
853
854 memcpy(qdev->ndev->dev_addr,
855 qdev->flash.flash_params_8012.mac_addr,
856 qdev->ndev->addr_len);
857
c4e84bde
RM		 858exit:
859 ql_sem_unlock(qdev, SEM_FLASH_MASK);
860 return status;
861}
862
863/* xgmac register are located behind the xgmac_addr and xgmac_data
864 * register pair. Each read/write requires us to wait for the ready
865 * bit before reading/writing the data.
866 */
867static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
868{
869 int status;
870 /* wait for reg to come ready */
871 status = ql_wait_reg_rdy(qdev,
872 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
873 if (status)
874 return status;
875 /* write the data to the data reg */
876 ql_write32(qdev, XGMAC_DATA, data);
877 /* trigger the write */
878 ql_write32(qdev, XGMAC_ADDR, reg);
879 return status;
880}
881
882/* xgmac register are located behind the xgmac_addr and xgmac_data
883 * register pair. Each read/write requires us to wait for the ready
884 * bit before reading/writing the data.
885 */
886int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
887{
888 int status = 0;
889 /* wait for reg to come ready */
890 status = ql_wait_reg_rdy(qdev,
891 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
892 if (status)
893 goto exit;
894 /* set up for reg read */
895 ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
896 /* wait for reg to come ready */
897 status = ql_wait_reg_rdy(qdev,
898 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
899 if (status)
900 goto exit;
901 /* get the data */
902 *data = ql_read32(qdev, XGMAC_DATA);
903exit:
904 return status;
905}
906
907/* This is used for reading the 64-bit statistics regs. */
908int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
909{
910 int status = 0;
911 u32 hi = 0;
912 u32 lo = 0;
913
914 status = ql_read_xgmac_reg(qdev, reg, &lo);
915 if (status)
916 goto exit;
917
918 status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
919 if (status)
920 goto exit;
921
922 *data = (u64) lo | ((u64) hi << 32);
923
924exit:
925 return status;
926}
927
cdca8d02
RM		 928static int ql_8000_port_initialize(struct ql_adapter *qdev)
929{
bcc2cb3b 930 int status;
cfec0cbc
RM		 931 /*
932 * Get MPI firmware version for driver banner
933 * and ethool info.
934 */
935 status = ql_mb_about_fw(qdev);
936 if (status)
937 goto exit;
bcc2cb3b
RM		 938 status = ql_mb_get_fw_state(qdev);
939 if (status)
940 goto exit;
941 /* Wake up a worker to get/set the TX/RX frame sizes. */
942 queue_delayed_work(qdev->workqueue, &qdev->mpi_port_cfg_work, 0);
943exit:
944 return status;
cdca8d02
RM		 945}
946
c4e84bde
RM		 947/* Take the MAC Core out of reset.
948 * Enable statistics counting.
949 * Take the transmitter/receiver out of reset.
950 * This functionality may be done in the MPI firmware at a
951 * later date.
952 */
b0c2aadf 953static int ql_8012_port_initialize(struct ql_adapter *qdev)
c4e84bde
RM		 954{
955 int status = 0;
956 u32 data;
957
958 if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
959 /* Another function has the semaphore, so
960 * wait for the port init bit to come ready.
961 */
962 QPRINTK(qdev, LINK, INFO,
963 "Another function has the semaphore, so wait for the port init bit to come ready.\n");
964 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
965 if (status) {
966 QPRINTK(qdev, LINK, CRIT,
967 "Port initialize timed out.\n");
968 }
969 return status;
970 }
971
972 QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
973 /* Set the core reset. */
974 status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
975 if (status)
976 goto end;
977 data |= GLOBAL_CFG_RESET;
978 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
979 if (status)
980 goto end;
981
982 /* Clear the core reset and turn on jumbo for receiver. */
983 data &= ~GLOBAL_CFG_RESET; /* Clear core reset. */
984 data |= GLOBAL_CFG_JUMBO; /* Turn on jumbo. */
985 data |= GLOBAL_CFG_TX_STAT_EN;
986 data |= GLOBAL_CFG_RX_STAT_EN;
987 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
988 if (status)
989 goto end;
990
991 /* Enable transmitter, and clear it's reset. */
992 status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
993 if (status)
994 goto end;
995 data &= ~TX_CFG_RESET; /* Clear the TX MAC reset. */
996 data |= TX_CFG_EN; /* Enable the transmitter. */
997 status = ql_write_xgmac_reg(qdev, TX_CFG, data);
998 if (status)
999 goto end;
1000
1001 /* Enable receiver and clear it's reset. */
1002 status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
1003 if (status)
1004 goto end;
1005 data &= ~RX_CFG_RESET; /* Clear the RX MAC reset. */
1006 data |= RX_CFG_EN; /* Enable the receiver. */
1007 status = ql_write_xgmac_reg(qdev, RX_CFG, data);
1008 if (status)
1009 goto end;
1010
1011 /* Turn on jumbo. */
1012 status =
1013 ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
1014 if (status)
1015 goto end;
1016 status =
1017 ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
1018 if (status)
1019 goto end;
1020
1021 /* Signal to the world that the port is enabled. */
1022 ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
1023end:
1024 ql_sem_unlock(qdev, qdev->xg_sem_mask);
1025 return status;
1026}
1027
7c734359
RM		 1028static inline unsigned int ql_lbq_block_size(struct ql_adapter *qdev)
1029{
1030 return PAGE_SIZE << qdev->lbq_buf_order;
1031}
1032
c4e84bde 1033/* Get the next large buffer. */
8668ae92 1034static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
c4e84bde
RM		 1035{
1036 struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
1037 rx_ring->lbq_curr_idx++;
1038 if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
1039 rx_ring->lbq_curr_idx = 0;
1040 rx_ring->lbq_free_cnt++;
1041 return lbq_desc;
1042}
1043
7c734359
RM		 1044static struct bq_desc *ql_get_curr_lchunk(struct ql_adapter *qdev,
1045 struct rx_ring *rx_ring)
1046{
1047 struct bq_desc *lbq_desc = ql_get_curr_lbuf(rx_ring);
1048
1049 pci_dma_sync_single_for_cpu(qdev->pdev,
1050 pci_unmap_addr(lbq_desc, mapaddr),
1051 rx_ring->lbq_buf_size,
1052 PCI_DMA_FROMDEVICE);
1053
1054 /* If it's the last chunk of our master page then
1055 * we unmap it.
1056 */
1057 if ((lbq_desc->p.pg_chunk.offset + rx_ring->lbq_buf_size)
1058 == ql_lbq_block_size(qdev))
1059 pci_unmap_page(qdev->pdev,
1060 lbq_desc->p.pg_chunk.map,
1061 ql_lbq_block_size(qdev),
1062 PCI_DMA_FROMDEVICE);
1063 return lbq_desc;
1064}
1065
c4e84bde 1066/* Get the next small buffer. */
8668ae92 1067static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
c4e84bde
RM		 1068{
1069 struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
1070 rx_ring->sbq_curr_idx++;
1071 if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
1072 rx_ring->sbq_curr_idx = 0;
1073 rx_ring->sbq_free_cnt++;
1074 return sbq_desc;
1075}
1076
1077/* Update an rx ring index. */
1078static void ql_update_cq(struct rx_ring *rx_ring)
1079{
1080 rx_ring->cnsmr_idx++;
1081 rx_ring->curr_entry++;
1082 if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
1083 rx_ring->cnsmr_idx = 0;
1084 rx_ring->curr_entry = rx_ring->cq_base;
1085 }
1086}
1087
1088static void ql_write_cq_idx(struct rx_ring *rx_ring)
1089{
1090 ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
1091}
1092
7c734359
RM		 1093static int ql_get_next_chunk(struct ql_adapter *qdev, struct rx_ring *rx_ring,
1094 struct bq_desc *lbq_desc)
1095{
1096 if (!rx_ring->pg_chunk.page) {
1097 u64 map;
1098 rx_ring->pg_chunk.page = alloc_pages(__GFP_COLD | __GFP_COMP |
1099 GFP_ATOMIC,
1100 qdev->lbq_buf_order);
1101 if (unlikely(!rx_ring->pg_chunk.page)) {
1102 QPRINTK(qdev, DRV, ERR,
1103 "page allocation failed.\n");
1104 return -ENOMEM;
1105 }
1106 rx_ring->pg_chunk.offset = 0;
1107 map = pci_map_page(qdev->pdev, rx_ring->pg_chunk.page,
1108 0, ql_lbq_block_size(qdev),
1109 PCI_DMA_FROMDEVICE);
1110 if (pci_dma_mapping_error(qdev->pdev, map)) {
1111 __free_pages(rx_ring->pg_chunk.page,
1112 qdev->lbq_buf_order);
1113 QPRINTK(qdev, DRV, ERR,
1114 "PCI mapping failed.\n");
1115 return -ENOMEM;
1116 }
1117 rx_ring->pg_chunk.map = map;
1118 rx_ring->pg_chunk.va = page_address(rx_ring->pg_chunk.page);
1119 }
1120
1121 /* Copy the current master pg_chunk info
1122 * to the current descriptor.
1123 */
1124 lbq_desc->p.pg_chunk = rx_ring->pg_chunk;
1125
1126 /* Adjust the master page chunk for next
1127 * buffer get.
1128 */
1129 rx_ring->pg_chunk.offset += rx_ring->lbq_buf_size;
1130 if (rx_ring->pg_chunk.offset == ql_lbq_block_size(qdev)) {
1131 rx_ring->pg_chunk.page = NULL;
1132 lbq_desc->p.pg_chunk.last_flag = 1;
1133 } else {
1134 rx_ring->pg_chunk.va += rx_ring->lbq_buf_size;
1135 get_page(rx_ring->pg_chunk.page);
1136 lbq_desc->p.pg_chunk.last_flag = 0;
1137 }
1138 return 0;
1139}
c4e84bde
RM		 1140/* Process (refill) a large buffer queue. */
1141static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1142{
49f2186d
RM		 1143 u32 clean_idx = rx_ring->lbq_clean_idx;
1144 u32 start_idx = clean_idx;
c4e84bde 1145 struct bq_desc *lbq_desc;
c4e84bde
RM		 1146 u64 map;
1147 int i;
1148
7c734359 1149 while (rx_ring->lbq_free_cnt > 32) {
c4e84bde
RM		 1150 for (i = 0; i < 16; i++) {
1151 QPRINTK(qdev, RX_STATUS, DEBUG,
1152 "lbq: try cleaning clean_idx = %d.\n",
1153 clean_idx);
1154 lbq_desc = &rx_ring->lbq[clean_idx];
7c734359
RM		 1155 if (ql_get_next_chunk(qdev, rx_ring, lbq_desc)) {
1156 QPRINTK(qdev, IFUP, ERR,
1157 "Could not get a page chunk.\n");
c4e84bde
RM		 1158 return;
1159 }
7c734359
RM		 1160
1161 map = lbq_desc->p.pg_chunk.map +
1162 lbq_desc->p.pg_chunk.offset;
c4e84bde 1163 pci_unmap_addr_set(lbq_desc, mapaddr, map);
7c734359
RM		 1164 pci_unmap_len_set(lbq_desc, maplen,
1165 rx_ring->lbq_buf_size);
2c9a0d41 1166 *lbq_desc->addr = cpu_to_le64(map);
7c734359
RM		 1167
1168 pci_dma_sync_single_for_device(qdev->pdev, map,
1169 rx_ring->lbq_buf_size,
1170 PCI_DMA_FROMDEVICE);
c4e84bde
RM		 1171 clean_idx++;
1172 if (clean_idx == rx_ring->lbq_len)
1173 clean_idx = 0;
1174 }
1175
1176 rx_ring->lbq_clean_idx = clean_idx;
1177 rx_ring->lbq_prod_idx += 16;
1178 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
1179 rx_ring->lbq_prod_idx = 0;
49f2186d
RM		 1180 rx_ring->lbq_free_cnt -= 16;
1181 }
1182
1183 if (start_idx != clean_idx) {
c4e84bde
RM		 1184 QPRINTK(qdev, RX_STATUS, DEBUG,
1185 "lbq: updating prod idx = %d.\n",
1186 rx_ring->lbq_prod_idx);
1187 ql_write_db_reg(rx_ring->lbq_prod_idx,
1188 rx_ring->lbq_prod_idx_db_reg);
c4e84bde
RM		 1189 }
1190}
1191
1192/* Process (refill) a small buffer queue. */
1193static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1194{
49f2186d
RM		 1195 u32 clean_idx = rx_ring->sbq_clean_idx;
1196 u32 start_idx = clean_idx;
c4e84bde 1197 struct bq_desc *sbq_desc;
c4e84bde
RM		 1198 u64 map;
1199 int i;
1200
1201 while (rx_ring->sbq_free_cnt > 16) {
1202 for (i = 0; i < 16; i++) {
1203 sbq_desc = &rx_ring->sbq[clean_idx];
1204 QPRINTK(qdev, RX_STATUS, DEBUG,
1205 "sbq: try cleaning clean_idx = %d.\n",
1206 clean_idx);
c4e84bde
RM		 1207 if (sbq_desc->p.skb == NULL) {
1208 QPRINTK(qdev, RX_STATUS, DEBUG,
1209 "sbq: getting new skb for index %d.\n",
1210 sbq_desc->index);
1211 sbq_desc->p.skb =
1212 netdev_alloc_skb(qdev->ndev,
52e55f3c 1213 SMALL_BUFFER_SIZE);
c4e84bde
RM		 1214 if (sbq_desc->p.skb == NULL) {
1215 QPRINTK(qdev, PROBE, ERR,
1216 "Couldn't get an skb.\n");
1217 rx_ring->sbq_clean_idx = clean_idx;
1218 return;
1219 }
1220 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
1221 map = pci_map_single(qdev->pdev,
1222 sbq_desc->p.skb->data,
52e55f3c
RM		 1223 rx_ring->sbq_buf_size,
1224 PCI_DMA_FROMDEVICE);
c907a35a
RM		 1225 if (pci_dma_mapping_error(qdev->pdev, map)) {
1226 QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
1227 rx_ring->sbq_clean_idx = clean_idx;
06a3d510
RM		 1228 dev_kfree_skb_any(sbq_desc->p.skb);
1229 sbq_desc->p.skb = NULL;
c907a35a
RM		 1230 return;
1231 }
c4e84bde
RM		 1232 pci_unmap_addr_set(sbq_desc, mapaddr, map);
1233 pci_unmap_len_set(sbq_desc, maplen,
52e55f3c 1234 rx_ring->sbq_buf_size);
2c9a0d41 1235 *sbq_desc->addr = cpu_to_le64(map);
c4e84bde
RM		 1236 }
1237
1238 clean_idx++;
1239 if (clean_idx == rx_ring->sbq_len)
1240 clean_idx = 0;
1241 }
1242 rx_ring->sbq_clean_idx = clean_idx;
1243 rx_ring->sbq_prod_idx += 16;
1244 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
1245 rx_ring->sbq_prod_idx = 0;
49f2186d
RM		 1246 rx_ring->sbq_free_cnt -= 16;
1247 }
1248
1249 if (start_idx != clean_idx) {
c4e84bde
RM		 1250 QPRINTK(qdev, RX_STATUS, DEBUG,
1251 "sbq: updating prod idx = %d.\n",
1252 rx_ring->sbq_prod_idx);
1253 ql_write_db_reg(rx_ring->sbq_prod_idx,
1254 rx_ring->sbq_prod_idx_db_reg);
c4e84bde
RM		 1255 }
1256}
1257
1258static void ql_update_buffer_queues(struct ql_adapter *qdev,
1259 struct rx_ring *rx_ring)
1260{
1261 ql_update_sbq(qdev, rx_ring);
1262 ql_update_lbq(qdev, rx_ring);
1263}
1264
1265/* Unmaps tx buffers. Can be called from send() if a pci mapping
1266 * fails at some stage, or from the interrupt when a tx completes.
1267 */
1268static void ql_unmap_send(struct ql_adapter *qdev,
1269 struct tx_ring_desc *tx_ring_desc, int mapped)
1270{
1271 int i;
1272 for (i = 0; i < mapped; i++) {
1273 if (i == 0 || (i == 7 && mapped > 7)) {
1274 /*
1275 * Unmap the skb->data area, or the
1276 * external sglist (AKA the Outbound
1277 * Address List (OAL)).
1278 * If its the zeroeth element, then it's
1279 * the skb->data area. If it's the 7th
1280 * element and there is more than 6 frags,
1281 * then its an OAL.
1282 */
1283 if (i == 7) {
1284 QPRINTK(qdev, TX_DONE, DEBUG,
1285 "unmapping OAL area.\n");
1286 }
1287 pci_unmap_single(qdev->pdev,
1288 pci_unmap_addr(&tx_ring_desc->map[i],
1289 mapaddr),
1290 pci_unmap_len(&tx_ring_desc->map[i],
1291 maplen),
1292 PCI_DMA_TODEVICE);
1293 } else {
1294 QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1295 i);
1296 pci_unmap_page(qdev->pdev,
1297 pci_unmap_addr(&tx_ring_desc->map[i],
1298 mapaddr),
1299 pci_unmap_len(&tx_ring_desc->map[i],
1300 maplen), PCI_DMA_TODEVICE);
1301 }
1302 }
1303
1304}
1305
1306/* Map the buffers for this transmit. This will return
1307 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1308 */
1309static int ql_map_send(struct ql_adapter *qdev,
1310 struct ob_mac_iocb_req *mac_iocb_ptr,
1311 struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1312{
1313 int len = skb_headlen(skb);
1314 dma_addr_t map;
1315 int frag_idx, err, map_idx = 0;
1316 struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1317 int frag_cnt = skb_shinfo(skb)->nr_frags;
1318
1319 if (frag_cnt) {
1320 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1321 }
1322 /*
1323 * Map the skb buffer first.
1324 */
1325 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1326
1327 err = pci_dma_mapping_error(qdev->pdev, map);
1328 if (err) {
1329 QPRINTK(qdev, TX_QUEUED, ERR,
1330 "PCI mapping failed with error: %d\n", err);
1331
1332 return NETDEV_TX_BUSY;
1333 }
1334
1335 tbd->len = cpu_to_le32(len);
1336 tbd->addr = cpu_to_le64(map);
1337 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1338 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1339 map_idx++;
1340
1341 /*
1342 * This loop fills the remainder of the 8 address descriptors
1343 * in the IOCB. If there are more than 7 fragments, then the
1344 * eighth address desc will point to an external list (OAL).
1345 * When this happens, the remainder of the frags will be stored
1346 * in this list.
1347 */
1348 for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1349 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1350 tbd++;
1351 if (frag_idx == 6 && frag_cnt > 7) {
1352 /* Let's tack on an sglist.
1353 * Our control block will now
1354 * look like this:
1355 * iocb->seg[0] = skb->data
1356 * iocb->seg[1] = frag[0]
1357 * iocb->seg[2] = frag[1]
1358 * iocb->seg[3] = frag[2]
1359 * iocb->seg[4] = frag[3]
1360 * iocb->seg[5] = frag[4]
1361 * iocb->seg[6] = frag[5]
1362 * iocb->seg[7] = ptr to OAL (external sglist)
1363 * oal->seg[0] = frag[6]
1364 * oal->seg[1] = frag[7]
1365 * oal->seg[2] = frag[8]
1366 * oal->seg[3] = frag[9]
1367 * oal->seg[4] = frag[10]
1368 * etc...
1369 */
1370 /* Tack on the OAL in the eighth segment of IOCB. */
1371 map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1372 sizeof(struct oal),
1373 PCI_DMA_TODEVICE);
1374 err = pci_dma_mapping_error(qdev->pdev, map);
1375 if (err) {
1376 QPRINTK(qdev, TX_QUEUED, ERR,
1377 "PCI mapping outbound address list with error: %d\n",
1378 err);
1379 goto map_error;
1380 }
1381
1382 tbd->addr = cpu_to_le64(map);
1383 /*
1384 * The length is the number of fragments
1385 * that remain to be mapped times the length
1386 * of our sglist (OAL).
1387 */
1388 tbd->len =
1389 cpu_to_le32((sizeof(struct tx_buf_desc) *
1390 (frag_cnt - frag_idx)) | TX_DESC_C);
1391 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1392 map);
1393 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1394 sizeof(struct oal));
1395 tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1396 map_idx++;
1397 }
1398
1399 map =
1400 pci_map_page(qdev->pdev, frag->page,
1401 frag->page_offset, frag->size,
1402 PCI_DMA_TODEVICE);
1403
1404 err = pci_dma_mapping_error(qdev->pdev, map);
1405 if (err) {
1406 QPRINTK(qdev, TX_QUEUED, ERR,
1407 "PCI mapping frags failed with error: %d.\n",
1408 err);
1409 goto map_error;
1410 }
1411
1412 tbd->addr = cpu_to_le64(map);
1413 tbd->len = cpu_to_le32(frag->size);
1414 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1415 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1416 frag->size);
1417
1418 }
1419 /* Save the number of segments we've mapped. */
1420 tx_ring_desc->map_cnt = map_idx;
1421 /* Terminate the last segment. */
1422 tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1423 return NETDEV_TX_OK;
1424
1425map_error:
1426 /*
1427 * If the first frag mapping failed, then i will be zero.
1428 * This causes the unmap of the skb->data area. Otherwise
1429 * we pass in the number of frags that mapped successfully
1430 * so they can be umapped.
1431 */
1432 ql_unmap_send(qdev, tx_ring_desc, map_idx);
1433 return NETDEV_TX_BUSY;
1434}
1435
4f848c0a
RM		 1436/* Process an inbound completion from an rx ring. */
1437static void ql_process_mac_rx_page(struct ql_adapter *qdev,
1438 struct rx_ring *rx_ring,
1439 struct ib_mac_iocb_rsp *ib_mac_rsp,
1440 u32 length,
1441 u16 vlan_id)
1442{
1443 struct net_device *ndev = qdev->ndev;
1444 struct sk_buff *skb = NULL;
1445 void *addr;
1446 struct bq_desc *lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1447 struct napi_struct *napi = &rx_ring->napi;
1448
1449 skb = netdev_alloc_skb(ndev, length);
1450 if (!skb) {
1451 QPRINTK(qdev, DRV, ERR, "Couldn't get an skb, "
1452 "need to unwind!.\n");
1453 rx_ring->rx_dropped++;
1454 put_page(lbq_desc->p.pg_chunk.page);
1455 return;
1456 }
1457
1458 addr = lbq_desc->p.pg_chunk.va;
1459 prefetch(addr);
1460
1461
1462 /* Frame error, so drop the packet. */
1463 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1464 QPRINTK(qdev, DRV, ERR, "Receive error, flags2 = 0x%x\n",
1465 ib_mac_rsp->flags2);
1466 rx_ring->rx_errors++;
1467 goto err_out;
1468 }
1469
1470 /* The max framesize filter on this chip is set higher than
1471 * MTU since FCoE uses 2k frames.
1472 */
1473 if (skb->len > ndev->mtu + ETH_HLEN) {
1474 QPRINTK(qdev, DRV, ERR, "Segment too small, dropping.\n");
1475 rx_ring->rx_dropped++;
1476 goto err_out;
1477 }
1478 memcpy(skb_put(skb, ETH_HLEN), addr, ETH_HLEN);
1479 QPRINTK(qdev, RX_STATUS, DEBUG,
1480 "%d bytes of headers and data in large. Chain "
1481 "page to new skb and pull tail.\n", length);
1482 skb_fill_page_desc(skb, 0, lbq_desc->p.pg_chunk.page,
1483 lbq_desc->p.pg_chunk.offset+ETH_HLEN,
1484 length-ETH_HLEN);
1485 skb->len += length-ETH_HLEN;
1486 skb->data_len += length-ETH_HLEN;
1487 skb->truesize += length-ETH_HLEN;
1488
1489 rx_ring->rx_packets++;
1490 rx_ring->rx_bytes += skb->len;
1491 skb->protocol = eth_type_trans(skb, ndev);
1492 skb->ip_summed = CHECKSUM_NONE;
1493
1494 if (qdev->rx_csum &&
1495 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1496 /* TCP frame. */
1497 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1498 QPRINTK(qdev, RX_STATUS, DEBUG,
1499 "TCP checksum done!\n");
1500 skb->ip_summed = CHECKSUM_UNNECESSARY;
1501 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1502 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1503 /* Unfragmented ipv4 UDP frame. */
1504 struct iphdr *iph = (struct iphdr *) skb->data;
1505 if (!(iph->frag_off &
1506 cpu_to_be16(IP_MF|IP_OFFSET))) {
1507 skb->ip_summed = CHECKSUM_UNNECESSARY;
1508 QPRINTK(qdev, RX_STATUS, DEBUG,
1509 "TCP checksum done!\n");
1510 }
1511 }
1512 }
1513
1514 skb_record_rx_queue(skb, rx_ring->cq_id);
1515 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
1516 if (qdev->vlgrp && (vlan_id != 0xffff))
1517 vlan_gro_receive(napi, qdev->vlgrp, vlan_id, skb);
1518 else
1519 napi_gro_receive(napi, skb);
1520 } else {
1521 if (qdev->vlgrp && (vlan_id != 0xffff))
1522 vlan_hwaccel_receive_skb(skb, qdev->vlgrp, vlan_id);
1523 else
1524 netif_receive_skb(skb);
1525 }
1526 return;
1527err_out:
1528 dev_kfree_skb_any(skb);
1529 put_page(lbq_desc->p.pg_chunk.page);
1530}
1531
1532/* Process an inbound completion from an rx ring. */
1533static void ql_process_mac_rx_skb(struct ql_adapter *qdev,
1534 struct rx_ring *rx_ring,
1535 struct ib_mac_iocb_rsp *ib_mac_rsp,
1536 u32 length,
1537 u16 vlan_id)
1538{
1539 struct net_device *ndev = qdev->ndev;
1540 struct sk_buff *skb = NULL;
1541 struct sk_buff *new_skb = NULL;
1542 struct bq_desc *sbq_desc = ql_get_curr_sbuf(rx_ring);
1543
1544 skb = sbq_desc->p.skb;
1545 /* Allocate new_skb and copy */
1546 new_skb = netdev_alloc_skb(qdev->ndev, length + NET_IP_ALIGN);
1547 if (new_skb == NULL) {
1548 QPRINTK(qdev, PROBE, ERR,
1549 "No skb available, drop the packet.\n");
1550 rx_ring->rx_dropped++;
1551 return;
1552 }
1553 skb_reserve(new_skb, NET_IP_ALIGN);
1554 memcpy(skb_put(new_skb, length), skb->data, length);
1555 skb = new_skb;
1556
1557 /* Frame error, so drop the packet. */
1558 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1559 QPRINTK(qdev, DRV, ERR, "Receive error, flags2 = 0x%x\n",
1560 ib_mac_rsp->flags2);
1561 dev_kfree_skb_any(skb);
1562 rx_ring->rx_errors++;
1563 return;
1564 }
1565
1566 /* loopback self test for ethtool */
1567 if (test_bit(QL_SELFTEST, &qdev->flags)) {
1568 ql_check_lb_frame(qdev, skb);
1569 dev_kfree_skb_any(skb);
1570 return;
1571 }
1572
1573 /* The max framesize filter on this chip is set higher than
1574 * MTU since FCoE uses 2k frames.
1575 */
1576 if (skb->len > ndev->mtu + ETH_HLEN) {
1577 dev_kfree_skb_any(skb);
1578 rx_ring->rx_dropped++;
1579 return;
1580 }
1581
1582 prefetch(skb->data);
1583 skb->dev = ndev;
1584 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1585 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1586 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1587 IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1588 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1589 IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1590 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1591 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1592 }
1593 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P)
1594 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1595
1596 rx_ring->rx_packets++;
1597 rx_ring->rx_bytes += skb->len;
1598 skb->protocol = eth_type_trans(skb, ndev);
1599 skb->ip_summed = CHECKSUM_NONE;
1600
1601 /* If rx checksum is on, and there are no
1602 * csum or frame errors.
1603 */
1604 if (qdev->rx_csum &&
1605 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1606 /* TCP frame. */
1607 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1608 QPRINTK(qdev, RX_STATUS, DEBUG,
1609 "TCP checksum done!\n");
1610 skb->ip_summed = CHECKSUM_UNNECESSARY;
1611 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1612 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1613 /* Unfragmented ipv4 UDP frame. */
1614 struct iphdr *iph = (struct iphdr *) skb->data;
1615 if (!(iph->frag_off &
1616 cpu_to_be16(IP_MF|IP_OFFSET))) {
1617 skb->ip_summed = CHECKSUM_UNNECESSARY;
1618 QPRINTK(qdev, RX_STATUS, DEBUG,
1619 "TCP checksum done!\n");
1620 }
1621 }
1622 }
1623
1624 skb_record_rx_queue(skb, rx_ring->cq_id);
1625 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
1626 if (qdev->vlgrp && (vlan_id != 0xffff))
1627 vlan_gro_receive(&rx_ring->napi, qdev->vlgrp,
1628 vlan_id, skb);
1629 else
1630 napi_gro_receive(&rx_ring->napi, skb);
1631 } else {
1632 if (qdev->vlgrp && (vlan_id != 0xffff))
1633 vlan_hwaccel_receive_skb(skb, qdev->vlgrp, vlan_id);
1634 else
1635 netif_receive_skb(skb);
1636 }
1637}
1638
8668ae92 1639static void ql_realign_skb(struct sk_buff *skb, int len)
c4e84bde
RM		 1640{
1641 void *temp_addr = skb->data;
1642
1643 /* Undo the skb_reserve(skb,32) we did before
1644 * giving to hardware, and realign data on
1645 * a 2-byte boundary.
1646 */
1647 skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1648 skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1649 skb_copy_to_linear_data(skb, temp_addr,
1650 (unsigned int)len);
1651}
1652
1653/*
1654 * This function builds an skb for the given inbound
1655 * completion. It will be rewritten for readability in the near
1656 * future, but for not it works well.
1657 */
1658static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1659 struct rx_ring *rx_ring,
1660 struct ib_mac_iocb_rsp *ib_mac_rsp)
1661{
1662 struct bq_desc *lbq_desc;
1663 struct bq_desc *sbq_desc;
1664 struct sk_buff *skb = NULL;
1665 u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1666 u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1667
1668 /*
1669 * Handle the header buffer if present.
1670 */
1671 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1672 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1673 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1674 /*
1675 * Headers fit nicely into a small buffer.
1676 */
1677 sbq_desc = ql_get_curr_sbuf(rx_ring);
1678 pci_unmap_single(qdev->pdev,
1679 pci_unmap_addr(sbq_desc, mapaddr),
1680 pci_unmap_len(sbq_desc, maplen),
1681 PCI_DMA_FROMDEVICE);
1682 skb = sbq_desc->p.skb;
1683 ql_realign_skb(skb, hdr_len);
1684 skb_put(skb, hdr_len);
1685 sbq_desc->p.skb = NULL;
1686 }
1687
1688 /*
1689 * Handle the data buffer(s).
1690 */
1691 if (unlikely(!length)) { /* Is there data too? */
1692 QPRINTK(qdev, RX_STATUS, DEBUG,
1693 "No Data buffer in this packet.\n");
1694 return skb;
1695 }
1696
1697 if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1698 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1699 QPRINTK(qdev, RX_STATUS, DEBUG,
1700 "Headers in small, data of %d bytes in small, combine them.\n", length);
1701 /*
1702 * Data is less than small buffer size so it's
1703 * stuffed in a small buffer.
1704 * For this case we append the data
1705 * from the "data" small buffer to the "header" small
1706 * buffer.
1707 */
1708 sbq_desc = ql_get_curr_sbuf(rx_ring);
1709 pci_dma_sync_single_for_cpu(qdev->pdev,
1710 pci_unmap_addr
1711 (sbq_desc, mapaddr),
1712 pci_unmap_len
1713 (sbq_desc, maplen),
1714 PCI_DMA_FROMDEVICE);
1715 memcpy(skb_put(skb, length),
1716 sbq_desc->p.skb->data, length);
1717 pci_dma_sync_single_for_device(qdev->pdev,
1718 pci_unmap_addr
1719 (sbq_desc,
1720 mapaddr),
1721 pci_unmap_len
1722 (sbq_desc,
1723 maplen),
1724 PCI_DMA_FROMDEVICE);
1725 } else {
1726 QPRINTK(qdev, RX_STATUS, DEBUG,
1727 "%d bytes in a single small buffer.\n", length);
1728 sbq_desc = ql_get_curr_sbuf(rx_ring);
1729 skb = sbq_desc->p.skb;
1730 ql_realign_skb(skb, length);
1731 skb_put(skb, length);
1732 pci_unmap_single(qdev->pdev,
1733 pci_unmap_addr(sbq_desc,
1734 mapaddr),
1735 pci_unmap_len(sbq_desc,
1736 maplen),
1737 PCI_DMA_FROMDEVICE);
1738 sbq_desc->p.skb = NULL;
1739 }
1740 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1741 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1742 QPRINTK(qdev, RX_STATUS, DEBUG,
1743 "Header in small, %d bytes in large. Chain large to small!\n", length);
1744 /*
1745 * The data is in a single large buffer. We
1746 * chain it to the header buffer's skb and let
1747 * it rip.
1748 */
7c734359 1749 lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
c4e84bde 1750 QPRINTK(qdev, RX_STATUS, DEBUG,
7c734359
RM		 1751 "Chaining page at offset = %d,"
1752 "for %d bytes to skb.\n",
1753 lbq_desc->p.pg_chunk.offset, length);
1754 skb_fill_page_desc(skb, 0, lbq_desc->p.pg_chunk.page,
1755 lbq_desc->p.pg_chunk.offset,
1756 length);
c4e84bde
RM		 1757 skb->len += length;
1758 skb->data_len += length;
1759 skb->truesize += length;
c4e84bde
RM		 1760 } else {
1761 /*
1762 * The headers and data are in a single large buffer. We
1763 * copy it to a new skb and let it go. This can happen with
1764 * jumbo mtu on a non-TCP/UDP frame.
1765 */
7c734359 1766 lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
c4e84bde
RM		 1767 skb = netdev_alloc_skb(qdev->ndev, length);
1768 if (skb == NULL) {
1769 QPRINTK(qdev, PROBE, DEBUG,
1770 "No skb available, drop the packet.\n");
1771 return NULL;
1772 }
4055c7d4
RM		 1773 pci_unmap_page(qdev->pdev,
1774 pci_unmap_addr(lbq_desc,
1775 mapaddr),
1776 pci_unmap_len(lbq_desc, maplen),
1777 PCI_DMA_FROMDEVICE);
c4e84bde
RM		 1778 skb_reserve(skb, NET_IP_ALIGN);
1779 QPRINTK(qdev, RX_STATUS, DEBUG,
1780 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
7c734359
RM		 1781 skb_fill_page_desc(skb, 0,
1782 lbq_desc->p.pg_chunk.page,
1783 lbq_desc->p.pg_chunk.offset,
1784 length);
c4e84bde
RM		 1785 skb->len += length;
1786 skb->data_len += length;
1787 skb->truesize += length;
1788 length -= length;
c4e84bde
RM		 1789 __pskb_pull_tail(skb,
1790 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1791 VLAN_ETH_HLEN : ETH_HLEN);
1792 }
1793 } else {
1794 /*
1795 * The data is in a chain of large buffers
1796 * pointed to by a small buffer. We loop
1797 * thru and chain them to the our small header
1798 * buffer's skb.
1799 * frags: There are 18 max frags and our small
1800 * buffer will hold 32 of them. The thing is,
1801 * we'll use 3 max for our 9000 byte jumbo
1802 * frames. If the MTU goes up we could
1803 * eventually be in trouble.
1804 */
7c734359 1805 int size, i = 0;
c4e84bde
RM		 1806 sbq_desc = ql_get_curr_sbuf(rx_ring);
1807 pci_unmap_single(qdev->pdev,
1808 pci_unmap_addr(sbq_desc, mapaddr),
1809 pci_unmap_len(sbq_desc, maplen),
1810 PCI_DMA_FROMDEVICE);
1811 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1812 /*
1813 * This is an non TCP/UDP IP frame, so
1814 * the headers aren't split into a small
1815 * buffer. We have to use the small buffer
1816 * that contains our sg list as our skb to
1817 * send upstairs. Copy the sg list here to
1818 * a local buffer and use it to find the
1819 * pages to chain.
1820 */
1821 QPRINTK(qdev, RX_STATUS, DEBUG,
1822 "%d bytes of headers & data in chain of large.\n", length);
1823 skb = sbq_desc->p.skb;
c4e84bde
RM		 1824 sbq_desc->p.skb = NULL;
1825 skb_reserve(skb, NET_IP_ALIGN);
c4e84bde
RM		 1826 }
1827 while (length > 0) {
7c734359
RM		 1828 lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1829 size = (length < rx_ring->lbq_buf_size) ? length :
1830 rx_ring->lbq_buf_size;
c4e84bde
RM		 1831
1832 QPRINTK(qdev, RX_STATUS, DEBUG,
1833 "Adding page %d to skb for %d bytes.\n",
1834 i, size);
7c734359
RM		 1835 skb_fill_page_desc(skb, i,
1836 lbq_desc->p.pg_chunk.page,
1837 lbq_desc->p.pg_chunk.offset,
1838 size);
c4e84bde
RM		 1839 skb->len += size;
1840 skb->data_len += size;
1841 skb->truesize += size;
1842 length -= size;
c4e84bde
RM		 1843 i++;
1844 }
1845 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1846 VLAN_ETH_HLEN : ETH_HLEN);
1847 }
1848 return skb;
1849}
1850
1851/* Process an inbound completion from an rx ring. */
4f848c0a 1852static void ql_process_mac_split_rx_intr(struct ql_adapter *qdev,
c4e84bde 1853 struct rx_ring *rx_ring,
4f848c0a
RM		 1854 struct ib_mac_iocb_rsp *ib_mac_rsp,
1855 u16 vlan_id)
c4e84bde
RM		 1856{
1857 struct net_device *ndev = qdev->ndev;
1858 struct sk_buff *skb = NULL;
1859
1860 QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1861
1862 skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1863 if (unlikely(!skb)) {
1864 QPRINTK(qdev, RX_STATUS, DEBUG,
1865 "No skb available, drop packet.\n");
885ee398 1866 rx_ring->rx_dropped++;
c4e84bde
RM		 1867 return;
1868 }
1869
a32959cd
RM		 1870 /* Frame error, so drop the packet. */
1871 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1872 QPRINTK(qdev, DRV, ERR, "Receive error, flags2 = 0x%x\n",
1873 ib_mac_rsp->flags2);
1874 dev_kfree_skb_any(skb);
885ee398 1875 rx_ring->rx_errors++;
a32959cd
RM		 1876 return;
1877 }
ec33a491
RM		 1878
1879 /* The max framesize filter on this chip is set higher than
1880 * MTU since FCoE uses 2k frames.
1881 */
1882 if (skb->len > ndev->mtu + ETH_HLEN) {
1883 dev_kfree_skb_any(skb);
885ee398 1884 rx_ring->rx_dropped++;
ec33a491
RM		 1885 return;
1886 }
1887
9dfbbaa6
RM		 1888 /* loopback self test for ethtool */
1889 if (test_bit(QL_SELFTEST, &qdev->flags)) {
1890 ql_check_lb_frame(qdev, skb);
1891 dev_kfree_skb_any(skb);
1892 return;
1893 }
1894
c4e84bde
RM		 1895 prefetch(skb->data);
1896 skb->dev = ndev;
1897 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1898 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1899 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1900 IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1901 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1902 IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1903 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1904 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
885ee398 1905 rx_ring->rx_multicast++;
c4e84bde
RM		 1906 }
1907 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1908 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1909 }
d555f592 1910
d555f592
RM		 1911 skb->protocol = eth_type_trans(skb, ndev);
1912 skb->ip_summed = CHECKSUM_NONE;
1913
1914 /* If rx checksum is on, and there are no
1915 * csum or frame errors.
1916 */
1917 if (qdev->rx_csum &&
d555f592
RM		 1918 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1919 /* TCP frame. */
1920 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1921 QPRINTK(qdev, RX_STATUS, DEBUG,
1922 "TCP checksum done!\n");
1923 skb->ip_summed = CHECKSUM_UNNECESSARY;
1924 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1925 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1926 /* Unfragmented ipv4 UDP frame. */
1927 struct iphdr *iph = (struct iphdr *) skb->data;
1928 if (!(iph->frag_off &
1929 cpu_to_be16(IP_MF|IP_OFFSET))) {
1930 skb->ip_summed = CHECKSUM_UNNECESSARY;
1931 QPRINTK(qdev, RX_STATUS, DEBUG,
1932 "TCP checksum done!\n");
1933 }
1934 }
c4e84bde 1935 }
d555f592 1936
885ee398
RM		 1937 rx_ring->rx_packets++;
1938 rx_ring->rx_bytes += skb->len;
b2014ff8 1939 skb_record_rx_queue(skb, rx_ring->cq_id);
22bdd4f5
RM		 1940 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
1941 if (qdev->vlgrp &&
1942 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1943 (vlan_id != 0))
1944 vlan_gro_receive(&rx_ring->napi, qdev->vlgrp,
1945 vlan_id, skb);
1946 else
1947 napi_gro_receive(&rx_ring->napi, skb);
c4e84bde 1948 } else {
22bdd4f5
RM		 1949 if (qdev->vlgrp &&
1950 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1951 (vlan_id != 0))
1952 vlan_hwaccel_receive_skb(skb, qdev->vlgrp, vlan_id);
1953 else
1954 netif_receive_skb(skb);
c4e84bde 1955 }
c4e84bde
RM		 1956}
1957
4f848c0a
RM		 1958/* Process an inbound completion from an rx ring. */
1959static unsigned long ql_process_mac_rx_intr(struct ql_adapter *qdev,
1960 struct rx_ring *rx_ring,
1961 struct ib_mac_iocb_rsp *ib_mac_rsp)
1962{
1963 u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1964 u16 vlan_id = (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1965 ((le16_to_cpu(ib_mac_rsp->vlan_id) &
1966 IB_MAC_IOCB_RSP_VLAN_MASK)) : 0xffff;
1967
1968 QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1969
1970 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV) {
1971 /* The data and headers are split into
1972 * separate buffers.
1973 */
1974 ql_process_mac_split_rx_intr(qdev, rx_ring, ib_mac_rsp,
1975 vlan_id);
1976 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1977 /* The data fit in a single small buffer.
1978 * Allocate a new skb, copy the data and
1979 * return the buffer to the free pool.
1980 */
1981 ql_process_mac_rx_skb(qdev, rx_ring, ib_mac_rsp,
1982 length, vlan_id);
1983 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1984 /* Non-TCP packet in a page chunk. Allocate an
1985 * skb, tack it on frags, and send it up.
1986 */
1987 ql_process_mac_rx_page(qdev, rx_ring, ib_mac_rsp,
1988 length, vlan_id);
1989 } else {
1990 struct bq_desc *lbq_desc;
1991
1992 /* Free small buffer that holds the IAL */
1993 lbq_desc = ql_get_curr_sbuf(rx_ring);
1994 QPRINTK(qdev, RX_ERR, ERR, "Dropping frame, len %d > mtu %d\n",
1995 length, qdev->ndev->mtu);
1996
1997 /* Unwind the large buffers for this frame. */
1998 while (length > 0) {
1999 lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
2000 length -= (length < rx_ring->lbq_buf_size) ?
2001 length : rx_ring->lbq_buf_size;
2002 put_page(lbq_desc->p.pg_chunk.page);
2003 }
2004 }
2005
2006 return (unsigned long)length;
2007}
2008
c4e84bde
RM		 2009/* Process an outbound completion from an rx ring. */
2010static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
2011 struct ob_mac_iocb_rsp *mac_rsp)
2012{
2013 struct tx_ring *tx_ring;
2014 struct tx_ring_desc *tx_ring_desc;
2015
2016 QL_DUMP_OB_MAC_RSP(mac_rsp);
2017 tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
2018 tx_ring_desc = &tx_ring->q[mac_rsp->tid];
2019 ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
885ee398
RM		 2020 tx_ring->tx_bytes += (tx_ring_desc->skb)->len;
2021 tx_ring->tx_packets++;
c4e84bde
RM		 2022 dev_kfree_skb(tx_ring_desc->skb);
2023 tx_ring_desc->skb = NULL;
2024
2025 if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
2026 OB_MAC_IOCB_RSP_S |
2027 OB_MAC_IOCB_RSP_L |
2028 OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
2029 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
2030 QPRINTK(qdev, TX_DONE, WARNING,
2031 "Total descriptor length did not match transfer length.\n");
2032 }
2033 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
2034 QPRINTK(qdev, TX_DONE, WARNING,
2035 "Frame too short to be legal, not sent.\n");
2036 }
2037 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
2038 QPRINTK(qdev, TX_DONE, WARNING,
2039 "Frame too long, but sent anyway.\n");
2040 }
2041 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
2042 QPRINTK(qdev, TX_DONE, WARNING,
2043 "PCI backplane error. Frame not sent.\n");
2044 }
2045 }
2046 atomic_inc(&tx_ring->tx_count);
2047}
2048
2049/* Fire up a handler to reset the MPI processor. */
2050void ql_queue_fw_error(struct ql_adapter *qdev)
2051{
6a473308 2052 ql_link_off(qdev);
c4e84bde
RM		 2053 queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
2054}
2055
2056void ql_queue_asic_error(struct ql_adapter *qdev)
2057{
6a473308 2058 ql_link_off(qdev);
c4e84bde 2059 ql_disable_interrupts(qdev);
6497b607
RM		 2060 /* Clear adapter up bit to signal the recovery
2061 * process that it shouldn't kill the reset worker
2062 * thread
2063 */
2064 clear_bit(QL_ADAPTER_UP, &qdev->flags);
c4e84bde
RM		 2065 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
2066}
2067
2068static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
2069 struct ib_ae_iocb_rsp *ib_ae_rsp)
2070{
2071 switch (ib_ae_rsp->event) {
2072 case MGMT_ERR_EVENT:
2073 QPRINTK(qdev, RX_ERR, ERR,
2074 "Management Processor Fatal Error.\n");
2075 ql_queue_fw_error(qdev);
2076 return;
2077
2078 case CAM_LOOKUP_ERR_EVENT:
2079 QPRINTK(qdev, LINK, ERR,
2080 "Multiple CAM hits lookup occurred.\n");
2081 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
2082 ql_queue_asic_error(qdev);
2083 return;
2084
2085 case SOFT_ECC_ERROR_EVENT:
2086 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
2087 ql_queue_asic_error(qdev);
2088 break;
2089
2090 case PCI_ERR_ANON_BUF_RD:
2091 QPRINTK(qdev, RX_ERR, ERR,
2092 "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
2093 ib_ae_rsp->q_id);
2094 ql_queue_asic_error(qdev);
2095 break;
2096
2097 default:
2098 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
2099 ib_ae_rsp->event);
2100 ql_queue_asic_error(qdev);
2101 break;
2102 }
2103}
2104
2105static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
2106{
2107 struct ql_adapter *qdev = rx_ring->qdev;
ba7cd3ba 2108 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 2109 struct ob_mac_iocb_rsp *net_rsp = NULL;
2110 int count = 0;
2111
1e213303 2112 struct tx_ring *tx_ring;
c4e84bde
RM		 2113 /* While there are entries in the completion queue. */
2114 while (prod != rx_ring->cnsmr_idx) {
2115
2116 QPRINTK(qdev, RX_STATUS, DEBUG,
2117 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
2118 prod, rx_ring->cnsmr_idx);
2119
2120 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
2121 rmb();
2122 switch (net_rsp->opcode) {
2123
2124 case OPCODE_OB_MAC_TSO_IOCB:
2125 case OPCODE_OB_MAC_IOCB:
2126 ql_process_mac_tx_intr(qdev, net_rsp);
2127 break;
2128 default:
2129 QPRINTK(qdev, RX_STATUS, DEBUG,
2130 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
2131 net_rsp->opcode);
2132 }
2133 count++;
2134 ql_update_cq(rx_ring);
ba7cd3ba 2135 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 2136 }
2137 ql_write_cq_idx(rx_ring);
1e213303
RM		 2138 tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
2139 if (__netif_subqueue_stopped(qdev->ndev, tx_ring->wq_id) &&
2140 net_rsp != NULL) {
c4e84bde
RM		 2141 if (atomic_read(&tx_ring->queue_stopped) &&
2142 (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
2143 /*
2144 * The queue got stopped because the tx_ring was full.
2145 * Wake it up, because it's now at least 25% empty.
2146 */
1e213303 2147 netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
c4e84bde
RM		 2148 }
2149
2150 return count;
2151}
2152
2153static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
2154{
2155 struct ql_adapter *qdev = rx_ring->qdev;
ba7cd3ba 2156 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 2157 struct ql_net_rsp_iocb *net_rsp;
2158 int count = 0;
2159
2160 /* While there are entries in the completion queue. */
2161 while (prod != rx_ring->cnsmr_idx) {
2162
2163 QPRINTK(qdev, RX_STATUS, DEBUG,
2164 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
2165 prod, rx_ring->cnsmr_idx);
2166
2167 net_rsp = rx_ring->curr_entry;
2168 rmb();
2169 switch (net_rsp->opcode) {
2170 case OPCODE_IB_MAC_IOCB:
2171 ql_process_mac_rx_intr(qdev, rx_ring,
2172 (struct ib_mac_iocb_rsp *)
2173 net_rsp);
2174 break;
2175
2176 case OPCODE_IB_AE_IOCB:
2177 ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
2178 net_rsp);
2179 break;
2180 default:
2181 {
2182 QPRINTK(qdev, RX_STATUS, DEBUG,
2183 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
2184 net_rsp->opcode);
2185 }
2186 }
2187 count++;
2188 ql_update_cq(rx_ring);
ba7cd3ba 2189 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 2190 if (count == budget)
2191 break;
2192 }
2193 ql_update_buffer_queues(qdev, rx_ring);
2194 ql_write_cq_idx(rx_ring);
2195 return count;
2196}
2197
2198static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
2199{
2200 struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
2201 struct ql_adapter *qdev = rx_ring->qdev;
39aa8165
RM		 2202 struct rx_ring *trx_ring;
2203 int i, work_done = 0;
2204 struct intr_context *ctx = &qdev->intr_context[rx_ring->cq_id];
c4e84bde
RM		 2205
2206 QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
2207 rx_ring->cq_id);
2208
39aa8165
RM		 2209 /* Service the TX rings first. They start
2210 * right after the RSS rings. */
2211 for (i = qdev->rss_ring_count; i < qdev->rx_ring_count; i++) {
2212 trx_ring = &qdev->rx_ring[i];
2213 /* If this TX completion ring belongs to this vector and
2214 * it's not empty then service it.
2215 */
2216 if ((ctx->irq_mask & (1 << trx_ring->cq_id)) &&
2217 (ql_read_sh_reg(trx_ring->prod_idx_sh_reg) !=
2218 trx_ring->cnsmr_idx)) {
2219 QPRINTK(qdev, INTR, DEBUG,
2220 "%s: Servicing TX completion ring %d.\n",
2221 __func__, trx_ring->cq_id);
2222 ql_clean_outbound_rx_ring(trx_ring);
2223 }
2224 }
2225
2226 /*
2227 * Now service the RSS ring if it's active.
2228 */
2229 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
2230 rx_ring->cnsmr_idx) {
2231 QPRINTK(qdev, INTR, DEBUG,
2232 "%s: Servicing RX completion ring %d.\n",
2233 __func__, rx_ring->cq_id);
2234 work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
2235 }
2236
c4e84bde 2237 if (work_done < budget) {
22bdd4f5 2238 napi_complete(napi);
c4e84bde
RM		 2239 ql_enable_completion_interrupt(qdev, rx_ring->irq);
2240 }
2241 return work_done;
2242}
2243
01e6b953 2244static void qlge_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
c4e84bde
RM		 2245{
2246 struct ql_adapter *qdev = netdev_priv(ndev);
2247
2248 qdev->vlgrp = grp;
2249 if (grp) {
2250 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
2251 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
2252 NIC_RCV_CFG_VLAN_MATCH_AND_NON);
2253 } else {
2254 QPRINTK(qdev, IFUP, DEBUG,
2255 "Turning off VLAN in NIC_RCV_CFG.\n");
2256 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
2257 }
2258}
2259
01e6b953 2260static void qlge_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
c4e84bde
RM		 2261{
2262 struct ql_adapter *qdev = netdev_priv(ndev);
2263 u32 enable_bit = MAC_ADDR_E;
cc288f54 2264 int status;
c4e84bde 2265
cc288f54
RM		 2266 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
2267 if (status)
2268 return;
c4e84bde
RM		 2269 if (ql_set_mac_addr_reg
2270 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
2271 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
2272 }
cc288f54 2273 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
c4e84bde
RM		 2274}
2275
01e6b953 2276static void qlge_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
c4e84bde
RM		 2277{
2278 struct ql_adapter *qdev = netdev_priv(ndev);
2279 u32 enable_bit = 0;
cc288f54
RM		 2280 int status;
2281
2282 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
2283 if (status)
2284 return;
c4e84bde 2285
c4e84bde
RM		 2286 if (ql_set_mac_addr_reg
2287 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
2288 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
2289 }
cc288f54 2290 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
c4e84bde
RM		 2291
2292}
2293
c4e84bde
RM		 2294/* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
2295static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
2296{
2297 struct rx_ring *rx_ring = dev_id;
288379f0 2298 napi_schedule(&rx_ring->napi);
c4e84bde
RM		 2299 return IRQ_HANDLED;
2300}
2301
c4e84bde
RM		 2302/* This handles a fatal error, MPI activity, and the default
2303 * rx_ring in an MSI-X multiple vector environment.
2304 * In MSI/Legacy environment it also process the rest of
2305 * the rx_rings.
2306 */
2307static irqreturn_t qlge_isr(int irq, void *dev_id)
2308{
2309 struct rx_ring *rx_ring = dev_id;
2310 struct ql_adapter *qdev = rx_ring->qdev;
2311 struct intr_context *intr_context = &qdev->intr_context[0];
2312 u32 var;
c4e84bde
RM		 2313 int work_done = 0;
2314
bb0d215c
RM		 2315 spin_lock(&qdev->hw_lock);
2316 if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
2317 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
2318 spin_unlock(&qdev->hw_lock);
2319 return IRQ_NONE;
c4e84bde 2320 }
bb0d215c 2321 spin_unlock(&qdev->hw_lock);
c4e84bde 2322
bb0d215c 2323 var = ql_disable_completion_interrupt(qdev, intr_context->intr);
c4e84bde
RM		 2324
2325 /*
2326 * Check for fatal error.
2327 */
2328 if (var & STS_FE) {
2329 ql_queue_asic_error(qdev);
2330 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
2331 var = ql_read32(qdev, ERR_STS);
2332 QPRINTK(qdev, INTR, ERR,
2333 "Resetting chip. Error Status Register = 0x%x\n", var);
2334 return IRQ_HANDLED;
2335 }
2336
2337 /*
2338 * Check MPI processor activity.
2339 */
5ee22a5a
RM		 2340 if ((var & STS_PI) &&
2341 (ql_read32(qdev, INTR_MASK) & INTR_MASK_PI)) {
c4e84bde
RM		 2342 /*
2343 * We've got an async event or mailbox completion.
2344 * Handle it and clear the source of the interrupt.
2345 */
2346 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
2347 ql_disable_completion_interrupt(qdev, intr_context->intr);
5ee22a5a
RM		 2348 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
2349 queue_delayed_work_on(smp_processor_id(),
2350 qdev->workqueue, &qdev->mpi_work, 0);
c4e84bde
RM		 2351 work_done++;
2352 }
2353
2354 /*
39aa8165
RM		 2355 * Get the bit-mask that shows the active queues for this
2356 * pass. Compare it to the queues that this irq services
2357 * and call napi if there's a match.
c4e84bde 2358 */
39aa8165
RM		 2359 var = ql_read32(qdev, ISR1);
2360 if (var & intr_context->irq_mask) {
32a5b2a0 2361 QPRINTK(qdev, INTR, INFO,
39aa8165
RM		 2362 "Waking handler for rx_ring[0].\n");
2363 ql_disable_completion_interrupt(qdev, intr_context->intr);
32a5b2a0
RM		 2364 napi_schedule(&rx_ring->napi);
2365 work_done++;
2366 }
bb0d215c 2367 ql_enable_completion_interrupt(qdev, intr_context->intr);
c4e84bde
RM		 2368 return work_done ? IRQ_HANDLED : IRQ_NONE;
2369}
2370
2371static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2372{
2373
2374 if (skb_is_gso(skb)) {
2375 int err;
2376 if (skb_header_cloned(skb)) {
2377 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2378 if (err)
2379 return err;
2380 }
2381
2382 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2383 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
2384 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2385 mac_iocb_ptr->total_hdrs_len =
2386 cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
2387 mac_iocb_ptr->net_trans_offset =
2388 cpu_to_le16(skb_network_offset(skb) |
2389 skb_transport_offset(skb)
2390 << OB_MAC_TRANSPORT_HDR_SHIFT);
2391 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
2392 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
2393 if (likely(skb->protocol == htons(ETH_P_IP))) {
2394 struct iphdr *iph = ip_hdr(skb);
2395 iph->check = 0;
2396 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2397 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2398 iph->daddr, 0,
2399 IPPROTO_TCP,
2400 0);
2401 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2402 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
2403 tcp_hdr(skb)->check =
2404 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2405 &ipv6_hdr(skb)->daddr,
2406 0, IPPROTO_TCP, 0);
2407 }
2408 return 1;
2409 }
2410 return 0;
2411}
2412
2413static void ql_hw_csum_setup(struct sk_buff *skb,
2414 struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2415{
2416 int len;
2417 struct iphdr *iph = ip_hdr(skb);
fd2df4f7 2418 __sum16 *check;
c4e84bde
RM		 2419 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2420 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2421 mac_iocb_ptr->net_trans_offset =
2422 cpu_to_le16(skb_network_offset(skb) |
2423 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
2424
2425 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2426 len = (ntohs(iph->tot_len) - (iph->ihl << 2));
2427 if (likely(iph->protocol == IPPROTO_TCP)) {
2428 check = &(tcp_hdr(skb)->check);
2429 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
2430 mac_iocb_ptr->total_hdrs_len =
2431 cpu_to_le16(skb_transport_offset(skb) +
2432 (tcp_hdr(skb)->doff << 2));
2433 } else {
2434 check = &(udp_hdr(skb)->check);
2435 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
2436 mac_iocb_ptr->total_hdrs_len =
2437 cpu_to_le16(skb_transport_offset(skb) +
2438 sizeof(struct udphdr));
2439 }
2440 *check = ~csum_tcpudp_magic(iph->saddr,
2441 iph->daddr, len, iph->protocol, 0);
2442}
2443
61357325 2444static netdev_tx_t qlge_send(struct sk_buff *skb, struct net_device *ndev)
c4e84bde
RM		 2445{
2446 struct tx_ring_desc *tx_ring_desc;
2447 struct ob_mac_iocb_req *mac_iocb_ptr;
2448 struct ql_adapter *qdev = netdev_priv(ndev);
2449 int tso;
2450 struct tx_ring *tx_ring;
1e213303 2451 u32 tx_ring_idx = (u32) skb->queue_mapping;
c4e84bde
RM		 2452
2453 tx_ring = &qdev->tx_ring[tx_ring_idx];
2454
74c50b4b
RM		 2455 if (skb_padto(skb, ETH_ZLEN))
2456 return NETDEV_TX_OK;
2457
c4e84bde
RM		 2458 if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2459 QPRINTK(qdev, TX_QUEUED, INFO,
2460 "%s: shutting down tx queue %d du to lack of resources.\n",
2461 __func__, tx_ring_idx);
1e213303 2462 netif_stop_subqueue(ndev, tx_ring->wq_id);
c4e84bde 2463 atomic_inc(&tx_ring->queue_stopped);
885ee398 2464 tx_ring->tx_errors++;
c4e84bde
RM		 2465 return NETDEV_TX_BUSY;
2466 }
2467 tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
2468 mac_iocb_ptr = tx_ring_desc->queue_entry;
e332471c 2469 memset((void *)mac_iocb_ptr, 0, sizeof(*mac_iocb_ptr));
c4e84bde
RM		 2470
2471 mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
2472 mac_iocb_ptr->tid = tx_ring_desc->index;
2473 /* We use the upper 32-bits to store the tx queue for this IO.
2474 * When we get the completion we can use it to establish the context.
2475 */
2476 mac_iocb_ptr->txq_idx = tx_ring_idx;
2477 tx_ring_desc->skb = skb;
2478
2479 mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
2480
2481 if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
2482 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
2483 vlan_tx_tag_get(skb));
2484 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
2485 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
2486 }
2487 tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2488 if (tso < 0) {
2489 dev_kfree_skb_any(skb);
2490 return NETDEV_TX_OK;
2491 } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2492 ql_hw_csum_setup(skb,
2493 (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2494 }
0d979f74
RM		 2495 if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
2496 NETDEV_TX_OK) {
2497 QPRINTK(qdev, TX_QUEUED, ERR,
2498 "Could not map the segments.\n");
885ee398 2499 tx_ring->tx_errors++;
0d979f74
RM		 2500 return NETDEV_TX_BUSY;
2501 }
c4e84bde
RM		 2502 QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
2503 tx_ring->prod_idx++;
2504 if (tx_ring->prod_idx == tx_ring->wq_len)
2505 tx_ring->prod_idx = 0;
2506 wmb();
2507
2508 ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
c4e84bde
RM		 2509 QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
2510 tx_ring->prod_idx, skb->len);
2511
2512 atomic_dec(&tx_ring->tx_count);
2513 return NETDEV_TX_OK;
2514}
2515
9dfbbaa6 2516
c4e84bde
RM		 2517static void ql_free_shadow_space(struct ql_adapter *qdev)
2518{
2519 if (qdev->rx_ring_shadow_reg_area) {
2520 pci_free_consistent(qdev->pdev,
2521 PAGE_SIZE,
2522 qdev->rx_ring_shadow_reg_area,
2523 qdev->rx_ring_shadow_reg_dma);
2524 qdev->rx_ring_shadow_reg_area = NULL;
2525 }
2526 if (qdev->tx_ring_shadow_reg_area) {
2527 pci_free_consistent(qdev->pdev,
2528 PAGE_SIZE,
2529 qdev->tx_ring_shadow_reg_area,
2530 qdev->tx_ring_shadow_reg_dma);
2531 qdev->tx_ring_shadow_reg_area = NULL;
2532 }
2533}
2534
2535static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2536{
2537 qdev->rx_ring_shadow_reg_area =
2538 pci_alloc_consistent(qdev->pdev,
2539 PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2540 if (qdev->rx_ring_shadow_reg_area == NULL) {
2541 QPRINTK(qdev, IFUP, ERR,
2542 "Allocation of RX shadow space failed.\n");
2543 return -ENOMEM;
2544 }
b25215d0 2545 memset(qdev->rx_ring_shadow_reg_area, 0, PAGE_SIZE);
c4e84bde
RM		 2546 qdev->tx_ring_shadow_reg_area =
2547 pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2548 &qdev->tx_ring_shadow_reg_dma);
2549 if (qdev->tx_ring_shadow_reg_area == NULL) {
2550 QPRINTK(qdev, IFUP, ERR,
2551 "Allocation of TX shadow space failed.\n");
2552 goto err_wqp_sh_area;
2553 }
b25215d0 2554 memset(qdev->tx_ring_shadow_reg_area, 0, PAGE_SIZE);
c4e84bde
RM		 2555 return 0;
2556
2557err_wqp_sh_area:
2558 pci_free_consistent(qdev->pdev,
2559 PAGE_SIZE,
2560 qdev->rx_ring_shadow_reg_area,
2561 qdev->rx_ring_shadow_reg_dma);
2562 return -ENOMEM;
2563}
2564
2565static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2566{
2567 struct tx_ring_desc *tx_ring_desc;
2568 int i;
2569 struct ob_mac_iocb_req *mac_iocb_ptr;
2570
2571 mac_iocb_ptr = tx_ring->wq_base;
2572 tx_ring_desc = tx_ring->q;
2573 for (i = 0; i < tx_ring->wq_len; i++) {
2574 tx_ring_desc->index = i;
2575 tx_ring_desc->skb = NULL;
2576 tx_ring_desc->queue_entry = mac_iocb_ptr;
2577 mac_iocb_ptr++;
2578 tx_ring_desc++;
2579 }
2580 atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2581 atomic_set(&tx_ring->queue_stopped, 0);
2582}
2583
2584static void ql_free_tx_resources(struct ql_adapter *qdev,
2585 struct tx_ring *tx_ring)
2586{
2587 if (tx_ring->wq_base) {
2588 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2589 tx_ring->wq_base, tx_ring->wq_base_dma);
2590 tx_ring->wq_base = NULL;
2591 }
2592 kfree(tx_ring->q);
2593 tx_ring->q = NULL;
2594}
2595
2596static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2597 struct tx_ring *tx_ring)
2598{
2599 tx_ring->wq_base =
2600 pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2601 &tx_ring->wq_base_dma);
2602
8e95a202
JP		 2603 if ((tx_ring->wq_base == NULL) ||
2604 tx_ring->wq_base_dma & WQ_ADDR_ALIGN) {
c4e84bde
RM		 2605 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2606 return -ENOMEM;
2607 }
2608 tx_ring->q =
2609 kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2610 if (tx_ring->q == NULL)
2611 goto err;
2612
2613 return 0;
2614err:
2615 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2616 tx_ring->wq_base, tx_ring->wq_base_dma);
2617 return -ENOMEM;
2618}
2619
8668ae92 2620static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
c4e84bde 2621{
c4e84bde
RM		 2622 struct bq_desc *lbq_desc;
2623
7c734359
RM		 2624 uint32_t curr_idx, clean_idx;
2625
2626 curr_idx = rx_ring->lbq_curr_idx;
2627 clean_idx = rx_ring->lbq_clean_idx;
2628 while (curr_idx != clean_idx) {
2629 lbq_desc = &rx_ring->lbq[curr_idx];
2630
2631 if (lbq_desc->p.pg_chunk.last_flag) {
c4e84bde 2632 pci_unmap_page(qdev->pdev,
7c734359
RM		 2633 lbq_desc->p.pg_chunk.map,
2634 ql_lbq_block_size(qdev),
c4e84bde 2635 PCI_DMA_FROMDEVICE);
7c734359 2636 lbq_desc->p.pg_chunk.last_flag = 0;
c4e84bde 2637 }
7c734359
RM		 2638
2639 put_page(lbq_desc->p.pg_chunk.page);
2640 lbq_desc->p.pg_chunk.page = NULL;
2641
2642 if (++curr_idx == rx_ring->lbq_len)
2643 curr_idx = 0;
2644
c4e84bde
RM		 2645 }
2646}
2647
8668ae92 2648static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
c4e84bde
RM		 2649{
2650 int i;
2651 struct bq_desc *sbq_desc;
2652
2653 for (i = 0; i < rx_ring->sbq_len; i++) {
2654 sbq_desc = &rx_ring->sbq[i];
2655 if (sbq_desc == NULL) {
2656 QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2657 return;
2658 }
2659 if (sbq_desc->p.skb) {
2660 pci_unmap_single(qdev->pdev,
2661 pci_unmap_addr(sbq_desc, mapaddr),
2662 pci_unmap_len(sbq_desc, maplen),
2663 PCI_DMA_FROMDEVICE);
2664 dev_kfree_skb(sbq_desc->p.skb);
2665 sbq_desc->p.skb = NULL;
2666 }
c4e84bde
RM		 2667 }
2668}
2669
4545a3f2
RM		 2670/* Free all large and small rx buffers associated
2671 * with the completion queues for this device.
2672 */
2673static void ql_free_rx_buffers(struct ql_adapter *qdev)
2674{
2675 int i;
2676 struct rx_ring *rx_ring;
2677
2678 for (i = 0; i < qdev->rx_ring_count; i++) {
2679 rx_ring = &qdev->rx_ring[i];
2680 if (rx_ring->lbq)
2681 ql_free_lbq_buffers(qdev, rx_ring);
2682 if (rx_ring->sbq)
2683 ql_free_sbq_buffers(qdev, rx_ring);
2684 }
2685}
2686
2687static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
2688{
2689 struct rx_ring *rx_ring;
2690 int i;
2691
2692 for (i = 0; i < qdev->rx_ring_count; i++) {
2693 rx_ring = &qdev->rx_ring[i];
2694 if (rx_ring->type != TX_Q)
2695 ql_update_buffer_queues(qdev, rx_ring);
2696 }
2697}
2698
2699static void ql_init_lbq_ring(struct ql_adapter *qdev,
2700 struct rx_ring *rx_ring)
2701{
2702 int i;
2703 struct bq_desc *lbq_desc;
2704 __le64 *bq = rx_ring->lbq_base;
2705
2706 memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
2707 for (i = 0; i < rx_ring->lbq_len; i++) {
2708 lbq_desc = &rx_ring->lbq[i];
2709 memset(lbq_desc, 0, sizeof(*lbq_desc));
2710 lbq_desc->index = i;
2711 lbq_desc->addr = bq;
2712 bq++;
2713 }
2714}
2715
2716static void ql_init_sbq_ring(struct ql_adapter *qdev,
c4e84bde
RM		 2717 struct rx_ring *rx_ring)
2718{
2719 int i;
2720 struct bq_desc *sbq_desc;
2c9a0d41 2721 __le64 *bq = rx_ring->sbq_base;
c4e84bde 2722
4545a3f2 2723 memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
c4e84bde
RM		 2724 for (i = 0; i < rx_ring->sbq_len; i++) {
2725 sbq_desc = &rx_ring->sbq[i];
4545a3f2 2726 memset(sbq_desc, 0, sizeof(*sbq_desc));
c4e84bde 2727 sbq_desc->index = i;
2c9a0d41 2728 sbq_desc->addr = bq;
c4e84bde
RM		 2729 bq++;
2730 }
c4e84bde
RM		 2731}
2732
2733static void ql_free_rx_resources(struct ql_adapter *qdev,
2734 struct rx_ring *rx_ring)
2735{
c4e84bde
RM		 2736 /* Free the small buffer queue. */
2737 if (rx_ring->sbq_base) {
2738 pci_free_consistent(qdev->pdev,
2739 rx_ring->sbq_size,
2740 rx_ring->sbq_base, rx_ring->sbq_base_dma);
2741 rx_ring->sbq_base = NULL;
2742 }
2743
2744 /* Free the small buffer queue control blocks. */
2745 kfree(rx_ring->sbq);
2746 rx_ring->sbq = NULL;
2747
2748 /* Free the large buffer queue. */
2749 if (rx_ring->lbq_base) {
2750 pci_free_consistent(qdev->pdev,
2751 rx_ring->lbq_size,
2752 rx_ring->lbq_base, rx_ring->lbq_base_dma);
2753 rx_ring->lbq_base = NULL;
2754 }
2755
2756 /* Free the large buffer queue control blocks. */
2757 kfree(rx_ring->lbq);
2758 rx_ring->lbq = NULL;
2759
2760 /* Free the rx queue. */
2761 if (rx_ring->cq_base) {
2762 pci_free_consistent(qdev->pdev,
2763 rx_ring->cq_size,
2764 rx_ring->cq_base, rx_ring->cq_base_dma);
2765 rx_ring->cq_base = NULL;
2766 }
2767}
2768
2769/* Allocate queues and buffers for this completions queue based
2770 * on the values in the parameter structure. */
2771static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2772 struct rx_ring *rx_ring)
2773{
2774
2775 /*
2776 * Allocate the completion queue for this rx_ring.
2777 */
2778 rx_ring->cq_base =
2779 pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2780 &rx_ring->cq_base_dma);
2781
2782 if (rx_ring->cq_base == NULL) {
2783 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2784 return -ENOMEM;
2785 }
2786
2787 if (rx_ring->sbq_len) {
2788 /*
2789 * Allocate small buffer queue.
2790 */
2791 rx_ring->sbq_base =
2792 pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2793 &rx_ring->sbq_base_dma);
2794
2795 if (rx_ring->sbq_base == NULL) {
2796 QPRINTK(qdev, IFUP, ERR,
2797 "Small buffer queue allocation failed.\n");
2798 goto err_mem;
2799 }
2800
2801 /*
2802 * Allocate small buffer queue control blocks.
2803 */
2804 rx_ring->sbq =
2805 kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2806 GFP_KERNEL);
2807 if (rx_ring->sbq == NULL) {
2808 QPRINTK(qdev, IFUP, ERR,
2809 "Small buffer queue control block allocation failed.\n");
2810 goto err_mem;
2811 }
2812
4545a3f2 2813 ql_init_sbq_ring(qdev, rx_ring);
c4e84bde
RM		 2814 }
2815
2816 if (rx_ring->lbq_len) {
2817 /*
2818 * Allocate large buffer queue.
2819 */
2820 rx_ring->lbq_base =
2821 pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2822 &rx_ring->lbq_base_dma);
2823
2824 if (rx_ring->lbq_base == NULL) {
2825 QPRINTK(qdev, IFUP, ERR,
2826 "Large buffer queue allocation failed.\n");
2827 goto err_mem;
2828 }
2829 /*
2830 * Allocate large buffer queue control blocks.
2831 */
2832 rx_ring->lbq =
2833 kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2834 GFP_KERNEL);
2835 if (rx_ring->lbq == NULL) {
2836 QPRINTK(qdev, IFUP, ERR,
2837 "Large buffer queue control block allocation failed.\n");
2838 goto err_mem;
2839 }
2840
4545a3f2 2841 ql_init_lbq_ring(qdev, rx_ring);
c4e84bde
RM		 2842 }
2843
2844 return 0;
2845
2846err_mem:
2847 ql_free_rx_resources(qdev, rx_ring);
2848 return -ENOMEM;
2849}
2850
2851static void ql_tx_ring_clean(struct ql_adapter *qdev)
2852{
2853 struct tx_ring *tx_ring;
2854 struct tx_ring_desc *tx_ring_desc;
2855 int i, j;
2856
2857 /*
2858 * Loop through all queues and free
2859 * any resources.
2860 */
2861 for (j = 0; j < qdev->tx_ring_count; j++) {
2862 tx_ring = &qdev->tx_ring[j];
2863 for (i = 0; i < tx_ring->wq_len; i++) {
2864 tx_ring_desc = &tx_ring->q[i];
2865 if (tx_ring_desc && tx_ring_desc->skb) {
2866 QPRINTK(qdev, IFDOWN, ERR,
2867 "Freeing lost SKB %p, from queue %d, index %d.\n",
2868 tx_ring_desc->skb, j,
2869 tx_ring_desc->index);
2870 ql_unmap_send(qdev, tx_ring_desc,
2871 tx_ring_desc->map_cnt);
2872 dev_kfree_skb(tx_ring_desc->skb);
2873 tx_ring_desc->skb = NULL;
2874 }
2875 }
2876 }
2877}
2878
c4e84bde
RM		 2879static void ql_free_mem_resources(struct ql_adapter *qdev)
2880{
2881 int i;
2882
2883 for (i = 0; i < qdev->tx_ring_count; i++)
2884 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2885 for (i = 0; i < qdev->rx_ring_count; i++)
2886 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2887 ql_free_shadow_space(qdev);
2888}
2889
2890static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2891{
2892 int i;
2893
2894 /* Allocate space for our shadow registers and such. */
2895 if (ql_alloc_shadow_space(qdev))
2896 return -ENOMEM;
2897
2898 for (i = 0; i < qdev->rx_ring_count; i++) {
2899 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2900 QPRINTK(qdev, IFUP, ERR,
2901 "RX resource allocation failed.\n");
2902 goto err_mem;
2903 }
2904 }
2905 /* Allocate tx queue resources */
2906 for (i = 0; i < qdev->tx_ring_count; i++) {
2907 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2908 QPRINTK(qdev, IFUP, ERR,
2909 "TX resource allocation failed.\n");
2910 goto err_mem;
2911 }
2912 }
2913 return 0;
2914
2915err_mem:
2916 ql_free_mem_resources(qdev);
2917 return -ENOMEM;
2918}
2919
2920/* Set up the rx ring control block and pass it to the chip.
2921 * The control block is defined as
2922 * "Completion Queue Initialization Control Block", or cqicb.
2923 */
2924static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2925{
2926 struct cqicb *cqicb = &rx_ring->cqicb;
2927 void *shadow_reg = qdev->rx_ring_shadow_reg_area +
b8facca0 2928 (rx_ring->cq_id * RX_RING_SHADOW_SPACE);
c4e84bde 2929 u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
b8facca0 2930 (rx_ring->cq_id * RX_RING_SHADOW_SPACE);
c4e84bde
RM		 2931 void __iomem *doorbell_area =
2932 qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2933 int err = 0;
2934 u16 bq_len;
d4a4aba6 2935 u64 tmp;
b8facca0
RM		 2936 __le64 *base_indirect_ptr;
2937 int page_entries;
c4e84bde
RM		 2938
2939 /* Set up the shadow registers for this ring. */
2940 rx_ring->prod_idx_sh_reg = shadow_reg;
2941 rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
7c734359 2942 *rx_ring->prod_idx_sh_reg = 0;
c4e84bde
RM		 2943 shadow_reg += sizeof(u64);
2944 shadow_reg_dma += sizeof(u64);
2945 rx_ring->lbq_base_indirect = shadow_reg;
2946 rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
b8facca0
RM		 2947 shadow_reg += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
2948 shadow_reg_dma += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
c4e84bde
RM		 2949 rx_ring->sbq_base_indirect = shadow_reg;
2950 rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2951
2952 /* PCI doorbell mem area + 0x00 for consumer index register */
8668ae92 2953 rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
c4e84bde
RM		 2954 rx_ring->cnsmr_idx = 0;
2955 rx_ring->curr_entry = rx_ring->cq_base;
2956
2957 /* PCI doorbell mem area + 0x04 for valid register */
2958 rx_ring->valid_db_reg = doorbell_area + 0x04;
2959
2960 /* PCI doorbell mem area + 0x18 for large buffer consumer */
8668ae92 2961 rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
c4e84bde
RM		 2962
2963 /* PCI doorbell mem area + 0x1c */
8668ae92 2964 rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
c4e84bde
RM		 2965
2966 memset((void *)cqicb, 0, sizeof(struct cqicb));
2967 cqicb->msix_vect = rx_ring->irq;
2968
459caf5a
RM		 2969 bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2970 cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
c4e84bde 2971
97345524 2972 cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
c4e84bde 2973
97345524 2974 cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
c4e84bde
RM		 2975
2976 /*
2977 * Set up the control block load flags.
2978 */
2979 cqicb->flags = FLAGS_LC | /* Load queue base address */
2980 FLAGS_LV | /* Load MSI-X vector */
2981 FLAGS_LI; /* Load irq delay values */
2982 if (rx_ring->lbq_len) {
2983 cqicb->flags |= FLAGS_LL; /* Load lbq values */
a419aef8 2984 tmp = (u64)rx_ring->lbq_base_dma;
b8facca0
RM		 2985 base_indirect_ptr = (__le64 *) rx_ring->lbq_base_indirect;
2986 page_entries = 0;
2987 do {
2988 *base_indirect_ptr = cpu_to_le64(tmp);
2989 tmp += DB_PAGE_SIZE;
2990 base_indirect_ptr++;
2991 page_entries++;
2992 } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
97345524
RM		 2993 cqicb->lbq_addr =
2994 cpu_to_le64(rx_ring->lbq_base_indirect_dma);
459caf5a
RM		 2995 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2996 (u16) rx_ring->lbq_buf_size;
2997 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2998 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2999 (u16) rx_ring->lbq_len;
c4e84bde 3000 cqicb->lbq_len = cpu_to_le16(bq_len);
4545a3f2 3001 rx_ring->lbq_prod_idx = 0;
c4e84bde 3002 rx_ring->lbq_curr_idx = 0;
4545a3f2
RM		 3003 rx_ring->lbq_clean_idx = 0;
3004 rx_ring->lbq_free_cnt = rx_ring->lbq_len;
c4e84bde
RM		 3005 }
3006 if (rx_ring->sbq_len) {
3007 cqicb->flags |= FLAGS_LS; /* Load sbq values */
a419aef8 3008 tmp = (u64)rx_ring->sbq_base_dma;
b8facca0
RM		 3009 base_indirect_ptr = (__le64 *) rx_ring->sbq_base_indirect;
3010 page_entries = 0;
3011 do {
3012 *base_indirect_ptr = cpu_to_le64(tmp);
3013 tmp += DB_PAGE_SIZE;
3014 base_indirect_ptr++;
3015 page_entries++;
3016 } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->sbq_len));
97345524
RM		 3017 cqicb->sbq_addr =
3018 cpu_to_le64(rx_ring->sbq_base_indirect_dma);
c4e84bde 3019 cqicb->sbq_buf_size =
52e55f3c 3020 cpu_to_le16((u16)(rx_ring->sbq_buf_size));
459caf5a
RM		 3021 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
3022 (u16) rx_ring->sbq_len;
c4e84bde 3023 cqicb->sbq_len = cpu_to_le16(bq_len);
4545a3f2 3024 rx_ring->sbq_prod_idx = 0;
c4e84bde 3025 rx_ring->sbq_curr_idx = 0;
4545a3f2
RM		 3026 rx_ring->sbq_clean_idx = 0;
3027 rx_ring->sbq_free_cnt = rx_ring->sbq_len;
c4e84bde
RM		 3028 }
3029 switch (rx_ring->type) {
3030 case TX_Q:
c4e84bde
RM		 3031 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
3032 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
3033 break;
c4e84bde
RM		 3034 case RX_Q:
3035 /* Inbound completion handling rx_rings run in
3036 * separate NAPI contexts.
3037 */
3038 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
3039 64);
3040 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
3041 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
3042 break;
3043 default:
3044 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
3045 rx_ring->type);
3046 }
4974097a 3047 QPRINTK(qdev, IFUP, DEBUG, "Initializing rx work queue.\n");
c4e84bde
RM		 3048 err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
3049 CFG_LCQ, rx_ring->cq_id);
3050 if (err) {
3051 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
3052 return err;
3053 }
c4e84bde
RM		 3054 return err;
3055}
3056
3057static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
3058{
3059 struct wqicb *wqicb = (struct wqicb *)tx_ring;
3060 void __iomem *doorbell_area =
3061 qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
3062 void *shadow_reg = qdev->tx_ring_shadow_reg_area +
3063 (tx_ring->wq_id * sizeof(u64));
3064 u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
3065 (tx_ring->wq_id * sizeof(u64));
3066 int err = 0;
3067
3068 /*
3069 * Assign doorbell registers for this tx_ring.
3070 */
3071 /* TX PCI doorbell mem area for tx producer index */
8668ae92 3072 tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
c4e84bde
RM		 3073 tx_ring->prod_idx = 0;
3074 /* TX PCI doorbell mem area + 0x04 */
3075 tx_ring->valid_db_reg = doorbell_area + 0x04;
3076
3077 /*
3078 * Assign shadow registers for this tx_ring.
3079 */
3080 tx_ring->cnsmr_idx_sh_reg = shadow_reg;
3081 tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
3082
3083 wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
3084 wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
3085 Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
3086 wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
3087 wqicb->rid = 0;
97345524 3088 wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
c4e84bde 3089
97345524 3090 wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
c4e84bde
RM		 3091
3092 ql_init_tx_ring(qdev, tx_ring);
3093
e332471c 3094 err = ql_write_cfg(qdev, wqicb, sizeof(*wqicb), CFG_LRQ,
c4e84bde
RM		 3095 (u16) tx_ring->wq_id);
3096 if (err) {
3097 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
3098 return err;
3099 }
4974097a 3100 QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded WQICB.\n");
c4e84bde
RM		 3101 return err;
3102}
3103
3104static void ql_disable_msix(struct ql_adapter *qdev)
3105{
3106 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
3107 pci_disable_msix(qdev->pdev);
3108 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
3109 kfree(qdev->msi_x_entry);
3110 qdev->msi_x_entry = NULL;
3111 } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3112 pci_disable_msi(qdev->pdev);
3113 clear_bit(QL_MSI_ENABLED, &qdev->flags);
3114 }
3115}
3116
a4ab6137
RM		 3117/* We start by trying to get the number of vectors
3118 * stored in qdev->intr_count. If we don't get that
3119 * many then we reduce the count and try again.
3120 */
c4e84bde
RM		 3121static void ql_enable_msix(struct ql_adapter *qdev)
3122{
a4ab6137 3123 int i, err;
c4e84bde 3124
c4e84bde 3125 /* Get the MSIX vectors. */
a5a62a1c 3126 if (qlge_irq_type == MSIX_IRQ) {
c4e84bde
RM		 3127 /* Try to alloc space for the msix struct,
3128 * if it fails then go to MSI/legacy.
3129 */
a4ab6137 3130 qdev->msi_x_entry = kcalloc(qdev->intr_count,
c4e84bde
RM		 3131 sizeof(struct msix_entry),
3132 GFP_KERNEL);
3133 if (!qdev->msi_x_entry) {
a5a62a1c 3134 qlge_irq_type = MSI_IRQ;
c4e84bde
RM		 3135 goto msi;
3136 }
3137
a4ab6137 3138 for (i = 0; i < qdev->intr_count; i++)
c4e84bde
RM		 3139 qdev->msi_x_entry[i].entry = i;
3140
a4ab6137
RM		 3141 /* Loop to get our vectors. We start with
3142 * what we want and settle for what we get.
3143 */
3144 do {
3145 err = pci_enable_msix(qdev->pdev,
3146 qdev->msi_x_entry, qdev->intr_count);
3147 if (err > 0)
3148 qdev->intr_count = err;
3149 } while (err > 0);
3150
3151 if (err < 0) {
c4e84bde
RM		 3152 kfree(qdev->msi_x_entry);
3153 qdev->msi_x_entry = NULL;
3154 QPRINTK(qdev, IFUP, WARNING,
3155 "MSI-X Enable failed, trying MSI.\n");
a4ab6137 3156 qdev->intr_count = 1;
a5a62a1c 3157 qlge_irq_type = MSI_IRQ;
a4ab6137
RM		 3158 } else if (err == 0) {
3159 set_bit(QL_MSIX_ENABLED, &qdev->flags);
3160 QPRINTK(qdev, IFUP, INFO,
3161 "MSI-X Enabled, got %d vectors.\n",
3162 qdev->intr_count);
3163 return;
c4e84bde
RM		 3164 }
3165 }
3166msi:
a4ab6137 3167 qdev->intr_count = 1;
a5a62a1c 3168 if (qlge_irq_type == MSI_IRQ) {
c4e84bde
RM		 3169 if (!pci_enable_msi(qdev->pdev)) {
3170 set_bit(QL_MSI_ENABLED, &qdev->flags);
3171 QPRINTK(qdev, IFUP, INFO,
3172 "Running with MSI interrupts.\n");
3173 return;
3174 }
3175 }
a5a62a1c 3176 qlge_irq_type = LEG_IRQ;
c4e84bde
RM		 3177 QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
3178}
3179
39aa8165
RM		 3180/* Each vector services 1 RSS ring and and 1 or more
3181 * TX completion rings. This function loops through
3182 * the TX completion rings and assigns the vector that
3183 * will service it. An example would be if there are
3184 * 2 vectors (so 2 RSS rings) and 8 TX completion rings.
3185 * This would mean that vector 0 would service RSS ring 0
3186 * and TX competion rings 0,1,2 and 3. Vector 1 would
3187 * service RSS ring 1 and TX completion rings 4,5,6 and 7.
3188 */
3189static void ql_set_tx_vect(struct ql_adapter *qdev)
3190{
3191 int i, j, vect;
3192 u32 tx_rings_per_vector = qdev->tx_ring_count / qdev->intr_count;
3193
3194 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
3195 /* Assign irq vectors to TX rx_rings.*/
3196 for (vect = 0, j = 0, i = qdev->rss_ring_count;
3197 i < qdev->rx_ring_count; i++) {
3198 if (j == tx_rings_per_vector) {
3199 vect++;
3200 j = 0;
3201 }
3202 qdev->rx_ring[i].irq = vect;
3203 j++;
3204 }
3205 } else {
3206 /* For single vector all rings have an irq
3207 * of zero.
3208 */
3209 for (i = 0; i < qdev->rx_ring_count; i++)
3210 qdev->rx_ring[i].irq = 0;
3211 }
3212}
3213
3214/* Set the interrupt mask for this vector. Each vector
3215 * will service 1 RSS ring and 1 or more TX completion
3216 * rings. This function sets up a bit mask per vector
3217 * that indicates which rings it services.
3218 */
3219static void ql_set_irq_mask(struct ql_adapter *qdev, struct intr_context *ctx)
3220{
3221 int j, vect = ctx->intr;
3222 u32 tx_rings_per_vector = qdev->tx_ring_count / qdev->intr_count;
3223
3224 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
3225 /* Add the RSS ring serviced by this vector
3226 * to the mask.
3227 */
3228 ctx->irq_mask = (1 << qdev->rx_ring[vect].cq_id);
3229 /* Add the TX ring(s) serviced by this vector
3230 * to the mask. */
3231 for (j = 0; j < tx_rings_per_vector; j++) {
3232 ctx->irq_mask |=
3233 (1 << qdev->rx_ring[qdev->rss_ring_count +
3234 (vect * tx_rings_per_vector) + j].cq_id);
3235 }
3236 } else {
3237 /* For single vector we just shift each queue's
3238 * ID into the mask.
3239 */
3240 for (j = 0; j < qdev->rx_ring_count; j++)
3241 ctx->irq_mask |= (1 << qdev->rx_ring[j].cq_id);
3242 }
3243}
3244
c4e84bde
RM		 3245/*
3246 * Here we build the intr_context structures based on
3247 * our rx_ring count and intr vector count.
3248 * The intr_context structure is used to hook each vector
3249 * to possibly different handlers.
3250 */
3251static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
3252{
3253 int i = 0;
3254 struct intr_context *intr_context = &qdev->intr_context[0];
3255
c4e84bde
RM		 3256 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
3257 /* Each rx_ring has it's
3258 * own intr_context since we have separate
3259 * vectors for each queue.
c4e84bde
RM		 3260 */
3261 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
3262 qdev->rx_ring[i].irq = i;
3263 intr_context->intr = i;
3264 intr_context->qdev = qdev;
39aa8165
RM		 3265 /* Set up this vector's bit-mask that indicates
3266 * which queues it services.
3267 */
3268 ql_set_irq_mask(qdev, intr_context);
c4e84bde
RM		 3269 /*
3270 * We set up each vectors enable/disable/read bits so
3271 * there's no bit/mask calculations in the critical path.
3272 */
3273 intr_context->intr_en_mask =
3274 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3275 INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
3276 | i;
3277 intr_context->intr_dis_mask =
3278 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3279 INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
3280 INTR_EN_IHD | i;
3281 intr_context->intr_read_mask =
3282 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3283 INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
3284 i;
39aa8165
RM		 3285 if (i == 0) {
3286 /* The first vector/queue handles
3287 * broadcast/multicast, fatal errors,
3288 * and firmware events. This in addition
3289 * to normal inbound NAPI processing.
c4e84bde 3290 */
39aa8165 3291 intr_context->handler = qlge_isr;
b2014ff8
RM		 3292 sprintf(intr_context->name, "%s-rx-%d",
3293 qdev->ndev->name, i);
3294 } else {
c4e84bde 3295 /*
39aa8165 3296 * Inbound queues handle unicast frames only.
c4e84bde 3297 */
39aa8165
RM		 3298 intr_context->handler = qlge_msix_rx_isr;
3299 sprintf(intr_context->name, "%s-rx-%d",
c4e84bde 3300 qdev->ndev->name, i);
c4e84bde
RM		 3301 }
3302 }
3303 } else {
3304 /*
3305 * All rx_rings use the same intr_context since
3306 * there is only one vector.
3307 */
3308 intr_context->intr = 0;
3309 intr_context->qdev = qdev;
3310 /*
3311 * We set up each vectors enable/disable/read bits so
3312 * there's no bit/mask calculations in the critical path.
3313 */
3314 intr_context->intr_en_mask =
3315 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
3316 intr_context->intr_dis_mask =
3317 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3318 INTR_EN_TYPE_DISABLE;
3319 intr_context->intr_read_mask =
3320 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
3321 /*
3322 * Single interrupt means one handler for all rings.
3323 */
3324 intr_context->handler = qlge_isr;
3325 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
39aa8165
RM		 3326 /* Set up this vector's bit-mask that indicates
3327 * which queues it services. In this case there is
3328 * a single vector so it will service all RSS and
3329 * TX completion rings.
3330 */
3331 ql_set_irq_mask(qdev, intr_context);
c4e84bde 3332 }
39aa8165
RM		 3333 /* Tell the TX completion rings which MSIx vector
3334 * they will be using.
3335 */
3336 ql_set_tx_vect(qdev);
c4e84bde
RM		 3337}
3338
3339static void ql_free_irq(struct ql_adapter *qdev)
3340{
3341 int i;
3342 struct intr_context *intr_context = &qdev->intr_context[0];
3343
3344 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
3345 if (intr_context->hooked) {
3346 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
3347 free_irq(qdev->msi_x_entry[i].vector,
3348 &qdev->rx_ring[i]);
4974097a 3349 QPRINTK(qdev, IFDOWN, DEBUG,
c4e84bde
RM		 3350 "freeing msix interrupt %d.\n", i);
3351 } else {
3352 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
4974097a 3353 QPRINTK(qdev, IFDOWN, DEBUG,
c4e84bde
RM		 3354 "freeing msi interrupt %d.\n", i);
3355 }
3356 }
3357 }
3358 ql_disable_msix(qdev);
3359}
3360
3361static int ql_request_irq(struct ql_adapter *qdev)
3362{
3363 int i;
3364 int status = 0;
3365 struct pci_dev *pdev = qdev->pdev;
3366 struct intr_context *intr_context = &qdev->intr_context[0];
3367
3368 ql_resolve_queues_to_irqs(qdev);
3369
3370 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
3371 atomic_set(&intr_context->irq_cnt, 0);
3372 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
3373 status = request_irq(qdev->msi_x_entry[i].vector,
3374 intr_context->handler,
3375 0,
3376 intr_context->name,
3377 &qdev->rx_ring[i]);
3378 if (status) {
3379 QPRINTK(qdev, IFUP, ERR,
3380 "Failed request for MSIX interrupt %d.\n",
3381 i);
3382 goto err_irq;
3383 } else {
4974097a 3384 QPRINTK(qdev, IFUP, DEBUG,
c4e84bde
RM		 3385 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
3386 i,
3387 qdev->rx_ring[i].type ==
3388 DEFAULT_Q ? "DEFAULT_Q" : "",
3389 qdev->rx_ring[i].type ==
3390 TX_Q ? "TX_Q" : "",
3391 qdev->rx_ring[i].type ==
3392 RX_Q ? "RX_Q" : "", intr_context->name);
3393 }
3394 } else {
3395 QPRINTK(qdev, IFUP, DEBUG,
3396 "trying msi or legacy interrupts.\n");
3397 QPRINTK(qdev, IFUP, DEBUG,
3398 "%s: irq = %d.\n", __func__, pdev->irq);
3399 QPRINTK(qdev, IFUP, DEBUG,
3400 "%s: context->name = %s.\n", __func__,
3401 intr_context->name);
3402 QPRINTK(qdev, IFUP, DEBUG,
3403 "%s: dev_id = 0x%p.\n", __func__,
3404 &qdev->rx_ring[0]);
3405 status =
3406 request_irq(pdev->irq, qlge_isr,
3407 test_bit(QL_MSI_ENABLED,
3408 &qdev->
3409 flags) ? 0 : IRQF_SHARED,
3410 intr_context->name, &qdev->rx_ring[0]);
3411 if (status)
3412 goto err_irq;
3413
3414 QPRINTK(qdev, IFUP, ERR,
3415 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
3416 i,
3417 qdev->rx_ring[0].type ==
3418 DEFAULT_Q ? "DEFAULT_Q" : "",
3419 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
3420 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
3421 intr_context->name);
3422 }
3423 intr_context->hooked = 1;
3424 }
3425 return status;
3426err_irq:
3427 QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
3428 ql_free_irq(qdev);
3429 return status;
3430}
3431
3432static int ql_start_rss(struct ql_adapter *qdev)
3433{
541ae28c
RM		 3434 u8 init_hash_seed[] = {0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2,
3435 0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f,
3436 0xb0, 0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b,
3437 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80,
3438 0x30, 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b,
3439 0xbe, 0xac, 0x01, 0xfa};
c4e84bde
RM		 3440 struct ricb *ricb = &qdev->ricb;
3441 int status = 0;
3442 int i;
3443 u8 *hash_id = (u8 *) ricb->hash_cq_id;
3444
e332471c 3445 memset((void *)ricb, 0, sizeof(*ricb));
c4e84bde 3446
b2014ff8 3447 ricb->base_cq = RSS_L4K;
c4e84bde 3448 ricb->flags =
541ae28c
RM		 3449 (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RT4 | RSS_RT6);
3450 ricb->mask = cpu_to_le16((u16)(0x3ff));
c4e84bde
RM		 3451
3452 /*
3453 * Fill out the Indirection Table.
3454 */
541ae28c
RM		 3455 for (i = 0; i < 1024; i++)
3456 hash_id[i] = (i & (qdev->rss_ring_count - 1));
c4e84bde 3457
541ae28c
RM		 3458 memcpy((void *)&ricb->ipv6_hash_key[0], init_hash_seed, 40);
3459 memcpy((void *)&ricb->ipv4_hash_key[0], init_hash_seed, 16);
c4e84bde 3460
4974097a 3461 QPRINTK(qdev, IFUP, DEBUG, "Initializing RSS.\n");
c4e84bde 3462
e332471c 3463 status = ql_write_cfg(qdev, ricb, sizeof(*ricb), CFG_LR, 0);
c4e84bde
RM		 3464 if (status) {
3465 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
3466 return status;
3467 }
4974097a 3468 QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded RICB.\n");
c4e84bde
RM		 3469 return status;
3470}
3471
a5f59dc9 3472static int ql_clear_routing_entries(struct ql_adapter *qdev)
c4e84bde 3473{
a5f59dc9 3474 int i, status = 0;
c4e84bde 3475
8587ea35
RM		 3476 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3477 if (status)
3478 return status;
c4e84bde
RM		 3479 /* Clear all the entries in the routing table. */
3480 for (i = 0; i < 16; i++) {
3481 status = ql_set_routing_reg(qdev, i, 0, 0);
3482 if (status) {
3483 QPRINTK(qdev, IFUP, ERR,
a5f59dc9
RM		 3484 "Failed to init routing register for CAM "
3485 "packets.\n");
3486 break;
c4e84bde
RM		 3487 }
3488 }
a5f59dc9
RM		 3489 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3490 return status;
3491}
3492
3493/* Initialize the frame-to-queue routing. */
3494static int ql_route_initialize(struct ql_adapter *qdev)
3495{
3496 int status = 0;
3497
fd21cf52
RM		 3498 /* Clear all the entries in the routing table. */
3499 status = ql_clear_routing_entries(qdev);
a5f59dc9
RM		 3500 if (status)
3501 return status;
3502
fd21cf52 3503 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
a5f59dc9 3504 if (status)
fd21cf52 3505 return status;
c4e84bde
RM		 3506
3507 status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
3508 if (status) {
3509 QPRINTK(qdev, IFUP, ERR,
3510 "Failed to init routing register for error packets.\n");
8587ea35 3511 goto exit;
c4e84bde
RM		 3512 }
3513 status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
3514 if (status) {
3515 QPRINTK(qdev, IFUP, ERR,
3516 "Failed to init routing register for broadcast packets.\n");
8587ea35 3517 goto exit;
c4e84bde
RM		 3518 }
3519 /* If we have more than one inbound queue, then turn on RSS in the
3520 * routing block.
3521 */
3522 if (qdev->rss_ring_count > 1) {
3523 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
3524 RT_IDX_RSS_MATCH, 1);
3525 if (status) {
3526 QPRINTK(qdev, IFUP, ERR,
3527 "Failed to init routing register for MATCH RSS packets.\n");
8587ea35 3528 goto exit;
c4e84bde
RM		 3529 }
3530 }
3531
3532 status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
3533 RT_IDX_CAM_HIT, 1);
8587ea35 3534 if (status)
c4e84bde
RM		 3535 QPRINTK(qdev, IFUP, ERR,
3536 "Failed to init routing register for CAM packets.\n");
8587ea35
RM		 3537exit:
3538 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
c4e84bde
RM		 3539 return status;
3540}
3541
2ee1e272 3542int ql_cam_route_initialize(struct ql_adapter *qdev)
bb58b5b6 3543{
7fab3bfe 3544 int status, set;
bb58b5b6 3545
7fab3bfe
RM		 3546 /* If check if the link is up and use to
3547 * determine if we are setting or clearing
3548 * the MAC address in the CAM.
3549 */
3550 set = ql_read32(qdev, STS);
3551 set &= qdev->port_link_up;
3552 status = ql_set_mac_addr(qdev, set);
bb58b5b6
RM		 3553 if (status) {
3554 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3555 return status;
3556 }
3557
3558 status = ql_route_initialize(qdev);
3559 if (status)
3560 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3561
3562 return status;
3563}
3564
c4e84bde
RM		 3565static int ql_adapter_initialize(struct ql_adapter *qdev)
3566{
3567 u32 value, mask;
3568 int i;
3569 int status = 0;
3570
3571 /*
3572 * Set up the System register to halt on errors.
3573 */
3574 value = SYS_EFE | SYS_FAE;
3575 mask = value << 16;
3576 ql_write32(qdev, SYS, mask | value);
3577
c9cf0a04
RM		 3578 /* Set the default queue, and VLAN behavior. */
3579 value = NIC_RCV_CFG_DFQ | NIC_RCV_CFG_RV;
3580 mask = NIC_RCV_CFG_DFQ_MASK | (NIC_RCV_CFG_RV << 16);
c4e84bde
RM		 3581 ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3582
3583 /* Set the MPI interrupt to enabled. */
3584 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3585
3586 /* Enable the function, set pagesize, enable error checking. */
3587 value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
572c526f
RM		 3588 FSC_EC | FSC_VM_PAGE_4K;
3589 value |= SPLT_SETTING;
c4e84bde
RM		 3590
3591 /* Set/clear header splitting. */
3592 mask = FSC_VM_PAGESIZE_MASK |
3593 FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3594 ql_write32(qdev, FSC, mask | value);
3595
572c526f 3596 ql_write32(qdev, SPLT_HDR, SPLT_LEN);
c4e84bde 3597
a3b71939
RM		 3598 /* Set RX packet routing to use port/pci function on which the
3599 * packet arrived on in addition to usual frame routing.
3600 * This is helpful on bonding where both interfaces can have
3601 * the same MAC address.
3602 */
3603 ql_write32(qdev, RST_FO, RST_FO_RR_MASK | RST_FO_RR_RCV_FUNC_CQ);
bc083ce9
RM		 3604 /* Reroute all packets to our Interface.
3605 * They may have been routed to MPI firmware
3606 * due to WOL.
3607 */
3608 value = ql_read32(qdev, MGMT_RCV_CFG);
3609 value &= ~MGMT_RCV_CFG_RM;
3610 mask = 0xffff0000;
3611
3612 /* Sticky reg needs clearing due to WOL. */
3613 ql_write32(qdev, MGMT_RCV_CFG, mask);
3614 ql_write32(qdev, MGMT_RCV_CFG, mask | value);
3615
3616 /* Default WOL is enable on Mezz cards */
3617 if (qdev->pdev->subsystem_device == 0x0068 ||
3618 qdev->pdev->subsystem_device == 0x0180)
3619 qdev->wol = WAKE_MAGIC;
a3b71939 3620
c4e84bde
RM		 3621 /* Start up the rx queues. */
3622 for (i = 0; i < qdev->rx_ring_count; i++) {
3623 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3624 if (status) {
3625 QPRINTK(qdev, IFUP, ERR,
3626 "Failed to start rx ring[%d].\n", i);
3627 return status;
3628 }
3629 }
3630
3631 /* If there is more than one inbound completion queue
3632 * then download a RICB to configure RSS.
3633 */
3634 if (qdev->rss_ring_count > 1) {
3635 status = ql_start_rss(qdev);
3636 if (status) {
3637 QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3638 return status;
3639 }
3640 }
3641
3642 /* Start up the tx queues. */
3643 for (i = 0; i < qdev->tx_ring_count; i++) {
3644 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3645 if (status) {
3646 QPRINTK(qdev, IFUP, ERR,
3647 "Failed to start tx ring[%d].\n", i);
3648 return status;
3649 }
3650 }
3651
b0c2aadf
RM		 3652 /* Initialize the port and set the max framesize. */
3653 status = qdev->nic_ops->port_initialize(qdev);
80928860
RM		 3654 if (status)
3655 QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
c4e84bde 3656
bb58b5b6
RM		 3657 /* Set up the MAC address and frame routing filter. */
3658 status = ql_cam_route_initialize(qdev);
c4e84bde 3659 if (status) {
bb58b5b6
RM		 3660 QPRINTK(qdev, IFUP, ERR,
3661 "Failed to init CAM/Routing tables.\n");
c4e84bde
RM		 3662 return status;
3663 }
3664
3665 /* Start NAPI for the RSS queues. */
b2014ff8 3666 for (i = 0; i < qdev->rss_ring_count; i++) {
4974097a 3667 QPRINTK(qdev, IFUP, DEBUG, "Enabling NAPI for rx_ring[%d].\n",
c4e84bde
RM		 3668 i);
3669 napi_enable(&qdev->rx_ring[i].napi);
3670 }
3671
3672 return status;
3673}
3674
3675/* Issue soft reset to chip. */
3676static int ql_adapter_reset(struct ql_adapter *qdev)
3677{
3678 u32 value;
c4e84bde 3679 int status = 0;
a5f59dc9 3680 unsigned long end_jiffies;
c4e84bde 3681
a5f59dc9
RM		 3682 /* Clear all the entries in the routing table. */
3683 status = ql_clear_routing_entries(qdev);
3684 if (status) {
3685 QPRINTK(qdev, IFUP, ERR, "Failed to clear routing bits.\n");
3686 return status;
3687 }
3688
3689 end_jiffies = jiffies +
3690 max((unsigned long)1, usecs_to_jiffies(30));
84087f4d
RM		 3691
3692 /* Stop management traffic. */
3693 ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_STOP);
3694
3695 /* Wait for the NIC and MGMNT FIFOs to empty. */
3696 ql_wait_fifo_empty(qdev);
3697
c4e84bde 3698 ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
a75ee7f1 3699
c4e84bde
RM		 3700 do {
3701 value = ql_read32(qdev, RST_FO);
3702 if ((value & RST_FO_FR) == 0)
3703 break;
a75ee7f1
RM		 3704 cpu_relax();
3705 } while (time_before(jiffies, end_jiffies));
c4e84bde 3706
c4e84bde 3707 if (value & RST_FO_FR) {
c4e84bde 3708 QPRINTK(qdev, IFDOWN, ERR,
3ac49a1c 3709 "ETIMEDOUT!!! errored out of resetting the chip!\n");
a75ee7f1 3710 status = -ETIMEDOUT;
c4e84bde
RM		 3711 }
3712
84087f4d
RM		 3713 /* Resume management traffic. */
3714 ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_RESUME);
c4e84bde
RM		 3715 return status;
3716}
3717
3718static void ql_display_dev_info(struct net_device *ndev)
3719{
3720 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3721
3722 QPRINTK(qdev, PROBE, INFO,
e4552f51 3723 "Function #%d, Port %d, NIC Roll %d, NIC Rev = %d, "
c4e84bde
RM		 3724 "XG Roll = %d, XG Rev = %d.\n",
3725 qdev->func,
e4552f51 3726 qdev->port,
c4e84bde
RM		 3727 qdev->chip_rev_id & 0x0000000f,
3728 qdev->chip_rev_id >> 4 & 0x0000000f,
3729 qdev->chip_rev_id >> 8 & 0x0000000f,
3730 qdev->chip_rev_id >> 12 & 0x0000000f);
7c510e4b 3731 QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
c4e84bde
RM		 3732}
3733
bc083ce9
RM		 3734int ql_wol(struct ql_adapter *qdev)
3735{
3736 int status = 0;
3737 u32 wol = MB_WOL_DISABLE;
3738
3739 /* The CAM is still intact after a reset, but if we
3740 * are doing WOL, then we may need to program the
3741 * routing regs. We would also need to issue the mailbox
3742 * commands to instruct the MPI what to do per the ethtool
3743 * settings.
3744 */
3745
3746 if (qdev->wol & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_PHY | WAKE_UCAST |
3747 WAKE_MCAST | WAKE_BCAST)) {
3748 QPRINTK(qdev, IFDOWN, ERR,
3749 "Unsupported WOL paramter. qdev->wol = 0x%x.\n",
3750 qdev->wol);
3751 return -EINVAL;
3752 }
3753
3754 if (qdev->wol & WAKE_MAGIC) {
3755 status = ql_mb_wol_set_magic(qdev, 1);
3756 if (status) {
3757 QPRINTK(qdev, IFDOWN, ERR,
3758 "Failed to set magic packet on %s.\n",
3759 qdev->ndev->name);
3760 return status;
3761 } else
3762 QPRINTK(qdev, DRV, INFO,
3763 "Enabled magic packet successfully on %s.\n",
3764 qdev->ndev->name);
3765
3766 wol |= MB_WOL_MAGIC_PKT;
3767 }
3768
3769 if (qdev->wol) {
bc083ce9
RM		 3770 wol |= MB_WOL_MODE_ON;
3771 status = ql_mb_wol_mode(qdev, wol);
3772 QPRINTK(qdev, DRV, ERR, "WOL %s (wol code 0x%x) on %s\n",
3773 (status == 0) ? "Sucessfully set" : "Failed", wol,
3774 qdev->ndev->name);
3775 }
3776
3777 return status;
3778}
3779
c4e84bde
RM		 3780static int ql_adapter_down(struct ql_adapter *qdev)
3781{
c4e84bde 3782 int i, status = 0;
c4e84bde 3783
6a473308 3784 ql_link_off(qdev);
c4e84bde 3785
6497b607
RM		 3786 /* Don't kill the reset worker thread if we
3787 * are in the process of recovery.
3788 */
3789 if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3790 cancel_delayed_work_sync(&qdev->asic_reset_work);
c4e84bde
RM		 3791 cancel_delayed_work_sync(&qdev->mpi_reset_work);
3792 cancel_delayed_work_sync(&qdev->mpi_work);
2ee1e272 3793 cancel_delayed_work_sync(&qdev->mpi_idc_work);
bcc2cb3b 3794 cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
c4e84bde 3795
39aa8165
RM		 3796 for (i = 0; i < qdev->rss_ring_count; i++)
3797 napi_disable(&qdev->rx_ring[i].napi);
c4e84bde
RM		 3798
3799 clear_bit(QL_ADAPTER_UP, &qdev->flags);
3800
3801 ql_disable_interrupts(qdev);
3802
3803 ql_tx_ring_clean(qdev);
3804
6b318cb3
RM		 3805 /* Call netif_napi_del() from common point.
3806 */
b2014ff8 3807 for (i = 0; i < qdev->rss_ring_count; i++)
6b318cb3
RM		 3808 netif_napi_del(&qdev->rx_ring[i].napi);
3809
4545a3f2 3810 ql_free_rx_buffers(qdev);
2d6a5e95 3811
c4e84bde
RM		 3812 status = ql_adapter_reset(qdev);
3813 if (status)
3814 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3815 qdev->func);
c4e84bde
RM		 3816 return status;
3817}
3818
3819static int ql_adapter_up(struct ql_adapter *qdev)
3820{
3821 int err = 0;
3822
c4e84bde
RM		 3823 err = ql_adapter_initialize(qdev);
3824 if (err) {
3825 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
c4e84bde
RM		 3826 goto err_init;
3827 }
c4e84bde 3828 set_bit(QL_ADAPTER_UP, &qdev->flags);
4545a3f2 3829 ql_alloc_rx_buffers(qdev);
8b007de1
RM		 3830 /* If the port is initialized and the
3831 * link is up the turn on the carrier.
3832 */
3833 if ((ql_read32(qdev, STS) & qdev->port_init) &&
3834 (ql_read32(qdev, STS) & qdev->port_link_up))
6a473308 3835 ql_link_on(qdev);
c4e84bde
RM		 3836 ql_enable_interrupts(qdev);
3837 ql_enable_all_completion_interrupts(qdev);
1e213303 3838 netif_tx_start_all_queues(qdev->ndev);
c4e84bde
RM		 3839
3840 return 0;
3841err_init:
3842 ql_adapter_reset(qdev);
3843 return err;
3844}
3845
c4e84bde
RM		 3846static void ql_release_adapter_resources(struct ql_adapter *qdev)
3847{
3848 ql_free_mem_resources(qdev);
3849 ql_free_irq(qdev);
3850}
3851
3852static int ql_get_adapter_resources(struct ql_adapter *qdev)
3853{
3854 int status = 0;
3855
3856 if (ql_alloc_mem_resources(qdev)) {
3857 QPRINTK(qdev, IFUP, ERR, "Unable to allocate memory.\n");
3858 return -ENOMEM;
3859 }
3860 status = ql_request_irq(qdev);
c4e84bde
RM		 3861 return status;
3862}
3863
3864static int qlge_close(struct net_device *ndev)
3865{
3866 struct ql_adapter *qdev = netdev_priv(ndev);
3867
3868 /*
3869 * Wait for device to recover from a reset.
3870 * (Rarely happens, but possible.)
3871 */
3872 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3873 msleep(1);
3874 ql_adapter_down(qdev);
3875 ql_release_adapter_resources(qdev);
c4e84bde
RM		 3876 return 0;
3877}
3878
3879static int ql_configure_rings(struct ql_adapter *qdev)
3880{
3881 int i;
3882 struct rx_ring *rx_ring;
3883 struct tx_ring *tx_ring;
a4ab6137 3884 int cpu_cnt = min(MAX_CPUS, (int)num_online_cpus());
7c734359
RM		 3885 unsigned int lbq_buf_len = (qdev->ndev->mtu > 1500) ?
3886 LARGE_BUFFER_MAX_SIZE : LARGE_BUFFER_MIN_SIZE;
3887
3888 qdev->lbq_buf_order = get_order(lbq_buf_len);
a4ab6137
RM		 3889
3890 /* In a perfect world we have one RSS ring for each CPU
3891 * and each has it's own vector. To do that we ask for
3892 * cpu_cnt vectors. ql_enable_msix() will adjust the
3893 * vector count to what we actually get. We then
3894 * allocate an RSS ring for each.
3895 * Essentially, we are doing min(cpu_count, msix_vector_count).
c4e84bde 3896 */
a4ab6137
RM		 3897 qdev->intr_count = cpu_cnt;
3898 ql_enable_msix(qdev);
3899 /* Adjust the RSS ring count to the actual vector count. */
3900 qdev->rss_ring_count = qdev->intr_count;
c4e84bde 3901 qdev->tx_ring_count = cpu_cnt;
b2014ff8 3902 qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count;
c4e84bde 3903
c4e84bde
RM		 3904 for (i = 0; i < qdev->tx_ring_count; i++) {
3905 tx_ring = &qdev->tx_ring[i];
e332471c 3906 memset((void *)tx_ring, 0, sizeof(*tx_ring));
c4e84bde
RM		 3907 tx_ring->qdev = qdev;
3908 tx_ring->wq_id = i;
3909 tx_ring->wq_len = qdev->tx_ring_size;
3910 tx_ring->wq_size =
3911 tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3912
3913 /*
3914 * The completion queue ID for the tx rings start
39aa8165 3915 * immediately after the rss rings.
c4e84bde 3916 */
39aa8165 3917 tx_ring->cq_id = qdev->rss_ring_count + i;
c4e84bde
RM		 3918 }
3919
3920 for (i = 0; i < qdev->rx_ring_count; i++) {
3921 rx_ring = &qdev->rx_ring[i];
e332471c 3922 memset((void *)rx_ring, 0, sizeof(*rx_ring));
c4e84bde
RM		 3923 rx_ring->qdev = qdev;
3924 rx_ring->cq_id = i;
3925 rx_ring->cpu = i % cpu_cnt; /* CPU to run handler on. */
b2014ff8 3926 if (i < qdev->rss_ring_count) {
39aa8165
RM		 3927 /*
3928 * Inbound (RSS) queues.
3929 */
c4e84bde
RM		 3930 rx_ring->cq_len = qdev->rx_ring_size;
3931 rx_ring->cq_size =
3932 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3933 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3934 rx_ring->lbq_size =
2c9a0d41 3935 rx_ring->lbq_len * sizeof(__le64);
7c734359
RM		 3936 rx_ring->lbq_buf_size = (u16)lbq_buf_len;
3937 QPRINTK(qdev, IFUP, DEBUG,
3938 "lbq_buf_size %d, order = %d\n",
3939 rx_ring->lbq_buf_size, qdev->lbq_buf_order);
c4e84bde
RM		 3940 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3941 rx_ring->sbq_size =
2c9a0d41 3942 rx_ring->sbq_len * sizeof(__le64);
52e55f3c 3943 rx_ring->sbq_buf_size = SMALL_BUF_MAP_SIZE;
b2014ff8
RM		 3944 rx_ring->type = RX_Q;
3945 } else {
c4e84bde
RM		 3946 /*
3947 * Outbound queue handles outbound completions only.
3948 */
3949 /* outbound cq is same size as tx_ring it services. */
3950 rx_ring->cq_len = qdev->tx_ring_size;
3951 rx_ring->cq_size =
3952 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3953 rx_ring->lbq_len = 0;
3954 rx_ring->lbq_size = 0;
3955 rx_ring->lbq_buf_size = 0;
3956 rx_ring->sbq_len = 0;
3957 rx_ring->sbq_size = 0;
3958 rx_ring->sbq_buf_size = 0;
3959 rx_ring->type = TX_Q;
c4e84bde
RM		 3960 }
3961 }
3962 return 0;
3963}
3964
3965static int qlge_open(struct net_device *ndev)
3966{
3967 int err = 0;
3968 struct ql_adapter *qdev = netdev_priv(ndev);
3969
74e12435
RM		 3970 err = ql_adapter_reset(qdev);
3971 if (err)
3972 return err;
3973
c4e84bde
RM		 3974 err = ql_configure_rings(qdev);
3975 if (err)
3976 return err;
3977
3978 err = ql_get_adapter_resources(qdev);
3979 if (err)
3980 goto error_up;
3981
3982 err = ql_adapter_up(qdev);
3983 if (err)
3984 goto error_up;
3985
3986 return err;
3987
3988error_up:
3989 ql_release_adapter_resources(qdev);
c4e84bde
RM		 3990 return err;
3991}
3992
7c734359
RM		 3993static int ql_change_rx_buffers(struct ql_adapter *qdev)
3994{
3995 struct rx_ring *rx_ring;
3996 int i, status;
3997 u32 lbq_buf_len;
3998
3999 /* Wait for an oustanding reset to complete. */
4000 if (!test_bit(QL_ADAPTER_UP, &qdev->flags)) {
4001 int i = 3;
4002 while (i-- && !test_bit(QL_ADAPTER_UP, &qdev->flags)) {
4003 QPRINTK(qdev, IFUP, ERR,
4004 "Waiting for adapter UP...\n");
4005 ssleep(1);
4006 }
4007
4008 if (!i) {
4009 QPRINTK(qdev, IFUP, ERR,
4010 "Timed out waiting for adapter UP\n");
4011 return -ETIMEDOUT;
4012 }
4013 }
4014
4015 status = ql_adapter_down(qdev);
4016 if (status)
4017 goto error;
4018
4019 /* Get the new rx buffer size. */
4020 lbq_buf_len = (qdev->ndev->mtu > 1500) ?
4021 LARGE_BUFFER_MAX_SIZE : LARGE_BUFFER_MIN_SIZE;
4022 qdev->lbq_buf_order = get_order(lbq_buf_len);
4023
4024 for (i = 0; i < qdev->rss_ring_count; i++) {
4025 rx_ring = &qdev->rx_ring[i];
4026 /* Set the new size. */
4027 rx_ring->lbq_buf_size = lbq_buf_len;
4028 }
4029
4030 status = ql_adapter_up(qdev);
4031 if (status)
4032 goto error;
4033
4034 return status;
4035error:
4036 QPRINTK(qdev, IFUP, ALERT,
4037 "Driver up/down cycle failed, closing device.\n");
4038 set_bit(QL_ADAPTER_UP, &qdev->flags);
4039 dev_close(qdev->ndev);
4040 return status;
4041}
4042
c4e84bde
RM		 4043static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
4044{
4045 struct ql_adapter *qdev = netdev_priv(ndev);
7c734359 4046 int status;
c4e84bde
RM		 4047
4048 if (ndev->mtu == 1500 && new_mtu == 9000) {
4049 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
4050 } else if (ndev->mtu == 9000 && new_mtu == 1500) {
4051 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
4052 } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
4053 (ndev->mtu == 9000 && new_mtu == 9000)) {
4054 return 0;
4055 } else
4056 return -EINVAL;
7c734359
RM		 4057
4058 queue_delayed_work(qdev->workqueue,
4059 &qdev->mpi_port_cfg_work, 3*HZ);
4060
4061 if (!netif_running(qdev->ndev)) {
4062 ndev->mtu = new_mtu;
4063 return 0;
4064 }
4065
c4e84bde 4066 ndev->mtu = new_mtu;
7c734359
RM		 4067 status = ql_change_rx_buffers(qdev);
4068 if (status) {
4069 QPRINTK(qdev, IFUP, ERR,
4070 "Changing MTU failed.\n");
4071 }
4072
4073 return status;
c4e84bde
RM		 4074}
4075
4076static struct net_device_stats *qlge_get_stats(struct net_device
4077 *ndev)
4078{
885ee398
RM		 4079 struct ql_adapter *qdev = netdev_priv(ndev);
4080 struct rx_ring *rx_ring = &qdev->rx_ring[0];
4081 struct tx_ring *tx_ring = &qdev->tx_ring[0];
4082 unsigned long pkts, mcast, dropped, errors, bytes;
4083 int i;
4084
4085 /* Get RX stats. */
4086 pkts = mcast = dropped = errors = bytes = 0;
4087 for (i = 0; i < qdev->rss_ring_count; i++, rx_ring++) {
4088 pkts += rx_ring->rx_packets;
4089 bytes += rx_ring->rx_bytes;
4090 dropped += rx_ring->rx_dropped;
4091 errors += rx_ring->rx_errors;
4092 mcast += rx_ring->rx_multicast;
4093 }
4094 ndev->stats.rx_packets = pkts;
4095 ndev->stats.rx_bytes = bytes;
4096 ndev->stats.rx_dropped = dropped;
4097 ndev->stats.rx_errors = errors;
4098 ndev->stats.multicast = mcast;
4099
4100 /* Get TX stats. */
4101 pkts = errors = bytes = 0;
4102 for (i = 0; i < qdev->tx_ring_count; i++, tx_ring++) {
4103 pkts += tx_ring->tx_packets;
4104 bytes += tx_ring->tx_bytes;
4105 errors += tx_ring->tx_errors;
4106 }
4107 ndev->stats.tx_packets = pkts;
4108 ndev->stats.tx_bytes = bytes;
4109 ndev->stats.tx_errors = errors;
bcc90f55 4110 return &ndev->stats;
c4e84bde
RM		 4111}
4112
4113static void qlge_set_multicast_list(struct net_device *ndev)
4114{
4115 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
4116 struct dev_mc_list *mc_ptr;
cc288f54 4117 int i, status;
c4e84bde 4118
cc288f54
RM		 4119 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
4120 if (status)
4121 return;
c4e84bde
RM		 4122 /*
4123 * Set or clear promiscuous mode if a
4124 * transition is taking place.
4125 */
4126 if (ndev->flags & IFF_PROMISC) {
4127 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
4128 if (ql_set_routing_reg
4129 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
4130 QPRINTK(qdev, HW, ERR,
4131 "Failed to set promiscous mode.\n");
4132 } else {
4133 set_bit(QL_PROMISCUOUS, &qdev->flags);
4134 }
4135 }
4136 } else {
4137 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
4138 if (ql_set_routing_reg
4139 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
4140 QPRINTK(qdev, HW, ERR,
4141 "Failed to clear promiscous mode.\n");
4142 } else {
4143 clear_bit(QL_PROMISCUOUS, &qdev->flags);
4144 }
4145 }
4146 }
4147
4148 /*
4149 * Set or clear all multicast mode if a
4150 * transition is taking place.
4151 */
4152 if ((ndev->flags & IFF_ALLMULTI) ||
4153 (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
4154 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
4155 if (ql_set_routing_reg
4156 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
4157 QPRINTK(qdev, HW, ERR,
4158 "Failed to set all-multi mode.\n");
4159 } else {
4160 set_bit(QL_ALLMULTI, &qdev->flags);
4161 }
4162 }
4163 } else {
4164 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
4165 if (ql_set_routing_reg
4166 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
4167 QPRINTK(qdev, HW, ERR,
4168 "Failed to clear all-multi mode.\n");
4169 } else {
4170 clear_bit(QL_ALLMULTI, &qdev->flags);
4171 }
4172 }
4173 }
4174
4175 if (ndev->mc_count) {
cc288f54
RM		 4176 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
4177 if (status)
4178 goto exit;
c4e84bde
RM		 4179 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
4180 i++, mc_ptr = mc_ptr->next)
4181 if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
4182 MAC_ADDR_TYPE_MULTI_MAC, i)) {
4183 QPRINTK(qdev, HW, ERR,
4184 "Failed to loadmulticast address.\n");
cc288f54 4185 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
c4e84bde
RM		 4186 goto exit;
4187 }
cc288f54 4188 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
c4e84bde
RM		 4189 if (ql_set_routing_reg
4190 (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
4191 QPRINTK(qdev, HW, ERR,
4192 "Failed to set multicast match mode.\n");
4193 } else {
4194 set_bit(QL_ALLMULTI, &qdev->flags);
4195 }
4196 }
4197exit:
8587ea35 4198 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
c4e84bde
RM		 4199}
4200
4201static int qlge_set_mac_address(struct net_device *ndev, void *p)
4202{
4203 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
4204 struct sockaddr *addr = p;
cc288f54 4205 int status;
c4e84bde 4206
c4e84bde
RM		 4207 if (!is_valid_ether_addr(addr->sa_data))
4208 return -EADDRNOTAVAIL;
4209 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
4210
cc288f54
RM		 4211 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
4212 if (status)
4213 return status;
cc288f54
RM		 4214 status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
4215 MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
cc288f54
RM		 4216 if (status)
4217 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
4218 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
4219 return status;
c4e84bde
RM		 4220}
4221
4222static void qlge_tx_timeout(struct net_device *ndev)
4223{
4224 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
6497b607 4225 ql_queue_asic_error(qdev);
c4e84bde
RM		 4226}
4227
4228static void ql_asic_reset_work(struct work_struct *work)
4229{
4230 struct ql_adapter *qdev =
4231 container_of(work, struct ql_adapter, asic_reset_work.work);
db98812f 4232 int status;
f2c0d8df 4233 rtnl_lock();
db98812f
RM		 4234 status = ql_adapter_down(qdev);
4235 if (status)
4236 goto error;
4237
4238 status = ql_adapter_up(qdev);
4239 if (status)
4240 goto error;
2cd6dbaa
RM		 4241
4242 /* Restore rx mode. */
4243 clear_bit(QL_ALLMULTI, &qdev->flags);
4244 clear_bit(QL_PROMISCUOUS, &qdev->flags);
4245 qlge_set_multicast_list(qdev->ndev);
4246
f2c0d8df 4247 rtnl_unlock();
db98812f
RM		 4248 return;
4249error:
4250 QPRINTK(qdev, IFUP, ALERT,
4251 "Driver up/down cycle failed, closing device\n");
f2c0d8df 4252
db98812f
RM		 4253 set_bit(QL_ADAPTER_UP, &qdev->flags);
4254 dev_close(qdev->ndev);
4255 rtnl_unlock();
c4e84bde
RM		 4256}
4257
b0c2aadf
RM		 4258static struct nic_operations qla8012_nic_ops = {
4259 .get_flash = ql_get_8012_flash_params,
4260 .port_initialize = ql_8012_port_initialize,
4261};
4262
cdca8d02
RM		 4263static struct nic_operations qla8000_nic_ops = {
4264 .get_flash = ql_get_8000_flash_params,
4265 .port_initialize = ql_8000_port_initialize,
4266};
4267
e4552f51
RM		 4268/* Find the pcie function number for the other NIC
4269 * on this chip. Since both NIC functions share a
4270 * common firmware we have the lowest enabled function
4271 * do any common work. Examples would be resetting
4272 * after a fatal firmware error, or doing a firmware
4273 * coredump.
4274 */
4275static int ql_get_alt_pcie_func(struct ql_adapter *qdev)
4276{
4277 int status = 0;
4278 u32 temp;
4279 u32 nic_func1, nic_func2;
4280
4281 status = ql_read_mpi_reg(qdev, MPI_TEST_FUNC_PORT_CFG,
4282 &temp);
4283 if (status)
4284 return status;
4285
4286 nic_func1 = ((temp >> MPI_TEST_NIC1_FUNC_SHIFT) &
4287 MPI_TEST_NIC_FUNC_MASK);
4288 nic_func2 = ((temp >> MPI_TEST_NIC2_FUNC_SHIFT) &
4289 MPI_TEST_NIC_FUNC_MASK);
4290
4291 if (qdev->func == nic_func1)
4292 qdev->alt_func = nic_func2;
4293 else if (qdev->func == nic_func2)
4294 qdev->alt_func = nic_func1;
4295 else
4296 status = -EIO;
4297
4298 return status;
4299}
b0c2aadf 4300
e4552f51 4301static int ql_get_board_info(struct ql_adapter *qdev)
c4e84bde 4302{
e4552f51 4303 int status;
c4e84bde
RM		 4304 qdev->func =
4305 (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
e4552f51
RM		 4306 if (qdev->func > 3)
4307 return -EIO;
4308
4309 status = ql_get_alt_pcie_func(qdev);
4310 if (status)
4311 return status;
4312
4313 qdev->port = (qdev->func < qdev->alt_func) ? 0 : 1;
4314 if (qdev->port) {
c4e84bde
RM		 4315 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
4316 qdev->port_link_up = STS_PL1;
4317 qdev->port_init = STS_PI1;
4318 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
4319 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
4320 } else {
4321 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
4322 qdev->port_link_up = STS_PL0;
4323 qdev->port_init = STS_PI0;
4324 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
4325 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
4326 }
4327 qdev->chip_rev_id = ql_read32(qdev, REV_ID);
b0c2aadf
RM		 4328 qdev->device_id = qdev->pdev->device;
4329 if (qdev->device_id == QLGE_DEVICE_ID_8012)
4330 qdev->nic_ops = &qla8012_nic_ops;
cdca8d02
RM		 4331 else if (qdev->device_id == QLGE_DEVICE_ID_8000)
4332 qdev->nic_ops = &qla8000_nic_ops;
e4552f51 4333 return status;
c4e84bde
RM		 4334}
4335
4336static void ql_release_all(struct pci_dev *pdev)
4337{
4338 struct net_device *ndev = pci_get_drvdata(pdev);
4339 struct ql_adapter *qdev = netdev_priv(ndev);
4340
4341 if (qdev->workqueue) {
4342 destroy_workqueue(qdev->workqueue);
4343 qdev->workqueue = NULL;
4344 }
39aa8165 4345
c4e84bde 4346 if (qdev->reg_base)
8668ae92 4347 iounmap(qdev->reg_base);
c4e84bde
RM		 4348 if (qdev->doorbell_area)
4349 iounmap(qdev->doorbell_area);
4350 pci_release_regions(pdev);
4351 pci_set_drvdata(pdev, NULL);
4352}
4353
4354static int __devinit ql_init_device(struct pci_dev *pdev,
4355 struct net_device *ndev, int cards_found)
4356{
4357 struct ql_adapter *qdev = netdev_priv(ndev);
1d1023d0 4358 int err = 0;
c4e84bde 4359
e332471c 4360 memset((void *)qdev, 0, sizeof(*qdev));
c4e84bde
RM		 4361 err = pci_enable_device(pdev);
4362 if (err) {
4363 dev_err(&pdev->dev, "PCI device enable failed.\n");
4364 return err;
4365 }
4366
ebd6e774
RM		 4367 qdev->ndev = ndev;
4368 qdev->pdev = pdev;
4369 pci_set_drvdata(pdev, ndev);
c4e84bde 4370
bc9167f3
RM		 4371 /* Set PCIe read request size */
4372 err = pcie_set_readrq(pdev, 4096);
4373 if (err) {
4374 dev_err(&pdev->dev, "Set readrq failed.\n");
4375 goto err_out;
4376 }
4377
c4e84bde
RM		 4378 err = pci_request_regions(pdev, DRV_NAME);
4379 if (err) {
4380 dev_err(&pdev->dev, "PCI region request failed.\n");
ebd6e774 4381 return err;
c4e84bde
RM		 4382 }
4383
4384 pci_set_master(pdev);
6a35528a 4385 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
c4e84bde 4386 set_bit(QL_DMA64, &qdev->flags);
6a35528a 4387 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
c4e84bde 4388 } else {
284901a9 4389 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
c4e84bde 4390 if (!err)
284901a9 4391 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
c4e84bde
RM		 4392 }
4393
4394 if (err) {
4395 dev_err(&pdev->dev, "No usable DMA configuration.\n");
4396 goto err_out;
4397 }
4398
73475339
RM		 4399 /* Set PCIe reset type for EEH to fundamental. */
4400 pdev->needs_freset = 1;
6d190c6e 4401 pci_save_state(pdev);
c4e84bde
RM		 4402 qdev->reg_base =
4403 ioremap_nocache(pci_resource_start(pdev, 1),
4404 pci_resource_len(pdev, 1));
4405 if (!qdev->reg_base) {
4406 dev_err(&pdev->dev, "Register mapping failed.\n");
4407 err = -ENOMEM;
4408 goto err_out;
4409 }
4410
4411 qdev->doorbell_area_size = pci_resource_len(pdev, 3);
4412 qdev->doorbell_area =
4413 ioremap_nocache(pci_resource_start(pdev, 3),
4414 pci_resource_len(pdev, 3));
4415 if (!qdev->doorbell_area) {
4416 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
4417 err = -ENOMEM;
4418 goto err_out;
4419 }
4420
e4552f51
RM		 4421 err = ql_get_board_info(qdev);
4422 if (err) {
4423 dev_err(&pdev->dev, "Register access failed.\n");
4424 err = -EIO;
4425 goto err_out;
4426 }
c4e84bde
RM		 4427 qdev->msg_enable = netif_msg_init(debug, default_msg);
4428 spin_lock_init(&qdev->hw_lock);
4429 spin_lock_init(&qdev->stats_lock);
4430
4431 /* make sure the EEPROM is good */
b0c2aadf 4432 err = qdev->nic_ops->get_flash(qdev);
c4e84bde
RM		 4433 if (err) {
4434 dev_err(&pdev->dev, "Invalid FLASH.\n");
4435 goto err_out;
4436 }
4437
c4e84bde
RM		 4438 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
4439
4440 /* Set up the default ring sizes. */
4441 qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
4442 qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
4443
4444 /* Set up the coalescing parameters. */
4445 qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
4446 qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
4447 qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
4448 qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
4449
4450 /*
4451 * Set up the operating parameters.
4452 */
4453 qdev->rx_csum = 1;
c4e84bde
RM		 4454 qdev->workqueue = create_singlethread_workqueue(ndev->name);
4455 INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
4456 INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
4457 INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
bcc2cb3b 4458 INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work);
2ee1e272 4459 INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work);
bcc2cb3b 4460 init_completion(&qdev->ide_completion);
c4e84bde
RM		 4461
4462 if (!cards_found) {
4463 dev_info(&pdev->dev, "%s\n", DRV_STRING);
4464 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
4465 DRV_NAME, DRV_VERSION);
4466 }
4467 return 0;
4468err_out:
4469 ql_release_all(pdev);
4470 pci_disable_device(pdev);
4471 return err;
4472}
4473
25ed7849
SH		 4474static const struct net_device_ops qlge_netdev_ops = {
4475 .ndo_open = qlge_open,
4476 .ndo_stop = qlge_close,
4477 .ndo_start_xmit = qlge_send,
4478 .ndo_change_mtu = qlge_change_mtu,
4479 .ndo_get_stats = qlge_get_stats,
4480 .ndo_set_multicast_list = qlge_set_multicast_list,
4481 .ndo_set_mac_address = qlge_set_mac_address,
4482 .ndo_validate_addr = eth_validate_addr,
4483 .ndo_tx_timeout = qlge_tx_timeout,
01e6b953
RM		 4484 .ndo_vlan_rx_register = qlge_vlan_rx_register,
4485 .ndo_vlan_rx_add_vid = qlge_vlan_rx_add_vid,
4486 .ndo_vlan_rx_kill_vid = qlge_vlan_rx_kill_vid,
25ed7849
SH		 4487};
4488
c4e84bde
RM		 4489static int __devinit qlge_probe(struct pci_dev *pdev,
4490 const struct pci_device_id *pci_entry)
4491{
4492 struct net_device *ndev = NULL;
4493 struct ql_adapter *qdev = NULL;
4494 static int cards_found = 0;
4495 int err = 0;
4496
1e213303
RM		 4497 ndev = alloc_etherdev_mq(sizeof(struct ql_adapter),
4498 min(MAX_CPUS, (int)num_online_cpus()));
c4e84bde
RM		 4499 if (!ndev)
4500 return -ENOMEM;
4501
4502 err = ql_init_device(pdev, ndev, cards_found);
4503 if (err < 0) {
4504 free_netdev(ndev);
4505 return err;
4506 }
4507
4508 qdev = netdev_priv(ndev);
4509 SET_NETDEV_DEV(ndev, &pdev->dev);
4510 ndev->features = (0
4511 | NETIF_F_IP_CSUM
4512 | NETIF_F_SG
4513 | NETIF_F_TSO
4514 | NETIF_F_TSO6
4515 | NETIF_F_TSO_ECN
4516 | NETIF_F_HW_VLAN_TX
4517 | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
22bdd4f5 4518 ndev->features |= NETIF_F_GRO;
c4e84bde
RM		 4519
4520 if (test_bit(QL_DMA64, &qdev->flags))
4521 ndev->features |= NETIF_F_HIGHDMA;
4522
4523 /*
4524 * Set up net_device structure.
4525 */
4526 ndev->tx_queue_len = qdev->tx_ring_size;
4527 ndev->irq = pdev->irq;
25ed7849
SH		 4528
4529 ndev->netdev_ops = &qlge_netdev_ops;
c4e84bde 4530 SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
c4e84bde 4531 ndev->watchdog_timeo = 10 * HZ;
25ed7849 4532
c4e84bde
RM		 4533 err = register_netdev(ndev);
4534 if (err) {
4535 dev_err(&pdev->dev, "net device registration failed.\n");
4536 ql_release_all(pdev);
4537 pci_disable_device(pdev);
4538 return err;
4539 }
6a473308 4540 ql_link_off(qdev);
c4e84bde 4541 ql_display_dev_info(ndev);
9dfbbaa6 4542 atomic_set(&qdev->lb_count, 0);
c4e84bde
RM		 4543 cards_found++;
4544 return 0;
4545}
4546
9dfbbaa6
RM		 4547netdev_tx_t ql_lb_send(struct sk_buff *skb, struct net_device *ndev)
4548{
4549 return qlge_send(skb, ndev);
4550}
4551
4552int ql_clean_lb_rx_ring(struct rx_ring *rx_ring, int budget)
4553{
4554 return ql_clean_inbound_rx_ring(rx_ring, budget);
4555}
4556
c4e84bde
RM		 4557static void __devexit qlge_remove(struct pci_dev *pdev)
4558{
4559 struct net_device *ndev = pci_get_drvdata(pdev);
4560 unregister_netdev(ndev);
4561 ql_release_all(pdev);
4562 pci_disable_device(pdev);
4563 free_netdev(ndev);
4564}
4565
6d190c6e
RM		 4566/* Clean up resources without touching hardware. */
4567static void ql_eeh_close(struct net_device *ndev)
4568{
4569 int i;
4570 struct ql_adapter *qdev = netdev_priv(ndev);
4571
4572 if (netif_carrier_ok(ndev)) {
4573 netif_carrier_off(ndev);
4574 netif_stop_queue(ndev);
4575 }
4576
4577 if (test_bit(QL_ADAPTER_UP, &qdev->flags))
4578 cancel_delayed_work_sync(&qdev->asic_reset_work);
4579 cancel_delayed_work_sync(&qdev->mpi_reset_work);
4580 cancel_delayed_work_sync(&qdev->mpi_work);
4581 cancel_delayed_work_sync(&qdev->mpi_idc_work);
4582 cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
4583
4584 for (i = 0; i < qdev->rss_ring_count; i++)
4585 netif_napi_del(&qdev->rx_ring[i].napi);
4586
4587 clear_bit(QL_ADAPTER_UP, &qdev->flags);
4588 ql_tx_ring_clean(qdev);
4589 ql_free_rx_buffers(qdev);
4590 ql_release_adapter_resources(qdev);
4591}
4592
c4e84bde
RM		 4593/*
4594 * This callback is called by the PCI subsystem whenever
4595 * a PCI bus error is detected.
4596 */
4597static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
4598 enum pci_channel_state state)
4599{
4600 struct net_device *ndev = pci_get_drvdata(pdev);
fbc663ce 4601
6d190c6e
RM		 4602 switch (state) {
4603 case pci_channel_io_normal:
4604 return PCI_ERS_RESULT_CAN_RECOVER;
4605 case pci_channel_io_frozen:
4606 netif_device_detach(ndev);
4607 if (netif_running(ndev))
4608 ql_eeh_close(ndev);
4609 pci_disable_device(pdev);
4610 return PCI_ERS_RESULT_NEED_RESET;
4611 case pci_channel_io_perm_failure:
4612 dev_err(&pdev->dev,
4613 "%s: pci_channel_io_perm_failure.\n", __func__);
fbc663ce 4614 return PCI_ERS_RESULT_DISCONNECT;
6d190c6e 4615 }
c4e84bde
RM		 4616
4617 /* Request a slot reset. */
4618 return PCI_ERS_RESULT_NEED_RESET;
4619}
4620
4621/*
4622 * This callback is called after the PCI buss has been reset.
4623 * Basically, this tries to restart the card from scratch.
4624 * This is a shortened version of the device probe/discovery code,
4625 * it resembles the first-half of the () routine.
4626 */
4627static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
4628{
4629 struct net_device *ndev = pci_get_drvdata(pdev);
4630 struct ql_adapter *qdev = netdev_priv(ndev);
4631
6d190c6e
RM		 4632 pdev->error_state = pci_channel_io_normal;
4633
4634 pci_restore_state(pdev);
c4e84bde
RM		 4635 if (pci_enable_device(pdev)) {
4636 QPRINTK(qdev, IFUP, ERR,
4637 "Cannot re-enable PCI device after reset.\n");
4638 return PCI_ERS_RESULT_DISCONNECT;
4639 }
c4e84bde 4640 pci_set_master(pdev);
c4e84bde
RM		 4641 return PCI_ERS_RESULT_RECOVERED;
4642}
4643
4644static void qlge_io_resume(struct pci_dev *pdev)
4645{
4646 struct net_device *ndev = pci_get_drvdata(pdev);
4647 struct ql_adapter *qdev = netdev_priv(ndev);
6d190c6e 4648 int err = 0;
c4e84bde 4649
6d190c6e
RM		 4650 if (ql_adapter_reset(qdev))
4651 QPRINTK(qdev, DRV, ERR, "reset FAILED!\n");
c4e84bde 4652 if (netif_running(ndev)) {
6d190c6e
RM		 4653 err = qlge_open(ndev);
4654 if (err) {
c4e84bde
RM		 4655 QPRINTK(qdev, IFUP, ERR,
4656 "Device initialization failed after reset.\n");
4657 return;
4658 }
6d190c6e
RM		 4659 } else {
4660 QPRINTK(qdev, IFUP, ERR,
4661 "Device was not running prior to EEH.\n");
c4e84bde 4662 }
c4e84bde
RM		 4663 netif_device_attach(ndev);
4664}
4665
4666static struct pci_error_handlers qlge_err_handler = {
4667 .error_detected = qlge_io_error_detected,
4668 .slot_reset = qlge_io_slot_reset,
4669 .resume = qlge_io_resume,
4670};
4671
4672static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
4673{
4674 struct net_device *ndev = pci_get_drvdata(pdev);
4675 struct ql_adapter *qdev = netdev_priv(ndev);
6b318cb3 4676 int err;
c4e84bde
RM		 4677
4678 netif_device_detach(ndev);
4679
4680 if (netif_running(ndev)) {
4681 err = ql_adapter_down(qdev);
4682 if (!err)
4683 return err;
4684 }
4685
bc083ce9 4686 ql_wol(qdev);
c4e84bde
RM		 4687 err = pci_save_state(pdev);
4688 if (err)
4689 return err;
4690
4691 pci_disable_device(pdev);
4692
4693 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4694
4695 return 0;
4696}
4697
04da2cf9 4698#ifdef CONFIG_PM
c4e84bde
RM		 4699static int qlge_resume(struct pci_dev *pdev)
4700{
4701 struct net_device *ndev = pci_get_drvdata(pdev);
4702 struct ql_adapter *qdev = netdev_priv(ndev);
4703 int err;
4704
4705 pci_set_power_state(pdev, PCI_D0);
4706 pci_restore_state(pdev);
4707 err = pci_enable_device(pdev);
4708 if (err) {
4709 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
4710 return err;
4711 }
4712 pci_set_master(pdev);
4713
4714 pci_enable_wake(pdev, PCI_D3hot, 0);
4715 pci_enable_wake(pdev, PCI_D3cold, 0);
4716
4717 if (netif_running(ndev)) {
4718 err = ql_adapter_up(qdev);
4719 if (err)
4720 return err;
4721 }
4722
4723 netif_device_attach(ndev);
4724
4725 return 0;
4726}
04da2cf9 4727#endif /* CONFIG_PM */
c4e84bde
RM		 4728
4729static void qlge_shutdown(struct pci_dev *pdev)
4730{
4731 qlge_suspend(pdev, PMSG_SUSPEND);
4732}
4733
4734static struct pci_driver qlge_driver = {
4735 .name = DRV_NAME,
4736 .id_table = qlge_pci_tbl,
4737 .probe = qlge_probe,
4738 .remove = __devexit_p(qlge_remove),
4739#ifdef CONFIG_PM
4740 .suspend = qlge_suspend,
4741 .resume = qlge_resume,
4742#endif
4743 .shutdown = qlge_shutdown,
4744 .err_handler = &qlge_err_handler
4745};
4746
4747static int __init qlge_init_module(void)
4748{
4749 return pci_register_driver(&qlge_driver);
4750}
4751
4752static void __exit qlge_exit(void)
4753{
4754 pci_unregister_driver(&qlge_driver);
4755}
4756
4757module_init(qlge_init_module);
4758module_exit(qlge_exit);
Linux kernel - Deliverables
This page took 0.49839 seconds and 5 git commands to generate.