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qlge: bugfix: Use netif_receive_skb() and vlan_hwaccel_receive_skb().
[deliverable/linux.git] / drivers / net / qlge / qlge_main.c
CommitLineData
c4e84bde
RM		 1/*
2 * QLogic qlge NIC HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 * See LICENSE.qlge for copyright and licensing details.
5 * Author: Linux qlge network device driver by
6 * Ron Mercer <ron.mercer@qlogic.com>
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/list.h>
13#include <linux/pci.h>
14#include <linux/dma-mapping.h>
15#include <linux/pagemap.h>
16#include <linux/sched.h>
17#include <linux/slab.h>
18#include <linux/dmapool.h>
19#include <linux/mempool.h>
20#include <linux/spinlock.h>
21#include <linux/kthread.h>
22#include <linux/interrupt.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/in.h>
26#include <linux/ip.h>
27#include <linux/ipv6.h>
28#include <net/ipv6.h>
29#include <linux/tcp.h>
30#include <linux/udp.h>
31#include <linux/if_arp.h>
32#include <linux/if_ether.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/skbuff.h>
37#include <linux/rtnetlink.h>
38#include <linux/if_vlan.h>
c4e84bde
RM		 39#include <linux/delay.h>
40#include <linux/mm.h>
41#include <linux/vmalloc.h>
b7c6bfb7 42#include <net/ip6_checksum.h>
c4e84bde
RM		 43
44#include "qlge.h"
45
46char qlge_driver_name[] = DRV_NAME;
47const char qlge_driver_version[] = DRV_VERSION;
48
49MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50MODULE_DESCRIPTION(DRV_STRING " ");
51MODULE_LICENSE("GPL");
52MODULE_VERSION(DRV_VERSION);
53
54static const u32 default_msg =
55 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
56/* NETIF_MSG_TIMER | */
57 NETIF_MSG_IFDOWN |
58 NETIF_MSG_IFUP |
59 NETIF_MSG_RX_ERR |
60 NETIF_MSG_TX_ERR |
61 NETIF_MSG_TX_QUEUED |
62 NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS |
63/* NETIF_MSG_PKTDATA | */
64 NETIF_MSG_HW | NETIF_MSG_WOL | 0;
65
66static int debug = 0x00007fff; /* defaults above */
67module_param(debug, int, 0);
68MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
69
70#define MSIX_IRQ 0
71#define MSI_IRQ 1
72#define LEG_IRQ 2
73static int irq_type = MSIX_IRQ;
74module_param(irq_type, int, MSIX_IRQ);
75MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
76
77static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
78 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID)},
c4e84bde
RM		 79 /* required last entry */
80 {0,}
81};
82
83MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
84
85/* This hardware semaphore causes exclusive access to
86 * resources shared between the NIC driver, MPI firmware,
87 * FCOE firmware and the FC driver.
88 */
89static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
90{
91 u32 sem_bits = 0;
92
93 switch (sem_mask) {
94 case SEM_XGMAC0_MASK:
95 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
96 break;
97 case SEM_XGMAC1_MASK:
98 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
99 break;
100 case SEM_ICB_MASK:
101 sem_bits = SEM_SET << SEM_ICB_SHIFT;
102 break;
103 case SEM_MAC_ADDR_MASK:
104 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
105 break;
106 case SEM_FLASH_MASK:
107 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
108 break;
109 case SEM_PROBE_MASK:
110 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
111 break;
112 case SEM_RT_IDX_MASK:
113 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
114 break;
115 case SEM_PROC_REG_MASK:
116 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
117 break;
118 default:
119 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
120 return -EINVAL;
121 }
122
123 ql_write32(qdev, SEM, sem_bits | sem_mask);
124 return !(ql_read32(qdev, SEM) & sem_bits);
125}
126
127int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
128{
0857e9d7 129 unsigned int wait_count = 30;
c4e84bde
RM		 130 do {
131 if (!ql_sem_trylock(qdev, sem_mask))
132 return 0;
0857e9d7
RM		 133 udelay(100);
134 } while (--wait_count);
c4e84bde
RM		 135 return -ETIMEDOUT;
136}
137
138void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
139{
140 ql_write32(qdev, SEM, sem_mask);
141 ql_read32(qdev, SEM); /* flush */
142}
143
144/* This function waits for a specific bit to come ready
145 * in a given register. It is used mostly by the initialize
146 * process, but is also used in kernel thread API such as
147 * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
148 */
149int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
150{
151 u32 temp;
152 int count = UDELAY_COUNT;
153
154 while (count) {
155 temp = ql_read32(qdev, reg);
156
157 /* check for errors */
158 if (temp & err_bit) {
159 QPRINTK(qdev, PROBE, ALERT,
160 "register 0x%.08x access error, value = 0x%.08x!.\n",
161 reg, temp);
162 return -EIO;
163 } else if (temp & bit)
164 return 0;
165 udelay(UDELAY_DELAY);
166 count--;
167 }
168 QPRINTK(qdev, PROBE, ALERT,
169 "Timed out waiting for reg %x to come ready.\n", reg);
170 return -ETIMEDOUT;
171}
172
173/* The CFG register is used to download TX and RX control blocks
174 * to the chip. This function waits for an operation to complete.
175 */
176static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
177{
178 int count = UDELAY_COUNT;
179 u32 temp;
180
181 while (count) {
182 temp = ql_read32(qdev, CFG);
183 if (temp & CFG_LE)
184 return -EIO;
185 if (!(temp & bit))
186 return 0;
187 udelay(UDELAY_DELAY);
188 count--;
189 }
190 return -ETIMEDOUT;
191}
192
193
194/* Used to issue init control blocks to hw. Maps control block,
195 * sets address, triggers download, waits for completion.
196 */
197int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
198 u16 q_id)
199{
200 u64 map;
201 int status = 0;
202 int direction;
203 u32 mask;
204 u32 value;
205
206 direction =
207 (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
208 PCI_DMA_FROMDEVICE;
209
210 map = pci_map_single(qdev->pdev, ptr, size, direction);
211 if (pci_dma_mapping_error(qdev->pdev, map)) {
212 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
213 return -ENOMEM;
214 }
215
216 status = ql_wait_cfg(qdev, bit);
217 if (status) {
218 QPRINTK(qdev, IFUP, ERR,
219 "Timed out waiting for CFG to come ready.\n");
220 goto exit;
221 }
222
223 status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
224 if (status)
225 goto exit;
226 ql_write32(qdev, ICB_L, (u32) map);
227 ql_write32(qdev, ICB_H, (u32) (map >> 32));
228 ql_sem_unlock(qdev, SEM_ICB_MASK); /* does flush too */
229
230 mask = CFG_Q_MASK | (bit << 16);
231 value = bit | (q_id << CFG_Q_SHIFT);
232 ql_write32(qdev, CFG, (mask | value));
233
234 /*
235 * Wait for the bit to clear after signaling hw.
236 */
237 status = ql_wait_cfg(qdev, bit);
238exit:
239 pci_unmap_single(qdev->pdev, map, size, direction);
240 return status;
241}
242
243/* Get a specific MAC address from the CAM. Used for debug and reg dump. */
244int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
245 u32 *value)
246{
247 u32 offset = 0;
248 int status;
249
250 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
251 if (status)
252 return status;
253 switch (type) {
254 case MAC_ADDR_TYPE_MULTI_MAC:
255 case MAC_ADDR_TYPE_CAM_MAC:
256 {
257 status =
258 ql_wait_reg_rdy(qdev,
939678f8 259 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 260 if (status)
261 goto exit;
262 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
263 (index << MAC_ADDR_IDX_SHIFT) | /* index */
264 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
265 status =
266 ql_wait_reg_rdy(qdev,
939678f8 267 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
c4e84bde
RM		 268 if (status)
269 goto exit;
270 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
271 status =
272 ql_wait_reg_rdy(qdev,
939678f8 273 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 274 if (status)
275 goto exit;
276 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
277 (index << MAC_ADDR_IDX_SHIFT) | /* index */
278 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
279 status =
280 ql_wait_reg_rdy(qdev,
939678f8 281 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
c4e84bde
RM		 282 if (status)
283 goto exit;
284 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
285 if (type == MAC_ADDR_TYPE_CAM_MAC) {
286 status =
287 ql_wait_reg_rdy(qdev,
939678f8 288 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 289 if (status)
290 goto exit;
291 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
292 (index << MAC_ADDR_IDX_SHIFT) | /* index */
293 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
294 status =
295 ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
939678f8 296 MAC_ADDR_MR, 0);
c4e84bde
RM		 297 if (status)
298 goto exit;
299 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
300 }
301 break;
302 }
303 case MAC_ADDR_TYPE_VLAN:
304 case MAC_ADDR_TYPE_MULTI_FLTR:
305 default:
306 QPRINTK(qdev, IFUP, CRIT,
307 "Address type %d not yet supported.\n", type);
308 status = -EPERM;
309 }
310exit:
311 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
312 return status;
313}
314
315/* Set up a MAC, multicast or VLAN address for the
316 * inbound frame matching.
317 */
318static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
319 u16 index)
320{
321 u32 offset = 0;
322 int status = 0;
323
324 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
325 if (status)
326 return status;
327 switch (type) {
328 case MAC_ADDR_TYPE_MULTI_MAC:
329 case MAC_ADDR_TYPE_CAM_MAC:
330 {
331 u32 cam_output;
332 u32 upper = (addr[0] << 8) | addr[1];
333 u32 lower =
334 (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
335 (addr[5]);
336
337 QPRINTK(qdev, IFUP, INFO,
7c510e4b 338 "Adding %s address %pM"
c4e84bde
RM		 339 " at index %d in the CAM.\n",
340 ((type ==
341 MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
7c510e4b 342 "UNICAST"), addr, index);
c4e84bde
RM		 343
344 status =
345 ql_wait_reg_rdy(qdev,
939678f8 346 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 347 if (status)
348 goto exit;
349 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
350 (index << MAC_ADDR_IDX_SHIFT) | /* index */
351 type); /* type */
352 ql_write32(qdev, MAC_ADDR_DATA, lower);
353 status =
354 ql_wait_reg_rdy(qdev,
939678f8 355 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 356 if (status)
357 goto exit;
358 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
359 (index << MAC_ADDR_IDX_SHIFT) | /* index */
360 type); /* type */
361 ql_write32(qdev, MAC_ADDR_DATA, upper);
362 status =
363 ql_wait_reg_rdy(qdev,
939678f8 364 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 365 if (status)
366 goto exit;
367 ql_write32(qdev, MAC_ADDR_IDX, (offset) | /* offset */
368 (index << MAC_ADDR_IDX_SHIFT) | /* index */
369 type); /* type */
370 /* This field should also include the queue id
371 and possibly the function id. Right now we hardcode
372 the route field to NIC core.
373 */
374 if (type == MAC_ADDR_TYPE_CAM_MAC) {
375 cam_output = (CAM_OUT_ROUTE_NIC |
376 (qdev->
377 func << CAM_OUT_FUNC_SHIFT) |
378 (qdev->
379 rss_ring_first_cq_id <<
380 CAM_OUT_CQ_ID_SHIFT));
381 if (qdev->vlgrp)
382 cam_output |= CAM_OUT_RV;
383 /* route to NIC core */
384 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
385 }
386 break;
387 }
388 case MAC_ADDR_TYPE_VLAN:
389 {
390 u32 enable_bit = *((u32 *) &addr[0]);
391 /* For VLAN, the addr actually holds a bit that
392 * either enables or disables the vlan id we are
393 * addressing. It's either MAC_ADDR_E on or off.
394 * That's bit-27 we're talking about.
395 */
396 QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
397 (enable_bit ? "Adding" : "Removing"),
398 index, (enable_bit ? "to" : "from"));
399
400 status =
401 ql_wait_reg_rdy(qdev,
939678f8 402 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 403 if (status)
404 goto exit;
405 ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
406 (index << MAC_ADDR_IDX_SHIFT) | /* index */
407 type | /* type */
408 enable_bit); /* enable/disable */
409 break;
410 }
411 case MAC_ADDR_TYPE_MULTI_FLTR:
412 default:
413 QPRINTK(qdev, IFUP, CRIT,
414 "Address type %d not yet supported.\n", type);
415 status = -EPERM;
416 }
417exit:
418 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
419 return status;
420}
421
422/* Get a specific frame routing value from the CAM.
423 * Used for debug and reg dump.
424 */
425int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
426{
427 int status = 0;
428
429 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
430 if (status)
431 goto exit;
432
939678f8 433 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
c4e84bde
RM		 434 if (status)
435 goto exit;
436
437 ql_write32(qdev, RT_IDX,
438 RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
939678f8 439 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
c4e84bde
RM		 440 if (status)
441 goto exit;
442 *value = ql_read32(qdev, RT_DATA);
443exit:
444 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
445 return status;
446}
447
448/* The NIC function for this chip has 16 routing indexes. Each one can be used
449 * to route different frame types to various inbound queues. We send broadcast/
450 * multicast/error frames to the default queue for slow handling,
451 * and CAM hit/RSS frames to the fast handling queues.
452 */
453static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
454 int enable)
455{
456 int status;
457 u32 value = 0;
458
459 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
460 if (status)
461 return status;
462
463 QPRINTK(qdev, IFUP, DEBUG,
464 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
465 (enable ? "Adding" : "Removing"),
466 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
467 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
468 ((index ==
469 RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
470 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
471 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
472 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
473 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
474 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
475 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
476 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
477 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
478 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
479 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
480 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
481 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
482 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
483 (enable ? "to" : "from"));
484
485 switch (mask) {
486 case RT_IDX_CAM_HIT:
487 {
488 value = RT_IDX_DST_CAM_Q | /* dest */
489 RT_IDX_TYPE_NICQ | /* type */
490 (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
491 break;
492 }
493 case RT_IDX_VALID: /* Promiscuous Mode frames. */
494 {
495 value = RT_IDX_DST_DFLT_Q | /* dest */
496 RT_IDX_TYPE_NICQ | /* type */
497 (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
498 break;
499 }
500 case RT_IDX_ERR: /* Pass up MAC,IP,TCP/UDP error frames. */
501 {
502 value = RT_IDX_DST_DFLT_Q | /* dest */
503 RT_IDX_TYPE_NICQ | /* type */
504 (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
505 break;
506 }
507 case RT_IDX_BCAST: /* Pass up Broadcast frames to default Q. */
508 {
509 value = RT_IDX_DST_DFLT_Q | /* dest */
510 RT_IDX_TYPE_NICQ | /* type */
511 (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
512 break;
513 }
514 case RT_IDX_MCAST: /* Pass up All Multicast frames. */
515 {
516 value = RT_IDX_DST_CAM_Q | /* dest */
517 RT_IDX_TYPE_NICQ | /* type */
518 (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
519 break;
520 }
521 case RT_IDX_MCAST_MATCH: /* Pass up matched Multicast frames. */
522 {
523 value = RT_IDX_DST_CAM_Q | /* dest */
524 RT_IDX_TYPE_NICQ | /* type */
525 (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
526 break;
527 }
528 case RT_IDX_RSS_MATCH: /* Pass up matched RSS frames. */
529 {
530 value = RT_IDX_DST_RSS | /* dest */
531 RT_IDX_TYPE_NICQ | /* type */
532 (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
533 break;
534 }
535 case 0: /* Clear the E-bit on an entry. */
536 {
537 value = RT_IDX_DST_DFLT_Q | /* dest */
538 RT_IDX_TYPE_NICQ | /* type */
539 (index << RT_IDX_IDX_SHIFT);/* index */
540 break;
541 }
542 default:
543 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
544 mask);
545 status = -EPERM;
546 goto exit;
547 }
548
549 if (value) {
550 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
551 if (status)
552 goto exit;
553 value |= (enable ? RT_IDX_E : 0);
554 ql_write32(qdev, RT_IDX, value);
555 ql_write32(qdev, RT_DATA, enable ? mask : 0);
556 }
557exit:
558 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
559 return status;
560}
561
562static void ql_enable_interrupts(struct ql_adapter *qdev)
563{
564 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
565}
566
567static void ql_disable_interrupts(struct ql_adapter *qdev)
568{
569 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
570}
571
572/* If we're running with multiple MSI-X vectors then we enable on the fly.
573 * Otherwise, we may have multiple outstanding workers and don't want to
574 * enable until the last one finishes. In this case, the irq_cnt gets
575 * incremented everytime we queue a worker and decremented everytime
576 * a worker finishes. Once it hits zero we enable the interrupt.
577 */
bb0d215c 578u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
c4e84bde 579{
bb0d215c
RM		 580 u32 var = 0;
581 unsigned long hw_flags = 0;
582 struct intr_context *ctx = qdev->intr_context + intr;
583
584 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
585 /* Always enable if we're MSIX multi interrupts and
586 * it's not the default (zeroeth) interrupt.
587 */
c4e84bde 588 ql_write32(qdev, INTR_EN,
bb0d215c
RM		 589 ctx->intr_en_mask);
590 var = ql_read32(qdev, STS);
591 return var;
c4e84bde 592 }
bb0d215c
RM		 593
594 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
595 if (atomic_dec_and_test(&ctx->irq_cnt)) {
596 ql_write32(qdev, INTR_EN,
597 ctx->intr_en_mask);
598 var = ql_read32(qdev, STS);
599 }
600 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
601 return var;
c4e84bde
RM		 602}
603
604static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
605{
606 u32 var = 0;
bb0d215c
RM		 607 unsigned long hw_flags;
608 struct intr_context *ctx;
c4e84bde 609
bb0d215c
RM		 610 /* HW disables for us if we're MSIX multi interrupts and
611 * it's not the default (zeroeth) interrupt.
612 */
613 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
614 return 0;
615
616 ctx = qdev->intr_context + intr;
617 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
618 if (!atomic_read(&ctx->irq_cnt)) {
c4e84bde 619 ql_write32(qdev, INTR_EN,
bb0d215c 620 ctx->intr_dis_mask);
c4e84bde
RM		 621 var = ql_read32(qdev, STS);
622 }
bb0d215c
RM		 623 atomic_inc(&ctx->irq_cnt);
624 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
c4e84bde
RM		 625 return var;
626}
627
628static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
629{
630 int i;
631 for (i = 0; i < qdev->intr_count; i++) {
632 /* The enable call does a atomic_dec_and_test
633 * and enables only if the result is zero.
634 * So we precharge it here.
635 */
bb0d215c
RM		 636 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
637 i == 0))
638 atomic_set(&qdev->intr_context[i].irq_cnt, 1);
c4e84bde
RM		 639 ql_enable_completion_interrupt(qdev, i);
640 }
641
642}
643
26351479 644static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
c4e84bde
RM		 645{
646 int status = 0;
647 /* wait for reg to come ready */
648 status = ql_wait_reg_rdy(qdev,
649 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
650 if (status)
651 goto exit;
652 /* set up for reg read */
653 ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
654 /* wait for reg to come ready */
655 status = ql_wait_reg_rdy(qdev,
656 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
657 if (status)
658 goto exit;
26351479
RM		 659 /* This data is stored on flash as an array of
660 * __le32. Since ql_read32() returns cpu endian
661 * we need to swap it back.
662 */
663 *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
c4e84bde
RM		 664exit:
665 return status;
666}
667
668static int ql_get_flash_params(struct ql_adapter *qdev)
669{
670 int i;
671 int status;
26351479 672 __le32 *p = (__le32 *)&qdev->flash;
e78f5fa7
RM		 673 u32 offset = 0;
674
675 /* Second function's parameters follow the first
676 * function's.
677 */
678 if (qdev->func)
679 offset = sizeof(qdev->flash) / sizeof(u32);
c4e84bde
RM		 680
681 if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
682 return -ETIMEDOUT;
683
684 for (i = 0; i < sizeof(qdev->flash) / sizeof(u32); i++, p++) {
e78f5fa7 685 status = ql_read_flash_word(qdev, i+offset, p);
c4e84bde
RM		 686 if (status) {
687 QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
688 goto exit;
689 }
690
691 }
692exit:
693 ql_sem_unlock(qdev, SEM_FLASH_MASK);
694 return status;
695}
696
697/* xgmac register are located behind the xgmac_addr and xgmac_data
698 * register pair. Each read/write requires us to wait for the ready
699 * bit before reading/writing the data.
700 */
701static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
702{
703 int status;
704 /* wait for reg to come ready */
705 status = ql_wait_reg_rdy(qdev,
706 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
707 if (status)
708 return status;
709 /* write the data to the data reg */
710 ql_write32(qdev, XGMAC_DATA, data);
711 /* trigger the write */
712 ql_write32(qdev, XGMAC_ADDR, reg);
713 return status;
714}
715
716/* xgmac register are located behind the xgmac_addr and xgmac_data
717 * register pair. Each read/write requires us to wait for the ready
718 * bit before reading/writing the data.
719 */
720int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
721{
722 int status = 0;
723 /* wait for reg to come ready */
724 status = ql_wait_reg_rdy(qdev,
725 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
726 if (status)
727 goto exit;
728 /* set up for reg read */
729 ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
730 /* wait for reg to come ready */
731 status = ql_wait_reg_rdy(qdev,
732 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
733 if (status)
734 goto exit;
735 /* get the data */
736 *data = ql_read32(qdev, XGMAC_DATA);
737exit:
738 return status;
739}
740
741/* This is used for reading the 64-bit statistics regs. */
742int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
743{
744 int status = 0;
745 u32 hi = 0;
746 u32 lo = 0;
747
748 status = ql_read_xgmac_reg(qdev, reg, &lo);
749 if (status)
750 goto exit;
751
752 status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
753 if (status)
754 goto exit;
755
756 *data = (u64) lo | ((u64) hi << 32);
757
758exit:
759 return status;
760}
761
762/* Take the MAC Core out of reset.
763 * Enable statistics counting.
764 * Take the transmitter/receiver out of reset.
765 * This functionality may be done in the MPI firmware at a
766 * later date.
767 */
768static int ql_port_initialize(struct ql_adapter *qdev)
769{
770 int status = 0;
771 u32 data;
772
773 if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
774 /* Another function has the semaphore, so
775 * wait for the port init bit to come ready.
776 */
777 QPRINTK(qdev, LINK, INFO,
778 "Another function has the semaphore, so wait for the port init bit to come ready.\n");
779 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
780 if (status) {
781 QPRINTK(qdev, LINK, CRIT,
782 "Port initialize timed out.\n");
783 }
784 return status;
785 }
786
787 QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
788 /* Set the core reset. */
789 status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
790 if (status)
791 goto end;
792 data |= GLOBAL_CFG_RESET;
793 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
794 if (status)
795 goto end;
796
797 /* Clear the core reset and turn on jumbo for receiver. */
798 data &= ~GLOBAL_CFG_RESET; /* Clear core reset. */
799 data |= GLOBAL_CFG_JUMBO; /* Turn on jumbo. */
800 data |= GLOBAL_CFG_TX_STAT_EN;
801 data |= GLOBAL_CFG_RX_STAT_EN;
802 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
803 if (status)
804 goto end;
805
806 /* Enable transmitter, and clear it's reset. */
807 status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
808 if (status)
809 goto end;
810 data &= ~TX_CFG_RESET; /* Clear the TX MAC reset. */
811 data |= TX_CFG_EN; /* Enable the transmitter. */
812 status = ql_write_xgmac_reg(qdev, TX_CFG, data);
813 if (status)
814 goto end;
815
816 /* Enable receiver and clear it's reset. */
817 status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
818 if (status)
819 goto end;
820 data &= ~RX_CFG_RESET; /* Clear the RX MAC reset. */
821 data |= RX_CFG_EN; /* Enable the receiver. */
822 status = ql_write_xgmac_reg(qdev, RX_CFG, data);
823 if (status)
824 goto end;
825
826 /* Turn on jumbo. */
827 status =
828 ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
829 if (status)
830 goto end;
831 status =
832 ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
833 if (status)
834 goto end;
835
836 /* Signal to the world that the port is enabled. */
837 ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
838end:
839 ql_sem_unlock(qdev, qdev->xg_sem_mask);
840 return status;
841}
842
843/* Get the next large buffer. */
8668ae92 844static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
c4e84bde
RM		 845{
846 struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
847 rx_ring->lbq_curr_idx++;
848 if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
849 rx_ring->lbq_curr_idx = 0;
850 rx_ring->lbq_free_cnt++;
851 return lbq_desc;
852}
853
854/* Get the next small buffer. */
8668ae92 855static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
c4e84bde
RM		 856{
857 struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
858 rx_ring->sbq_curr_idx++;
859 if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
860 rx_ring->sbq_curr_idx = 0;
861 rx_ring->sbq_free_cnt++;
862 return sbq_desc;
863}
864
865/* Update an rx ring index. */
866static void ql_update_cq(struct rx_ring *rx_ring)
867{
868 rx_ring->cnsmr_idx++;
869 rx_ring->curr_entry++;
870 if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
871 rx_ring->cnsmr_idx = 0;
872 rx_ring->curr_entry = rx_ring->cq_base;
873 }
874}
875
876static void ql_write_cq_idx(struct rx_ring *rx_ring)
877{
878 ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
879}
880
881/* Process (refill) a large buffer queue. */
882static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
883{
884 int clean_idx = rx_ring->lbq_clean_idx;
885 struct bq_desc *lbq_desc;
c4e84bde
RM		 886 u64 map;
887 int i;
888
889 while (rx_ring->lbq_free_cnt > 16) {
890 for (i = 0; i < 16; i++) {
891 QPRINTK(qdev, RX_STATUS, DEBUG,
892 "lbq: try cleaning clean_idx = %d.\n",
893 clean_idx);
894 lbq_desc = &rx_ring->lbq[clean_idx];
c4e84bde
RM		 895 if (lbq_desc->p.lbq_page == NULL) {
896 QPRINTK(qdev, RX_STATUS, DEBUG,
897 "lbq: getting new page for index %d.\n",
898 lbq_desc->index);
899 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
900 if (lbq_desc->p.lbq_page == NULL) {
901 QPRINTK(qdev, RX_STATUS, ERR,
902 "Couldn't get a page.\n");
903 return;
904 }
905 map = pci_map_page(qdev->pdev,
906 lbq_desc->p.lbq_page,
907 0, PAGE_SIZE,
908 PCI_DMA_FROMDEVICE);
909 if (pci_dma_mapping_error(qdev->pdev, map)) {
910 QPRINTK(qdev, RX_STATUS, ERR,
911 "PCI mapping failed.\n");
912 return;
913 }
914 pci_unmap_addr_set(lbq_desc, mapaddr, map);
915 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
2c9a0d41 916 *lbq_desc->addr = cpu_to_le64(map);
c4e84bde
RM		 917 }
918 clean_idx++;
919 if (clean_idx == rx_ring->lbq_len)
920 clean_idx = 0;
921 }
922
923 rx_ring->lbq_clean_idx = clean_idx;
924 rx_ring->lbq_prod_idx += 16;
925 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
926 rx_ring->lbq_prod_idx = 0;
927 QPRINTK(qdev, RX_STATUS, DEBUG,
928 "lbq: updating prod idx = %d.\n",
929 rx_ring->lbq_prod_idx);
930 ql_write_db_reg(rx_ring->lbq_prod_idx,
931 rx_ring->lbq_prod_idx_db_reg);
932 rx_ring->lbq_free_cnt -= 16;
933 }
934}
935
936/* Process (refill) a small buffer queue. */
937static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
938{
939 int clean_idx = rx_ring->sbq_clean_idx;
940 struct bq_desc *sbq_desc;
c4e84bde
RM		 941 u64 map;
942 int i;
943
944 while (rx_ring->sbq_free_cnt > 16) {
945 for (i = 0; i < 16; i++) {
946 sbq_desc = &rx_ring->sbq[clean_idx];
947 QPRINTK(qdev, RX_STATUS, DEBUG,
948 "sbq: try cleaning clean_idx = %d.\n",
949 clean_idx);
c4e84bde
RM		 950 if (sbq_desc->p.skb == NULL) {
951 QPRINTK(qdev, RX_STATUS, DEBUG,
952 "sbq: getting new skb for index %d.\n",
953 sbq_desc->index);
954 sbq_desc->p.skb =
955 netdev_alloc_skb(qdev->ndev,
956 rx_ring->sbq_buf_size);
957 if (sbq_desc->p.skb == NULL) {
958 QPRINTK(qdev, PROBE, ERR,
959 "Couldn't get an skb.\n");
960 rx_ring->sbq_clean_idx = clean_idx;
961 return;
962 }
963 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
964 map = pci_map_single(qdev->pdev,
965 sbq_desc->p.skb->data,
966 rx_ring->sbq_buf_size /
967 2, PCI_DMA_FROMDEVICE);
c907a35a
RM		 968 if (pci_dma_mapping_error(qdev->pdev, map)) {
969 QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
970 rx_ring->sbq_clean_idx = clean_idx;
971 return;
972 }
c4e84bde
RM		 973 pci_unmap_addr_set(sbq_desc, mapaddr, map);
974 pci_unmap_len_set(sbq_desc, maplen,
975 rx_ring->sbq_buf_size / 2);
2c9a0d41 976 *sbq_desc->addr = cpu_to_le64(map);
c4e84bde
RM		 977 }
978
979 clean_idx++;
980 if (clean_idx == rx_ring->sbq_len)
981 clean_idx = 0;
982 }
983 rx_ring->sbq_clean_idx = clean_idx;
984 rx_ring->sbq_prod_idx += 16;
985 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
986 rx_ring->sbq_prod_idx = 0;
987 QPRINTK(qdev, RX_STATUS, DEBUG,
988 "sbq: updating prod idx = %d.\n",
989 rx_ring->sbq_prod_idx);
990 ql_write_db_reg(rx_ring->sbq_prod_idx,
991 rx_ring->sbq_prod_idx_db_reg);
992
993 rx_ring->sbq_free_cnt -= 16;
994 }
995}
996
997static void ql_update_buffer_queues(struct ql_adapter *qdev,
998 struct rx_ring *rx_ring)
999{
1000 ql_update_sbq(qdev, rx_ring);
1001 ql_update_lbq(qdev, rx_ring);
1002}
1003
1004/* Unmaps tx buffers. Can be called from send() if a pci mapping
1005 * fails at some stage, or from the interrupt when a tx completes.
1006 */
1007static void ql_unmap_send(struct ql_adapter *qdev,
1008 struct tx_ring_desc *tx_ring_desc, int mapped)
1009{
1010 int i;
1011 for (i = 0; i < mapped; i++) {
1012 if (i == 0 || (i == 7 && mapped > 7)) {
1013 /*
1014 * Unmap the skb->data area, or the
1015 * external sglist (AKA the Outbound
1016 * Address List (OAL)).
1017 * If its the zeroeth element, then it's
1018 * the skb->data area. If it's the 7th
1019 * element and there is more than 6 frags,
1020 * then its an OAL.
1021 */
1022 if (i == 7) {
1023 QPRINTK(qdev, TX_DONE, DEBUG,
1024 "unmapping OAL area.\n");
1025 }
1026 pci_unmap_single(qdev->pdev,
1027 pci_unmap_addr(&tx_ring_desc->map[i],
1028 mapaddr),
1029 pci_unmap_len(&tx_ring_desc->map[i],
1030 maplen),
1031 PCI_DMA_TODEVICE);
1032 } else {
1033 QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1034 i);
1035 pci_unmap_page(qdev->pdev,
1036 pci_unmap_addr(&tx_ring_desc->map[i],
1037 mapaddr),
1038 pci_unmap_len(&tx_ring_desc->map[i],
1039 maplen), PCI_DMA_TODEVICE);
1040 }
1041 }
1042
1043}
1044
1045/* Map the buffers for this transmit. This will return
1046 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1047 */
1048static int ql_map_send(struct ql_adapter *qdev,
1049 struct ob_mac_iocb_req *mac_iocb_ptr,
1050 struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1051{
1052 int len = skb_headlen(skb);
1053 dma_addr_t map;
1054 int frag_idx, err, map_idx = 0;
1055 struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1056 int frag_cnt = skb_shinfo(skb)->nr_frags;
1057
1058 if (frag_cnt) {
1059 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1060 }
1061 /*
1062 * Map the skb buffer first.
1063 */
1064 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1065
1066 err = pci_dma_mapping_error(qdev->pdev, map);
1067 if (err) {
1068 QPRINTK(qdev, TX_QUEUED, ERR,
1069 "PCI mapping failed with error: %d\n", err);
1070
1071 return NETDEV_TX_BUSY;
1072 }
1073
1074 tbd->len = cpu_to_le32(len);
1075 tbd->addr = cpu_to_le64(map);
1076 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1077 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1078 map_idx++;
1079
1080 /*
1081 * This loop fills the remainder of the 8 address descriptors
1082 * in the IOCB. If there are more than 7 fragments, then the
1083 * eighth address desc will point to an external list (OAL).
1084 * When this happens, the remainder of the frags will be stored
1085 * in this list.
1086 */
1087 for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1088 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1089 tbd++;
1090 if (frag_idx == 6 && frag_cnt > 7) {
1091 /* Let's tack on an sglist.
1092 * Our control block will now
1093 * look like this:
1094 * iocb->seg[0] = skb->data
1095 * iocb->seg[1] = frag[0]
1096 * iocb->seg[2] = frag[1]
1097 * iocb->seg[3] = frag[2]
1098 * iocb->seg[4] = frag[3]
1099 * iocb->seg[5] = frag[4]
1100 * iocb->seg[6] = frag[5]
1101 * iocb->seg[7] = ptr to OAL (external sglist)
1102 * oal->seg[0] = frag[6]
1103 * oal->seg[1] = frag[7]
1104 * oal->seg[2] = frag[8]
1105 * oal->seg[3] = frag[9]
1106 * oal->seg[4] = frag[10]
1107 * etc...
1108 */
1109 /* Tack on the OAL in the eighth segment of IOCB. */
1110 map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1111 sizeof(struct oal),
1112 PCI_DMA_TODEVICE);
1113 err = pci_dma_mapping_error(qdev->pdev, map);
1114 if (err) {
1115 QPRINTK(qdev, TX_QUEUED, ERR,
1116 "PCI mapping outbound address list with error: %d\n",
1117 err);
1118 goto map_error;
1119 }
1120
1121 tbd->addr = cpu_to_le64(map);
1122 /*
1123 * The length is the number of fragments
1124 * that remain to be mapped times the length
1125 * of our sglist (OAL).
1126 */
1127 tbd->len =
1128 cpu_to_le32((sizeof(struct tx_buf_desc) *
1129 (frag_cnt - frag_idx)) | TX_DESC_C);
1130 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1131 map);
1132 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1133 sizeof(struct oal));
1134 tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1135 map_idx++;
1136 }
1137
1138 map =
1139 pci_map_page(qdev->pdev, frag->page,
1140 frag->page_offset, frag->size,
1141 PCI_DMA_TODEVICE);
1142
1143 err = pci_dma_mapping_error(qdev->pdev, map);
1144 if (err) {
1145 QPRINTK(qdev, TX_QUEUED, ERR,
1146 "PCI mapping frags failed with error: %d.\n",
1147 err);
1148 goto map_error;
1149 }
1150
1151 tbd->addr = cpu_to_le64(map);
1152 tbd->len = cpu_to_le32(frag->size);
1153 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1154 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1155 frag->size);
1156
1157 }
1158 /* Save the number of segments we've mapped. */
1159 tx_ring_desc->map_cnt = map_idx;
1160 /* Terminate the last segment. */
1161 tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1162 return NETDEV_TX_OK;
1163
1164map_error:
1165 /*
1166 * If the first frag mapping failed, then i will be zero.
1167 * This causes the unmap of the skb->data area. Otherwise
1168 * we pass in the number of frags that mapped successfully
1169 * so they can be umapped.
1170 */
1171 ql_unmap_send(qdev, tx_ring_desc, map_idx);
1172 return NETDEV_TX_BUSY;
1173}
1174
8668ae92 1175static void ql_realign_skb(struct sk_buff *skb, int len)
c4e84bde
RM		 1176{
1177 void *temp_addr = skb->data;
1178
1179 /* Undo the skb_reserve(skb,32) we did before
1180 * giving to hardware, and realign data on
1181 * a 2-byte boundary.
1182 */
1183 skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1184 skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1185 skb_copy_to_linear_data(skb, temp_addr,
1186 (unsigned int)len);
1187}
1188
1189/*
1190 * This function builds an skb for the given inbound
1191 * completion. It will be rewritten for readability in the near
1192 * future, but for not it works well.
1193 */
1194static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1195 struct rx_ring *rx_ring,
1196 struct ib_mac_iocb_rsp *ib_mac_rsp)
1197{
1198 struct bq_desc *lbq_desc;
1199 struct bq_desc *sbq_desc;
1200 struct sk_buff *skb = NULL;
1201 u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1202 u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1203
1204 /*
1205 * Handle the header buffer if present.
1206 */
1207 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1208 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1209 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1210 /*
1211 * Headers fit nicely into a small buffer.
1212 */
1213 sbq_desc = ql_get_curr_sbuf(rx_ring);
1214 pci_unmap_single(qdev->pdev,
1215 pci_unmap_addr(sbq_desc, mapaddr),
1216 pci_unmap_len(sbq_desc, maplen),
1217 PCI_DMA_FROMDEVICE);
1218 skb = sbq_desc->p.skb;
1219 ql_realign_skb(skb, hdr_len);
1220 skb_put(skb, hdr_len);
1221 sbq_desc->p.skb = NULL;
1222 }
1223
1224 /*
1225 * Handle the data buffer(s).
1226 */
1227 if (unlikely(!length)) { /* Is there data too? */
1228 QPRINTK(qdev, RX_STATUS, DEBUG,
1229 "No Data buffer in this packet.\n");
1230 return skb;
1231 }
1232
1233 if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1234 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1235 QPRINTK(qdev, RX_STATUS, DEBUG,
1236 "Headers in small, data of %d bytes in small, combine them.\n", length);
1237 /*
1238 * Data is less than small buffer size so it's
1239 * stuffed in a small buffer.
1240 * For this case we append the data
1241 * from the "data" small buffer to the "header" small
1242 * buffer.
1243 */
1244 sbq_desc = ql_get_curr_sbuf(rx_ring);
1245 pci_dma_sync_single_for_cpu(qdev->pdev,
1246 pci_unmap_addr
1247 (sbq_desc, mapaddr),
1248 pci_unmap_len
1249 (sbq_desc, maplen),
1250 PCI_DMA_FROMDEVICE);
1251 memcpy(skb_put(skb, length),
1252 sbq_desc->p.skb->data, length);
1253 pci_dma_sync_single_for_device(qdev->pdev,
1254 pci_unmap_addr
1255 (sbq_desc,
1256 mapaddr),
1257 pci_unmap_len
1258 (sbq_desc,
1259 maplen),
1260 PCI_DMA_FROMDEVICE);
1261 } else {
1262 QPRINTK(qdev, RX_STATUS, DEBUG,
1263 "%d bytes in a single small buffer.\n", length);
1264 sbq_desc = ql_get_curr_sbuf(rx_ring);
1265 skb = sbq_desc->p.skb;
1266 ql_realign_skb(skb, length);
1267 skb_put(skb, length);
1268 pci_unmap_single(qdev->pdev,
1269 pci_unmap_addr(sbq_desc,
1270 mapaddr),
1271 pci_unmap_len(sbq_desc,
1272 maplen),
1273 PCI_DMA_FROMDEVICE);
1274 sbq_desc->p.skb = NULL;
1275 }
1276 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1277 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1278 QPRINTK(qdev, RX_STATUS, DEBUG,
1279 "Header in small, %d bytes in large. Chain large to small!\n", length);
1280 /*
1281 * The data is in a single large buffer. We
1282 * chain it to the header buffer's skb and let
1283 * it rip.
1284 */
1285 lbq_desc = ql_get_curr_lbuf(rx_ring);
1286 pci_unmap_page(qdev->pdev,
1287 pci_unmap_addr(lbq_desc,
1288 mapaddr),
1289 pci_unmap_len(lbq_desc, maplen),
1290 PCI_DMA_FROMDEVICE);
1291 QPRINTK(qdev, RX_STATUS, DEBUG,
1292 "Chaining page to skb.\n");
1293 skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1294 0, length);
1295 skb->len += length;
1296 skb->data_len += length;
1297 skb->truesize += length;
1298 lbq_desc->p.lbq_page = NULL;
1299 } else {
1300 /*
1301 * The headers and data are in a single large buffer. We
1302 * copy it to a new skb and let it go. This can happen with
1303 * jumbo mtu on a non-TCP/UDP frame.
1304 */
1305 lbq_desc = ql_get_curr_lbuf(rx_ring);
1306 skb = netdev_alloc_skb(qdev->ndev, length);
1307 if (skb == NULL) {
1308 QPRINTK(qdev, PROBE, DEBUG,
1309 "No skb available, drop the packet.\n");
1310 return NULL;
1311 }
4055c7d4
RM		 1312 pci_unmap_page(qdev->pdev,
1313 pci_unmap_addr(lbq_desc,
1314 mapaddr),
1315 pci_unmap_len(lbq_desc, maplen),
1316 PCI_DMA_FROMDEVICE);
c4e84bde
RM		 1317 skb_reserve(skb, NET_IP_ALIGN);
1318 QPRINTK(qdev, RX_STATUS, DEBUG,
1319 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1320 skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1321 0, length);
1322 skb->len += length;
1323 skb->data_len += length;
1324 skb->truesize += length;
1325 length -= length;
1326 lbq_desc->p.lbq_page = NULL;
1327 __pskb_pull_tail(skb,
1328 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1329 VLAN_ETH_HLEN : ETH_HLEN);
1330 }
1331 } else {
1332 /*
1333 * The data is in a chain of large buffers
1334 * pointed to by a small buffer. We loop
1335 * thru and chain them to the our small header
1336 * buffer's skb.
1337 * frags: There are 18 max frags and our small
1338 * buffer will hold 32 of them. The thing is,
1339 * we'll use 3 max for our 9000 byte jumbo
1340 * frames. If the MTU goes up we could
1341 * eventually be in trouble.
1342 */
1343 int size, offset, i = 0;
2c9a0d41 1344 __le64 *bq, bq_array[8];
c4e84bde
RM		 1345 sbq_desc = ql_get_curr_sbuf(rx_ring);
1346 pci_unmap_single(qdev->pdev,
1347 pci_unmap_addr(sbq_desc, mapaddr),
1348 pci_unmap_len(sbq_desc, maplen),
1349 PCI_DMA_FROMDEVICE);
1350 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1351 /*
1352 * This is an non TCP/UDP IP frame, so
1353 * the headers aren't split into a small
1354 * buffer. We have to use the small buffer
1355 * that contains our sg list as our skb to
1356 * send upstairs. Copy the sg list here to
1357 * a local buffer and use it to find the
1358 * pages to chain.
1359 */
1360 QPRINTK(qdev, RX_STATUS, DEBUG,
1361 "%d bytes of headers & data in chain of large.\n", length);
1362 skb = sbq_desc->p.skb;
1363 bq = &bq_array[0];
1364 memcpy(bq, skb->data, sizeof(bq_array));
1365 sbq_desc->p.skb = NULL;
1366 skb_reserve(skb, NET_IP_ALIGN);
1367 } else {
1368 QPRINTK(qdev, RX_STATUS, DEBUG,
1369 "Headers in small, %d bytes of data in chain of large.\n", length);
2c9a0d41 1370 bq = (__le64 *)sbq_desc->p.skb->data;
c4e84bde
RM		 1371 }
1372 while (length > 0) {
1373 lbq_desc = ql_get_curr_lbuf(rx_ring);
c4e84bde
RM		 1374 pci_unmap_page(qdev->pdev,
1375 pci_unmap_addr(lbq_desc,
1376 mapaddr),
1377 pci_unmap_len(lbq_desc,
1378 maplen),
1379 PCI_DMA_FROMDEVICE);
1380 size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1381 offset = 0;
1382
1383 QPRINTK(qdev, RX_STATUS, DEBUG,
1384 "Adding page %d to skb for %d bytes.\n",
1385 i, size);
1386 skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1387 offset, size);
1388 skb->len += size;
1389 skb->data_len += size;
1390 skb->truesize += size;
1391 length -= size;
1392 lbq_desc->p.lbq_page = NULL;
1393 bq++;
1394 i++;
1395 }
1396 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1397 VLAN_ETH_HLEN : ETH_HLEN);
1398 }
1399 return skb;
1400}
1401
1402/* Process an inbound completion from an rx ring. */
1403static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1404 struct rx_ring *rx_ring,
1405 struct ib_mac_iocb_rsp *ib_mac_rsp)
1406{
1407 struct net_device *ndev = qdev->ndev;
1408 struct sk_buff *skb = NULL;
1409
1410 QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1411
1412 skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1413 if (unlikely(!skb)) {
1414 QPRINTK(qdev, RX_STATUS, DEBUG,
1415 "No skb available, drop packet.\n");
1416 return;
1417 }
1418
1419 prefetch(skb->data);
1420 skb->dev = ndev;
1421 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1422 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1423 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1424 IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1425 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1426 IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1427 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1428 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1429 }
1430 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1431 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1432 }
1433 if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) {
1434 QPRINTK(qdev, RX_STATUS, ERR,
1435 "Bad checksum for this %s packet.\n",
1436 ((ib_mac_rsp->
1437 flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP"));
1438 skb->ip_summed = CHECKSUM_NONE;
1439 } else if (qdev->rx_csum &&
1440 ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ||
1441 ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1442 !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) {
1443 QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n");
1444 skb->ip_summed = CHECKSUM_UNNECESSARY;
1445 }
1446 qdev->stats.rx_packets++;
1447 qdev->stats.rx_bytes += skb->len;
1448 skb->protocol = eth_type_trans(skb, ndev);
1449 if (qdev->vlgrp && (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)) {
1450 QPRINTK(qdev, RX_STATUS, DEBUG,
1451 "Passing a VLAN packet upstream.\n");
7a9deb66 1452 vlan_hwaccel_receive_skb(skb, qdev->vlgrp,
c4e84bde
RM		 1453 le16_to_cpu(ib_mac_rsp->vlan_id));
1454 } else {
1455 QPRINTK(qdev, RX_STATUS, DEBUG,
1456 "Passing a normal packet upstream.\n");
7a9deb66 1457 netif_receive_skb(skb);
c4e84bde 1458 }
c4e84bde
RM		 1459}
1460
1461/* Process an outbound completion from an rx ring. */
1462static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1463 struct ob_mac_iocb_rsp *mac_rsp)
1464{
1465 struct tx_ring *tx_ring;
1466 struct tx_ring_desc *tx_ring_desc;
1467
1468 QL_DUMP_OB_MAC_RSP(mac_rsp);
1469 tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1470 tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1471 ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1472 qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1473 qdev->stats.tx_packets++;
1474 dev_kfree_skb(tx_ring_desc->skb);
1475 tx_ring_desc->skb = NULL;
1476
1477 if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1478 OB_MAC_IOCB_RSP_S |
1479 OB_MAC_IOCB_RSP_L |
1480 OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1481 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1482 QPRINTK(qdev, TX_DONE, WARNING,
1483 "Total descriptor length did not match transfer length.\n");
1484 }
1485 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1486 QPRINTK(qdev, TX_DONE, WARNING,
1487 "Frame too short to be legal, not sent.\n");
1488 }
1489 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1490 QPRINTK(qdev, TX_DONE, WARNING,
1491 "Frame too long, but sent anyway.\n");
1492 }
1493 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1494 QPRINTK(qdev, TX_DONE, WARNING,
1495 "PCI backplane error. Frame not sent.\n");
1496 }
1497 }
1498 atomic_inc(&tx_ring->tx_count);
1499}
1500
1501/* Fire up a handler to reset the MPI processor. */
1502void ql_queue_fw_error(struct ql_adapter *qdev)
1503{
1504 netif_stop_queue(qdev->ndev);
1505 netif_carrier_off(qdev->ndev);
1506 queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1507}
1508
1509void ql_queue_asic_error(struct ql_adapter *qdev)
1510{
1511 netif_stop_queue(qdev->ndev);
1512 netif_carrier_off(qdev->ndev);
1513 ql_disable_interrupts(qdev);
1514 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1515}
1516
1517static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1518 struct ib_ae_iocb_rsp *ib_ae_rsp)
1519{
1520 switch (ib_ae_rsp->event) {
1521 case MGMT_ERR_EVENT:
1522 QPRINTK(qdev, RX_ERR, ERR,
1523 "Management Processor Fatal Error.\n");
1524 ql_queue_fw_error(qdev);
1525 return;
1526
1527 case CAM_LOOKUP_ERR_EVENT:
1528 QPRINTK(qdev, LINK, ERR,
1529 "Multiple CAM hits lookup occurred.\n");
1530 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1531 ql_queue_asic_error(qdev);
1532 return;
1533
1534 case SOFT_ECC_ERROR_EVENT:
1535 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1536 ql_queue_asic_error(qdev);
1537 break;
1538
1539 case PCI_ERR_ANON_BUF_RD:
1540 QPRINTK(qdev, RX_ERR, ERR,
1541 "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1542 ib_ae_rsp->q_id);
1543 ql_queue_asic_error(qdev);
1544 break;
1545
1546 default:
1547 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1548 ib_ae_rsp->event);
1549 ql_queue_asic_error(qdev);
1550 break;
1551 }
1552}
1553
1554static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1555{
1556 struct ql_adapter *qdev = rx_ring->qdev;
ba7cd3ba 1557 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 1558 struct ob_mac_iocb_rsp *net_rsp = NULL;
1559 int count = 0;
1560
1561 /* While there are entries in the completion queue. */
1562 while (prod != rx_ring->cnsmr_idx) {
1563
1564 QPRINTK(qdev, RX_STATUS, DEBUG,
1565 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1566 prod, rx_ring->cnsmr_idx);
1567
1568 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1569 rmb();
1570 switch (net_rsp->opcode) {
1571
1572 case OPCODE_OB_MAC_TSO_IOCB:
1573 case OPCODE_OB_MAC_IOCB:
1574 ql_process_mac_tx_intr(qdev, net_rsp);
1575 break;
1576 default:
1577 QPRINTK(qdev, RX_STATUS, DEBUG,
1578 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1579 net_rsp->opcode);
1580 }
1581 count++;
1582 ql_update_cq(rx_ring);
ba7cd3ba 1583 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 1584 }
1585 ql_write_cq_idx(rx_ring);
1586 if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
1587 struct tx_ring *tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1588 if (atomic_read(&tx_ring->queue_stopped) &&
1589 (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1590 /*
1591 * The queue got stopped because the tx_ring was full.
1592 * Wake it up, because it's now at least 25% empty.
1593 */
1594 netif_wake_queue(qdev->ndev);
1595 }
1596
1597 return count;
1598}
1599
1600static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1601{
1602 struct ql_adapter *qdev = rx_ring->qdev;
ba7cd3ba 1603 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 1604 struct ql_net_rsp_iocb *net_rsp;
1605 int count = 0;
1606
1607 /* While there are entries in the completion queue. */
1608 while (prod != rx_ring->cnsmr_idx) {
1609
1610 QPRINTK(qdev, RX_STATUS, DEBUG,
1611 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1612 prod, rx_ring->cnsmr_idx);
1613
1614 net_rsp = rx_ring->curr_entry;
1615 rmb();
1616 switch (net_rsp->opcode) {
1617 case OPCODE_IB_MAC_IOCB:
1618 ql_process_mac_rx_intr(qdev, rx_ring,
1619 (struct ib_mac_iocb_rsp *)
1620 net_rsp);
1621 break;
1622
1623 case OPCODE_IB_AE_IOCB:
1624 ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1625 net_rsp);
1626 break;
1627 default:
1628 {
1629 QPRINTK(qdev, RX_STATUS, DEBUG,
1630 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1631 net_rsp->opcode);
1632 }
1633 }
1634 count++;
1635 ql_update_cq(rx_ring);
ba7cd3ba 1636 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 1637 if (count == budget)
1638 break;
1639 }
1640 ql_update_buffer_queues(qdev, rx_ring);
1641 ql_write_cq_idx(rx_ring);
1642 return count;
1643}
1644
1645static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1646{
1647 struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1648 struct ql_adapter *qdev = rx_ring->qdev;
1649 int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1650
1651 QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1652 rx_ring->cq_id);
1653
1654 if (work_done < budget) {
908a7a16 1655 __netif_rx_complete(napi);
c4e84bde
RM		 1656 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1657 }
1658 return work_done;
1659}
1660
1661static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1662{
1663 struct ql_adapter *qdev = netdev_priv(ndev);
1664
1665 qdev->vlgrp = grp;
1666 if (grp) {
1667 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1668 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1669 NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1670 } else {
1671 QPRINTK(qdev, IFUP, DEBUG,
1672 "Turning off VLAN in NIC_RCV_CFG.\n");
1673 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1674 }
1675}
1676
1677static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1678{
1679 struct ql_adapter *qdev = netdev_priv(ndev);
1680 u32 enable_bit = MAC_ADDR_E;
1681
1682 spin_lock(&qdev->hw_lock);
1683 if (ql_set_mac_addr_reg
1684 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1685 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1686 }
1687 spin_unlock(&qdev->hw_lock);
1688}
1689
1690static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1691{
1692 struct ql_adapter *qdev = netdev_priv(ndev);
1693 u32 enable_bit = 0;
1694
1695 spin_lock(&qdev->hw_lock);
1696 if (ql_set_mac_addr_reg
1697 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1698 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1699 }
1700 spin_unlock(&qdev->hw_lock);
1701
1702}
1703
1704/* Worker thread to process a given rx_ring that is dedicated
1705 * to outbound completions.
1706 */
1707static void ql_tx_clean(struct work_struct *work)
1708{
1709 struct rx_ring *rx_ring =
1710 container_of(work, struct rx_ring, rx_work.work);
1711 ql_clean_outbound_rx_ring(rx_ring);
1712 ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1713
1714}
1715
1716/* Worker thread to process a given rx_ring that is dedicated
1717 * to inbound completions.
1718 */
1719static void ql_rx_clean(struct work_struct *work)
1720{
1721 struct rx_ring *rx_ring =
1722 container_of(work, struct rx_ring, rx_work.work);
1723 ql_clean_inbound_rx_ring(rx_ring, 64);
1724 ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1725}
1726
1727/* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1728static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1729{
1730 struct rx_ring *rx_ring = dev_id;
1731 queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1732 &rx_ring->rx_work, 0);
1733 return IRQ_HANDLED;
1734}
1735
1736/* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1737static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1738{
1739 struct rx_ring *rx_ring = dev_id;
908a7a16 1740 netif_rx_schedule(&rx_ring->napi);
c4e84bde
RM		 1741 return IRQ_HANDLED;
1742}
1743
c4e84bde
RM		 1744/* This handles a fatal error, MPI activity, and the default
1745 * rx_ring in an MSI-X multiple vector environment.
1746 * In MSI/Legacy environment it also process the rest of
1747 * the rx_rings.
1748 */
1749static irqreturn_t qlge_isr(int irq, void *dev_id)
1750{
1751 struct rx_ring *rx_ring = dev_id;
1752 struct ql_adapter *qdev = rx_ring->qdev;
1753 struct intr_context *intr_context = &qdev->intr_context[0];
1754 u32 var;
1755 int i;
1756 int work_done = 0;
1757
bb0d215c
RM		 1758 spin_lock(&qdev->hw_lock);
1759 if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1760 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1761 spin_unlock(&qdev->hw_lock);
1762 return IRQ_NONE;
c4e84bde 1763 }
bb0d215c 1764 spin_unlock(&qdev->hw_lock);
c4e84bde 1765
bb0d215c 1766 var = ql_disable_completion_interrupt(qdev, intr_context->intr);
c4e84bde
RM		 1767
1768 /*
1769 * Check for fatal error.
1770 */
1771 if (var & STS_FE) {
1772 ql_queue_asic_error(qdev);
1773 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1774 var = ql_read32(qdev, ERR_STS);
1775 QPRINTK(qdev, INTR, ERR,
1776 "Resetting chip. Error Status Register = 0x%x\n", var);
1777 return IRQ_HANDLED;
1778 }
1779
1780 /*
1781 * Check MPI processor activity.
1782 */
1783 if (var & STS_PI) {
1784 /*
1785 * We've got an async event or mailbox completion.
1786 * Handle it and clear the source of the interrupt.
1787 */
1788 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1789 ql_disable_completion_interrupt(qdev, intr_context->intr);
1790 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1791 &qdev->mpi_work, 0);
1792 work_done++;
1793 }
1794
1795 /*
1796 * Check the default queue and wake handler if active.
1797 */
1798 rx_ring = &qdev->rx_ring[0];
ba7cd3ba 1799 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
c4e84bde
RM		 1800 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1801 ql_disable_completion_interrupt(qdev, intr_context->intr);
1802 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1803 &rx_ring->rx_work, 0);
1804 work_done++;
1805 }
1806
1807 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1808 /*
1809 * Start the DPC for each active queue.
1810 */
1811 for (i = 1; i < qdev->rx_ring_count; i++) {
1812 rx_ring = &qdev->rx_ring[i];
ba7cd3ba 1813 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
c4e84bde
RM		 1814 rx_ring->cnsmr_idx) {
1815 QPRINTK(qdev, INTR, INFO,
1816 "Waking handler for rx_ring[%d].\n", i);
1817 ql_disable_completion_interrupt(qdev,
1818 intr_context->
1819 intr);
1820 if (i < qdev->rss_ring_first_cq_id)
1821 queue_delayed_work_on(rx_ring->cpu,
1822 qdev->q_workqueue,
1823 &rx_ring->rx_work,
1824 0);
1825 else
908a7a16 1826 netif_rx_schedule(&rx_ring->napi);
c4e84bde
RM		 1827 work_done++;
1828 }
1829 }
1830 }
bb0d215c 1831 ql_enable_completion_interrupt(qdev, intr_context->intr);
c4e84bde
RM		 1832 return work_done ? IRQ_HANDLED : IRQ_NONE;
1833}
1834
1835static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1836{
1837
1838 if (skb_is_gso(skb)) {
1839 int err;
1840 if (skb_header_cloned(skb)) {
1841 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1842 if (err)
1843 return err;
1844 }
1845
1846 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1847 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1848 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1849 mac_iocb_ptr->total_hdrs_len =
1850 cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1851 mac_iocb_ptr->net_trans_offset =
1852 cpu_to_le16(skb_network_offset(skb) |
1853 skb_transport_offset(skb)
1854 << OB_MAC_TRANSPORT_HDR_SHIFT);
1855 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1856 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1857 if (likely(skb->protocol == htons(ETH_P_IP))) {
1858 struct iphdr *iph = ip_hdr(skb);
1859 iph->check = 0;
1860 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1861 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1862 iph->daddr, 0,
1863 IPPROTO_TCP,
1864 0);
1865 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1866 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
1867 tcp_hdr(skb)->check =
1868 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1869 &ipv6_hdr(skb)->daddr,
1870 0, IPPROTO_TCP, 0);
1871 }
1872 return 1;
1873 }
1874 return 0;
1875}
1876
1877static void ql_hw_csum_setup(struct sk_buff *skb,
1878 struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1879{
1880 int len;
1881 struct iphdr *iph = ip_hdr(skb);
fd2df4f7 1882 __sum16 *check;
c4e84bde
RM		 1883 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1884 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1885 mac_iocb_ptr->net_trans_offset =
1886 cpu_to_le16(skb_network_offset(skb) |
1887 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
1888
1889 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1890 len = (ntohs(iph->tot_len) - (iph->ihl << 2));
1891 if (likely(iph->protocol == IPPROTO_TCP)) {
1892 check = &(tcp_hdr(skb)->check);
1893 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
1894 mac_iocb_ptr->total_hdrs_len =
1895 cpu_to_le16(skb_transport_offset(skb) +
1896 (tcp_hdr(skb)->doff << 2));
1897 } else {
1898 check = &(udp_hdr(skb)->check);
1899 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
1900 mac_iocb_ptr->total_hdrs_len =
1901 cpu_to_le16(skb_transport_offset(skb) +
1902 sizeof(struct udphdr));
1903 }
1904 *check = ~csum_tcpudp_magic(iph->saddr,
1905 iph->daddr, len, iph->protocol, 0);
1906}
1907
1908static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
1909{
1910 struct tx_ring_desc *tx_ring_desc;
1911 struct ob_mac_iocb_req *mac_iocb_ptr;
1912 struct ql_adapter *qdev = netdev_priv(ndev);
1913 int tso;
1914 struct tx_ring *tx_ring;
1915 u32 tx_ring_idx = (u32) QL_TXQ_IDX(qdev, skb);
1916
1917 tx_ring = &qdev->tx_ring[tx_ring_idx];
1918
1919 if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
1920 QPRINTK(qdev, TX_QUEUED, INFO,
1921 "%s: shutting down tx queue %d du to lack of resources.\n",
1922 __func__, tx_ring_idx);
1923 netif_stop_queue(ndev);
1924 atomic_inc(&tx_ring->queue_stopped);
1925 return NETDEV_TX_BUSY;
1926 }
1927 tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
1928 mac_iocb_ptr = tx_ring_desc->queue_entry;
1929 memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
1930 if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) != NETDEV_TX_OK) {
1931 QPRINTK(qdev, TX_QUEUED, ERR, "Could not map the segments.\n");
1932 return NETDEV_TX_BUSY;
1933 }
1934
1935 mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
1936 mac_iocb_ptr->tid = tx_ring_desc->index;
1937 /* We use the upper 32-bits to store the tx queue for this IO.
1938 * When we get the completion we can use it to establish the context.
1939 */
1940 mac_iocb_ptr->txq_idx = tx_ring_idx;
1941 tx_ring_desc->skb = skb;
1942
1943 mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
1944
1945 if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
1946 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
1947 vlan_tx_tag_get(skb));
1948 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
1949 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
1950 }
1951 tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1952 if (tso < 0) {
1953 dev_kfree_skb_any(skb);
1954 return NETDEV_TX_OK;
1955 } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
1956 ql_hw_csum_setup(skb,
1957 (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1958 }
1959 QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
1960 tx_ring->prod_idx++;
1961 if (tx_ring->prod_idx == tx_ring->wq_len)
1962 tx_ring->prod_idx = 0;
1963 wmb();
1964
1965 ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
1966 ndev->trans_start = jiffies;
1967 QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
1968 tx_ring->prod_idx, skb->len);
1969
1970 atomic_dec(&tx_ring->tx_count);
1971 return NETDEV_TX_OK;
1972}
1973
1974static void ql_free_shadow_space(struct ql_adapter *qdev)
1975{
1976 if (qdev->rx_ring_shadow_reg_area) {
1977 pci_free_consistent(qdev->pdev,
1978 PAGE_SIZE,
1979 qdev->rx_ring_shadow_reg_area,
1980 qdev->rx_ring_shadow_reg_dma);
1981 qdev->rx_ring_shadow_reg_area = NULL;
1982 }
1983 if (qdev->tx_ring_shadow_reg_area) {
1984 pci_free_consistent(qdev->pdev,
1985 PAGE_SIZE,
1986 qdev->tx_ring_shadow_reg_area,
1987 qdev->tx_ring_shadow_reg_dma);
1988 qdev->tx_ring_shadow_reg_area = NULL;
1989 }
1990}
1991
1992static int ql_alloc_shadow_space(struct ql_adapter *qdev)
1993{
1994 qdev->rx_ring_shadow_reg_area =
1995 pci_alloc_consistent(qdev->pdev,
1996 PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
1997 if (qdev->rx_ring_shadow_reg_area == NULL) {
1998 QPRINTK(qdev, IFUP, ERR,
1999 "Allocation of RX shadow space failed.\n");
2000 return -ENOMEM;
2001 }
2002 qdev->tx_ring_shadow_reg_area =
2003 pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2004 &qdev->tx_ring_shadow_reg_dma);
2005 if (qdev->tx_ring_shadow_reg_area == NULL) {
2006 QPRINTK(qdev, IFUP, ERR,
2007 "Allocation of TX shadow space failed.\n");
2008 goto err_wqp_sh_area;
2009 }
2010 return 0;
2011
2012err_wqp_sh_area:
2013 pci_free_consistent(qdev->pdev,
2014 PAGE_SIZE,
2015 qdev->rx_ring_shadow_reg_area,
2016 qdev->rx_ring_shadow_reg_dma);
2017 return -ENOMEM;
2018}
2019
2020static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2021{
2022 struct tx_ring_desc *tx_ring_desc;
2023 int i;
2024 struct ob_mac_iocb_req *mac_iocb_ptr;
2025
2026 mac_iocb_ptr = tx_ring->wq_base;
2027 tx_ring_desc = tx_ring->q;
2028 for (i = 0; i < tx_ring->wq_len; i++) {
2029 tx_ring_desc->index = i;
2030 tx_ring_desc->skb = NULL;
2031 tx_ring_desc->queue_entry = mac_iocb_ptr;
2032 mac_iocb_ptr++;
2033 tx_ring_desc++;
2034 }
2035 atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2036 atomic_set(&tx_ring->queue_stopped, 0);
2037}
2038
2039static void ql_free_tx_resources(struct ql_adapter *qdev,
2040 struct tx_ring *tx_ring)
2041{
2042 if (tx_ring->wq_base) {
2043 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2044 tx_ring->wq_base, tx_ring->wq_base_dma);
2045 tx_ring->wq_base = NULL;
2046 }
2047 kfree(tx_ring->q);
2048 tx_ring->q = NULL;
2049}
2050
2051static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2052 struct tx_ring *tx_ring)
2053{
2054 tx_ring->wq_base =
2055 pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2056 &tx_ring->wq_base_dma);
2057
2058 if ((tx_ring->wq_base == NULL)
2059 || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2060 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2061 return -ENOMEM;
2062 }
2063 tx_ring->q =
2064 kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2065 if (tx_ring->q == NULL)
2066 goto err;
2067
2068 return 0;
2069err:
2070 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2071 tx_ring->wq_base, tx_ring->wq_base_dma);
2072 return -ENOMEM;
2073}
2074
8668ae92 2075static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
c4e84bde
RM		 2076{
2077 int i;
2078 struct bq_desc *lbq_desc;
2079
2080 for (i = 0; i < rx_ring->lbq_len; i++) {
2081 lbq_desc = &rx_ring->lbq[i];
2082 if (lbq_desc->p.lbq_page) {
2083 pci_unmap_page(qdev->pdev,
2084 pci_unmap_addr(lbq_desc, mapaddr),
2085 pci_unmap_len(lbq_desc, maplen),
2086 PCI_DMA_FROMDEVICE);
2087
2088 put_page(lbq_desc->p.lbq_page);
2089 lbq_desc->p.lbq_page = NULL;
2090 }
c4e84bde
RM		 2091 }
2092}
2093
2094/*
2095 * Allocate and map a page for each element of the lbq.
2096 */
2097static int ql_alloc_lbq_buffers(struct ql_adapter *qdev,
2098 struct rx_ring *rx_ring)
2099{
2100 int i;
2101 struct bq_desc *lbq_desc;
2102 u64 map;
2c9a0d41 2103 __le64 *bq = rx_ring->lbq_base;
c4e84bde
RM		 2104
2105 for (i = 0; i < rx_ring->lbq_len; i++) {
2106 lbq_desc = &rx_ring->lbq[i];
2107 memset(lbq_desc, 0, sizeof(lbq_desc));
2c9a0d41 2108 lbq_desc->addr = bq;
c4e84bde
RM		 2109 lbq_desc->index = i;
2110 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
2111 if (unlikely(!lbq_desc->p.lbq_page)) {
2112 QPRINTK(qdev, IFUP, ERR, "failed alloc_page().\n");
2113 goto mem_error;
2114 } else {
2115 map = pci_map_page(qdev->pdev,
2116 lbq_desc->p.lbq_page,
2117 0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
2118 if (pci_dma_mapping_error(qdev->pdev, map)) {
2119 QPRINTK(qdev, IFUP, ERR,
2120 "PCI mapping failed.\n");
2121 goto mem_error;
2122 }
2123 pci_unmap_addr_set(lbq_desc, mapaddr, map);
2124 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
2c9a0d41 2125 *lbq_desc->addr = cpu_to_le64(map);
c4e84bde
RM		 2126 }
2127 bq++;
2128 }
2129 return 0;
2130mem_error:
2131 ql_free_lbq_buffers(qdev, rx_ring);
2132 return -ENOMEM;
2133}
2134
8668ae92 2135static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
c4e84bde
RM		 2136{
2137 int i;
2138 struct bq_desc *sbq_desc;
2139
2140 for (i = 0; i < rx_ring->sbq_len; i++) {
2141 sbq_desc = &rx_ring->sbq[i];
2142 if (sbq_desc == NULL) {
2143 QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2144 return;
2145 }
2146 if (sbq_desc->p.skb) {
2147 pci_unmap_single(qdev->pdev,
2148 pci_unmap_addr(sbq_desc, mapaddr),
2149 pci_unmap_len(sbq_desc, maplen),
2150 PCI_DMA_FROMDEVICE);
2151 dev_kfree_skb(sbq_desc->p.skb);
2152 sbq_desc->p.skb = NULL;
2153 }
c4e84bde
RM		 2154 }
2155}
2156
2157/* Allocate and map an skb for each element of the sbq. */
2158static int ql_alloc_sbq_buffers(struct ql_adapter *qdev,
2159 struct rx_ring *rx_ring)
2160{
2161 int i;
2162 struct bq_desc *sbq_desc;
2163 struct sk_buff *skb;
2164 u64 map;
2c9a0d41 2165 __le64 *bq = rx_ring->sbq_base;
c4e84bde
RM		 2166
2167 for (i = 0; i < rx_ring->sbq_len; i++) {
2168 sbq_desc = &rx_ring->sbq[i];
2169 memset(sbq_desc, 0, sizeof(sbq_desc));
2170 sbq_desc->index = i;
2c9a0d41 2171 sbq_desc->addr = bq;
c4e84bde
RM		 2172 skb = netdev_alloc_skb(qdev->ndev, rx_ring->sbq_buf_size);
2173 if (unlikely(!skb)) {
2174 /* Better luck next round */
2175 QPRINTK(qdev, IFUP, ERR,
2176 "small buff alloc failed for %d bytes at index %d.\n",
2177 rx_ring->sbq_buf_size, i);
2178 goto mem_err;
2179 }
2180 skb_reserve(skb, QLGE_SB_PAD);
2181 sbq_desc->p.skb = skb;
2182 /*
2183 * Map only half the buffer. Because the
2184 * other half may get some data copied to it
2185 * when the completion arrives.
2186 */
2187 map = pci_map_single(qdev->pdev,
2188 skb->data,
2189 rx_ring->sbq_buf_size / 2,
2190 PCI_DMA_FROMDEVICE);
2191 if (pci_dma_mapping_error(qdev->pdev, map)) {
2192 QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
2193 goto mem_err;
2194 }
2195 pci_unmap_addr_set(sbq_desc, mapaddr, map);
2196 pci_unmap_len_set(sbq_desc, maplen, rx_ring->sbq_buf_size / 2);
2c9a0d41 2197 *sbq_desc->addr = cpu_to_le64(map);
c4e84bde
RM		 2198 bq++;
2199 }
2200 return 0;
2201mem_err:
2202 ql_free_sbq_buffers(qdev, rx_ring);
2203 return -ENOMEM;
2204}
2205
2206static void ql_free_rx_resources(struct ql_adapter *qdev,
2207 struct rx_ring *rx_ring)
2208{
2209 if (rx_ring->sbq_len)
2210 ql_free_sbq_buffers(qdev, rx_ring);
2211 if (rx_ring->lbq_len)
2212 ql_free_lbq_buffers(qdev, rx_ring);
2213
2214 /* Free the small buffer queue. */
2215 if (rx_ring->sbq_base) {
2216 pci_free_consistent(qdev->pdev,
2217 rx_ring->sbq_size,
2218 rx_ring->sbq_base, rx_ring->sbq_base_dma);
2219 rx_ring->sbq_base = NULL;
2220 }
2221
2222 /* Free the small buffer queue control blocks. */
2223 kfree(rx_ring->sbq);
2224 rx_ring->sbq = NULL;
2225
2226 /* Free the large buffer queue. */
2227 if (rx_ring->lbq_base) {
2228 pci_free_consistent(qdev->pdev,
2229 rx_ring->lbq_size,
2230 rx_ring->lbq_base, rx_ring->lbq_base_dma);
2231 rx_ring->lbq_base = NULL;
2232 }
2233
2234 /* Free the large buffer queue control blocks. */
2235 kfree(rx_ring->lbq);
2236 rx_ring->lbq = NULL;
2237
2238 /* Free the rx queue. */
2239 if (rx_ring->cq_base) {
2240 pci_free_consistent(qdev->pdev,
2241 rx_ring->cq_size,
2242 rx_ring->cq_base, rx_ring->cq_base_dma);
2243 rx_ring->cq_base = NULL;
2244 }
2245}
2246
2247/* Allocate queues and buffers for this completions queue based
2248 * on the values in the parameter structure. */
2249static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2250 struct rx_ring *rx_ring)
2251{
2252
2253 /*
2254 * Allocate the completion queue for this rx_ring.
2255 */
2256 rx_ring->cq_base =
2257 pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2258 &rx_ring->cq_base_dma);
2259
2260 if (rx_ring->cq_base == NULL) {
2261 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2262 return -ENOMEM;
2263 }
2264
2265 if (rx_ring->sbq_len) {
2266 /*
2267 * Allocate small buffer queue.
2268 */
2269 rx_ring->sbq_base =
2270 pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2271 &rx_ring->sbq_base_dma);
2272
2273 if (rx_ring->sbq_base == NULL) {
2274 QPRINTK(qdev, IFUP, ERR,
2275 "Small buffer queue allocation failed.\n");
2276 goto err_mem;
2277 }
2278
2279 /*
2280 * Allocate small buffer queue control blocks.
2281 */
2282 rx_ring->sbq =
2283 kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2284 GFP_KERNEL);
2285 if (rx_ring->sbq == NULL) {
2286 QPRINTK(qdev, IFUP, ERR,
2287 "Small buffer queue control block allocation failed.\n");
2288 goto err_mem;
2289 }
2290
2291 if (ql_alloc_sbq_buffers(qdev, rx_ring)) {
2292 QPRINTK(qdev, IFUP, ERR,
2293 "Small buffer allocation failed.\n");
2294 goto err_mem;
2295 }
2296 }
2297
2298 if (rx_ring->lbq_len) {
2299 /*
2300 * Allocate large buffer queue.
2301 */
2302 rx_ring->lbq_base =
2303 pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2304 &rx_ring->lbq_base_dma);
2305
2306 if (rx_ring->lbq_base == NULL) {
2307 QPRINTK(qdev, IFUP, ERR,
2308 "Large buffer queue allocation failed.\n");
2309 goto err_mem;
2310 }
2311 /*
2312 * Allocate large buffer queue control blocks.
2313 */
2314 rx_ring->lbq =
2315 kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2316 GFP_KERNEL);
2317 if (rx_ring->lbq == NULL) {
2318 QPRINTK(qdev, IFUP, ERR,
2319 "Large buffer queue control block allocation failed.\n");
2320 goto err_mem;
2321 }
2322
2323 /*
2324 * Allocate the buffers.
2325 */
2326 if (ql_alloc_lbq_buffers(qdev, rx_ring)) {
2327 QPRINTK(qdev, IFUP, ERR,
2328 "Large buffer allocation failed.\n");
2329 goto err_mem;
2330 }
2331 }
2332
2333 return 0;
2334
2335err_mem:
2336 ql_free_rx_resources(qdev, rx_ring);
2337 return -ENOMEM;
2338}
2339
2340static void ql_tx_ring_clean(struct ql_adapter *qdev)
2341{
2342 struct tx_ring *tx_ring;
2343 struct tx_ring_desc *tx_ring_desc;
2344 int i, j;
2345
2346 /*
2347 * Loop through all queues and free
2348 * any resources.
2349 */
2350 for (j = 0; j < qdev->tx_ring_count; j++) {
2351 tx_ring = &qdev->tx_ring[j];
2352 for (i = 0; i < tx_ring->wq_len; i++) {
2353 tx_ring_desc = &tx_ring->q[i];
2354 if (tx_ring_desc && tx_ring_desc->skb) {
2355 QPRINTK(qdev, IFDOWN, ERR,
2356 "Freeing lost SKB %p, from queue %d, index %d.\n",
2357 tx_ring_desc->skb, j,
2358 tx_ring_desc->index);
2359 ql_unmap_send(qdev, tx_ring_desc,
2360 tx_ring_desc->map_cnt);
2361 dev_kfree_skb(tx_ring_desc->skb);
2362 tx_ring_desc->skb = NULL;
2363 }
2364 }
2365 }
2366}
2367
c4e84bde
RM		 2368static void ql_free_mem_resources(struct ql_adapter *qdev)
2369{
2370 int i;
2371
2372 for (i = 0; i < qdev->tx_ring_count; i++)
2373 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2374 for (i = 0; i < qdev->rx_ring_count; i++)
2375 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2376 ql_free_shadow_space(qdev);
2377}
2378
2379static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2380{
2381 int i;
2382
2383 /* Allocate space for our shadow registers and such. */
2384 if (ql_alloc_shadow_space(qdev))
2385 return -ENOMEM;
2386
2387 for (i = 0; i < qdev->rx_ring_count; i++) {
2388 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2389 QPRINTK(qdev, IFUP, ERR,
2390 "RX resource allocation failed.\n");
2391 goto err_mem;
2392 }
2393 }
2394 /* Allocate tx queue resources */
2395 for (i = 0; i < qdev->tx_ring_count; i++) {
2396 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2397 QPRINTK(qdev, IFUP, ERR,
2398 "TX resource allocation failed.\n");
2399 goto err_mem;
2400 }
2401 }
2402 return 0;
2403
2404err_mem:
2405 ql_free_mem_resources(qdev);
2406 return -ENOMEM;
2407}
2408
2409/* Set up the rx ring control block and pass it to the chip.
2410 * The control block is defined as
2411 * "Completion Queue Initialization Control Block", or cqicb.
2412 */
2413static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2414{
2415 struct cqicb *cqicb = &rx_ring->cqicb;
2416 void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2417 (rx_ring->cq_id * sizeof(u64) * 4);
2418 u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2419 (rx_ring->cq_id * sizeof(u64) * 4);
2420 void __iomem *doorbell_area =
2421 qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2422 int err = 0;
2423 u16 bq_len;
2424
2425 /* Set up the shadow registers for this ring. */
2426 rx_ring->prod_idx_sh_reg = shadow_reg;
2427 rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2428 shadow_reg += sizeof(u64);
2429 shadow_reg_dma += sizeof(u64);
2430 rx_ring->lbq_base_indirect = shadow_reg;
2431 rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2432 shadow_reg += sizeof(u64);
2433 shadow_reg_dma += sizeof(u64);
2434 rx_ring->sbq_base_indirect = shadow_reg;
2435 rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2436
2437 /* PCI doorbell mem area + 0x00 for consumer index register */
8668ae92 2438 rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
c4e84bde
RM		 2439 rx_ring->cnsmr_idx = 0;
2440 rx_ring->curr_entry = rx_ring->cq_base;
2441
2442 /* PCI doorbell mem area + 0x04 for valid register */
2443 rx_ring->valid_db_reg = doorbell_area + 0x04;
2444
2445 /* PCI doorbell mem area + 0x18 for large buffer consumer */
8668ae92 2446 rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
c4e84bde
RM		 2447
2448 /* PCI doorbell mem area + 0x1c */
8668ae92 2449 rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
c4e84bde
RM		 2450
2451 memset((void *)cqicb, 0, sizeof(struct cqicb));
2452 cqicb->msix_vect = rx_ring->irq;
2453
459caf5a
RM		 2454 bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2455 cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
c4e84bde 2456
97345524 2457 cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
c4e84bde 2458
97345524 2459 cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
c4e84bde
RM		 2460
2461 /*
2462 * Set up the control block load flags.
2463 */
2464 cqicb->flags = FLAGS_LC | /* Load queue base address */
2465 FLAGS_LV | /* Load MSI-X vector */
2466 FLAGS_LI; /* Load irq delay values */
2467 if (rx_ring->lbq_len) {
2468 cqicb->flags |= FLAGS_LL; /* Load lbq values */
2469 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
97345524
RM		 2470 cqicb->lbq_addr =
2471 cpu_to_le64(rx_ring->lbq_base_indirect_dma);
459caf5a
RM		 2472 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2473 (u16) rx_ring->lbq_buf_size;
2474 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2475 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2476 (u16) rx_ring->lbq_len;
c4e84bde
RM		 2477 cqicb->lbq_len = cpu_to_le16(bq_len);
2478 rx_ring->lbq_prod_idx = rx_ring->lbq_len - 16;
2479 rx_ring->lbq_curr_idx = 0;
2480 rx_ring->lbq_clean_idx = rx_ring->lbq_prod_idx;
2481 rx_ring->lbq_free_cnt = 16;
2482 }
2483 if (rx_ring->sbq_len) {
2484 cqicb->flags |= FLAGS_LS; /* Load sbq values */
2485 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
97345524
RM		 2486 cqicb->sbq_addr =
2487 cpu_to_le64(rx_ring->sbq_base_indirect_dma);
c4e84bde
RM		 2488 cqicb->sbq_buf_size =
2489 cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
459caf5a
RM		 2490 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2491 (u16) rx_ring->sbq_len;
c4e84bde
RM		 2492 cqicb->sbq_len = cpu_to_le16(bq_len);
2493 rx_ring->sbq_prod_idx = rx_ring->sbq_len - 16;
2494 rx_ring->sbq_curr_idx = 0;
2495 rx_ring->sbq_clean_idx = rx_ring->sbq_prod_idx;
2496 rx_ring->sbq_free_cnt = 16;
2497 }
2498 switch (rx_ring->type) {
2499 case TX_Q:
2500 /* If there's only one interrupt, then we use
2501 * worker threads to process the outbound
2502 * completion handling rx_rings. We do this so
2503 * they can be run on multiple CPUs. There is
2504 * room to play with this more where we would only
2505 * run in a worker if there are more than x number
2506 * of outbound completions on the queue and more
2507 * than one queue active. Some threshold that
2508 * would indicate a benefit in spite of the cost
2509 * of a context switch.
2510 * If there's more than one interrupt, then the
2511 * outbound completions are processed in the ISR.
2512 */
2513 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2514 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2515 else {
2516 /* With all debug warnings on we see a WARN_ON message
2517 * when we free the skb in the interrupt context.
2518 */
2519 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2520 }
2521 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2522 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2523 break;
2524 case DEFAULT_Q:
2525 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2526 cqicb->irq_delay = 0;
2527 cqicb->pkt_delay = 0;
2528 break;
2529 case RX_Q:
2530 /* Inbound completion handling rx_rings run in
2531 * separate NAPI contexts.
2532 */
2533 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2534 64);
2535 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2536 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2537 break;
2538 default:
2539 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2540 rx_ring->type);
2541 }
2542 QPRINTK(qdev, IFUP, INFO, "Initializing rx work queue.\n");
2543 err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2544 CFG_LCQ, rx_ring->cq_id);
2545 if (err) {
2546 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2547 return err;
2548 }
2549 QPRINTK(qdev, IFUP, INFO, "Successfully loaded CQICB.\n");
2550 /*
2551 * Advance the producer index for the buffer queues.
2552 */
2553 wmb();
2554 if (rx_ring->lbq_len)
2555 ql_write_db_reg(rx_ring->lbq_prod_idx,
2556 rx_ring->lbq_prod_idx_db_reg);
2557 if (rx_ring->sbq_len)
2558 ql_write_db_reg(rx_ring->sbq_prod_idx,
2559 rx_ring->sbq_prod_idx_db_reg);
2560 return err;
2561}
2562
2563static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2564{
2565 struct wqicb *wqicb = (struct wqicb *)tx_ring;
2566 void __iomem *doorbell_area =
2567 qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2568 void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2569 (tx_ring->wq_id * sizeof(u64));
2570 u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2571 (tx_ring->wq_id * sizeof(u64));
2572 int err = 0;
2573
2574 /*
2575 * Assign doorbell registers for this tx_ring.
2576 */
2577 /* TX PCI doorbell mem area for tx producer index */
8668ae92 2578 tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
c4e84bde
RM		 2579 tx_ring->prod_idx = 0;
2580 /* TX PCI doorbell mem area + 0x04 */
2581 tx_ring->valid_db_reg = doorbell_area + 0x04;
2582
2583 /*
2584 * Assign shadow registers for this tx_ring.
2585 */
2586 tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2587 tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2588
2589 wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2590 wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2591 Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2592 wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2593 wqicb->rid = 0;
97345524 2594 wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
c4e84bde 2595
97345524 2596 wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
c4e84bde
RM		 2597
2598 ql_init_tx_ring(qdev, tx_ring);
2599
2600 err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2601 (u16) tx_ring->wq_id);
2602 if (err) {
2603 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2604 return err;
2605 }
2606 QPRINTK(qdev, IFUP, INFO, "Successfully loaded WQICB.\n");
2607 return err;
2608}
2609
2610static void ql_disable_msix(struct ql_adapter *qdev)
2611{
2612 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2613 pci_disable_msix(qdev->pdev);
2614 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2615 kfree(qdev->msi_x_entry);
2616 qdev->msi_x_entry = NULL;
2617 } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2618 pci_disable_msi(qdev->pdev);
2619 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2620 }
2621}
2622
2623static void ql_enable_msix(struct ql_adapter *qdev)
2624{
2625 int i;
2626
2627 qdev->intr_count = 1;
2628 /* Get the MSIX vectors. */
2629 if (irq_type == MSIX_IRQ) {
2630 /* Try to alloc space for the msix struct,
2631 * if it fails then go to MSI/legacy.
2632 */
2633 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2634 sizeof(struct msix_entry),
2635 GFP_KERNEL);
2636 if (!qdev->msi_x_entry) {
2637 irq_type = MSI_IRQ;
2638 goto msi;
2639 }
2640
2641 for (i = 0; i < qdev->rx_ring_count; i++)
2642 qdev->msi_x_entry[i].entry = i;
2643
2644 if (!pci_enable_msix
2645 (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2646 set_bit(QL_MSIX_ENABLED, &qdev->flags);
2647 qdev->intr_count = qdev->rx_ring_count;
2648 QPRINTK(qdev, IFUP, INFO,
2649 "MSI-X Enabled, got %d vectors.\n",
2650 qdev->intr_count);
2651 return;
2652 } else {
2653 kfree(qdev->msi_x_entry);
2654 qdev->msi_x_entry = NULL;
2655 QPRINTK(qdev, IFUP, WARNING,
2656 "MSI-X Enable failed, trying MSI.\n");
2657 irq_type = MSI_IRQ;
2658 }
2659 }
2660msi:
2661 if (irq_type == MSI_IRQ) {
2662 if (!pci_enable_msi(qdev->pdev)) {
2663 set_bit(QL_MSI_ENABLED, &qdev->flags);
2664 QPRINTK(qdev, IFUP, INFO,
2665 "Running with MSI interrupts.\n");
2666 return;
2667 }
2668 }
2669 irq_type = LEG_IRQ;
c4e84bde
RM		 2670 QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2671}
2672
2673/*
2674 * Here we build the intr_context structures based on
2675 * our rx_ring count and intr vector count.
2676 * The intr_context structure is used to hook each vector
2677 * to possibly different handlers.
2678 */
2679static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2680{
2681 int i = 0;
2682 struct intr_context *intr_context = &qdev->intr_context[0];
2683
2684 ql_enable_msix(qdev);
2685
2686 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2687 /* Each rx_ring has it's
2688 * own intr_context since we have separate
2689 * vectors for each queue.
2690 * This only true when MSI-X is enabled.
2691 */
2692 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2693 qdev->rx_ring[i].irq = i;
2694 intr_context->intr = i;
2695 intr_context->qdev = qdev;
2696 /*
2697 * We set up each vectors enable/disable/read bits so
2698 * there's no bit/mask calculations in the critical path.
2699 */
2700 intr_context->intr_en_mask =
2701 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2702 INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2703 | i;
2704 intr_context->intr_dis_mask =
2705 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2706 INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2707 INTR_EN_IHD | i;
2708 intr_context->intr_read_mask =
2709 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2710 INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2711 i;
2712
2713 if (i == 0) {
2714 /*
2715 * Default queue handles bcast/mcast plus
2716 * async events. Needs buffers.
2717 */
2718 intr_context->handler = qlge_isr;
2719 sprintf(intr_context->name, "%s-default-queue",
2720 qdev->ndev->name);
2721 } else if (i < qdev->rss_ring_first_cq_id) {
2722 /*
2723 * Outbound queue is for outbound completions only.
2724 */
2725 intr_context->handler = qlge_msix_tx_isr;
c224969e 2726 sprintf(intr_context->name, "%s-tx-%d",
c4e84bde
RM		 2727 qdev->ndev->name, i);
2728 } else {
2729 /*
2730 * Inbound queues handle unicast frames only.
2731 */
2732 intr_context->handler = qlge_msix_rx_isr;
c224969e 2733 sprintf(intr_context->name, "%s-rx-%d",
c4e84bde
RM		 2734 qdev->ndev->name, i);
2735 }
2736 }
2737 } else {
2738 /*
2739 * All rx_rings use the same intr_context since
2740 * there is only one vector.
2741 */
2742 intr_context->intr = 0;
2743 intr_context->qdev = qdev;
2744 /*
2745 * We set up each vectors enable/disable/read bits so
2746 * there's no bit/mask calculations in the critical path.
2747 */
2748 intr_context->intr_en_mask =
2749 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2750 intr_context->intr_dis_mask =
2751 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2752 INTR_EN_TYPE_DISABLE;
2753 intr_context->intr_read_mask =
2754 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2755 /*
2756 * Single interrupt means one handler for all rings.
2757 */
2758 intr_context->handler = qlge_isr;
2759 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2760 for (i = 0; i < qdev->rx_ring_count; i++)
2761 qdev->rx_ring[i].irq = 0;
2762 }
2763}
2764
2765static void ql_free_irq(struct ql_adapter *qdev)
2766{
2767 int i;
2768 struct intr_context *intr_context = &qdev->intr_context[0];
2769
2770 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2771 if (intr_context->hooked) {
2772 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2773 free_irq(qdev->msi_x_entry[i].vector,
2774 &qdev->rx_ring[i]);
2775 QPRINTK(qdev, IFDOWN, ERR,
2776 "freeing msix interrupt %d.\n", i);
2777 } else {
2778 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2779 QPRINTK(qdev, IFDOWN, ERR,
2780 "freeing msi interrupt %d.\n", i);
2781 }
2782 }
2783 }
2784 ql_disable_msix(qdev);
2785}
2786
2787static int ql_request_irq(struct ql_adapter *qdev)
2788{
2789 int i;
2790 int status = 0;
2791 struct pci_dev *pdev = qdev->pdev;
2792 struct intr_context *intr_context = &qdev->intr_context[0];
2793
2794 ql_resolve_queues_to_irqs(qdev);
2795
2796 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2797 atomic_set(&intr_context->irq_cnt, 0);
2798 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2799 status = request_irq(qdev->msi_x_entry[i].vector,
2800 intr_context->handler,
2801 0,
2802 intr_context->name,
2803 &qdev->rx_ring[i]);
2804 if (status) {
2805 QPRINTK(qdev, IFUP, ERR,
2806 "Failed request for MSIX interrupt %d.\n",
2807 i);
2808 goto err_irq;
2809 } else {
2810 QPRINTK(qdev, IFUP, INFO,
2811 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2812 i,
2813 qdev->rx_ring[i].type ==
2814 DEFAULT_Q ? "DEFAULT_Q" : "",
2815 qdev->rx_ring[i].type ==
2816 TX_Q ? "TX_Q" : "",
2817 qdev->rx_ring[i].type ==
2818 RX_Q ? "RX_Q" : "", intr_context->name);
2819 }
2820 } else {
2821 QPRINTK(qdev, IFUP, DEBUG,
2822 "trying msi or legacy interrupts.\n");
2823 QPRINTK(qdev, IFUP, DEBUG,
2824 "%s: irq = %d.\n", __func__, pdev->irq);
2825 QPRINTK(qdev, IFUP, DEBUG,
2826 "%s: context->name = %s.\n", __func__,
2827 intr_context->name);
2828 QPRINTK(qdev, IFUP, DEBUG,
2829 "%s: dev_id = 0x%p.\n", __func__,
2830 &qdev->rx_ring[0]);
2831 status =
2832 request_irq(pdev->irq, qlge_isr,
2833 test_bit(QL_MSI_ENABLED,
2834 &qdev->
2835 flags) ? 0 : IRQF_SHARED,
2836 intr_context->name, &qdev->rx_ring[0]);
2837 if (status)
2838 goto err_irq;
2839
2840 QPRINTK(qdev, IFUP, ERR,
2841 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2842 i,
2843 qdev->rx_ring[0].type ==
2844 DEFAULT_Q ? "DEFAULT_Q" : "",
2845 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2846 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2847 intr_context->name);
2848 }
2849 intr_context->hooked = 1;
2850 }
2851 return status;
2852err_irq:
2853 QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2854 ql_free_irq(qdev);
2855 return status;
2856}
2857
2858static int ql_start_rss(struct ql_adapter *qdev)
2859{
2860 struct ricb *ricb = &qdev->ricb;
2861 int status = 0;
2862 int i;
2863 u8 *hash_id = (u8 *) ricb->hash_cq_id;
2864
2865 memset((void *)ricb, 0, sizeof(ricb));
2866
2867 ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2868 ricb->flags =
2869 (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2870 RSS_RT6);
2871 ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2872
2873 /*
2874 * Fill out the Indirection Table.
2875 */
2876 for (i = 0; i < 32; i++)
2877 hash_id[i] = i & 1;
2878
2879 /*
2880 * Random values for the IPv6 and IPv4 Hash Keys.
2881 */
2882 get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2883 get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2884
2885 QPRINTK(qdev, IFUP, INFO, "Initializing RSS.\n");
2886
2887 status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2888 if (status) {
2889 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2890 return status;
2891 }
2892 QPRINTK(qdev, IFUP, INFO, "Successfully loaded RICB.\n");
2893 return status;
2894}
2895
2896/* Initialize the frame-to-queue routing. */
2897static int ql_route_initialize(struct ql_adapter *qdev)
2898{
2899 int status = 0;
2900 int i;
2901
2902 /* Clear all the entries in the routing table. */
2903 for (i = 0; i < 16; i++) {
2904 status = ql_set_routing_reg(qdev, i, 0, 0);
2905 if (status) {
2906 QPRINTK(qdev, IFUP, ERR,
2907 "Failed to init routing register for CAM packets.\n");
2908 return status;
2909 }
2910 }
2911
2912 status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
2913 if (status) {
2914 QPRINTK(qdev, IFUP, ERR,
2915 "Failed to init routing register for error packets.\n");
2916 return status;
2917 }
2918 status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
2919 if (status) {
2920 QPRINTK(qdev, IFUP, ERR,
2921 "Failed to init routing register for broadcast packets.\n");
2922 return status;
2923 }
2924 /* If we have more than one inbound queue, then turn on RSS in the
2925 * routing block.
2926 */
2927 if (qdev->rss_ring_count > 1) {
2928 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
2929 RT_IDX_RSS_MATCH, 1);
2930 if (status) {
2931 QPRINTK(qdev, IFUP, ERR,
2932 "Failed to init routing register for MATCH RSS packets.\n");
2933 return status;
2934 }
2935 }
2936
2937 status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
2938 RT_IDX_CAM_HIT, 1);
2939 if (status) {
2940 QPRINTK(qdev, IFUP, ERR,
2941 "Failed to init routing register for CAM packets.\n");
2942 return status;
2943 }
2944 return status;
2945}
2946
2947static int ql_adapter_initialize(struct ql_adapter *qdev)
2948{
2949 u32 value, mask;
2950 int i;
2951 int status = 0;
2952
2953 /*
2954 * Set up the System register to halt on errors.
2955 */
2956 value = SYS_EFE | SYS_FAE;
2957 mask = value << 16;
2958 ql_write32(qdev, SYS, mask | value);
2959
2960 /* Set the default queue. */
2961 value = NIC_RCV_CFG_DFQ;
2962 mask = NIC_RCV_CFG_DFQ_MASK;
2963 ql_write32(qdev, NIC_RCV_CFG, (mask | value));
2964
2965 /* Set the MPI interrupt to enabled. */
2966 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
2967
2968 /* Enable the function, set pagesize, enable error checking. */
2969 value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
2970 FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
2971
2972 /* Set/clear header splitting. */
2973 mask = FSC_VM_PAGESIZE_MASK |
2974 FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
2975 ql_write32(qdev, FSC, mask | value);
2976
2977 ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
2978 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
2979
2980 /* Start up the rx queues. */
2981 for (i = 0; i < qdev->rx_ring_count; i++) {
2982 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
2983 if (status) {
2984 QPRINTK(qdev, IFUP, ERR,
2985 "Failed to start rx ring[%d].\n", i);
2986 return status;
2987 }
2988 }
2989
2990 /* If there is more than one inbound completion queue
2991 * then download a RICB to configure RSS.
2992 */
2993 if (qdev->rss_ring_count > 1) {
2994 status = ql_start_rss(qdev);
2995 if (status) {
2996 QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
2997 return status;
2998 }
2999 }
3000
3001 /* Start up the tx queues. */
3002 for (i = 0; i < qdev->tx_ring_count; i++) {
3003 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3004 if (status) {
3005 QPRINTK(qdev, IFUP, ERR,
3006 "Failed to start tx ring[%d].\n", i);
3007 return status;
3008 }
3009 }
3010
3011 status = ql_port_initialize(qdev);
3012 if (status) {
3013 QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3014 return status;
3015 }
3016
3017 status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3018 MAC_ADDR_TYPE_CAM_MAC, qdev->func);
3019 if (status) {
3020 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3021 return status;
3022 }
3023
3024 status = ql_route_initialize(qdev);
3025 if (status) {
3026 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3027 return status;
3028 }
3029
3030 /* Start NAPI for the RSS queues. */
3031 for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3032 QPRINTK(qdev, IFUP, INFO, "Enabling NAPI for rx_ring[%d].\n",
3033 i);
3034 napi_enable(&qdev->rx_ring[i].napi);
3035 }
3036
3037 return status;
3038}
3039
3040/* Issue soft reset to chip. */
3041static int ql_adapter_reset(struct ql_adapter *qdev)
3042{
3043 u32 value;
3044 int max_wait_time;
3045 int status = 0;
3046 int resetCnt = 0;
3047
3048#define MAX_RESET_CNT 1
3049issueReset:
3050 resetCnt++;
3051 QPRINTK(qdev, IFDOWN, DEBUG, "Issue soft reset to chip.\n");
3052 ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3053 /* Wait for reset to complete. */
3054 max_wait_time = 3;
3055 QPRINTK(qdev, IFDOWN, DEBUG, "Wait %d seconds for reset to complete.\n",
3056 max_wait_time);
3057 do {
3058 value = ql_read32(qdev, RST_FO);
3059 if ((value & RST_FO_FR) == 0)
3060 break;
3061
3062 ssleep(1);
3063 } while ((--max_wait_time));
3064 if (value & RST_FO_FR) {
3065 QPRINTK(qdev, IFDOWN, ERR,
3066 "Stuck in SoftReset: FSC_SR:0x%08x\n", value);
3067 if (resetCnt < MAX_RESET_CNT)
3068 goto issueReset;
3069 }
3070 if (max_wait_time == 0) {
3071 status = -ETIMEDOUT;
3072 QPRINTK(qdev, IFDOWN, ERR,
3073 "ETIMEOUT!!! errored out of resetting the chip!\n");
3074 }
3075
3076 return status;
3077}
3078
3079static void ql_display_dev_info(struct net_device *ndev)
3080{
3081 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3082
3083 QPRINTK(qdev, PROBE, INFO,
3084 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3085 "XG Roll = %d, XG Rev = %d.\n",
3086 qdev->func,
3087 qdev->chip_rev_id & 0x0000000f,
3088 qdev->chip_rev_id >> 4 & 0x0000000f,
3089 qdev->chip_rev_id >> 8 & 0x0000000f,
3090 qdev->chip_rev_id >> 12 & 0x0000000f);
7c510e4b 3091 QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
c4e84bde
RM		 3092}
3093
3094static int ql_adapter_down(struct ql_adapter *qdev)
3095{
3096 struct net_device *ndev = qdev->ndev;
3097 int i, status = 0;
3098 struct rx_ring *rx_ring;
3099
3100 netif_stop_queue(ndev);
3101 netif_carrier_off(ndev);
3102
3103 cancel_delayed_work_sync(&qdev->asic_reset_work);
3104 cancel_delayed_work_sync(&qdev->mpi_reset_work);
3105 cancel_delayed_work_sync(&qdev->mpi_work);
3106
3107 /* The default queue at index 0 is always processed in
3108 * a workqueue.
3109 */
3110 cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3111
3112 /* The rest of the rx_rings are processed in
3113 * a workqueue only if it's a single interrupt
3114 * environment (MSI/Legacy).
3115 */
c062076c 3116 for (i = 1; i < qdev->rx_ring_count; i++) {
c4e84bde
RM		 3117 rx_ring = &qdev->rx_ring[i];
3118 /* Only the RSS rings use NAPI on multi irq
3119 * environment. Outbound completion processing
3120 * is done in interrupt context.
3121 */
3122 if (i >= qdev->rss_ring_first_cq_id) {
3123 napi_disable(&rx_ring->napi);
3124 } else {
3125 cancel_delayed_work_sync(&rx_ring->rx_work);
3126 }
3127 }
3128
3129 clear_bit(QL_ADAPTER_UP, &qdev->flags);
3130
3131 ql_disable_interrupts(qdev);
3132
3133 ql_tx_ring_clean(qdev);
3134
3135 spin_lock(&qdev->hw_lock);
3136 status = ql_adapter_reset(qdev);
3137 if (status)
3138 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3139 qdev->func);
3140 spin_unlock(&qdev->hw_lock);
3141 return status;
3142}
3143
3144static int ql_adapter_up(struct ql_adapter *qdev)
3145{
3146 int err = 0;
3147
3148 spin_lock(&qdev->hw_lock);
3149 err = ql_adapter_initialize(qdev);
3150 if (err) {
3151 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3152 spin_unlock(&qdev->hw_lock);
3153 goto err_init;
3154 }
3155 spin_unlock(&qdev->hw_lock);
3156 set_bit(QL_ADAPTER_UP, &qdev->flags);
3157 ql_enable_interrupts(qdev);
3158 ql_enable_all_completion_interrupts(qdev);
3159 if ((ql_read32(qdev, STS) & qdev->port_init)) {
3160 netif_carrier_on(qdev->ndev);
3161 netif_start_queue(qdev->ndev);
3162 }
3163
3164 return 0;
3165err_init:
3166 ql_adapter_reset(qdev);
3167 return err;
3168}
3169
3170static int ql_cycle_adapter(struct ql_adapter *qdev)
3171{
3172 int status;
3173
3174 status = ql_adapter_down(qdev);
3175 if (status)
3176 goto error;
3177
3178 status = ql_adapter_up(qdev);
3179 if (status)
3180 goto error;
3181
3182 return status;
3183error:
3184 QPRINTK(qdev, IFUP, ALERT,
3185 "Driver up/down cycle failed, closing device\n");
3186 rtnl_lock();
3187 dev_close(qdev->ndev);
3188 rtnl_unlock();
3189 return status;
3190}
3191
3192static void ql_release_adapter_resources(struct ql_adapter *qdev)
3193{
3194 ql_free_mem_resources(qdev);
3195 ql_free_irq(qdev);
3196}
3197
3198static int ql_get_adapter_resources(struct ql_adapter *qdev)
3199{
3200 int status = 0;
3201
3202 if (ql_alloc_mem_resources(qdev)) {
3203 QPRINTK(qdev, IFUP, ERR, "Unable to allocate memory.\n");
3204 return -ENOMEM;
3205 }
3206 status = ql_request_irq(qdev);
3207 if (status)
3208 goto err_irq;
3209 return status;
3210err_irq:
3211 ql_free_mem_resources(qdev);
3212 return status;
3213}
3214
3215static int qlge_close(struct net_device *ndev)
3216{
3217 struct ql_adapter *qdev = netdev_priv(ndev);
3218
3219 /*
3220 * Wait for device to recover from a reset.
3221 * (Rarely happens, but possible.)
3222 */
3223 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3224 msleep(1);
3225 ql_adapter_down(qdev);
3226 ql_release_adapter_resources(qdev);
c4e84bde
RM		 3227 return 0;
3228}
3229
3230static int ql_configure_rings(struct ql_adapter *qdev)
3231{
3232 int i;
3233 struct rx_ring *rx_ring;
3234 struct tx_ring *tx_ring;
3235 int cpu_cnt = num_online_cpus();
3236
3237 /*
3238 * For each processor present we allocate one
3239 * rx_ring for outbound completions, and one
3240 * rx_ring for inbound completions. Plus there is
3241 * always the one default queue. For the CPU
3242 * counts we end up with the following rx_rings:
3243 * rx_ring count =
3244 * one default queue +
3245 * (CPU count * outbound completion rx_ring) +
3246 * (CPU count * inbound (RSS) completion rx_ring)
3247 * To keep it simple we limit the total number of
3248 * queues to < 32, so we truncate CPU to 8.
3249 * This limitation can be removed when requested.
3250 */
3251
683d46a9
RM		 3252 if (cpu_cnt > MAX_CPUS)
3253 cpu_cnt = MAX_CPUS;
c4e84bde
RM		 3254
3255 /*
3256 * rx_ring[0] is always the default queue.
3257 */
3258 /* Allocate outbound completion ring for each CPU. */
3259 qdev->tx_ring_count = cpu_cnt;
3260 /* Allocate inbound completion (RSS) ring for each CPU. */
3261 qdev->rss_ring_count = cpu_cnt;
3262 /* cq_id for the first inbound ring handler. */
3263 qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3264 /*
3265 * qdev->rx_ring_count:
3266 * Total number of rx_rings. This includes the one
3267 * default queue, a number of outbound completion
3268 * handler rx_rings, and the number of inbound
3269 * completion handler rx_rings.
3270 */
3271 qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3272
c4e84bde
RM		 3273 for (i = 0; i < qdev->tx_ring_count; i++) {
3274 tx_ring = &qdev->tx_ring[i];
3275 memset((void *)tx_ring, 0, sizeof(tx_ring));
3276 tx_ring->qdev = qdev;
3277 tx_ring->wq_id = i;
3278 tx_ring->wq_len = qdev->tx_ring_size;
3279 tx_ring->wq_size =
3280 tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3281
3282 /*
3283 * The completion queue ID for the tx rings start
3284 * immediately after the default Q ID, which is zero.
3285 */
3286 tx_ring->cq_id = i + 1;
3287 }
3288
3289 for (i = 0; i < qdev->rx_ring_count; i++) {
3290 rx_ring = &qdev->rx_ring[i];
3291 memset((void *)rx_ring, 0, sizeof(rx_ring));
3292 rx_ring->qdev = qdev;
3293 rx_ring->cq_id = i;
3294 rx_ring->cpu = i % cpu_cnt; /* CPU to run handler on. */
3295 if (i == 0) { /* Default queue at index 0. */
3296 /*
3297 * Default queue handles bcast/mcast plus
3298 * async events. Needs buffers.
3299 */
3300 rx_ring->cq_len = qdev->rx_ring_size;
3301 rx_ring->cq_size =
3302 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3303 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3304 rx_ring->lbq_size =
2c9a0d41 3305 rx_ring->lbq_len * sizeof(__le64);
c4e84bde
RM		 3306 rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3307 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3308 rx_ring->sbq_size =
2c9a0d41 3309 rx_ring->sbq_len * sizeof(__le64);
c4e84bde
RM		 3310 rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3311 rx_ring->type = DEFAULT_Q;
3312 } else if (i < qdev->rss_ring_first_cq_id) {
3313 /*
3314 * Outbound queue handles outbound completions only.
3315 */
3316 /* outbound cq is same size as tx_ring it services. */
3317 rx_ring->cq_len = qdev->tx_ring_size;
3318 rx_ring->cq_size =
3319 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3320 rx_ring->lbq_len = 0;
3321 rx_ring->lbq_size = 0;
3322 rx_ring->lbq_buf_size = 0;
3323 rx_ring->sbq_len = 0;
3324 rx_ring->sbq_size = 0;
3325 rx_ring->sbq_buf_size = 0;
3326 rx_ring->type = TX_Q;
3327 } else { /* Inbound completions (RSS) queues */
3328 /*
3329 * Inbound queues handle unicast frames only.
3330 */
3331 rx_ring->cq_len = qdev->rx_ring_size;
3332 rx_ring->cq_size =
3333 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3334 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3335 rx_ring->lbq_size =
2c9a0d41 3336 rx_ring->lbq_len * sizeof(__le64);
c4e84bde
RM		 3337 rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3338 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3339 rx_ring->sbq_size =
2c9a0d41 3340 rx_ring->sbq_len * sizeof(__le64);
c4e84bde
RM		 3341 rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3342 rx_ring->type = RX_Q;
3343 }
3344 }
3345 return 0;
3346}
3347
3348static int qlge_open(struct net_device *ndev)
3349{
3350 int err = 0;
3351 struct ql_adapter *qdev = netdev_priv(ndev);
3352
3353 err = ql_configure_rings(qdev);
3354 if (err)
3355 return err;
3356
3357 err = ql_get_adapter_resources(qdev);
3358 if (err)
3359 goto error_up;
3360
3361 err = ql_adapter_up(qdev);
3362 if (err)
3363 goto error_up;
3364
3365 return err;
3366
3367error_up:
3368 ql_release_adapter_resources(qdev);
c4e84bde
RM		 3369 return err;
3370}
3371
3372static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3373{
3374 struct ql_adapter *qdev = netdev_priv(ndev);
3375
3376 if (ndev->mtu == 1500 && new_mtu == 9000) {
3377 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3378 } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3379 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3380 } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3381 (ndev->mtu == 9000 && new_mtu == 9000)) {
3382 return 0;
3383 } else
3384 return -EINVAL;
3385 ndev->mtu = new_mtu;
3386 return 0;
3387}
3388
3389static struct net_device_stats *qlge_get_stats(struct net_device
3390 *ndev)
3391{
3392 struct ql_adapter *qdev = netdev_priv(ndev);
3393 return &qdev->stats;
3394}
3395
3396static void qlge_set_multicast_list(struct net_device *ndev)
3397{
3398 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3399 struct dev_mc_list *mc_ptr;
3400 int i;
3401
3402 spin_lock(&qdev->hw_lock);
3403 /*
3404 * Set or clear promiscuous mode if a
3405 * transition is taking place.
3406 */
3407 if (ndev->flags & IFF_PROMISC) {
3408 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3409 if (ql_set_routing_reg
3410 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3411 QPRINTK(qdev, HW, ERR,
3412 "Failed to set promiscous mode.\n");
3413 } else {
3414 set_bit(QL_PROMISCUOUS, &qdev->flags);
3415 }
3416 }
3417 } else {
3418 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3419 if (ql_set_routing_reg
3420 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3421 QPRINTK(qdev, HW, ERR,
3422 "Failed to clear promiscous mode.\n");
3423 } else {
3424 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3425 }
3426 }
3427 }
3428
3429 /*
3430 * Set or clear all multicast mode if a
3431 * transition is taking place.
3432 */
3433 if ((ndev->flags & IFF_ALLMULTI) ||
3434 (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3435 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3436 if (ql_set_routing_reg
3437 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3438 QPRINTK(qdev, HW, ERR,
3439 "Failed to set all-multi mode.\n");
3440 } else {
3441 set_bit(QL_ALLMULTI, &qdev->flags);
3442 }
3443 }
3444 } else {
3445 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3446 if (ql_set_routing_reg
3447 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3448 QPRINTK(qdev, HW, ERR,
3449 "Failed to clear all-multi mode.\n");
3450 } else {
3451 clear_bit(QL_ALLMULTI, &qdev->flags);
3452 }
3453 }
3454 }
3455
3456 if (ndev->mc_count) {
3457 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3458 i++, mc_ptr = mc_ptr->next)
3459 if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3460 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3461 QPRINTK(qdev, HW, ERR,
3462 "Failed to loadmulticast address.\n");
3463 goto exit;
3464 }
3465 if (ql_set_routing_reg
3466 (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3467 QPRINTK(qdev, HW, ERR,
3468 "Failed to set multicast match mode.\n");
3469 } else {
3470 set_bit(QL_ALLMULTI, &qdev->flags);
3471 }
3472 }
3473exit:
3474 spin_unlock(&qdev->hw_lock);
3475}
3476
3477static int qlge_set_mac_address(struct net_device *ndev, void *p)
3478{
3479 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3480 struct sockaddr *addr = p;
8668ae92 3481 int ret = 0;
c4e84bde
RM		 3482
3483 if (netif_running(ndev))
3484 return -EBUSY;
3485
3486 if (!is_valid_ether_addr(addr->sa_data))
3487 return -EADDRNOTAVAIL;
3488 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3489
3490 spin_lock(&qdev->hw_lock);
3491 if (ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3492 MAC_ADDR_TYPE_CAM_MAC, qdev->func)) {/* Unicast */
3493 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
8668ae92 3494 ret = -1;
c4e84bde
RM		 3495 }
3496 spin_unlock(&qdev->hw_lock);
3497
8668ae92 3498 return ret;
c4e84bde
RM		 3499}
3500
3501static void qlge_tx_timeout(struct net_device *ndev)
3502{
3503 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3504 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
3505}
3506
3507static void ql_asic_reset_work(struct work_struct *work)
3508{
3509 struct ql_adapter *qdev =
3510 container_of(work, struct ql_adapter, asic_reset_work.work);
3511 ql_cycle_adapter(qdev);
3512}
3513
3514static void ql_get_board_info(struct ql_adapter *qdev)
3515{
3516 qdev->func =
3517 (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3518 if (qdev->func) {
3519 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3520 qdev->port_link_up = STS_PL1;
3521 qdev->port_init = STS_PI1;
3522 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3523 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3524 } else {
3525 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3526 qdev->port_link_up = STS_PL0;
3527 qdev->port_init = STS_PI0;
3528 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3529 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3530 }
3531 qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3532}
3533
3534static void ql_release_all(struct pci_dev *pdev)
3535{
3536 struct net_device *ndev = pci_get_drvdata(pdev);
3537 struct ql_adapter *qdev = netdev_priv(ndev);
3538
3539 if (qdev->workqueue) {
3540 destroy_workqueue(qdev->workqueue);
3541 qdev->workqueue = NULL;
3542 }
3543 if (qdev->q_workqueue) {
3544 destroy_workqueue(qdev->q_workqueue);
3545 qdev->q_workqueue = NULL;
3546 }
3547 if (qdev->reg_base)
8668ae92 3548 iounmap(qdev->reg_base);
c4e84bde
RM		 3549 if (qdev->doorbell_area)
3550 iounmap(qdev->doorbell_area);
3551 pci_release_regions(pdev);
3552 pci_set_drvdata(pdev, NULL);
3553}
3554
3555static int __devinit ql_init_device(struct pci_dev *pdev,
3556 struct net_device *ndev, int cards_found)
3557{
3558 struct ql_adapter *qdev = netdev_priv(ndev);
3559 int pos, err = 0;
3560 u16 val16;
3561
3562 memset((void *)qdev, 0, sizeof(qdev));
3563 err = pci_enable_device(pdev);
3564 if (err) {
3565 dev_err(&pdev->dev, "PCI device enable failed.\n");
3566 return err;
3567 }
3568
3569 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3570 if (pos <= 0) {
3571 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3572 "aborting.\n");
3573 goto err_out;
3574 } else {
3575 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3576 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3577 val16 |= (PCI_EXP_DEVCTL_CERE |
3578 PCI_EXP_DEVCTL_NFERE |
3579 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3580 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3581 }
3582
3583 err = pci_request_regions(pdev, DRV_NAME);
3584 if (err) {
3585 dev_err(&pdev->dev, "PCI region request failed.\n");
3586 goto err_out;
3587 }
3588
3589 pci_set_master(pdev);
3590 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3591 set_bit(QL_DMA64, &qdev->flags);
3592 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3593 } else {
3594 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3595 if (!err)
3596 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3597 }
3598
3599 if (err) {
3600 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3601 goto err_out;
3602 }
3603
3604 pci_set_drvdata(pdev, ndev);
3605 qdev->reg_base =
3606 ioremap_nocache(pci_resource_start(pdev, 1),
3607 pci_resource_len(pdev, 1));
3608 if (!qdev->reg_base) {
3609 dev_err(&pdev->dev, "Register mapping failed.\n");
3610 err = -ENOMEM;
3611 goto err_out;
3612 }
3613
3614 qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3615 qdev->doorbell_area =
3616 ioremap_nocache(pci_resource_start(pdev, 3),
3617 pci_resource_len(pdev, 3));
3618 if (!qdev->doorbell_area) {
3619 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3620 err = -ENOMEM;
3621 goto err_out;
3622 }
3623
3624 ql_get_board_info(qdev);
3625 qdev->ndev = ndev;
3626 qdev->pdev = pdev;
3627 qdev->msg_enable = netif_msg_init(debug, default_msg);
3628 spin_lock_init(&qdev->hw_lock);
3629 spin_lock_init(&qdev->stats_lock);
3630
3631 /* make sure the EEPROM is good */
3632 err = ql_get_flash_params(qdev);
3633 if (err) {
3634 dev_err(&pdev->dev, "Invalid FLASH.\n");
3635 goto err_out;
3636 }
3637
3638 if (!is_valid_ether_addr(qdev->flash.mac_addr))
3639 goto err_out;
3640
3641 memcpy(ndev->dev_addr, qdev->flash.mac_addr, ndev->addr_len);
3642 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3643
3644 /* Set up the default ring sizes. */
3645 qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3646 qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3647
3648 /* Set up the coalescing parameters. */
3649 qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3650 qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3651 qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3652 qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3653
3654 /*
3655 * Set up the operating parameters.
3656 */
3657 qdev->rx_csum = 1;
3658
3659 qdev->q_workqueue = create_workqueue(ndev->name);
3660 qdev->workqueue = create_singlethread_workqueue(ndev->name);
3661 INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3662 INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3663 INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3664
3665 if (!cards_found) {
3666 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3667 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3668 DRV_NAME, DRV_VERSION);
3669 }
3670 return 0;
3671err_out:
3672 ql_release_all(pdev);
3673 pci_disable_device(pdev);
3674 return err;
3675}
3676
25ed7849
SH		 3677
3678static const struct net_device_ops qlge_netdev_ops = {
3679 .ndo_open = qlge_open,
3680 .ndo_stop = qlge_close,
3681 .ndo_start_xmit = qlge_send,
3682 .ndo_change_mtu = qlge_change_mtu,
3683 .ndo_get_stats = qlge_get_stats,
3684 .ndo_set_multicast_list = qlge_set_multicast_list,
3685 .ndo_set_mac_address = qlge_set_mac_address,
3686 .ndo_validate_addr = eth_validate_addr,
3687 .ndo_tx_timeout = qlge_tx_timeout,
3688 .ndo_vlan_rx_register = ql_vlan_rx_register,
3689 .ndo_vlan_rx_add_vid = ql_vlan_rx_add_vid,
3690 .ndo_vlan_rx_kill_vid = ql_vlan_rx_kill_vid,
3691};
3692
c4e84bde
RM		 3693static int __devinit qlge_probe(struct pci_dev *pdev,
3694 const struct pci_device_id *pci_entry)
3695{
3696 struct net_device *ndev = NULL;
3697 struct ql_adapter *qdev = NULL;
3698 static int cards_found = 0;
3699 int err = 0;
3700
3701 ndev = alloc_etherdev(sizeof(struct ql_adapter));
3702 if (!ndev)
3703 return -ENOMEM;
3704
3705 err = ql_init_device(pdev, ndev, cards_found);
3706 if (err < 0) {
3707 free_netdev(ndev);
3708 return err;
3709 }
3710
3711 qdev = netdev_priv(ndev);
3712 SET_NETDEV_DEV(ndev, &pdev->dev);
3713 ndev->features = (0
3714 | NETIF_F_IP_CSUM
3715 | NETIF_F_SG
3716 | NETIF_F_TSO
3717 | NETIF_F_TSO6
3718 | NETIF_F_TSO_ECN
3719 | NETIF_F_HW_VLAN_TX
3720 | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3721
3722 if (test_bit(QL_DMA64, &qdev->flags))
3723 ndev->features |= NETIF_F_HIGHDMA;
3724
3725 /*
3726 * Set up net_device structure.
3727 */
3728 ndev->tx_queue_len = qdev->tx_ring_size;
3729 ndev->irq = pdev->irq;
25ed7849
SH		 3730
3731 ndev->netdev_ops = &qlge_netdev_ops;
c4e84bde 3732 SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
c4e84bde 3733 ndev->watchdog_timeo = 10 * HZ;
25ed7849 3734
c4e84bde
RM		 3735 err = register_netdev(ndev);
3736 if (err) {
3737 dev_err(&pdev->dev, "net device registration failed.\n");
3738 ql_release_all(pdev);
3739 pci_disable_device(pdev);
3740 return err;
3741 }
3742 netif_carrier_off(ndev);
3743 netif_stop_queue(ndev);
3744 ql_display_dev_info(ndev);
3745 cards_found++;
3746 return 0;
3747}
3748
3749static void __devexit qlge_remove(struct pci_dev *pdev)
3750{
3751 struct net_device *ndev = pci_get_drvdata(pdev);
3752 unregister_netdev(ndev);
3753 ql_release_all(pdev);
3754 pci_disable_device(pdev);
3755 free_netdev(ndev);
3756}
3757
3758/*
3759 * This callback is called by the PCI subsystem whenever
3760 * a PCI bus error is detected.
3761 */
3762static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3763 enum pci_channel_state state)
3764{
3765 struct net_device *ndev = pci_get_drvdata(pdev);
3766 struct ql_adapter *qdev = netdev_priv(ndev);
3767
3768 if (netif_running(ndev))
3769 ql_adapter_down(qdev);
3770
3771 pci_disable_device(pdev);
3772
3773 /* Request a slot reset. */
3774 return PCI_ERS_RESULT_NEED_RESET;
3775}
3776
3777/*
3778 * This callback is called after the PCI buss has been reset.
3779 * Basically, this tries to restart the card from scratch.
3780 * This is a shortened version of the device probe/discovery code,
3781 * it resembles the first-half of the () routine.
3782 */
3783static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3784{
3785 struct net_device *ndev = pci_get_drvdata(pdev);
3786 struct ql_adapter *qdev = netdev_priv(ndev);
3787
3788 if (pci_enable_device(pdev)) {
3789 QPRINTK(qdev, IFUP, ERR,
3790 "Cannot re-enable PCI device after reset.\n");
3791 return PCI_ERS_RESULT_DISCONNECT;
3792 }
3793
3794 pci_set_master(pdev);
3795
3796 netif_carrier_off(ndev);
3797 netif_stop_queue(ndev);
3798 ql_adapter_reset(qdev);
3799
3800 /* Make sure the EEPROM is good */
3801 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3802
3803 if (!is_valid_ether_addr(ndev->perm_addr)) {
3804 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3805 return PCI_ERS_RESULT_DISCONNECT;
3806 }
3807
3808 return PCI_ERS_RESULT_RECOVERED;
3809}
3810
3811static void qlge_io_resume(struct pci_dev *pdev)
3812{
3813 struct net_device *ndev = pci_get_drvdata(pdev);
3814 struct ql_adapter *qdev = netdev_priv(ndev);
3815
3816 pci_set_master(pdev);
3817
3818 if (netif_running(ndev)) {
3819 if (ql_adapter_up(qdev)) {
3820 QPRINTK(qdev, IFUP, ERR,
3821 "Device initialization failed after reset.\n");
3822 return;
3823 }
3824 }
3825
3826 netif_device_attach(ndev);
3827}
3828
3829static struct pci_error_handlers qlge_err_handler = {
3830 .error_detected = qlge_io_error_detected,
3831 .slot_reset = qlge_io_slot_reset,
3832 .resume = qlge_io_resume,
3833};
3834
3835static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3836{
3837 struct net_device *ndev = pci_get_drvdata(pdev);
3838 struct ql_adapter *qdev = netdev_priv(ndev);
0047e5d2 3839 int err, i;
c4e84bde
RM		 3840
3841 netif_device_detach(ndev);
3842
3843 if (netif_running(ndev)) {
3844 err = ql_adapter_down(qdev);
3845 if (!err)
3846 return err;
3847 }
3848
0047e5d2
RM		 3849 for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
3850 netif_napi_del(&qdev->rx_ring[i].napi);
3851
c4e84bde
RM		 3852 err = pci_save_state(pdev);
3853 if (err)
3854 return err;
3855
3856 pci_disable_device(pdev);
3857
3858 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3859
3860 return 0;
3861}
3862
04da2cf9 3863#ifdef CONFIG_PM
c4e84bde
RM		 3864static int qlge_resume(struct pci_dev *pdev)
3865{
3866 struct net_device *ndev = pci_get_drvdata(pdev);
3867 struct ql_adapter *qdev = netdev_priv(ndev);
3868 int err;
3869
3870 pci_set_power_state(pdev, PCI_D0);
3871 pci_restore_state(pdev);
3872 err = pci_enable_device(pdev);
3873 if (err) {
3874 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
3875 return err;
3876 }
3877 pci_set_master(pdev);
3878
3879 pci_enable_wake(pdev, PCI_D3hot, 0);
3880 pci_enable_wake(pdev, PCI_D3cold, 0);
3881
3882 if (netif_running(ndev)) {
3883 err = ql_adapter_up(qdev);
3884 if (err)
3885 return err;
3886 }
3887
3888 netif_device_attach(ndev);
3889
3890 return 0;
3891}
04da2cf9 3892#endif /* CONFIG_PM */
c4e84bde
RM		 3893
3894static void qlge_shutdown(struct pci_dev *pdev)
3895{
3896 qlge_suspend(pdev, PMSG_SUSPEND);
3897}
3898
3899static struct pci_driver qlge_driver = {
3900 .name = DRV_NAME,
3901 .id_table = qlge_pci_tbl,
3902 .probe = qlge_probe,
3903 .remove = __devexit_p(qlge_remove),
3904#ifdef CONFIG_PM
3905 .suspend = qlge_suspend,
3906 .resume = qlge_resume,
3907#endif
3908 .shutdown = qlge_shutdown,
3909 .err_handler = &qlge_err_handler
3910};
3911
3912static int __init qlge_init_module(void)
3913{
3914 return pci_register_driver(&qlge_driver);
3915}
3916
3917static void __exit qlge_exit(void)
3918{
3919 pci_unregister_driver(&qlge_driver);
3920}
3921
3922module_init(qlge_init_module);
3923module_exit(qlge_exit);
Linux kernel - Deliverables
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