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qlge: bugfix: Add missing pci_mapping_err checking.
[deliverable/linux.git] / drivers / net / qlge / qlge_main.c
CommitLineData
c4e84bde
RM		 1/*
2 * QLogic qlge NIC HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 * See LICENSE.qlge for copyright and licensing details.
5 * Author: Linux qlge network device driver by
6 * Ron Mercer <ron.mercer@qlogic.com>
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/list.h>
13#include <linux/pci.h>
14#include <linux/dma-mapping.h>
15#include <linux/pagemap.h>
16#include <linux/sched.h>
17#include <linux/slab.h>
18#include <linux/dmapool.h>
19#include <linux/mempool.h>
20#include <linux/spinlock.h>
21#include <linux/kthread.h>
22#include <linux/interrupt.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/in.h>
26#include <linux/ip.h>
27#include <linux/ipv6.h>
28#include <net/ipv6.h>
29#include <linux/tcp.h>
30#include <linux/udp.h>
31#include <linux/if_arp.h>
32#include <linux/if_ether.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/skbuff.h>
37#include <linux/rtnetlink.h>
38#include <linux/if_vlan.h>
c4e84bde
RM		 39#include <linux/delay.h>
40#include <linux/mm.h>
41#include <linux/vmalloc.h>
b7c6bfb7 42#include <net/ip6_checksum.h>
c4e84bde
RM		 43
44#include "qlge.h"
45
46char qlge_driver_name[] = DRV_NAME;
47const char qlge_driver_version[] = DRV_VERSION;
48
49MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50MODULE_DESCRIPTION(DRV_STRING " ");
51MODULE_LICENSE("GPL");
52MODULE_VERSION(DRV_VERSION);
53
54static const u32 default_msg =
55 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
56/* NETIF_MSG_TIMER | */
57 NETIF_MSG_IFDOWN |
58 NETIF_MSG_IFUP |
59 NETIF_MSG_RX_ERR |
60 NETIF_MSG_TX_ERR |
61 NETIF_MSG_TX_QUEUED |
62 NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS |
63/* NETIF_MSG_PKTDATA | */
64 NETIF_MSG_HW | NETIF_MSG_WOL | 0;
65
66static int debug = 0x00007fff; /* defaults above */
67module_param(debug, int, 0);
68MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
69
70#define MSIX_IRQ 0
71#define MSI_IRQ 1
72#define LEG_IRQ 2
73static int irq_type = MSIX_IRQ;
74module_param(irq_type, int, MSIX_IRQ);
75MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
76
77static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
78 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID)},
79 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID1)},
80 /* required last entry */
81 {0,}
82};
83
84MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
85
86/* This hardware semaphore causes exclusive access to
87 * resources shared between the NIC driver, MPI firmware,
88 * FCOE firmware and the FC driver.
89 */
90static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
91{
92 u32 sem_bits = 0;
93
94 switch (sem_mask) {
95 case SEM_XGMAC0_MASK:
96 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
97 break;
98 case SEM_XGMAC1_MASK:
99 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
100 break;
101 case SEM_ICB_MASK:
102 sem_bits = SEM_SET << SEM_ICB_SHIFT;
103 break;
104 case SEM_MAC_ADDR_MASK:
105 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
106 break;
107 case SEM_FLASH_MASK:
108 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
109 break;
110 case SEM_PROBE_MASK:
111 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
112 break;
113 case SEM_RT_IDX_MASK:
114 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
115 break;
116 case SEM_PROC_REG_MASK:
117 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
118 break;
119 default:
120 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
121 return -EINVAL;
122 }
123
124 ql_write32(qdev, SEM, sem_bits | sem_mask);
125 return !(ql_read32(qdev, SEM) & sem_bits);
126}
127
128int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
129{
130 unsigned int seconds = 3;
131 do {
132 if (!ql_sem_trylock(qdev, sem_mask))
133 return 0;
134 ssleep(1);
135 } while (--seconds);
136 return -ETIMEDOUT;
137}
138
139void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
140{
141 ql_write32(qdev, SEM, sem_mask);
142 ql_read32(qdev, SEM); /* flush */
143}
144
145/* This function waits for a specific bit to come ready
146 * in a given register. It is used mostly by the initialize
147 * process, but is also used in kernel thread API such as
148 * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
149 */
150int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
151{
152 u32 temp;
153 int count = UDELAY_COUNT;
154
155 while (count) {
156 temp = ql_read32(qdev, reg);
157
158 /* check for errors */
159 if (temp & err_bit) {
160 QPRINTK(qdev, PROBE, ALERT,
161 "register 0x%.08x access error, value = 0x%.08x!.\n",
162 reg, temp);
163 return -EIO;
164 } else if (temp & bit)
165 return 0;
166 udelay(UDELAY_DELAY);
167 count--;
168 }
169 QPRINTK(qdev, PROBE, ALERT,
170 "Timed out waiting for reg %x to come ready.\n", reg);
171 return -ETIMEDOUT;
172}
173
174/* The CFG register is used to download TX and RX control blocks
175 * to the chip. This function waits for an operation to complete.
176 */
177static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
178{
179 int count = UDELAY_COUNT;
180 u32 temp;
181
182 while (count) {
183 temp = ql_read32(qdev, CFG);
184 if (temp & CFG_LE)
185 return -EIO;
186 if (!(temp & bit))
187 return 0;
188 udelay(UDELAY_DELAY);
189 count--;
190 }
191 return -ETIMEDOUT;
192}
193
194
195/* Used to issue init control blocks to hw. Maps control block,
196 * sets address, triggers download, waits for completion.
197 */
198int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
199 u16 q_id)
200{
201 u64 map;
202 int status = 0;
203 int direction;
204 u32 mask;
205 u32 value;
206
207 direction =
208 (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
209 PCI_DMA_FROMDEVICE;
210
211 map = pci_map_single(qdev->pdev, ptr, size, direction);
212 if (pci_dma_mapping_error(qdev->pdev, map)) {
213 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
214 return -ENOMEM;
215 }
216
217 status = ql_wait_cfg(qdev, bit);
218 if (status) {
219 QPRINTK(qdev, IFUP, ERR,
220 "Timed out waiting for CFG to come ready.\n");
221 goto exit;
222 }
223
224 status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
225 if (status)
226 goto exit;
227 ql_write32(qdev, ICB_L, (u32) map);
228 ql_write32(qdev, ICB_H, (u32) (map >> 32));
229 ql_sem_unlock(qdev, SEM_ICB_MASK); /* does flush too */
230
231 mask = CFG_Q_MASK | (bit << 16);
232 value = bit | (q_id << CFG_Q_SHIFT);
233 ql_write32(qdev, CFG, (mask | value));
234
235 /*
236 * Wait for the bit to clear after signaling hw.
237 */
238 status = ql_wait_cfg(qdev, bit);
239exit:
240 pci_unmap_single(qdev->pdev, map, size, direction);
241 return status;
242}
243
244/* Get a specific MAC address from the CAM. Used for debug and reg dump. */
245int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
246 u32 *value)
247{
248 u32 offset = 0;
249 int status;
250
251 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
252 if (status)
253 return status;
254 switch (type) {
255 case MAC_ADDR_TYPE_MULTI_MAC:
256 case MAC_ADDR_TYPE_CAM_MAC:
257 {
258 status =
259 ql_wait_reg_rdy(qdev,
260 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
261 if (status)
262 goto exit;
263 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
264 (index << MAC_ADDR_IDX_SHIFT) | /* index */
265 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
266 status =
267 ql_wait_reg_rdy(qdev,
268 MAC_ADDR_IDX, MAC_ADDR_MR, MAC_ADDR_E);
269 if (status)
270 goto exit;
271 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
272 status =
273 ql_wait_reg_rdy(qdev,
274 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
275 if (status)
276 goto exit;
277 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
278 (index << MAC_ADDR_IDX_SHIFT) | /* index */
279 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
280 status =
281 ql_wait_reg_rdy(qdev,
282 MAC_ADDR_IDX, MAC_ADDR_MR, MAC_ADDR_E);
283 if (status)
284 goto exit;
285 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
286 if (type == MAC_ADDR_TYPE_CAM_MAC) {
287 status =
288 ql_wait_reg_rdy(qdev,
289 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
290 if (status)
291 goto exit;
292 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
293 (index << MAC_ADDR_IDX_SHIFT) | /* index */
294 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
295 status =
296 ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
297 MAC_ADDR_MR, MAC_ADDR_E);
298 if (status)
299 goto exit;
300 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
301 }
302 break;
303 }
304 case MAC_ADDR_TYPE_VLAN:
305 case MAC_ADDR_TYPE_MULTI_FLTR:
306 default:
307 QPRINTK(qdev, IFUP, CRIT,
308 "Address type %d not yet supported.\n", type);
309 status = -EPERM;
310 }
311exit:
312 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
313 return status;
314}
315
316/* Set up a MAC, multicast or VLAN address for the
317 * inbound frame matching.
318 */
319static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
320 u16 index)
321{
322 u32 offset = 0;
323 int status = 0;
324
325 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
326 if (status)
327 return status;
328 switch (type) {
329 case MAC_ADDR_TYPE_MULTI_MAC:
330 case MAC_ADDR_TYPE_CAM_MAC:
331 {
332 u32 cam_output;
333 u32 upper = (addr[0] << 8) | addr[1];
334 u32 lower =
335 (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
336 (addr[5]);
337
338 QPRINTK(qdev, IFUP, INFO,
7c510e4b 339 "Adding %s address %pM"
c4e84bde
RM		 340 " at index %d in the CAM.\n",
341 ((type ==
342 MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
7c510e4b 343 "UNICAST"), addr, index);
c4e84bde
RM		 344
345 status =
346 ql_wait_reg_rdy(qdev,
347 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
348 if (status)
349 goto exit;
350 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
351 (index << MAC_ADDR_IDX_SHIFT) | /* index */
352 type); /* type */
353 ql_write32(qdev, MAC_ADDR_DATA, lower);
354 status =
355 ql_wait_reg_rdy(qdev,
356 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
357 if (status)
358 goto exit;
359 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
360 (index << MAC_ADDR_IDX_SHIFT) | /* index */
361 type); /* type */
362 ql_write32(qdev, MAC_ADDR_DATA, upper);
363 status =
364 ql_wait_reg_rdy(qdev,
365 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
366 if (status)
367 goto exit;
368 ql_write32(qdev, MAC_ADDR_IDX, (offset) | /* offset */
369 (index << MAC_ADDR_IDX_SHIFT) | /* index */
370 type); /* type */
371 /* This field should also include the queue id
372 and possibly the function id. Right now we hardcode
373 the route field to NIC core.
374 */
375 if (type == MAC_ADDR_TYPE_CAM_MAC) {
376 cam_output = (CAM_OUT_ROUTE_NIC |
377 (qdev->
378 func << CAM_OUT_FUNC_SHIFT) |
379 (qdev->
380 rss_ring_first_cq_id <<
381 CAM_OUT_CQ_ID_SHIFT));
382 if (qdev->vlgrp)
383 cam_output |= CAM_OUT_RV;
384 /* route to NIC core */
385 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
386 }
387 break;
388 }
389 case MAC_ADDR_TYPE_VLAN:
390 {
391 u32 enable_bit = *((u32 *) &addr[0]);
392 /* For VLAN, the addr actually holds a bit that
393 * either enables or disables the vlan id we are
394 * addressing. It's either MAC_ADDR_E on or off.
395 * That's bit-27 we're talking about.
396 */
397 QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
398 (enable_bit ? "Adding" : "Removing"),
399 index, (enable_bit ? "to" : "from"));
400
401 status =
402 ql_wait_reg_rdy(qdev,
403 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
404 if (status)
405 goto exit;
406 ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
407 (index << MAC_ADDR_IDX_SHIFT) | /* index */
408 type | /* type */
409 enable_bit); /* enable/disable */
410 break;
411 }
412 case MAC_ADDR_TYPE_MULTI_FLTR:
413 default:
414 QPRINTK(qdev, IFUP, CRIT,
415 "Address type %d not yet supported.\n", type);
416 status = -EPERM;
417 }
418exit:
419 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
420 return status;
421}
422
423/* Get a specific frame routing value from the CAM.
424 * Used for debug and reg dump.
425 */
426int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
427{
428 int status = 0;
429
430 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
431 if (status)
432 goto exit;
433
434 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, RT_IDX_E);
435 if (status)
436 goto exit;
437
438 ql_write32(qdev, RT_IDX,
439 RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
440 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, RT_IDX_E);
441 if (status)
442 goto exit;
443 *value = ql_read32(qdev, RT_DATA);
444exit:
445 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
446 return status;
447}
448
449/* The NIC function for this chip has 16 routing indexes. Each one can be used
450 * to route different frame types to various inbound queues. We send broadcast/
451 * multicast/error frames to the default queue for slow handling,
452 * and CAM hit/RSS frames to the fast handling queues.
453 */
454static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
455 int enable)
456{
457 int status;
458 u32 value = 0;
459
460 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
461 if (status)
462 return status;
463
464 QPRINTK(qdev, IFUP, DEBUG,
465 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
466 (enable ? "Adding" : "Removing"),
467 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
468 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
469 ((index ==
470 RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
471 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
472 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
473 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
474 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
475 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
476 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
477 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
478 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
479 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
480 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
481 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
482 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
483 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
484 (enable ? "to" : "from"));
485
486 switch (mask) {
487 case RT_IDX_CAM_HIT:
488 {
489 value = RT_IDX_DST_CAM_Q | /* dest */
490 RT_IDX_TYPE_NICQ | /* type */
491 (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
492 break;
493 }
494 case RT_IDX_VALID: /* Promiscuous Mode frames. */
495 {
496 value = RT_IDX_DST_DFLT_Q | /* dest */
497 RT_IDX_TYPE_NICQ | /* type */
498 (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
499 break;
500 }
501 case RT_IDX_ERR: /* Pass up MAC,IP,TCP/UDP error frames. */
502 {
503 value = RT_IDX_DST_DFLT_Q | /* dest */
504 RT_IDX_TYPE_NICQ | /* type */
505 (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
506 break;
507 }
508 case RT_IDX_BCAST: /* Pass up Broadcast frames to default Q. */
509 {
510 value = RT_IDX_DST_DFLT_Q | /* dest */
511 RT_IDX_TYPE_NICQ | /* type */
512 (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
513 break;
514 }
515 case RT_IDX_MCAST: /* Pass up All Multicast frames. */
516 {
517 value = RT_IDX_DST_CAM_Q | /* dest */
518 RT_IDX_TYPE_NICQ | /* type */
519 (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
520 break;
521 }
522 case RT_IDX_MCAST_MATCH: /* Pass up matched Multicast frames. */
523 {
524 value = RT_IDX_DST_CAM_Q | /* dest */
525 RT_IDX_TYPE_NICQ | /* type */
526 (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
527 break;
528 }
529 case RT_IDX_RSS_MATCH: /* Pass up matched RSS frames. */
530 {
531 value = RT_IDX_DST_RSS | /* dest */
532 RT_IDX_TYPE_NICQ | /* type */
533 (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
534 break;
535 }
536 case 0: /* Clear the E-bit on an entry. */
537 {
538 value = RT_IDX_DST_DFLT_Q | /* dest */
539 RT_IDX_TYPE_NICQ | /* type */
540 (index << RT_IDX_IDX_SHIFT);/* index */
541 break;
542 }
543 default:
544 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
545 mask);
546 status = -EPERM;
547 goto exit;
548 }
549
550 if (value) {
551 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
552 if (status)
553 goto exit;
554 value |= (enable ? RT_IDX_E : 0);
555 ql_write32(qdev, RT_IDX, value);
556 ql_write32(qdev, RT_DATA, enable ? mask : 0);
557 }
558exit:
559 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
560 return status;
561}
562
563static void ql_enable_interrupts(struct ql_adapter *qdev)
564{
565 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
566}
567
568static void ql_disable_interrupts(struct ql_adapter *qdev)
569{
570 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
571}
572
573/* If we're running with multiple MSI-X vectors then we enable on the fly.
574 * Otherwise, we may have multiple outstanding workers and don't want to
575 * enable until the last one finishes. In this case, the irq_cnt gets
576 * incremented everytime we queue a worker and decremented everytime
577 * a worker finishes. Once it hits zero we enable the interrupt.
578 */
bb0d215c 579u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
c4e84bde 580{
bb0d215c
RM		 581 u32 var = 0;
582 unsigned long hw_flags = 0;
583 struct intr_context *ctx = qdev->intr_context + intr;
584
585 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
586 /* Always enable if we're MSIX multi interrupts and
587 * it's not the default (zeroeth) interrupt.
588 */
c4e84bde 589 ql_write32(qdev, INTR_EN,
bb0d215c
RM		 590 ctx->intr_en_mask);
591 var = ql_read32(qdev, STS);
592 return var;
c4e84bde 593 }
bb0d215c
RM		 594
595 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
596 if (atomic_dec_and_test(&ctx->irq_cnt)) {
597 ql_write32(qdev, INTR_EN,
598 ctx->intr_en_mask);
599 var = ql_read32(qdev, STS);
600 }
601 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
602 return var;
c4e84bde
RM		 603}
604
605static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
606{
607 u32 var = 0;
bb0d215c
RM		 608 unsigned long hw_flags;
609 struct intr_context *ctx;
c4e84bde 610
bb0d215c
RM		 611 /* HW disables for us if we're MSIX multi interrupts and
612 * it's not the default (zeroeth) interrupt.
613 */
614 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
615 return 0;
616
617 ctx = qdev->intr_context + intr;
618 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
619 if (!atomic_read(&ctx->irq_cnt)) {
c4e84bde 620 ql_write32(qdev, INTR_EN,
bb0d215c 621 ctx->intr_dis_mask);
c4e84bde
RM		 622 var = ql_read32(qdev, STS);
623 }
bb0d215c
RM		 624 atomic_inc(&ctx->irq_cnt);
625 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
c4e84bde
RM		 626 return var;
627}
628
629static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
630{
631 int i;
632 for (i = 0; i < qdev->intr_count; i++) {
633 /* The enable call does a atomic_dec_and_test
634 * and enables only if the result is zero.
635 * So we precharge it here.
636 */
bb0d215c
RM		 637 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
638 i == 0))
639 atomic_set(&qdev->intr_context[i].irq_cnt, 1);
c4e84bde
RM		 640 ql_enable_completion_interrupt(qdev, i);
641 }
642
643}
644
8668ae92 645static int ql_read_flash_word(struct ql_adapter *qdev, int offset, u32 *data)
c4e84bde
RM		 646{
647 int status = 0;
648 /* wait for reg to come ready */
649 status = ql_wait_reg_rdy(qdev,
650 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
651 if (status)
652 goto exit;
653 /* set up for reg read */
654 ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
655 /* wait for reg to come ready */
656 status = ql_wait_reg_rdy(qdev,
657 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
658 if (status)
659 goto exit;
660 /* get the data */
661 *data = ql_read32(qdev, FLASH_DATA);
662exit:
663 return status;
664}
665
666static int ql_get_flash_params(struct ql_adapter *qdev)
667{
668 int i;
669 int status;
670 u32 *p = (u32 *)&qdev->flash;
671
672 if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
673 return -ETIMEDOUT;
674
675 for (i = 0; i < sizeof(qdev->flash) / sizeof(u32); i++, p++) {
676 status = ql_read_flash_word(qdev, i, p);
677 if (status) {
678 QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
679 goto exit;
680 }
681
682 }
683exit:
684 ql_sem_unlock(qdev, SEM_FLASH_MASK);
685 return status;
686}
687
688/* xgmac register are located behind the xgmac_addr and xgmac_data
689 * register pair. Each read/write requires us to wait for the ready
690 * bit before reading/writing the data.
691 */
692static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
693{
694 int status;
695 /* wait for reg to come ready */
696 status = ql_wait_reg_rdy(qdev,
697 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
698 if (status)
699 return status;
700 /* write the data to the data reg */
701 ql_write32(qdev, XGMAC_DATA, data);
702 /* trigger the write */
703 ql_write32(qdev, XGMAC_ADDR, reg);
704 return status;
705}
706
707/* xgmac register are located behind the xgmac_addr and xgmac_data
708 * register pair. Each read/write requires us to wait for the ready
709 * bit before reading/writing the data.
710 */
711int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
712{
713 int status = 0;
714 /* wait for reg to come ready */
715 status = ql_wait_reg_rdy(qdev,
716 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
717 if (status)
718 goto exit;
719 /* set up for reg read */
720 ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
721 /* wait for reg to come ready */
722 status = ql_wait_reg_rdy(qdev,
723 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
724 if (status)
725 goto exit;
726 /* get the data */
727 *data = ql_read32(qdev, XGMAC_DATA);
728exit:
729 return status;
730}
731
732/* This is used for reading the 64-bit statistics regs. */
733int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
734{
735 int status = 0;
736 u32 hi = 0;
737 u32 lo = 0;
738
739 status = ql_read_xgmac_reg(qdev, reg, &lo);
740 if (status)
741 goto exit;
742
743 status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
744 if (status)
745 goto exit;
746
747 *data = (u64) lo | ((u64) hi << 32);
748
749exit:
750 return status;
751}
752
753/* Take the MAC Core out of reset.
754 * Enable statistics counting.
755 * Take the transmitter/receiver out of reset.
756 * This functionality may be done in the MPI firmware at a
757 * later date.
758 */
759static int ql_port_initialize(struct ql_adapter *qdev)
760{
761 int status = 0;
762 u32 data;
763
764 if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
765 /* Another function has the semaphore, so
766 * wait for the port init bit to come ready.
767 */
768 QPRINTK(qdev, LINK, INFO,
769 "Another function has the semaphore, so wait for the port init bit to come ready.\n");
770 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
771 if (status) {
772 QPRINTK(qdev, LINK, CRIT,
773 "Port initialize timed out.\n");
774 }
775 return status;
776 }
777
778 QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
779 /* Set the core reset. */
780 status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
781 if (status)
782 goto end;
783 data |= GLOBAL_CFG_RESET;
784 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
785 if (status)
786 goto end;
787
788 /* Clear the core reset and turn on jumbo for receiver. */
789 data &= ~GLOBAL_CFG_RESET; /* Clear core reset. */
790 data |= GLOBAL_CFG_JUMBO; /* Turn on jumbo. */
791 data |= GLOBAL_CFG_TX_STAT_EN;
792 data |= GLOBAL_CFG_RX_STAT_EN;
793 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
794 if (status)
795 goto end;
796
797 /* Enable transmitter, and clear it's reset. */
798 status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
799 if (status)
800 goto end;
801 data &= ~TX_CFG_RESET; /* Clear the TX MAC reset. */
802 data |= TX_CFG_EN; /* Enable the transmitter. */
803 status = ql_write_xgmac_reg(qdev, TX_CFG, data);
804 if (status)
805 goto end;
806
807 /* Enable receiver and clear it's reset. */
808 status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
809 if (status)
810 goto end;
811 data &= ~RX_CFG_RESET; /* Clear the RX MAC reset. */
812 data |= RX_CFG_EN; /* Enable the receiver. */
813 status = ql_write_xgmac_reg(qdev, RX_CFG, data);
814 if (status)
815 goto end;
816
817 /* Turn on jumbo. */
818 status =
819 ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
820 if (status)
821 goto end;
822 status =
823 ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
824 if (status)
825 goto end;
826
827 /* Signal to the world that the port is enabled. */
828 ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
829end:
830 ql_sem_unlock(qdev, qdev->xg_sem_mask);
831 return status;
832}
833
834/* Get the next large buffer. */
8668ae92 835static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
c4e84bde
RM		 836{
837 struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
838 rx_ring->lbq_curr_idx++;
839 if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
840 rx_ring->lbq_curr_idx = 0;
841 rx_ring->lbq_free_cnt++;
842 return lbq_desc;
843}
844
845/* Get the next small buffer. */
8668ae92 846static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
c4e84bde
RM		 847{
848 struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
849 rx_ring->sbq_curr_idx++;
850 if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
851 rx_ring->sbq_curr_idx = 0;
852 rx_ring->sbq_free_cnt++;
853 return sbq_desc;
854}
855
856/* Update an rx ring index. */
857static void ql_update_cq(struct rx_ring *rx_ring)
858{
859 rx_ring->cnsmr_idx++;
860 rx_ring->curr_entry++;
861 if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
862 rx_ring->cnsmr_idx = 0;
863 rx_ring->curr_entry = rx_ring->cq_base;
864 }
865}
866
867static void ql_write_cq_idx(struct rx_ring *rx_ring)
868{
869 ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
870}
871
872/* Process (refill) a large buffer queue. */
873static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
874{
875 int clean_idx = rx_ring->lbq_clean_idx;
876 struct bq_desc *lbq_desc;
877 struct bq_element *bq;
878 u64 map;
879 int i;
880
881 while (rx_ring->lbq_free_cnt > 16) {
882 for (i = 0; i < 16; i++) {
883 QPRINTK(qdev, RX_STATUS, DEBUG,
884 "lbq: try cleaning clean_idx = %d.\n",
885 clean_idx);
886 lbq_desc = &rx_ring->lbq[clean_idx];
887 bq = lbq_desc->bq;
888 if (lbq_desc->p.lbq_page == NULL) {
889 QPRINTK(qdev, RX_STATUS, DEBUG,
890 "lbq: getting new page for index %d.\n",
891 lbq_desc->index);
892 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
893 if (lbq_desc->p.lbq_page == NULL) {
894 QPRINTK(qdev, RX_STATUS, ERR,
895 "Couldn't get a page.\n");
896 return;
897 }
898 map = pci_map_page(qdev->pdev,
899 lbq_desc->p.lbq_page,
900 0, PAGE_SIZE,
901 PCI_DMA_FROMDEVICE);
902 if (pci_dma_mapping_error(qdev->pdev, map)) {
903 QPRINTK(qdev, RX_STATUS, ERR,
904 "PCI mapping failed.\n");
905 return;
906 }
907 pci_unmap_addr_set(lbq_desc, mapaddr, map);
908 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
909 bq->addr_lo = /*lbq_desc->addr_lo = */
910 cpu_to_le32(map);
911 bq->addr_hi = /*lbq_desc->addr_hi = */
912 cpu_to_le32(map >> 32);
913 }
914 clean_idx++;
915 if (clean_idx == rx_ring->lbq_len)
916 clean_idx = 0;
917 }
918
919 rx_ring->lbq_clean_idx = clean_idx;
920 rx_ring->lbq_prod_idx += 16;
921 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
922 rx_ring->lbq_prod_idx = 0;
923 QPRINTK(qdev, RX_STATUS, DEBUG,
924 "lbq: updating prod idx = %d.\n",
925 rx_ring->lbq_prod_idx);
926 ql_write_db_reg(rx_ring->lbq_prod_idx,
927 rx_ring->lbq_prod_idx_db_reg);
928 rx_ring->lbq_free_cnt -= 16;
929 }
930}
931
932/* Process (refill) a small buffer queue. */
933static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
934{
935 int clean_idx = rx_ring->sbq_clean_idx;
936 struct bq_desc *sbq_desc;
937 struct bq_element *bq;
938 u64 map;
939 int i;
940
941 while (rx_ring->sbq_free_cnt > 16) {
942 for (i = 0; i < 16; i++) {
943 sbq_desc = &rx_ring->sbq[clean_idx];
944 QPRINTK(qdev, RX_STATUS, DEBUG,
945 "sbq: try cleaning clean_idx = %d.\n",
946 clean_idx);
947 bq = sbq_desc->bq;
948 if (sbq_desc->p.skb == NULL) {
949 QPRINTK(qdev, RX_STATUS, DEBUG,
950 "sbq: getting new skb for index %d.\n",
951 sbq_desc->index);
952 sbq_desc->p.skb =
953 netdev_alloc_skb(qdev->ndev,
954 rx_ring->sbq_buf_size);
955 if (sbq_desc->p.skb == NULL) {
956 QPRINTK(qdev, PROBE, ERR,
957 "Couldn't get an skb.\n");
958 rx_ring->sbq_clean_idx = clean_idx;
959 return;
960 }
961 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
962 map = pci_map_single(qdev->pdev,
963 sbq_desc->p.skb->data,
964 rx_ring->sbq_buf_size /
965 2, PCI_DMA_FROMDEVICE);
c907a35a
RM		 966 if (pci_dma_mapping_error(qdev->pdev, map)) {
967 QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
968 rx_ring->sbq_clean_idx = clean_idx;
969 return;
970 }
c4e84bde
RM		 971 pci_unmap_addr_set(sbq_desc, mapaddr, map);
972 pci_unmap_len_set(sbq_desc, maplen,
973 rx_ring->sbq_buf_size / 2);
974 bq->addr_lo = cpu_to_le32(map);
975 bq->addr_hi = cpu_to_le32(map >> 32);
976 }
977
978 clean_idx++;
979 if (clean_idx == rx_ring->sbq_len)
980 clean_idx = 0;
981 }
982 rx_ring->sbq_clean_idx = clean_idx;
983 rx_ring->sbq_prod_idx += 16;
984 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
985 rx_ring->sbq_prod_idx = 0;
986 QPRINTK(qdev, RX_STATUS, DEBUG,
987 "sbq: updating prod idx = %d.\n",
988 rx_ring->sbq_prod_idx);
989 ql_write_db_reg(rx_ring->sbq_prod_idx,
990 rx_ring->sbq_prod_idx_db_reg);
991
992 rx_ring->sbq_free_cnt -= 16;
993 }
994}
995
996static void ql_update_buffer_queues(struct ql_adapter *qdev,
997 struct rx_ring *rx_ring)
998{
999 ql_update_sbq(qdev, rx_ring);
1000 ql_update_lbq(qdev, rx_ring);
1001}
1002
1003/* Unmaps tx buffers. Can be called from send() if a pci mapping
1004 * fails at some stage, or from the interrupt when a tx completes.
1005 */
1006static void ql_unmap_send(struct ql_adapter *qdev,
1007 struct tx_ring_desc *tx_ring_desc, int mapped)
1008{
1009 int i;
1010 for (i = 0; i < mapped; i++) {
1011 if (i == 0 || (i == 7 && mapped > 7)) {
1012 /*
1013 * Unmap the skb->data area, or the
1014 * external sglist (AKA the Outbound
1015 * Address List (OAL)).
1016 * If its the zeroeth element, then it's
1017 * the skb->data area. If it's the 7th
1018 * element and there is more than 6 frags,
1019 * then its an OAL.
1020 */
1021 if (i == 7) {
1022 QPRINTK(qdev, TX_DONE, DEBUG,
1023 "unmapping OAL area.\n");
1024 }
1025 pci_unmap_single(qdev->pdev,
1026 pci_unmap_addr(&tx_ring_desc->map[i],
1027 mapaddr),
1028 pci_unmap_len(&tx_ring_desc->map[i],
1029 maplen),
1030 PCI_DMA_TODEVICE);
1031 } else {
1032 QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1033 i);
1034 pci_unmap_page(qdev->pdev,
1035 pci_unmap_addr(&tx_ring_desc->map[i],
1036 mapaddr),
1037 pci_unmap_len(&tx_ring_desc->map[i],
1038 maplen), PCI_DMA_TODEVICE);
1039 }
1040 }
1041
1042}
1043
1044/* Map the buffers for this transmit. This will return
1045 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1046 */
1047static int ql_map_send(struct ql_adapter *qdev,
1048 struct ob_mac_iocb_req *mac_iocb_ptr,
1049 struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1050{
1051 int len = skb_headlen(skb);
1052 dma_addr_t map;
1053 int frag_idx, err, map_idx = 0;
1054 struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1055 int frag_cnt = skb_shinfo(skb)->nr_frags;
1056
1057 if (frag_cnt) {
1058 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1059 }
1060 /*
1061 * Map the skb buffer first.
1062 */
1063 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1064
1065 err = pci_dma_mapping_error(qdev->pdev, map);
1066 if (err) {
1067 QPRINTK(qdev, TX_QUEUED, ERR,
1068 "PCI mapping failed with error: %d\n", err);
1069
1070 return NETDEV_TX_BUSY;
1071 }
1072
1073 tbd->len = cpu_to_le32(len);
1074 tbd->addr = cpu_to_le64(map);
1075 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1076 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1077 map_idx++;
1078
1079 /*
1080 * This loop fills the remainder of the 8 address descriptors
1081 * in the IOCB. If there are more than 7 fragments, then the
1082 * eighth address desc will point to an external list (OAL).
1083 * When this happens, the remainder of the frags will be stored
1084 * in this list.
1085 */
1086 for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1087 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1088 tbd++;
1089 if (frag_idx == 6 && frag_cnt > 7) {
1090 /* Let's tack on an sglist.
1091 * Our control block will now
1092 * look like this:
1093 * iocb->seg[0] = skb->data
1094 * iocb->seg[1] = frag[0]
1095 * iocb->seg[2] = frag[1]
1096 * iocb->seg[3] = frag[2]
1097 * iocb->seg[4] = frag[3]
1098 * iocb->seg[5] = frag[4]
1099 * iocb->seg[6] = frag[5]
1100 * iocb->seg[7] = ptr to OAL (external sglist)
1101 * oal->seg[0] = frag[6]
1102 * oal->seg[1] = frag[7]
1103 * oal->seg[2] = frag[8]
1104 * oal->seg[3] = frag[9]
1105 * oal->seg[4] = frag[10]
1106 * etc...
1107 */
1108 /* Tack on the OAL in the eighth segment of IOCB. */
1109 map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1110 sizeof(struct oal),
1111 PCI_DMA_TODEVICE);
1112 err = pci_dma_mapping_error(qdev->pdev, map);
1113 if (err) {
1114 QPRINTK(qdev, TX_QUEUED, ERR,
1115 "PCI mapping outbound address list with error: %d\n",
1116 err);
1117 goto map_error;
1118 }
1119
1120 tbd->addr = cpu_to_le64(map);
1121 /*
1122 * The length is the number of fragments
1123 * that remain to be mapped times the length
1124 * of our sglist (OAL).
1125 */
1126 tbd->len =
1127 cpu_to_le32((sizeof(struct tx_buf_desc) *
1128 (frag_cnt - frag_idx)) | TX_DESC_C);
1129 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1130 map);
1131 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1132 sizeof(struct oal));
1133 tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1134 map_idx++;
1135 }
1136
1137 map =
1138 pci_map_page(qdev->pdev, frag->page,
1139 frag->page_offset, frag->size,
1140 PCI_DMA_TODEVICE);
1141
1142 err = pci_dma_mapping_error(qdev->pdev, map);
1143 if (err) {
1144 QPRINTK(qdev, TX_QUEUED, ERR,
1145 "PCI mapping frags failed with error: %d.\n",
1146 err);
1147 goto map_error;
1148 }
1149
1150 tbd->addr = cpu_to_le64(map);
1151 tbd->len = cpu_to_le32(frag->size);
1152 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1153 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1154 frag->size);
1155
1156 }
1157 /* Save the number of segments we've mapped. */
1158 tx_ring_desc->map_cnt = map_idx;
1159 /* Terminate the last segment. */
1160 tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1161 return NETDEV_TX_OK;
1162
1163map_error:
1164 /*
1165 * If the first frag mapping failed, then i will be zero.
1166 * This causes the unmap of the skb->data area. Otherwise
1167 * we pass in the number of frags that mapped successfully
1168 * so they can be umapped.
1169 */
1170 ql_unmap_send(qdev, tx_ring_desc, map_idx);
1171 return NETDEV_TX_BUSY;
1172}
1173
8668ae92 1174static void ql_realign_skb(struct sk_buff *skb, int len)
c4e84bde
RM		 1175{
1176 void *temp_addr = skb->data;
1177
1178 /* Undo the skb_reserve(skb,32) we did before
1179 * giving to hardware, and realign data on
1180 * a 2-byte boundary.
1181 */
1182 skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1183 skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1184 skb_copy_to_linear_data(skb, temp_addr,
1185 (unsigned int)len);
1186}
1187
1188/*
1189 * This function builds an skb for the given inbound
1190 * completion. It will be rewritten for readability in the near
1191 * future, but for not it works well.
1192 */
1193static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1194 struct rx_ring *rx_ring,
1195 struct ib_mac_iocb_rsp *ib_mac_rsp)
1196{
1197 struct bq_desc *lbq_desc;
1198 struct bq_desc *sbq_desc;
1199 struct sk_buff *skb = NULL;
1200 u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1201 u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1202
1203 /*
1204 * Handle the header buffer if present.
1205 */
1206 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1207 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1208 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1209 /*
1210 * Headers fit nicely into a small buffer.
1211 */
1212 sbq_desc = ql_get_curr_sbuf(rx_ring);
1213 pci_unmap_single(qdev->pdev,
1214 pci_unmap_addr(sbq_desc, mapaddr),
1215 pci_unmap_len(sbq_desc, maplen),
1216 PCI_DMA_FROMDEVICE);
1217 skb = sbq_desc->p.skb;
1218 ql_realign_skb(skb, hdr_len);
1219 skb_put(skb, hdr_len);
1220 sbq_desc->p.skb = NULL;
1221 }
1222
1223 /*
1224 * Handle the data buffer(s).
1225 */
1226 if (unlikely(!length)) { /* Is there data too? */
1227 QPRINTK(qdev, RX_STATUS, DEBUG,
1228 "No Data buffer in this packet.\n");
1229 return skb;
1230 }
1231
1232 if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1233 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1234 QPRINTK(qdev, RX_STATUS, DEBUG,
1235 "Headers in small, data of %d bytes in small, combine them.\n", length);
1236 /*
1237 * Data is less than small buffer size so it's
1238 * stuffed in a small buffer.
1239 * For this case we append the data
1240 * from the "data" small buffer to the "header" small
1241 * buffer.
1242 */
1243 sbq_desc = ql_get_curr_sbuf(rx_ring);
1244 pci_dma_sync_single_for_cpu(qdev->pdev,
1245 pci_unmap_addr
1246 (sbq_desc, mapaddr),
1247 pci_unmap_len
1248 (sbq_desc, maplen),
1249 PCI_DMA_FROMDEVICE);
1250 memcpy(skb_put(skb, length),
1251 sbq_desc->p.skb->data, length);
1252 pci_dma_sync_single_for_device(qdev->pdev,
1253 pci_unmap_addr
1254 (sbq_desc,
1255 mapaddr),
1256 pci_unmap_len
1257 (sbq_desc,
1258 maplen),
1259 PCI_DMA_FROMDEVICE);
1260 } else {
1261 QPRINTK(qdev, RX_STATUS, DEBUG,
1262 "%d bytes in a single small buffer.\n", length);
1263 sbq_desc = ql_get_curr_sbuf(rx_ring);
1264 skb = sbq_desc->p.skb;
1265 ql_realign_skb(skb, length);
1266 skb_put(skb, length);
1267 pci_unmap_single(qdev->pdev,
1268 pci_unmap_addr(sbq_desc,
1269 mapaddr),
1270 pci_unmap_len(sbq_desc,
1271 maplen),
1272 PCI_DMA_FROMDEVICE);
1273 sbq_desc->p.skb = NULL;
1274 }
1275 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1276 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1277 QPRINTK(qdev, RX_STATUS, DEBUG,
1278 "Header in small, %d bytes in large. Chain large to small!\n", length);
1279 /*
1280 * The data is in a single large buffer. We
1281 * chain it to the header buffer's skb and let
1282 * it rip.
1283 */
1284 lbq_desc = ql_get_curr_lbuf(rx_ring);
1285 pci_unmap_page(qdev->pdev,
1286 pci_unmap_addr(lbq_desc,
1287 mapaddr),
1288 pci_unmap_len(lbq_desc, maplen),
1289 PCI_DMA_FROMDEVICE);
1290 QPRINTK(qdev, RX_STATUS, DEBUG,
1291 "Chaining page to skb.\n");
1292 skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1293 0, length);
1294 skb->len += length;
1295 skb->data_len += length;
1296 skb->truesize += length;
1297 lbq_desc->p.lbq_page = NULL;
1298 } else {
1299 /*
1300 * The headers and data are in a single large buffer. We
1301 * copy it to a new skb and let it go. This can happen with
1302 * jumbo mtu on a non-TCP/UDP frame.
1303 */
1304 lbq_desc = ql_get_curr_lbuf(rx_ring);
1305 skb = netdev_alloc_skb(qdev->ndev, length);
1306 if (skb == NULL) {
1307 QPRINTK(qdev, PROBE, DEBUG,
1308 "No skb available, drop the packet.\n");
1309 return NULL;
1310 }
1311 skb_reserve(skb, NET_IP_ALIGN);
1312 QPRINTK(qdev, RX_STATUS, DEBUG,
1313 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1314 skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1315 0, length);
1316 skb->len += length;
1317 skb->data_len += length;
1318 skb->truesize += length;
1319 length -= length;
1320 lbq_desc->p.lbq_page = NULL;
1321 __pskb_pull_tail(skb,
1322 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1323 VLAN_ETH_HLEN : ETH_HLEN);
1324 }
1325 } else {
1326 /*
1327 * The data is in a chain of large buffers
1328 * pointed to by a small buffer. We loop
1329 * thru and chain them to the our small header
1330 * buffer's skb.
1331 * frags: There are 18 max frags and our small
1332 * buffer will hold 32 of them. The thing is,
1333 * we'll use 3 max for our 9000 byte jumbo
1334 * frames. If the MTU goes up we could
1335 * eventually be in trouble.
1336 */
1337 int size, offset, i = 0;
1338 struct bq_element *bq, bq_array[8];
1339 sbq_desc = ql_get_curr_sbuf(rx_ring);
1340 pci_unmap_single(qdev->pdev,
1341 pci_unmap_addr(sbq_desc, mapaddr),
1342 pci_unmap_len(sbq_desc, maplen),
1343 PCI_DMA_FROMDEVICE);
1344 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1345 /*
1346 * This is an non TCP/UDP IP frame, so
1347 * the headers aren't split into a small
1348 * buffer. We have to use the small buffer
1349 * that contains our sg list as our skb to
1350 * send upstairs. Copy the sg list here to
1351 * a local buffer and use it to find the
1352 * pages to chain.
1353 */
1354 QPRINTK(qdev, RX_STATUS, DEBUG,
1355 "%d bytes of headers & data in chain of large.\n", length);
1356 skb = sbq_desc->p.skb;
1357 bq = &bq_array[0];
1358 memcpy(bq, skb->data, sizeof(bq_array));
1359 sbq_desc->p.skb = NULL;
1360 skb_reserve(skb, NET_IP_ALIGN);
1361 } else {
1362 QPRINTK(qdev, RX_STATUS, DEBUG,
1363 "Headers in small, %d bytes of data in chain of large.\n", length);
1364 bq = (struct bq_element *)sbq_desc->p.skb->data;
1365 }
1366 while (length > 0) {
1367 lbq_desc = ql_get_curr_lbuf(rx_ring);
1368 if ((bq->addr_lo & ~BQ_MASK) != lbq_desc->bq->addr_lo) {
1369 QPRINTK(qdev, RX_STATUS, ERR,
1370 "Panic!!! bad large buffer address, expected 0x%.08x, got 0x%.08x.\n",
1371 lbq_desc->bq->addr_lo, bq->addr_lo);
1372 return NULL;
1373 }
1374 pci_unmap_page(qdev->pdev,
1375 pci_unmap_addr(lbq_desc,
1376 mapaddr),
1377 pci_unmap_len(lbq_desc,
1378 maplen),
1379 PCI_DMA_FROMDEVICE);
1380 size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1381 offset = 0;
1382
1383 QPRINTK(qdev, RX_STATUS, DEBUG,
1384 "Adding page %d to skb for %d bytes.\n",
1385 i, size);
1386 skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1387 offset, size);
1388 skb->len += size;
1389 skb->data_len += size;
1390 skb->truesize += size;
1391 length -= size;
1392 lbq_desc->p.lbq_page = NULL;
1393 bq++;
1394 i++;
1395 }
1396 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1397 VLAN_ETH_HLEN : ETH_HLEN);
1398 }
1399 return skb;
1400}
1401
1402/* Process an inbound completion from an rx ring. */
1403static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1404 struct rx_ring *rx_ring,
1405 struct ib_mac_iocb_rsp *ib_mac_rsp)
1406{
1407 struct net_device *ndev = qdev->ndev;
1408 struct sk_buff *skb = NULL;
1409
1410 QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1411
1412 skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1413 if (unlikely(!skb)) {
1414 QPRINTK(qdev, RX_STATUS, DEBUG,
1415 "No skb available, drop packet.\n");
1416 return;
1417 }
1418
1419 prefetch(skb->data);
1420 skb->dev = ndev;
1421 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1422 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1423 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1424 IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1425 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1426 IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1427 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1428 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1429 }
1430 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1431 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1432 }
1433 if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) {
1434 QPRINTK(qdev, RX_STATUS, ERR,
1435 "Bad checksum for this %s packet.\n",
1436 ((ib_mac_rsp->
1437 flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP"));
1438 skb->ip_summed = CHECKSUM_NONE;
1439 } else if (qdev->rx_csum &&
1440 ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ||
1441 ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1442 !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) {
1443 QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n");
1444 skb->ip_summed = CHECKSUM_UNNECESSARY;
1445 }
1446 qdev->stats.rx_packets++;
1447 qdev->stats.rx_bytes += skb->len;
1448 skb->protocol = eth_type_trans(skb, ndev);
1449 if (qdev->vlgrp && (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)) {
1450 QPRINTK(qdev, RX_STATUS, DEBUG,
1451 "Passing a VLAN packet upstream.\n");
1452 vlan_hwaccel_rx(skb, qdev->vlgrp,
1453 le16_to_cpu(ib_mac_rsp->vlan_id));
1454 } else {
1455 QPRINTK(qdev, RX_STATUS, DEBUG,
1456 "Passing a normal packet upstream.\n");
1457 netif_rx(skb);
1458 }
c4e84bde
RM		 1459}
1460
1461/* Process an outbound completion from an rx ring. */
1462static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1463 struct ob_mac_iocb_rsp *mac_rsp)
1464{
1465 struct tx_ring *tx_ring;
1466 struct tx_ring_desc *tx_ring_desc;
1467
1468 QL_DUMP_OB_MAC_RSP(mac_rsp);
1469 tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1470 tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1471 ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1472 qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1473 qdev->stats.tx_packets++;
1474 dev_kfree_skb(tx_ring_desc->skb);
1475 tx_ring_desc->skb = NULL;
1476
1477 if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1478 OB_MAC_IOCB_RSP_S |
1479 OB_MAC_IOCB_RSP_L |
1480 OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1481 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1482 QPRINTK(qdev, TX_DONE, WARNING,
1483 "Total descriptor length did not match transfer length.\n");
1484 }
1485 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1486 QPRINTK(qdev, TX_DONE, WARNING,
1487 "Frame too short to be legal, not sent.\n");
1488 }
1489 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1490 QPRINTK(qdev, TX_DONE, WARNING,
1491 "Frame too long, but sent anyway.\n");
1492 }
1493 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1494 QPRINTK(qdev, TX_DONE, WARNING,
1495 "PCI backplane error. Frame not sent.\n");
1496 }
1497 }
1498 atomic_inc(&tx_ring->tx_count);
1499}
1500
1501/* Fire up a handler to reset the MPI processor. */
1502void ql_queue_fw_error(struct ql_adapter *qdev)
1503{
1504 netif_stop_queue(qdev->ndev);
1505 netif_carrier_off(qdev->ndev);
1506 queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1507}
1508
1509void ql_queue_asic_error(struct ql_adapter *qdev)
1510{
1511 netif_stop_queue(qdev->ndev);
1512 netif_carrier_off(qdev->ndev);
1513 ql_disable_interrupts(qdev);
1514 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1515}
1516
1517static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1518 struct ib_ae_iocb_rsp *ib_ae_rsp)
1519{
1520 switch (ib_ae_rsp->event) {
1521 case MGMT_ERR_EVENT:
1522 QPRINTK(qdev, RX_ERR, ERR,
1523 "Management Processor Fatal Error.\n");
1524 ql_queue_fw_error(qdev);
1525 return;
1526
1527 case CAM_LOOKUP_ERR_EVENT:
1528 QPRINTK(qdev, LINK, ERR,
1529 "Multiple CAM hits lookup occurred.\n");
1530 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1531 ql_queue_asic_error(qdev);
1532 return;
1533
1534 case SOFT_ECC_ERROR_EVENT:
1535 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1536 ql_queue_asic_error(qdev);
1537 break;
1538
1539 case PCI_ERR_ANON_BUF_RD:
1540 QPRINTK(qdev, RX_ERR, ERR,
1541 "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1542 ib_ae_rsp->q_id);
1543 ql_queue_asic_error(qdev);
1544 break;
1545
1546 default:
1547 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1548 ib_ae_rsp->event);
1549 ql_queue_asic_error(qdev);
1550 break;
1551 }
1552}
1553
1554static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1555{
1556 struct ql_adapter *qdev = rx_ring->qdev;
1557 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1558 struct ob_mac_iocb_rsp *net_rsp = NULL;
1559 int count = 0;
1560
1561 /* While there are entries in the completion queue. */
1562 while (prod != rx_ring->cnsmr_idx) {
1563
1564 QPRINTK(qdev, RX_STATUS, DEBUG,
1565 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1566 prod, rx_ring->cnsmr_idx);
1567
1568 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1569 rmb();
1570 switch (net_rsp->opcode) {
1571
1572 case OPCODE_OB_MAC_TSO_IOCB:
1573 case OPCODE_OB_MAC_IOCB:
1574 ql_process_mac_tx_intr(qdev, net_rsp);
1575 break;
1576 default:
1577 QPRINTK(qdev, RX_STATUS, DEBUG,
1578 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1579 net_rsp->opcode);
1580 }
1581 count++;
1582 ql_update_cq(rx_ring);
1583 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1584 }
1585 ql_write_cq_idx(rx_ring);
1586 if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
1587 struct tx_ring *tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1588 if (atomic_read(&tx_ring->queue_stopped) &&
1589 (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1590 /*
1591 * The queue got stopped because the tx_ring was full.
1592 * Wake it up, because it's now at least 25% empty.
1593 */
1594 netif_wake_queue(qdev->ndev);
1595 }
1596
1597 return count;
1598}
1599
1600static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1601{
1602 struct ql_adapter *qdev = rx_ring->qdev;
1603 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1604 struct ql_net_rsp_iocb *net_rsp;
1605 int count = 0;
1606
1607 /* While there are entries in the completion queue. */
1608 while (prod != rx_ring->cnsmr_idx) {
1609
1610 QPRINTK(qdev, RX_STATUS, DEBUG,
1611 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1612 prod, rx_ring->cnsmr_idx);
1613
1614 net_rsp = rx_ring->curr_entry;
1615 rmb();
1616 switch (net_rsp->opcode) {
1617 case OPCODE_IB_MAC_IOCB:
1618 ql_process_mac_rx_intr(qdev, rx_ring,
1619 (struct ib_mac_iocb_rsp *)
1620 net_rsp);
1621 break;
1622
1623 case OPCODE_IB_AE_IOCB:
1624 ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1625 net_rsp);
1626 break;
1627 default:
1628 {
1629 QPRINTK(qdev, RX_STATUS, DEBUG,
1630 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1631 net_rsp->opcode);
1632 }
1633 }
1634 count++;
1635 ql_update_cq(rx_ring);
1636 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1637 if (count == budget)
1638 break;
1639 }
1640 ql_update_buffer_queues(qdev, rx_ring);
1641 ql_write_cq_idx(rx_ring);
1642 return count;
1643}
1644
1645static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1646{
1647 struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1648 struct ql_adapter *qdev = rx_ring->qdev;
1649 int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1650
1651 QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1652 rx_ring->cq_id);
1653
1654 if (work_done < budget) {
908a7a16 1655 __netif_rx_complete(napi);
c4e84bde
RM		 1656 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1657 }
1658 return work_done;
1659}
1660
1661static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1662{
1663 struct ql_adapter *qdev = netdev_priv(ndev);
1664
1665 qdev->vlgrp = grp;
1666 if (grp) {
1667 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1668 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1669 NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1670 } else {
1671 QPRINTK(qdev, IFUP, DEBUG,
1672 "Turning off VLAN in NIC_RCV_CFG.\n");
1673 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1674 }
1675}
1676
1677static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1678{
1679 struct ql_adapter *qdev = netdev_priv(ndev);
1680 u32 enable_bit = MAC_ADDR_E;
1681
1682 spin_lock(&qdev->hw_lock);
1683 if (ql_set_mac_addr_reg
1684 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1685 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1686 }
1687 spin_unlock(&qdev->hw_lock);
1688}
1689
1690static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1691{
1692 struct ql_adapter *qdev = netdev_priv(ndev);
1693 u32 enable_bit = 0;
1694
1695 spin_lock(&qdev->hw_lock);
1696 if (ql_set_mac_addr_reg
1697 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1698 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1699 }
1700 spin_unlock(&qdev->hw_lock);
1701
1702}
1703
1704/* Worker thread to process a given rx_ring that is dedicated
1705 * to outbound completions.
1706 */
1707static void ql_tx_clean(struct work_struct *work)
1708{
1709 struct rx_ring *rx_ring =
1710 container_of(work, struct rx_ring, rx_work.work);
1711 ql_clean_outbound_rx_ring(rx_ring);
1712 ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1713
1714}
1715
1716/* Worker thread to process a given rx_ring that is dedicated
1717 * to inbound completions.
1718 */
1719static void ql_rx_clean(struct work_struct *work)
1720{
1721 struct rx_ring *rx_ring =
1722 container_of(work, struct rx_ring, rx_work.work);
1723 ql_clean_inbound_rx_ring(rx_ring, 64);
1724 ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1725}
1726
1727/* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1728static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1729{
1730 struct rx_ring *rx_ring = dev_id;
1731 queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1732 &rx_ring->rx_work, 0);
1733 return IRQ_HANDLED;
1734}
1735
1736/* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1737static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1738{
1739 struct rx_ring *rx_ring = dev_id;
908a7a16 1740 netif_rx_schedule(&rx_ring->napi);
c4e84bde
RM		 1741 return IRQ_HANDLED;
1742}
1743
c4e84bde
RM		 1744/* This handles a fatal error, MPI activity, and the default
1745 * rx_ring in an MSI-X multiple vector environment.
1746 * In MSI/Legacy environment it also process the rest of
1747 * the rx_rings.
1748 */
1749static irqreturn_t qlge_isr(int irq, void *dev_id)
1750{
1751 struct rx_ring *rx_ring = dev_id;
1752 struct ql_adapter *qdev = rx_ring->qdev;
1753 struct intr_context *intr_context = &qdev->intr_context[0];
1754 u32 var;
1755 int i;
1756 int work_done = 0;
1757
bb0d215c
RM		 1758 spin_lock(&qdev->hw_lock);
1759 if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1760 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1761 spin_unlock(&qdev->hw_lock);
1762 return IRQ_NONE;
c4e84bde 1763 }
bb0d215c 1764 spin_unlock(&qdev->hw_lock);
c4e84bde 1765
bb0d215c 1766 var = ql_disable_completion_interrupt(qdev, intr_context->intr);
c4e84bde
RM		 1767
1768 /*
1769 * Check for fatal error.
1770 */
1771 if (var & STS_FE) {
1772 ql_queue_asic_error(qdev);
1773 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1774 var = ql_read32(qdev, ERR_STS);
1775 QPRINTK(qdev, INTR, ERR,
1776 "Resetting chip. Error Status Register = 0x%x\n", var);
1777 return IRQ_HANDLED;
1778 }
1779
1780 /*
1781 * Check MPI processor activity.
1782 */
1783 if (var & STS_PI) {
1784 /*
1785 * We've got an async event or mailbox completion.
1786 * Handle it and clear the source of the interrupt.
1787 */
1788 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1789 ql_disable_completion_interrupt(qdev, intr_context->intr);
1790 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1791 &qdev->mpi_work, 0);
1792 work_done++;
1793 }
1794
1795 /*
1796 * Check the default queue and wake handler if active.
1797 */
1798 rx_ring = &qdev->rx_ring[0];
1799 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1800 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1801 ql_disable_completion_interrupt(qdev, intr_context->intr);
1802 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1803 &rx_ring->rx_work, 0);
1804 work_done++;
1805 }
1806
1807 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1808 /*
1809 * Start the DPC for each active queue.
1810 */
1811 for (i = 1; i < qdev->rx_ring_count; i++) {
1812 rx_ring = &qdev->rx_ring[i];
1813 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1814 rx_ring->cnsmr_idx) {
1815 QPRINTK(qdev, INTR, INFO,
1816 "Waking handler for rx_ring[%d].\n", i);
1817 ql_disable_completion_interrupt(qdev,
1818 intr_context->
1819 intr);
1820 if (i < qdev->rss_ring_first_cq_id)
1821 queue_delayed_work_on(rx_ring->cpu,
1822 qdev->q_workqueue,
1823 &rx_ring->rx_work,
1824 0);
1825 else
908a7a16 1826 netif_rx_schedule(&rx_ring->napi);
c4e84bde
RM		 1827 work_done++;
1828 }
1829 }
1830 }
bb0d215c 1831 ql_enable_completion_interrupt(qdev, intr_context->intr);
c4e84bde
RM		 1832 return work_done ? IRQ_HANDLED : IRQ_NONE;
1833}
1834
1835static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1836{
1837
1838 if (skb_is_gso(skb)) {
1839 int err;
1840 if (skb_header_cloned(skb)) {
1841 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1842 if (err)
1843 return err;
1844 }
1845
1846 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1847 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1848 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1849 mac_iocb_ptr->total_hdrs_len =
1850 cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1851 mac_iocb_ptr->net_trans_offset =
1852 cpu_to_le16(skb_network_offset(skb) |
1853 skb_transport_offset(skb)
1854 << OB_MAC_TRANSPORT_HDR_SHIFT);
1855 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1856 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1857 if (likely(skb->protocol == htons(ETH_P_IP))) {
1858 struct iphdr *iph = ip_hdr(skb);
1859 iph->check = 0;
1860 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1861 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1862 iph->daddr, 0,
1863 IPPROTO_TCP,
1864 0);
1865 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1866 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
1867 tcp_hdr(skb)->check =
1868 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1869 &ipv6_hdr(skb)->daddr,
1870 0, IPPROTO_TCP, 0);
1871 }
1872 return 1;
1873 }
1874 return 0;
1875}
1876
1877static void ql_hw_csum_setup(struct sk_buff *skb,
1878 struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1879{
1880 int len;
1881 struct iphdr *iph = ip_hdr(skb);
1882 u16 *check;
1883 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1884 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1885 mac_iocb_ptr->net_trans_offset =
1886 cpu_to_le16(skb_network_offset(skb) |
1887 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
1888
1889 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1890 len = (ntohs(iph->tot_len) - (iph->ihl << 2));
1891 if (likely(iph->protocol == IPPROTO_TCP)) {
1892 check = &(tcp_hdr(skb)->check);
1893 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
1894 mac_iocb_ptr->total_hdrs_len =
1895 cpu_to_le16(skb_transport_offset(skb) +
1896 (tcp_hdr(skb)->doff << 2));
1897 } else {
1898 check = &(udp_hdr(skb)->check);
1899 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
1900 mac_iocb_ptr->total_hdrs_len =
1901 cpu_to_le16(skb_transport_offset(skb) +
1902 sizeof(struct udphdr));
1903 }
1904 *check = ~csum_tcpudp_magic(iph->saddr,
1905 iph->daddr, len, iph->protocol, 0);
1906}
1907
1908static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
1909{
1910 struct tx_ring_desc *tx_ring_desc;
1911 struct ob_mac_iocb_req *mac_iocb_ptr;
1912 struct ql_adapter *qdev = netdev_priv(ndev);
1913 int tso;
1914 struct tx_ring *tx_ring;
1915 u32 tx_ring_idx = (u32) QL_TXQ_IDX(qdev, skb);
1916
1917 tx_ring = &qdev->tx_ring[tx_ring_idx];
1918
1919 if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
1920 QPRINTK(qdev, TX_QUEUED, INFO,
1921 "%s: shutting down tx queue %d du to lack of resources.\n",
1922 __func__, tx_ring_idx);
1923 netif_stop_queue(ndev);
1924 atomic_inc(&tx_ring->queue_stopped);
1925 return NETDEV_TX_BUSY;
1926 }
1927 tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
1928 mac_iocb_ptr = tx_ring_desc->queue_entry;
1929 memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
1930 if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) != NETDEV_TX_OK) {
1931 QPRINTK(qdev, TX_QUEUED, ERR, "Could not map the segments.\n");
1932 return NETDEV_TX_BUSY;
1933 }
1934
1935 mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
1936 mac_iocb_ptr->tid = tx_ring_desc->index;
1937 /* We use the upper 32-bits to store the tx queue for this IO.
1938 * When we get the completion we can use it to establish the context.
1939 */
1940 mac_iocb_ptr->txq_idx = tx_ring_idx;
1941 tx_ring_desc->skb = skb;
1942
1943 mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
1944
1945 if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
1946 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
1947 vlan_tx_tag_get(skb));
1948 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
1949 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
1950 }
1951 tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1952 if (tso < 0) {
1953 dev_kfree_skb_any(skb);
1954 return NETDEV_TX_OK;
1955 } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
1956 ql_hw_csum_setup(skb,
1957 (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1958 }
1959 QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
1960 tx_ring->prod_idx++;
1961 if (tx_ring->prod_idx == tx_ring->wq_len)
1962 tx_ring->prod_idx = 0;
1963 wmb();
1964
1965 ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
1966 ndev->trans_start = jiffies;
1967 QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
1968 tx_ring->prod_idx, skb->len);
1969
1970 atomic_dec(&tx_ring->tx_count);
1971 return NETDEV_TX_OK;
1972}
1973
1974static void ql_free_shadow_space(struct ql_adapter *qdev)
1975{
1976 if (qdev->rx_ring_shadow_reg_area) {
1977 pci_free_consistent(qdev->pdev,
1978 PAGE_SIZE,
1979 qdev->rx_ring_shadow_reg_area,
1980 qdev->rx_ring_shadow_reg_dma);
1981 qdev->rx_ring_shadow_reg_area = NULL;
1982 }
1983 if (qdev->tx_ring_shadow_reg_area) {
1984 pci_free_consistent(qdev->pdev,
1985 PAGE_SIZE,
1986 qdev->tx_ring_shadow_reg_area,
1987 qdev->tx_ring_shadow_reg_dma);
1988 qdev->tx_ring_shadow_reg_area = NULL;
1989 }
1990}
1991
1992static int ql_alloc_shadow_space(struct ql_adapter *qdev)
1993{
1994 qdev->rx_ring_shadow_reg_area =
1995 pci_alloc_consistent(qdev->pdev,
1996 PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
1997 if (qdev->rx_ring_shadow_reg_area == NULL) {
1998 QPRINTK(qdev, IFUP, ERR,
1999 "Allocation of RX shadow space failed.\n");
2000 return -ENOMEM;
2001 }
2002 qdev->tx_ring_shadow_reg_area =
2003 pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2004 &qdev->tx_ring_shadow_reg_dma);
2005 if (qdev->tx_ring_shadow_reg_area == NULL) {
2006 QPRINTK(qdev, IFUP, ERR,
2007 "Allocation of TX shadow space failed.\n");
2008 goto err_wqp_sh_area;
2009 }
2010 return 0;
2011
2012err_wqp_sh_area:
2013 pci_free_consistent(qdev->pdev,
2014 PAGE_SIZE,
2015 qdev->rx_ring_shadow_reg_area,
2016 qdev->rx_ring_shadow_reg_dma);
2017 return -ENOMEM;
2018}
2019
2020static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2021{
2022 struct tx_ring_desc *tx_ring_desc;
2023 int i;
2024 struct ob_mac_iocb_req *mac_iocb_ptr;
2025
2026 mac_iocb_ptr = tx_ring->wq_base;
2027 tx_ring_desc = tx_ring->q;
2028 for (i = 0; i < tx_ring->wq_len; i++) {
2029 tx_ring_desc->index = i;
2030 tx_ring_desc->skb = NULL;
2031 tx_ring_desc->queue_entry = mac_iocb_ptr;
2032 mac_iocb_ptr++;
2033 tx_ring_desc++;
2034 }
2035 atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2036 atomic_set(&tx_ring->queue_stopped, 0);
2037}
2038
2039static void ql_free_tx_resources(struct ql_adapter *qdev,
2040 struct tx_ring *tx_ring)
2041{
2042 if (tx_ring->wq_base) {
2043 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2044 tx_ring->wq_base, tx_ring->wq_base_dma);
2045 tx_ring->wq_base = NULL;
2046 }
2047 kfree(tx_ring->q);
2048 tx_ring->q = NULL;
2049}
2050
2051static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2052 struct tx_ring *tx_ring)
2053{
2054 tx_ring->wq_base =
2055 pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2056 &tx_ring->wq_base_dma);
2057
2058 if ((tx_ring->wq_base == NULL)
2059 || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2060 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2061 return -ENOMEM;
2062 }
2063 tx_ring->q =
2064 kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2065 if (tx_ring->q == NULL)
2066 goto err;
2067
2068 return 0;
2069err:
2070 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2071 tx_ring->wq_base, tx_ring->wq_base_dma);
2072 return -ENOMEM;
2073}
2074
8668ae92 2075static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
c4e84bde
RM		 2076{
2077 int i;
2078 struct bq_desc *lbq_desc;
2079
2080 for (i = 0; i < rx_ring->lbq_len; i++) {
2081 lbq_desc = &rx_ring->lbq[i];
2082 if (lbq_desc->p.lbq_page) {
2083 pci_unmap_page(qdev->pdev,
2084 pci_unmap_addr(lbq_desc, mapaddr),
2085 pci_unmap_len(lbq_desc, maplen),
2086 PCI_DMA_FROMDEVICE);
2087
2088 put_page(lbq_desc->p.lbq_page);
2089 lbq_desc->p.lbq_page = NULL;
2090 }
2091 lbq_desc->bq->addr_lo = 0;
2092 lbq_desc->bq->addr_hi = 0;
2093 }
2094}
2095
2096/*
2097 * Allocate and map a page for each element of the lbq.
2098 */
2099static int ql_alloc_lbq_buffers(struct ql_adapter *qdev,
2100 struct rx_ring *rx_ring)
2101{
2102 int i;
2103 struct bq_desc *lbq_desc;
2104 u64 map;
2105 struct bq_element *bq = rx_ring->lbq_base;
2106
2107 for (i = 0; i < rx_ring->lbq_len; i++) {
2108 lbq_desc = &rx_ring->lbq[i];
2109 memset(lbq_desc, 0, sizeof(lbq_desc));
2110 lbq_desc->bq = bq;
2111 lbq_desc->index = i;
2112 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
2113 if (unlikely(!lbq_desc->p.lbq_page)) {
2114 QPRINTK(qdev, IFUP, ERR, "failed alloc_page().\n");
2115 goto mem_error;
2116 } else {
2117 map = pci_map_page(qdev->pdev,
2118 lbq_desc->p.lbq_page,
2119 0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
2120 if (pci_dma_mapping_error(qdev->pdev, map)) {
2121 QPRINTK(qdev, IFUP, ERR,
2122 "PCI mapping failed.\n");
2123 goto mem_error;
2124 }
2125 pci_unmap_addr_set(lbq_desc, mapaddr, map);
2126 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
2127 bq->addr_lo = cpu_to_le32(map);
2128 bq->addr_hi = cpu_to_le32(map >> 32);
2129 }
2130 bq++;
2131 }
2132 return 0;
2133mem_error:
2134 ql_free_lbq_buffers(qdev, rx_ring);
2135 return -ENOMEM;
2136}
2137
8668ae92 2138static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
c4e84bde
RM		 2139{
2140 int i;
2141 struct bq_desc *sbq_desc;
2142
2143 for (i = 0; i < rx_ring->sbq_len; i++) {
2144 sbq_desc = &rx_ring->sbq[i];
2145 if (sbq_desc == NULL) {
2146 QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2147 return;
2148 }
2149 if (sbq_desc->p.skb) {
2150 pci_unmap_single(qdev->pdev,
2151 pci_unmap_addr(sbq_desc, mapaddr),
2152 pci_unmap_len(sbq_desc, maplen),
2153 PCI_DMA_FROMDEVICE);
2154 dev_kfree_skb(sbq_desc->p.skb);
2155 sbq_desc->p.skb = NULL;
2156 }
2157 if (sbq_desc->bq == NULL) {
2158 QPRINTK(qdev, IFUP, ERR, "sbq_desc->bq %d is NULL.\n",
2159 i);
2160 return;
2161 }
2162 sbq_desc->bq->addr_lo = 0;
2163 sbq_desc->bq->addr_hi = 0;
2164 }
2165}
2166
2167/* Allocate and map an skb for each element of the sbq. */
2168static int ql_alloc_sbq_buffers(struct ql_adapter *qdev,
2169 struct rx_ring *rx_ring)
2170{
2171 int i;
2172 struct bq_desc *sbq_desc;
2173 struct sk_buff *skb;
2174 u64 map;
2175 struct bq_element *bq = rx_ring->sbq_base;
2176
2177 for (i = 0; i < rx_ring->sbq_len; i++) {
2178 sbq_desc = &rx_ring->sbq[i];
2179 memset(sbq_desc, 0, sizeof(sbq_desc));
2180 sbq_desc->index = i;
2181 sbq_desc->bq = bq;
2182 skb = netdev_alloc_skb(qdev->ndev, rx_ring->sbq_buf_size);
2183 if (unlikely(!skb)) {
2184 /* Better luck next round */
2185 QPRINTK(qdev, IFUP, ERR,
2186 "small buff alloc failed for %d bytes at index %d.\n",
2187 rx_ring->sbq_buf_size, i);
2188 goto mem_err;
2189 }
2190 skb_reserve(skb, QLGE_SB_PAD);
2191 sbq_desc->p.skb = skb;
2192 /*
2193 * Map only half the buffer. Because the
2194 * other half may get some data copied to it
2195 * when the completion arrives.
2196 */
2197 map = pci_map_single(qdev->pdev,
2198 skb->data,
2199 rx_ring->sbq_buf_size / 2,
2200 PCI_DMA_FROMDEVICE);
2201 if (pci_dma_mapping_error(qdev->pdev, map)) {
2202 QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
2203 goto mem_err;
2204 }
2205 pci_unmap_addr_set(sbq_desc, mapaddr, map);
2206 pci_unmap_len_set(sbq_desc, maplen, rx_ring->sbq_buf_size / 2);
2207 bq->addr_lo = /*sbq_desc->addr_lo = */
2208 cpu_to_le32(map);
2209 bq->addr_hi = /*sbq_desc->addr_hi = */
2210 cpu_to_le32(map >> 32);
2211 bq++;
2212 }
2213 return 0;
2214mem_err:
2215 ql_free_sbq_buffers(qdev, rx_ring);
2216 return -ENOMEM;
2217}
2218
2219static void ql_free_rx_resources(struct ql_adapter *qdev,
2220 struct rx_ring *rx_ring)
2221{
2222 if (rx_ring->sbq_len)
2223 ql_free_sbq_buffers(qdev, rx_ring);
2224 if (rx_ring->lbq_len)
2225 ql_free_lbq_buffers(qdev, rx_ring);
2226
2227 /* Free the small buffer queue. */
2228 if (rx_ring->sbq_base) {
2229 pci_free_consistent(qdev->pdev,
2230 rx_ring->sbq_size,
2231 rx_ring->sbq_base, rx_ring->sbq_base_dma);
2232 rx_ring->sbq_base = NULL;
2233 }
2234
2235 /* Free the small buffer queue control blocks. */
2236 kfree(rx_ring->sbq);
2237 rx_ring->sbq = NULL;
2238
2239 /* Free the large buffer queue. */
2240 if (rx_ring->lbq_base) {
2241 pci_free_consistent(qdev->pdev,
2242 rx_ring->lbq_size,
2243 rx_ring->lbq_base, rx_ring->lbq_base_dma);
2244 rx_ring->lbq_base = NULL;
2245 }
2246
2247 /* Free the large buffer queue control blocks. */
2248 kfree(rx_ring->lbq);
2249 rx_ring->lbq = NULL;
2250
2251 /* Free the rx queue. */
2252 if (rx_ring->cq_base) {
2253 pci_free_consistent(qdev->pdev,
2254 rx_ring->cq_size,
2255 rx_ring->cq_base, rx_ring->cq_base_dma);
2256 rx_ring->cq_base = NULL;
2257 }
2258}
2259
2260/* Allocate queues and buffers for this completions queue based
2261 * on the values in the parameter structure. */
2262static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2263 struct rx_ring *rx_ring)
2264{
2265
2266 /*
2267 * Allocate the completion queue for this rx_ring.
2268 */
2269 rx_ring->cq_base =
2270 pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2271 &rx_ring->cq_base_dma);
2272
2273 if (rx_ring->cq_base == NULL) {
2274 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2275 return -ENOMEM;
2276 }
2277
2278 if (rx_ring->sbq_len) {
2279 /*
2280 * Allocate small buffer queue.
2281 */
2282 rx_ring->sbq_base =
2283 pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2284 &rx_ring->sbq_base_dma);
2285
2286 if (rx_ring->sbq_base == NULL) {
2287 QPRINTK(qdev, IFUP, ERR,
2288 "Small buffer queue allocation failed.\n");
2289 goto err_mem;
2290 }
2291
2292 /*
2293 * Allocate small buffer queue control blocks.
2294 */
2295 rx_ring->sbq =
2296 kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2297 GFP_KERNEL);
2298 if (rx_ring->sbq == NULL) {
2299 QPRINTK(qdev, IFUP, ERR,
2300 "Small buffer queue control block allocation failed.\n");
2301 goto err_mem;
2302 }
2303
2304 if (ql_alloc_sbq_buffers(qdev, rx_ring)) {
2305 QPRINTK(qdev, IFUP, ERR,
2306 "Small buffer allocation failed.\n");
2307 goto err_mem;
2308 }
2309 }
2310
2311 if (rx_ring->lbq_len) {
2312 /*
2313 * Allocate large buffer queue.
2314 */
2315 rx_ring->lbq_base =
2316 pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2317 &rx_ring->lbq_base_dma);
2318
2319 if (rx_ring->lbq_base == NULL) {
2320 QPRINTK(qdev, IFUP, ERR,
2321 "Large buffer queue allocation failed.\n");
2322 goto err_mem;
2323 }
2324 /*
2325 * Allocate large buffer queue control blocks.
2326 */
2327 rx_ring->lbq =
2328 kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2329 GFP_KERNEL);
2330 if (rx_ring->lbq == NULL) {
2331 QPRINTK(qdev, IFUP, ERR,
2332 "Large buffer queue control block allocation failed.\n");
2333 goto err_mem;
2334 }
2335
2336 /*
2337 * Allocate the buffers.
2338 */
2339 if (ql_alloc_lbq_buffers(qdev, rx_ring)) {
2340 QPRINTK(qdev, IFUP, ERR,
2341 "Large buffer allocation failed.\n");
2342 goto err_mem;
2343 }
2344 }
2345
2346 return 0;
2347
2348err_mem:
2349 ql_free_rx_resources(qdev, rx_ring);
2350 return -ENOMEM;
2351}
2352
2353static void ql_tx_ring_clean(struct ql_adapter *qdev)
2354{
2355 struct tx_ring *tx_ring;
2356 struct tx_ring_desc *tx_ring_desc;
2357 int i, j;
2358
2359 /*
2360 * Loop through all queues and free
2361 * any resources.
2362 */
2363 for (j = 0; j < qdev->tx_ring_count; j++) {
2364 tx_ring = &qdev->tx_ring[j];
2365 for (i = 0; i < tx_ring->wq_len; i++) {
2366 tx_ring_desc = &tx_ring->q[i];
2367 if (tx_ring_desc && tx_ring_desc->skb) {
2368 QPRINTK(qdev, IFDOWN, ERR,
2369 "Freeing lost SKB %p, from queue %d, index %d.\n",
2370 tx_ring_desc->skb, j,
2371 tx_ring_desc->index);
2372 ql_unmap_send(qdev, tx_ring_desc,
2373 tx_ring_desc->map_cnt);
2374 dev_kfree_skb(tx_ring_desc->skb);
2375 tx_ring_desc->skb = NULL;
2376 }
2377 }
2378 }
2379}
2380
2381static void ql_free_ring_cb(struct ql_adapter *qdev)
2382{
2383 kfree(qdev->ring_mem);
2384}
2385
2386static int ql_alloc_ring_cb(struct ql_adapter *qdev)
2387{
2388 /* Allocate space for tx/rx ring control blocks. */
2389 qdev->ring_mem_size =
2390 (qdev->tx_ring_count * sizeof(struct tx_ring)) +
2391 (qdev->rx_ring_count * sizeof(struct rx_ring));
2392 qdev->ring_mem = kmalloc(qdev->ring_mem_size, GFP_KERNEL);
2393 if (qdev->ring_mem == NULL) {
2394 return -ENOMEM;
2395 } else {
2396 qdev->rx_ring = qdev->ring_mem;
2397 qdev->tx_ring = qdev->ring_mem +
2398 (qdev->rx_ring_count * sizeof(struct rx_ring));
2399 }
2400 return 0;
2401}
2402
2403static void ql_free_mem_resources(struct ql_adapter *qdev)
2404{
2405 int i;
2406
2407 for (i = 0; i < qdev->tx_ring_count; i++)
2408 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2409 for (i = 0; i < qdev->rx_ring_count; i++)
2410 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2411 ql_free_shadow_space(qdev);
2412}
2413
2414static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2415{
2416 int i;
2417
2418 /* Allocate space for our shadow registers and such. */
2419 if (ql_alloc_shadow_space(qdev))
2420 return -ENOMEM;
2421
2422 for (i = 0; i < qdev->rx_ring_count; i++) {
2423 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2424 QPRINTK(qdev, IFUP, ERR,
2425 "RX resource allocation failed.\n");
2426 goto err_mem;
2427 }
2428 }
2429 /* Allocate tx queue resources */
2430 for (i = 0; i < qdev->tx_ring_count; i++) {
2431 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2432 QPRINTK(qdev, IFUP, ERR,
2433 "TX resource allocation failed.\n");
2434 goto err_mem;
2435 }
2436 }
2437 return 0;
2438
2439err_mem:
2440 ql_free_mem_resources(qdev);
2441 return -ENOMEM;
2442}
2443
2444/* Set up the rx ring control block and pass it to the chip.
2445 * The control block is defined as
2446 * "Completion Queue Initialization Control Block", or cqicb.
2447 */
2448static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2449{
2450 struct cqicb *cqicb = &rx_ring->cqicb;
2451 void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2452 (rx_ring->cq_id * sizeof(u64) * 4);
2453 u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2454 (rx_ring->cq_id * sizeof(u64) * 4);
2455 void __iomem *doorbell_area =
2456 qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2457 int err = 0;
2458 u16 bq_len;
2459
2460 /* Set up the shadow registers for this ring. */
2461 rx_ring->prod_idx_sh_reg = shadow_reg;
2462 rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2463 shadow_reg += sizeof(u64);
2464 shadow_reg_dma += sizeof(u64);
2465 rx_ring->lbq_base_indirect = shadow_reg;
2466 rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2467 shadow_reg += sizeof(u64);
2468 shadow_reg_dma += sizeof(u64);
2469 rx_ring->sbq_base_indirect = shadow_reg;
2470 rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2471
2472 /* PCI doorbell mem area + 0x00 for consumer index register */
8668ae92 2473 rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
c4e84bde
RM		 2474 rx_ring->cnsmr_idx = 0;
2475 rx_ring->curr_entry = rx_ring->cq_base;
2476
2477 /* PCI doorbell mem area + 0x04 for valid register */
2478 rx_ring->valid_db_reg = doorbell_area + 0x04;
2479
2480 /* PCI doorbell mem area + 0x18 for large buffer consumer */
8668ae92 2481 rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
c4e84bde
RM		 2482
2483 /* PCI doorbell mem area + 0x1c */
8668ae92 2484 rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
c4e84bde
RM		 2485
2486 memset((void *)cqicb, 0, sizeof(struct cqicb));
2487 cqicb->msix_vect = rx_ring->irq;
2488
2489 cqicb->len = cpu_to_le16(rx_ring->cq_len | LEN_V | LEN_CPP_CONT);
2490
2491 cqicb->addr_lo = cpu_to_le32(rx_ring->cq_base_dma);
2492 cqicb->addr_hi = cpu_to_le32((u64) rx_ring->cq_base_dma >> 32);
2493
2494 cqicb->prod_idx_addr_lo = cpu_to_le32(rx_ring->prod_idx_sh_reg_dma);
2495 cqicb->prod_idx_addr_hi =
2496 cpu_to_le32((u64) rx_ring->prod_idx_sh_reg_dma >> 32);
2497
2498 /*
2499 * Set up the control block load flags.
2500 */
2501 cqicb->flags = FLAGS_LC | /* Load queue base address */
2502 FLAGS_LV | /* Load MSI-X vector */
2503 FLAGS_LI; /* Load irq delay values */
2504 if (rx_ring->lbq_len) {
2505 cqicb->flags |= FLAGS_LL; /* Load lbq values */
2506 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
2507 cqicb->lbq_addr_lo =
2508 cpu_to_le32(rx_ring->lbq_base_indirect_dma);
2509 cqicb->lbq_addr_hi =
2510 cpu_to_le32((u64) rx_ring->lbq_base_indirect_dma >> 32);
2511 cqicb->lbq_buf_size = cpu_to_le32(rx_ring->lbq_buf_size);
2512 bq_len = (u16) rx_ring->lbq_len;
2513 cqicb->lbq_len = cpu_to_le16(bq_len);
2514 rx_ring->lbq_prod_idx = rx_ring->lbq_len - 16;
2515 rx_ring->lbq_curr_idx = 0;
2516 rx_ring->lbq_clean_idx = rx_ring->lbq_prod_idx;
2517 rx_ring->lbq_free_cnt = 16;
2518 }
2519 if (rx_ring->sbq_len) {
2520 cqicb->flags |= FLAGS_LS; /* Load sbq values */
2521 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
2522 cqicb->sbq_addr_lo =
2523 cpu_to_le32(rx_ring->sbq_base_indirect_dma);
2524 cqicb->sbq_addr_hi =
2525 cpu_to_le32((u64) rx_ring->sbq_base_indirect_dma >> 32);
2526 cqicb->sbq_buf_size =
2527 cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
2528 bq_len = (u16) rx_ring->sbq_len;
2529 cqicb->sbq_len = cpu_to_le16(bq_len);
2530 rx_ring->sbq_prod_idx = rx_ring->sbq_len - 16;
2531 rx_ring->sbq_curr_idx = 0;
2532 rx_ring->sbq_clean_idx = rx_ring->sbq_prod_idx;
2533 rx_ring->sbq_free_cnt = 16;
2534 }
2535 switch (rx_ring->type) {
2536 case TX_Q:
2537 /* If there's only one interrupt, then we use
2538 * worker threads to process the outbound
2539 * completion handling rx_rings. We do this so
2540 * they can be run on multiple CPUs. There is
2541 * room to play with this more where we would only
2542 * run in a worker if there are more than x number
2543 * of outbound completions on the queue and more
2544 * than one queue active. Some threshold that
2545 * would indicate a benefit in spite of the cost
2546 * of a context switch.
2547 * If there's more than one interrupt, then the
2548 * outbound completions are processed in the ISR.
2549 */
2550 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2551 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2552 else {
2553 /* With all debug warnings on we see a WARN_ON message
2554 * when we free the skb in the interrupt context.
2555 */
2556 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2557 }
2558 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2559 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2560 break;
2561 case DEFAULT_Q:
2562 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2563 cqicb->irq_delay = 0;
2564 cqicb->pkt_delay = 0;
2565 break;
2566 case RX_Q:
2567 /* Inbound completion handling rx_rings run in
2568 * separate NAPI contexts.
2569 */
2570 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2571 64);
2572 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2573 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2574 break;
2575 default:
2576 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2577 rx_ring->type);
2578 }
2579 QPRINTK(qdev, IFUP, INFO, "Initializing rx work queue.\n");
2580 err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2581 CFG_LCQ, rx_ring->cq_id);
2582 if (err) {
2583 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2584 return err;
2585 }
2586 QPRINTK(qdev, IFUP, INFO, "Successfully loaded CQICB.\n");
2587 /*
2588 * Advance the producer index for the buffer queues.
2589 */
2590 wmb();
2591 if (rx_ring->lbq_len)
2592 ql_write_db_reg(rx_ring->lbq_prod_idx,
2593 rx_ring->lbq_prod_idx_db_reg);
2594 if (rx_ring->sbq_len)
2595 ql_write_db_reg(rx_ring->sbq_prod_idx,
2596 rx_ring->sbq_prod_idx_db_reg);
2597 return err;
2598}
2599
2600static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2601{
2602 struct wqicb *wqicb = (struct wqicb *)tx_ring;
2603 void __iomem *doorbell_area =
2604 qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2605 void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2606 (tx_ring->wq_id * sizeof(u64));
2607 u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2608 (tx_ring->wq_id * sizeof(u64));
2609 int err = 0;
2610
2611 /*
2612 * Assign doorbell registers for this tx_ring.
2613 */
2614 /* TX PCI doorbell mem area for tx producer index */
8668ae92 2615 tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
c4e84bde
RM		 2616 tx_ring->prod_idx = 0;
2617 /* TX PCI doorbell mem area + 0x04 */
2618 tx_ring->valid_db_reg = doorbell_area + 0x04;
2619
2620 /*
2621 * Assign shadow registers for this tx_ring.
2622 */
2623 tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2624 tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2625
2626 wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2627 wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2628 Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2629 wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2630 wqicb->rid = 0;
2631 wqicb->addr_lo = cpu_to_le32(tx_ring->wq_base_dma);
2632 wqicb->addr_hi = cpu_to_le32((u64) tx_ring->wq_base_dma >> 32);
2633
2634 wqicb->cnsmr_idx_addr_lo = cpu_to_le32(tx_ring->cnsmr_idx_sh_reg_dma);
2635 wqicb->cnsmr_idx_addr_hi =
2636 cpu_to_le32((u64) tx_ring->cnsmr_idx_sh_reg_dma >> 32);
2637
2638 ql_init_tx_ring(qdev, tx_ring);
2639
2640 err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2641 (u16) tx_ring->wq_id);
2642 if (err) {
2643 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2644 return err;
2645 }
2646 QPRINTK(qdev, IFUP, INFO, "Successfully loaded WQICB.\n");
2647 return err;
2648}
2649
2650static void ql_disable_msix(struct ql_adapter *qdev)
2651{
2652 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2653 pci_disable_msix(qdev->pdev);
2654 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2655 kfree(qdev->msi_x_entry);
2656 qdev->msi_x_entry = NULL;
2657 } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2658 pci_disable_msi(qdev->pdev);
2659 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2660 }
2661}
2662
2663static void ql_enable_msix(struct ql_adapter *qdev)
2664{
2665 int i;
2666
2667 qdev->intr_count = 1;
2668 /* Get the MSIX vectors. */
2669 if (irq_type == MSIX_IRQ) {
2670 /* Try to alloc space for the msix struct,
2671 * if it fails then go to MSI/legacy.
2672 */
2673 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2674 sizeof(struct msix_entry),
2675 GFP_KERNEL);
2676 if (!qdev->msi_x_entry) {
2677 irq_type = MSI_IRQ;
2678 goto msi;
2679 }
2680
2681 for (i = 0; i < qdev->rx_ring_count; i++)
2682 qdev->msi_x_entry[i].entry = i;
2683
2684 if (!pci_enable_msix
2685 (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2686 set_bit(QL_MSIX_ENABLED, &qdev->flags);
2687 qdev->intr_count = qdev->rx_ring_count;
2688 QPRINTK(qdev, IFUP, INFO,
2689 "MSI-X Enabled, got %d vectors.\n",
2690 qdev->intr_count);
2691 return;
2692 } else {
2693 kfree(qdev->msi_x_entry);
2694 qdev->msi_x_entry = NULL;
2695 QPRINTK(qdev, IFUP, WARNING,
2696 "MSI-X Enable failed, trying MSI.\n");
2697 irq_type = MSI_IRQ;
2698 }
2699 }
2700msi:
2701 if (irq_type == MSI_IRQ) {
2702 if (!pci_enable_msi(qdev->pdev)) {
2703 set_bit(QL_MSI_ENABLED, &qdev->flags);
2704 QPRINTK(qdev, IFUP, INFO,
2705 "Running with MSI interrupts.\n");
2706 return;
2707 }
2708 }
2709 irq_type = LEG_IRQ;
c4e84bde
RM		 2710 QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2711}
2712
2713/*
2714 * Here we build the intr_context structures based on
2715 * our rx_ring count and intr vector count.
2716 * The intr_context structure is used to hook each vector
2717 * to possibly different handlers.
2718 */
2719static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2720{
2721 int i = 0;
2722 struct intr_context *intr_context = &qdev->intr_context[0];
2723
2724 ql_enable_msix(qdev);
2725
2726 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2727 /* Each rx_ring has it's
2728 * own intr_context since we have separate
2729 * vectors for each queue.
2730 * This only true when MSI-X is enabled.
2731 */
2732 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2733 qdev->rx_ring[i].irq = i;
2734 intr_context->intr = i;
2735 intr_context->qdev = qdev;
2736 /*
2737 * We set up each vectors enable/disable/read bits so
2738 * there's no bit/mask calculations in the critical path.
2739 */
2740 intr_context->intr_en_mask =
2741 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2742 INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2743 | i;
2744 intr_context->intr_dis_mask =
2745 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2746 INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2747 INTR_EN_IHD | i;
2748 intr_context->intr_read_mask =
2749 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2750 INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2751 i;
2752
2753 if (i == 0) {
2754 /*
2755 * Default queue handles bcast/mcast plus
2756 * async events. Needs buffers.
2757 */
2758 intr_context->handler = qlge_isr;
2759 sprintf(intr_context->name, "%s-default-queue",
2760 qdev->ndev->name);
2761 } else if (i < qdev->rss_ring_first_cq_id) {
2762 /*
2763 * Outbound queue is for outbound completions only.
2764 */
2765 intr_context->handler = qlge_msix_tx_isr;
2766 sprintf(intr_context->name, "%s-txq-%d",
2767 qdev->ndev->name, i);
2768 } else {
2769 /*
2770 * Inbound queues handle unicast frames only.
2771 */
2772 intr_context->handler = qlge_msix_rx_isr;
2773 sprintf(intr_context->name, "%s-rxq-%d",
2774 qdev->ndev->name, i);
2775 }
2776 }
2777 } else {
2778 /*
2779 * All rx_rings use the same intr_context since
2780 * there is only one vector.
2781 */
2782 intr_context->intr = 0;
2783 intr_context->qdev = qdev;
2784 /*
2785 * We set up each vectors enable/disable/read bits so
2786 * there's no bit/mask calculations in the critical path.
2787 */
2788 intr_context->intr_en_mask =
2789 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2790 intr_context->intr_dis_mask =
2791 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2792 INTR_EN_TYPE_DISABLE;
2793 intr_context->intr_read_mask =
2794 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2795 /*
2796 * Single interrupt means one handler for all rings.
2797 */
2798 intr_context->handler = qlge_isr;
2799 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2800 for (i = 0; i < qdev->rx_ring_count; i++)
2801 qdev->rx_ring[i].irq = 0;
2802 }
2803}
2804
2805static void ql_free_irq(struct ql_adapter *qdev)
2806{
2807 int i;
2808 struct intr_context *intr_context = &qdev->intr_context[0];
2809
2810 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2811 if (intr_context->hooked) {
2812 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2813 free_irq(qdev->msi_x_entry[i].vector,
2814 &qdev->rx_ring[i]);
2815 QPRINTK(qdev, IFDOWN, ERR,
2816 "freeing msix interrupt %d.\n", i);
2817 } else {
2818 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2819 QPRINTK(qdev, IFDOWN, ERR,
2820 "freeing msi interrupt %d.\n", i);
2821 }
2822 }
2823 }
2824 ql_disable_msix(qdev);
2825}
2826
2827static int ql_request_irq(struct ql_adapter *qdev)
2828{
2829 int i;
2830 int status = 0;
2831 struct pci_dev *pdev = qdev->pdev;
2832 struct intr_context *intr_context = &qdev->intr_context[0];
2833
2834 ql_resolve_queues_to_irqs(qdev);
2835
2836 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2837 atomic_set(&intr_context->irq_cnt, 0);
2838 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2839 status = request_irq(qdev->msi_x_entry[i].vector,
2840 intr_context->handler,
2841 0,
2842 intr_context->name,
2843 &qdev->rx_ring[i]);
2844 if (status) {
2845 QPRINTK(qdev, IFUP, ERR,
2846 "Failed request for MSIX interrupt %d.\n",
2847 i);
2848 goto err_irq;
2849 } else {
2850 QPRINTK(qdev, IFUP, INFO,
2851 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2852 i,
2853 qdev->rx_ring[i].type ==
2854 DEFAULT_Q ? "DEFAULT_Q" : "",
2855 qdev->rx_ring[i].type ==
2856 TX_Q ? "TX_Q" : "",
2857 qdev->rx_ring[i].type ==
2858 RX_Q ? "RX_Q" : "", intr_context->name);
2859 }
2860 } else {
2861 QPRINTK(qdev, IFUP, DEBUG,
2862 "trying msi or legacy interrupts.\n");
2863 QPRINTK(qdev, IFUP, DEBUG,
2864 "%s: irq = %d.\n", __func__, pdev->irq);
2865 QPRINTK(qdev, IFUP, DEBUG,
2866 "%s: context->name = %s.\n", __func__,
2867 intr_context->name);
2868 QPRINTK(qdev, IFUP, DEBUG,
2869 "%s: dev_id = 0x%p.\n", __func__,
2870 &qdev->rx_ring[0]);
2871 status =
2872 request_irq(pdev->irq, qlge_isr,
2873 test_bit(QL_MSI_ENABLED,
2874 &qdev->
2875 flags) ? 0 : IRQF_SHARED,
2876 intr_context->name, &qdev->rx_ring[0]);
2877 if (status)
2878 goto err_irq;
2879
2880 QPRINTK(qdev, IFUP, ERR,
2881 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2882 i,
2883 qdev->rx_ring[0].type ==
2884 DEFAULT_Q ? "DEFAULT_Q" : "",
2885 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2886 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2887 intr_context->name);
2888 }
2889 intr_context->hooked = 1;
2890 }
2891 return status;
2892err_irq:
2893 QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2894 ql_free_irq(qdev);
2895 return status;
2896}
2897
2898static int ql_start_rss(struct ql_adapter *qdev)
2899{
2900 struct ricb *ricb = &qdev->ricb;
2901 int status = 0;
2902 int i;
2903 u8 *hash_id = (u8 *) ricb->hash_cq_id;
2904
2905 memset((void *)ricb, 0, sizeof(ricb));
2906
2907 ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2908 ricb->flags =
2909 (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2910 RSS_RT6);
2911 ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2912
2913 /*
2914 * Fill out the Indirection Table.
2915 */
2916 for (i = 0; i < 32; i++)
2917 hash_id[i] = i & 1;
2918
2919 /*
2920 * Random values for the IPv6 and IPv4 Hash Keys.
2921 */
2922 get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2923 get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2924
2925 QPRINTK(qdev, IFUP, INFO, "Initializing RSS.\n");
2926
2927 status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2928 if (status) {
2929 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2930 return status;
2931 }
2932 QPRINTK(qdev, IFUP, INFO, "Successfully loaded RICB.\n");
2933 return status;
2934}
2935
2936/* Initialize the frame-to-queue routing. */
2937static int ql_route_initialize(struct ql_adapter *qdev)
2938{
2939 int status = 0;
2940 int i;
2941
2942 /* Clear all the entries in the routing table. */
2943 for (i = 0; i < 16; i++) {
2944 status = ql_set_routing_reg(qdev, i, 0, 0);
2945 if (status) {
2946 QPRINTK(qdev, IFUP, ERR,
2947 "Failed to init routing register for CAM packets.\n");
2948 return status;
2949 }
2950 }
2951
2952 status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
2953 if (status) {
2954 QPRINTK(qdev, IFUP, ERR,
2955 "Failed to init routing register for error packets.\n");
2956 return status;
2957 }
2958 status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
2959 if (status) {
2960 QPRINTK(qdev, IFUP, ERR,
2961 "Failed to init routing register for broadcast packets.\n");
2962 return status;
2963 }
2964 /* If we have more than one inbound queue, then turn on RSS in the
2965 * routing block.
2966 */
2967 if (qdev->rss_ring_count > 1) {
2968 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
2969 RT_IDX_RSS_MATCH, 1);
2970 if (status) {
2971 QPRINTK(qdev, IFUP, ERR,
2972 "Failed to init routing register for MATCH RSS packets.\n");
2973 return status;
2974 }
2975 }
2976
2977 status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
2978 RT_IDX_CAM_HIT, 1);
2979 if (status) {
2980 QPRINTK(qdev, IFUP, ERR,
2981 "Failed to init routing register for CAM packets.\n");
2982 return status;
2983 }
2984 return status;
2985}
2986
2987static int ql_adapter_initialize(struct ql_adapter *qdev)
2988{
2989 u32 value, mask;
2990 int i;
2991 int status = 0;
2992
2993 /*
2994 * Set up the System register to halt on errors.
2995 */
2996 value = SYS_EFE | SYS_FAE;
2997 mask = value << 16;
2998 ql_write32(qdev, SYS, mask | value);
2999
3000 /* Set the default queue. */
3001 value = NIC_RCV_CFG_DFQ;
3002 mask = NIC_RCV_CFG_DFQ_MASK;
3003 ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3004
3005 /* Set the MPI interrupt to enabled. */
3006 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3007
3008 /* Enable the function, set pagesize, enable error checking. */
3009 value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3010 FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3011
3012 /* Set/clear header splitting. */
3013 mask = FSC_VM_PAGESIZE_MASK |
3014 FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3015 ql_write32(qdev, FSC, mask | value);
3016
3017 ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3018 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3019
3020 /* Start up the rx queues. */
3021 for (i = 0; i < qdev->rx_ring_count; i++) {
3022 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3023 if (status) {
3024 QPRINTK(qdev, IFUP, ERR,
3025 "Failed to start rx ring[%d].\n", i);
3026 return status;
3027 }
3028 }
3029
3030 /* If there is more than one inbound completion queue
3031 * then download a RICB to configure RSS.
3032 */
3033 if (qdev->rss_ring_count > 1) {
3034 status = ql_start_rss(qdev);
3035 if (status) {
3036 QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3037 return status;
3038 }
3039 }
3040
3041 /* Start up the tx queues. */
3042 for (i = 0; i < qdev->tx_ring_count; i++) {
3043 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3044 if (status) {
3045 QPRINTK(qdev, IFUP, ERR,
3046 "Failed to start tx ring[%d].\n", i);
3047 return status;
3048 }
3049 }
3050
3051 status = ql_port_initialize(qdev);
3052 if (status) {
3053 QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3054 return status;
3055 }
3056
3057 status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3058 MAC_ADDR_TYPE_CAM_MAC, qdev->func);
3059 if (status) {
3060 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3061 return status;
3062 }
3063
3064 status = ql_route_initialize(qdev);
3065 if (status) {
3066 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3067 return status;
3068 }
3069
3070 /* Start NAPI for the RSS queues. */
3071 for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3072 QPRINTK(qdev, IFUP, INFO, "Enabling NAPI for rx_ring[%d].\n",
3073 i);
3074 napi_enable(&qdev->rx_ring[i].napi);
3075 }
3076
3077 return status;
3078}
3079
3080/* Issue soft reset to chip. */
3081static int ql_adapter_reset(struct ql_adapter *qdev)
3082{
3083 u32 value;
3084 int max_wait_time;
3085 int status = 0;
3086 int resetCnt = 0;
3087
3088#define MAX_RESET_CNT 1
3089issueReset:
3090 resetCnt++;
3091 QPRINTK(qdev, IFDOWN, DEBUG, "Issue soft reset to chip.\n");
3092 ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3093 /* Wait for reset to complete. */
3094 max_wait_time = 3;
3095 QPRINTK(qdev, IFDOWN, DEBUG, "Wait %d seconds for reset to complete.\n",
3096 max_wait_time);
3097 do {
3098 value = ql_read32(qdev, RST_FO);
3099 if ((value & RST_FO_FR) == 0)
3100 break;
3101
3102 ssleep(1);
3103 } while ((--max_wait_time));
3104 if (value & RST_FO_FR) {
3105 QPRINTK(qdev, IFDOWN, ERR,
3106 "Stuck in SoftReset: FSC_SR:0x%08x\n", value);
3107 if (resetCnt < MAX_RESET_CNT)
3108 goto issueReset;
3109 }
3110 if (max_wait_time == 0) {
3111 status = -ETIMEDOUT;
3112 QPRINTK(qdev, IFDOWN, ERR,
3113 "ETIMEOUT!!! errored out of resetting the chip!\n");
3114 }
3115
3116 return status;
3117}
3118
3119static void ql_display_dev_info(struct net_device *ndev)
3120{
3121 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3122
3123 QPRINTK(qdev, PROBE, INFO,
3124 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3125 "XG Roll = %d, XG Rev = %d.\n",
3126 qdev->func,
3127 qdev->chip_rev_id & 0x0000000f,
3128 qdev->chip_rev_id >> 4 & 0x0000000f,
3129 qdev->chip_rev_id >> 8 & 0x0000000f,
3130 qdev->chip_rev_id >> 12 & 0x0000000f);
7c510e4b 3131 QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
c4e84bde
RM		 3132}
3133
3134static int ql_adapter_down(struct ql_adapter *qdev)
3135{
3136 struct net_device *ndev = qdev->ndev;
3137 int i, status = 0;
3138 struct rx_ring *rx_ring;
3139
3140 netif_stop_queue(ndev);
3141 netif_carrier_off(ndev);
3142
3143 cancel_delayed_work_sync(&qdev->asic_reset_work);
3144 cancel_delayed_work_sync(&qdev->mpi_reset_work);
3145 cancel_delayed_work_sync(&qdev->mpi_work);
3146
3147 /* The default queue at index 0 is always processed in
3148 * a workqueue.
3149 */
3150 cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3151
3152 /* The rest of the rx_rings are processed in
3153 * a workqueue only if it's a single interrupt
3154 * environment (MSI/Legacy).
3155 */
c062076c 3156 for (i = 1; i < qdev->rx_ring_count; i++) {
c4e84bde
RM		 3157 rx_ring = &qdev->rx_ring[i];
3158 /* Only the RSS rings use NAPI on multi irq
3159 * environment. Outbound completion processing
3160 * is done in interrupt context.
3161 */
3162 if (i >= qdev->rss_ring_first_cq_id) {
3163 napi_disable(&rx_ring->napi);
3164 } else {
3165 cancel_delayed_work_sync(&rx_ring->rx_work);
3166 }
3167 }
3168
3169 clear_bit(QL_ADAPTER_UP, &qdev->flags);
3170
3171 ql_disable_interrupts(qdev);
3172
3173 ql_tx_ring_clean(qdev);
3174
3175 spin_lock(&qdev->hw_lock);
3176 status = ql_adapter_reset(qdev);
3177 if (status)
3178 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3179 qdev->func);
3180 spin_unlock(&qdev->hw_lock);
3181 return status;
3182}
3183
3184static int ql_adapter_up(struct ql_adapter *qdev)
3185{
3186 int err = 0;
3187
3188 spin_lock(&qdev->hw_lock);
3189 err = ql_adapter_initialize(qdev);
3190 if (err) {
3191 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3192 spin_unlock(&qdev->hw_lock);
3193 goto err_init;
3194 }
3195 spin_unlock(&qdev->hw_lock);
3196 set_bit(QL_ADAPTER_UP, &qdev->flags);
3197 ql_enable_interrupts(qdev);
3198 ql_enable_all_completion_interrupts(qdev);
3199 if ((ql_read32(qdev, STS) & qdev->port_init)) {
3200 netif_carrier_on(qdev->ndev);
3201 netif_start_queue(qdev->ndev);
3202 }
3203
3204 return 0;
3205err_init:
3206 ql_adapter_reset(qdev);
3207 return err;
3208}
3209
3210static int ql_cycle_adapter(struct ql_adapter *qdev)
3211{
3212 int status;
3213
3214 status = ql_adapter_down(qdev);
3215 if (status)
3216 goto error;
3217
3218 status = ql_adapter_up(qdev);
3219 if (status)
3220 goto error;
3221
3222 return status;
3223error:
3224 QPRINTK(qdev, IFUP, ALERT,
3225 "Driver up/down cycle failed, closing device\n");
3226 rtnl_lock();
3227 dev_close(qdev->ndev);
3228 rtnl_unlock();
3229 return status;
3230}
3231
3232static void ql_release_adapter_resources(struct ql_adapter *qdev)
3233{
3234 ql_free_mem_resources(qdev);
3235 ql_free_irq(qdev);
3236}
3237
3238static int ql_get_adapter_resources(struct ql_adapter *qdev)
3239{
3240 int status = 0;
3241
3242 if (ql_alloc_mem_resources(qdev)) {
3243 QPRINTK(qdev, IFUP, ERR, "Unable to allocate memory.\n");
3244 return -ENOMEM;
3245 }
3246 status = ql_request_irq(qdev);
3247 if (status)
3248 goto err_irq;
3249 return status;
3250err_irq:
3251 ql_free_mem_resources(qdev);
3252 return status;
3253}
3254
3255static int qlge_close(struct net_device *ndev)
3256{
3257 struct ql_adapter *qdev = netdev_priv(ndev);
3258
3259 /*
3260 * Wait for device to recover from a reset.
3261 * (Rarely happens, but possible.)
3262 */
3263 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3264 msleep(1);
3265 ql_adapter_down(qdev);
3266 ql_release_adapter_resources(qdev);
3267 ql_free_ring_cb(qdev);
3268 return 0;
3269}
3270
3271static int ql_configure_rings(struct ql_adapter *qdev)
3272{
3273 int i;
3274 struct rx_ring *rx_ring;
3275 struct tx_ring *tx_ring;
3276 int cpu_cnt = num_online_cpus();
3277
3278 /*
3279 * For each processor present we allocate one
3280 * rx_ring for outbound completions, and one
3281 * rx_ring for inbound completions. Plus there is
3282 * always the one default queue. For the CPU
3283 * counts we end up with the following rx_rings:
3284 * rx_ring count =
3285 * one default queue +
3286 * (CPU count * outbound completion rx_ring) +
3287 * (CPU count * inbound (RSS) completion rx_ring)
3288 * To keep it simple we limit the total number of
3289 * queues to < 32, so we truncate CPU to 8.
3290 * This limitation can be removed when requested.
3291 */
3292
3293 if (cpu_cnt > 8)
3294 cpu_cnt = 8;
3295
3296 /*
3297 * rx_ring[0] is always the default queue.
3298 */
3299 /* Allocate outbound completion ring for each CPU. */
3300 qdev->tx_ring_count = cpu_cnt;
3301 /* Allocate inbound completion (RSS) ring for each CPU. */
3302 qdev->rss_ring_count = cpu_cnt;
3303 /* cq_id for the first inbound ring handler. */
3304 qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3305 /*
3306 * qdev->rx_ring_count:
3307 * Total number of rx_rings. This includes the one
3308 * default queue, a number of outbound completion
3309 * handler rx_rings, and the number of inbound
3310 * completion handler rx_rings.
3311 */
3312 qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3313
3314 if (ql_alloc_ring_cb(qdev))
3315 return -ENOMEM;
3316
3317 for (i = 0; i < qdev->tx_ring_count; i++) {
3318 tx_ring = &qdev->tx_ring[i];
3319 memset((void *)tx_ring, 0, sizeof(tx_ring));
3320 tx_ring->qdev = qdev;
3321 tx_ring->wq_id = i;
3322 tx_ring->wq_len = qdev->tx_ring_size;
3323 tx_ring->wq_size =
3324 tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3325
3326 /*
3327 * The completion queue ID for the tx rings start
3328 * immediately after the default Q ID, which is zero.
3329 */
3330 tx_ring->cq_id = i + 1;
3331 }
3332
3333 for (i = 0; i < qdev->rx_ring_count; i++) {
3334 rx_ring = &qdev->rx_ring[i];
3335 memset((void *)rx_ring, 0, sizeof(rx_ring));
3336 rx_ring->qdev = qdev;
3337 rx_ring->cq_id = i;
3338 rx_ring->cpu = i % cpu_cnt; /* CPU to run handler on. */
3339 if (i == 0) { /* Default queue at index 0. */
3340 /*
3341 * Default queue handles bcast/mcast plus
3342 * async events. Needs buffers.
3343 */
3344 rx_ring->cq_len = qdev->rx_ring_size;
3345 rx_ring->cq_size =
3346 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3347 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3348 rx_ring->lbq_size =
3349 rx_ring->lbq_len * sizeof(struct bq_element);
3350 rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3351 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3352 rx_ring->sbq_size =
3353 rx_ring->sbq_len * sizeof(struct bq_element);
3354 rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3355 rx_ring->type = DEFAULT_Q;
3356 } else if (i < qdev->rss_ring_first_cq_id) {
3357 /*
3358 * Outbound queue handles outbound completions only.
3359 */
3360 /* outbound cq is same size as tx_ring it services. */
3361 rx_ring->cq_len = qdev->tx_ring_size;
3362 rx_ring->cq_size =
3363 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3364 rx_ring->lbq_len = 0;
3365 rx_ring->lbq_size = 0;
3366 rx_ring->lbq_buf_size = 0;
3367 rx_ring->sbq_len = 0;
3368 rx_ring->sbq_size = 0;
3369 rx_ring->sbq_buf_size = 0;
3370 rx_ring->type = TX_Q;
3371 } else { /* Inbound completions (RSS) queues */
3372 /*
3373 * Inbound queues handle unicast frames only.
3374 */
3375 rx_ring->cq_len = qdev->rx_ring_size;
3376 rx_ring->cq_size =
3377 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3378 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3379 rx_ring->lbq_size =
3380 rx_ring->lbq_len * sizeof(struct bq_element);
3381 rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3382 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3383 rx_ring->sbq_size =
3384 rx_ring->sbq_len * sizeof(struct bq_element);
3385 rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3386 rx_ring->type = RX_Q;
3387 }
3388 }
3389 return 0;
3390}
3391
3392static int qlge_open(struct net_device *ndev)
3393{
3394 int err = 0;
3395 struct ql_adapter *qdev = netdev_priv(ndev);
3396
3397 err = ql_configure_rings(qdev);
3398 if (err)
3399 return err;
3400
3401 err = ql_get_adapter_resources(qdev);
3402 if (err)
3403 goto error_up;
3404
3405 err = ql_adapter_up(qdev);
3406 if (err)
3407 goto error_up;
3408
3409 return err;
3410
3411error_up:
3412 ql_release_adapter_resources(qdev);
3413 ql_free_ring_cb(qdev);
3414 return err;
3415}
3416
3417static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3418{
3419 struct ql_adapter *qdev = netdev_priv(ndev);
3420
3421 if (ndev->mtu == 1500 && new_mtu == 9000) {
3422 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3423 } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3424 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3425 } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3426 (ndev->mtu == 9000 && new_mtu == 9000)) {
3427 return 0;
3428 } else
3429 return -EINVAL;
3430 ndev->mtu = new_mtu;
3431 return 0;
3432}
3433
3434static struct net_device_stats *qlge_get_stats(struct net_device
3435 *ndev)
3436{
3437 struct ql_adapter *qdev = netdev_priv(ndev);
3438 return &qdev->stats;
3439}
3440
3441static void qlge_set_multicast_list(struct net_device *ndev)
3442{
3443 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3444 struct dev_mc_list *mc_ptr;
3445 int i;
3446
3447 spin_lock(&qdev->hw_lock);
3448 /*
3449 * Set or clear promiscuous mode if a
3450 * transition is taking place.
3451 */
3452 if (ndev->flags & IFF_PROMISC) {
3453 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3454 if (ql_set_routing_reg
3455 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3456 QPRINTK(qdev, HW, ERR,
3457 "Failed to set promiscous mode.\n");
3458 } else {
3459 set_bit(QL_PROMISCUOUS, &qdev->flags);
3460 }
3461 }
3462 } else {
3463 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3464 if (ql_set_routing_reg
3465 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3466 QPRINTK(qdev, HW, ERR,
3467 "Failed to clear promiscous mode.\n");
3468 } else {
3469 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3470 }
3471 }
3472 }
3473
3474 /*
3475 * Set or clear all multicast mode if a
3476 * transition is taking place.
3477 */
3478 if ((ndev->flags & IFF_ALLMULTI) ||
3479 (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3480 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3481 if (ql_set_routing_reg
3482 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3483 QPRINTK(qdev, HW, ERR,
3484 "Failed to set all-multi mode.\n");
3485 } else {
3486 set_bit(QL_ALLMULTI, &qdev->flags);
3487 }
3488 }
3489 } else {
3490 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3491 if (ql_set_routing_reg
3492 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3493 QPRINTK(qdev, HW, ERR,
3494 "Failed to clear all-multi mode.\n");
3495 } else {
3496 clear_bit(QL_ALLMULTI, &qdev->flags);
3497 }
3498 }
3499 }
3500
3501 if (ndev->mc_count) {
3502 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3503 i++, mc_ptr = mc_ptr->next)
3504 if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3505 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3506 QPRINTK(qdev, HW, ERR,
3507 "Failed to loadmulticast address.\n");
3508 goto exit;
3509 }
3510 if (ql_set_routing_reg
3511 (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3512 QPRINTK(qdev, HW, ERR,
3513 "Failed to set multicast match mode.\n");
3514 } else {
3515 set_bit(QL_ALLMULTI, &qdev->flags);
3516 }
3517 }
3518exit:
3519 spin_unlock(&qdev->hw_lock);
3520}
3521
3522static int qlge_set_mac_address(struct net_device *ndev, void *p)
3523{
3524 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3525 struct sockaddr *addr = p;
8668ae92 3526 int ret = 0;
c4e84bde
RM		 3527
3528 if (netif_running(ndev))
3529 return -EBUSY;
3530
3531 if (!is_valid_ether_addr(addr->sa_data))
3532 return -EADDRNOTAVAIL;
3533 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3534
3535 spin_lock(&qdev->hw_lock);
3536 if (ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3537 MAC_ADDR_TYPE_CAM_MAC, qdev->func)) {/* Unicast */
3538 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
8668ae92 3539 ret = -1;
c4e84bde
RM		 3540 }
3541 spin_unlock(&qdev->hw_lock);
3542
8668ae92 3543 return ret;
c4e84bde
RM		 3544}
3545
3546static void qlge_tx_timeout(struct net_device *ndev)
3547{
3548 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3549 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
3550}
3551
3552static void ql_asic_reset_work(struct work_struct *work)
3553{
3554 struct ql_adapter *qdev =
3555 container_of(work, struct ql_adapter, asic_reset_work.work);
3556 ql_cycle_adapter(qdev);
3557}
3558
3559static void ql_get_board_info(struct ql_adapter *qdev)
3560{
3561 qdev->func =
3562 (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3563 if (qdev->func) {
3564 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3565 qdev->port_link_up = STS_PL1;
3566 qdev->port_init = STS_PI1;
3567 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3568 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3569 } else {
3570 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3571 qdev->port_link_up = STS_PL0;
3572 qdev->port_init = STS_PI0;
3573 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3574 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3575 }
3576 qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3577}
3578
3579static void ql_release_all(struct pci_dev *pdev)
3580{
3581 struct net_device *ndev = pci_get_drvdata(pdev);
3582 struct ql_adapter *qdev = netdev_priv(ndev);
3583
3584 if (qdev->workqueue) {
3585 destroy_workqueue(qdev->workqueue);
3586 qdev->workqueue = NULL;
3587 }
3588 if (qdev->q_workqueue) {
3589 destroy_workqueue(qdev->q_workqueue);
3590 qdev->q_workqueue = NULL;
3591 }
3592 if (qdev->reg_base)
8668ae92 3593 iounmap(qdev->reg_base);
c4e84bde
RM		 3594 if (qdev->doorbell_area)
3595 iounmap(qdev->doorbell_area);
3596 pci_release_regions(pdev);
3597 pci_set_drvdata(pdev, NULL);
3598}
3599
3600static int __devinit ql_init_device(struct pci_dev *pdev,
3601 struct net_device *ndev, int cards_found)
3602{
3603 struct ql_adapter *qdev = netdev_priv(ndev);
3604 int pos, err = 0;
3605 u16 val16;
3606
3607 memset((void *)qdev, 0, sizeof(qdev));
3608 err = pci_enable_device(pdev);
3609 if (err) {
3610 dev_err(&pdev->dev, "PCI device enable failed.\n");
3611 return err;
3612 }
3613
3614 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3615 if (pos <= 0) {
3616 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3617 "aborting.\n");
3618 goto err_out;
3619 } else {
3620 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3621 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3622 val16 |= (PCI_EXP_DEVCTL_CERE |
3623 PCI_EXP_DEVCTL_NFERE |
3624 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3625 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3626 }
3627
3628 err = pci_request_regions(pdev, DRV_NAME);
3629 if (err) {
3630 dev_err(&pdev->dev, "PCI region request failed.\n");
3631 goto err_out;
3632 }
3633
3634 pci_set_master(pdev);
3635 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3636 set_bit(QL_DMA64, &qdev->flags);
3637 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3638 } else {
3639 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3640 if (!err)
3641 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3642 }
3643
3644 if (err) {
3645 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3646 goto err_out;
3647 }
3648
3649 pci_set_drvdata(pdev, ndev);
3650 qdev->reg_base =
3651 ioremap_nocache(pci_resource_start(pdev, 1),
3652 pci_resource_len(pdev, 1));
3653 if (!qdev->reg_base) {
3654 dev_err(&pdev->dev, "Register mapping failed.\n");
3655 err = -ENOMEM;
3656 goto err_out;
3657 }
3658
3659 qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3660 qdev->doorbell_area =
3661 ioremap_nocache(pci_resource_start(pdev, 3),
3662 pci_resource_len(pdev, 3));
3663 if (!qdev->doorbell_area) {
3664 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3665 err = -ENOMEM;
3666 goto err_out;
3667 }
3668
3669 ql_get_board_info(qdev);
3670 qdev->ndev = ndev;
3671 qdev->pdev = pdev;
3672 qdev->msg_enable = netif_msg_init(debug, default_msg);
3673 spin_lock_init(&qdev->hw_lock);
3674 spin_lock_init(&qdev->stats_lock);
3675
3676 /* make sure the EEPROM is good */
3677 err = ql_get_flash_params(qdev);
3678 if (err) {
3679 dev_err(&pdev->dev, "Invalid FLASH.\n");
3680 goto err_out;
3681 }
3682
3683 if (!is_valid_ether_addr(qdev->flash.mac_addr))
3684 goto err_out;
3685
3686 memcpy(ndev->dev_addr, qdev->flash.mac_addr, ndev->addr_len);
3687 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3688
3689 /* Set up the default ring sizes. */
3690 qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3691 qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3692
3693 /* Set up the coalescing parameters. */
3694 qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3695 qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3696 qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3697 qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3698
3699 /*
3700 * Set up the operating parameters.
3701 */
3702 qdev->rx_csum = 1;
3703
3704 qdev->q_workqueue = create_workqueue(ndev->name);
3705 qdev->workqueue = create_singlethread_workqueue(ndev->name);
3706 INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3707 INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3708 INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3709
3710 if (!cards_found) {
3711 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3712 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3713 DRV_NAME, DRV_VERSION);
3714 }
3715 return 0;
3716err_out:
3717 ql_release_all(pdev);
3718 pci_disable_device(pdev);
3719 return err;
3720}
3721
25ed7849
SH		 3722
3723static const struct net_device_ops qlge_netdev_ops = {
3724 .ndo_open = qlge_open,
3725 .ndo_stop = qlge_close,
3726 .ndo_start_xmit = qlge_send,
3727 .ndo_change_mtu = qlge_change_mtu,
3728 .ndo_get_stats = qlge_get_stats,
3729 .ndo_set_multicast_list = qlge_set_multicast_list,
3730 .ndo_set_mac_address = qlge_set_mac_address,
3731 .ndo_validate_addr = eth_validate_addr,
3732 .ndo_tx_timeout = qlge_tx_timeout,
3733 .ndo_vlan_rx_register = ql_vlan_rx_register,
3734 .ndo_vlan_rx_add_vid = ql_vlan_rx_add_vid,
3735 .ndo_vlan_rx_kill_vid = ql_vlan_rx_kill_vid,
3736};
3737
c4e84bde
RM		 3738static int __devinit qlge_probe(struct pci_dev *pdev,
3739 const struct pci_device_id *pci_entry)
3740{
3741 struct net_device *ndev = NULL;
3742 struct ql_adapter *qdev = NULL;
3743 static int cards_found = 0;
3744 int err = 0;
3745
3746 ndev = alloc_etherdev(sizeof(struct ql_adapter));
3747 if (!ndev)
3748 return -ENOMEM;
3749
3750 err = ql_init_device(pdev, ndev, cards_found);
3751 if (err < 0) {
3752 free_netdev(ndev);
3753 return err;
3754 }
3755
3756 qdev = netdev_priv(ndev);
3757 SET_NETDEV_DEV(ndev, &pdev->dev);
3758 ndev->features = (0
3759 | NETIF_F_IP_CSUM
3760 | NETIF_F_SG
3761 | NETIF_F_TSO
3762 | NETIF_F_TSO6
3763 | NETIF_F_TSO_ECN
3764 | NETIF_F_HW_VLAN_TX
3765 | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3766
3767 if (test_bit(QL_DMA64, &qdev->flags))
3768 ndev->features |= NETIF_F_HIGHDMA;
3769
3770 /*
3771 * Set up net_device structure.
3772 */
3773 ndev->tx_queue_len = qdev->tx_ring_size;
3774 ndev->irq = pdev->irq;
25ed7849
SH		 3775
3776 ndev->netdev_ops = &qlge_netdev_ops;
c4e84bde 3777 SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
c4e84bde 3778 ndev->watchdog_timeo = 10 * HZ;
25ed7849 3779
c4e84bde
RM		 3780 err = register_netdev(ndev);
3781 if (err) {
3782 dev_err(&pdev->dev, "net device registration failed.\n");
3783 ql_release_all(pdev);
3784 pci_disable_device(pdev);
3785 return err;
3786 }
3787 netif_carrier_off(ndev);
3788 netif_stop_queue(ndev);
3789 ql_display_dev_info(ndev);
3790 cards_found++;
3791 return 0;
3792}
3793
3794static void __devexit qlge_remove(struct pci_dev *pdev)
3795{
3796 struct net_device *ndev = pci_get_drvdata(pdev);
3797 unregister_netdev(ndev);
3798 ql_release_all(pdev);
3799 pci_disable_device(pdev);
3800 free_netdev(ndev);
3801}
3802
3803/*
3804 * This callback is called by the PCI subsystem whenever
3805 * a PCI bus error is detected.
3806 */
3807static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3808 enum pci_channel_state state)
3809{
3810 struct net_device *ndev = pci_get_drvdata(pdev);
3811 struct ql_adapter *qdev = netdev_priv(ndev);
3812
3813 if (netif_running(ndev))
3814 ql_adapter_down(qdev);
3815
3816 pci_disable_device(pdev);
3817
3818 /* Request a slot reset. */
3819 return PCI_ERS_RESULT_NEED_RESET;
3820}
3821
3822/*
3823 * This callback is called after the PCI buss has been reset.
3824 * Basically, this tries to restart the card from scratch.
3825 * This is a shortened version of the device probe/discovery code,
3826 * it resembles the first-half of the () routine.
3827 */
3828static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3829{
3830 struct net_device *ndev = pci_get_drvdata(pdev);
3831 struct ql_adapter *qdev = netdev_priv(ndev);
3832
3833 if (pci_enable_device(pdev)) {
3834 QPRINTK(qdev, IFUP, ERR,
3835 "Cannot re-enable PCI device after reset.\n");
3836 return PCI_ERS_RESULT_DISCONNECT;
3837 }
3838
3839 pci_set_master(pdev);
3840
3841 netif_carrier_off(ndev);
3842 netif_stop_queue(ndev);
3843 ql_adapter_reset(qdev);
3844
3845 /* Make sure the EEPROM is good */
3846 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3847
3848 if (!is_valid_ether_addr(ndev->perm_addr)) {
3849 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3850 return PCI_ERS_RESULT_DISCONNECT;
3851 }
3852
3853 return PCI_ERS_RESULT_RECOVERED;
3854}
3855
3856static void qlge_io_resume(struct pci_dev *pdev)
3857{
3858 struct net_device *ndev = pci_get_drvdata(pdev);
3859 struct ql_adapter *qdev = netdev_priv(ndev);
3860
3861 pci_set_master(pdev);
3862
3863 if (netif_running(ndev)) {
3864 if (ql_adapter_up(qdev)) {
3865 QPRINTK(qdev, IFUP, ERR,
3866 "Device initialization failed after reset.\n");
3867 return;
3868 }
3869 }
3870
3871 netif_device_attach(ndev);
3872}
3873
3874static struct pci_error_handlers qlge_err_handler = {
3875 .error_detected = qlge_io_error_detected,
3876 .slot_reset = qlge_io_slot_reset,
3877 .resume = qlge_io_resume,
3878};
3879
3880static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3881{
3882 struct net_device *ndev = pci_get_drvdata(pdev);
3883 struct ql_adapter *qdev = netdev_priv(ndev);
3884 int err;
3885
3886 netif_device_detach(ndev);
3887
3888 if (netif_running(ndev)) {
3889 err = ql_adapter_down(qdev);
3890 if (!err)
3891 return err;
3892 }
3893
3894 err = pci_save_state(pdev);
3895 if (err)
3896 return err;
3897
3898 pci_disable_device(pdev);
3899
3900 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3901
3902 return 0;
3903}
3904
04da2cf9 3905#ifdef CONFIG_PM
c4e84bde
RM		 3906static int qlge_resume(struct pci_dev *pdev)
3907{
3908 struct net_device *ndev = pci_get_drvdata(pdev);
3909 struct ql_adapter *qdev = netdev_priv(ndev);
3910 int err;
3911
3912 pci_set_power_state(pdev, PCI_D0);
3913 pci_restore_state(pdev);
3914 err = pci_enable_device(pdev);
3915 if (err) {
3916 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
3917 return err;
3918 }
3919 pci_set_master(pdev);
3920
3921 pci_enable_wake(pdev, PCI_D3hot, 0);
3922 pci_enable_wake(pdev, PCI_D3cold, 0);
3923
3924 if (netif_running(ndev)) {
3925 err = ql_adapter_up(qdev);
3926 if (err)
3927 return err;
3928 }
3929
3930 netif_device_attach(ndev);
3931
3932 return 0;
3933}
04da2cf9 3934#endif /* CONFIG_PM */
c4e84bde
RM		 3935
3936static void qlge_shutdown(struct pci_dev *pdev)
3937{
3938 qlge_suspend(pdev, PMSG_SUSPEND);
3939}
3940
3941static struct pci_driver qlge_driver = {
3942 .name = DRV_NAME,
3943 .id_table = qlge_pci_tbl,
3944 .probe = qlge_probe,
3945 .remove = __devexit_p(qlge_remove),
3946#ifdef CONFIG_PM
3947 .suspend = qlge_suspend,
3948 .resume = qlge_resume,
3949#endif
3950 .shutdown = qlge_shutdown,
3951 .err_handler = &qlge_err_handler
3952};
3953
3954static int __init qlge_init_module(void)
3955{
3956 return pci_register_driver(&qlge_driver);
3957}
3958
3959static void __exit qlge_exit(void)
3960{
3961 pci_unregister_driver(&qlge_driver);
3962}
3963
3964module_init(qlge_init_module);
3965module_exit(qlge_exit);
Linux kernel - Deliverables
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