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qlge: Add support for firmware mailbox commands.
[deliverable/linux.git] / drivers / net / qlge / qlge_main.c
CommitLineData
c4e84bde
RM		 1/*
2 * QLogic qlge NIC HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 * See LICENSE.qlge for copyright and licensing details.
5 * Author: Linux qlge network device driver by
6 * Ron Mercer <ron.mercer@qlogic.com>
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/list.h>
13#include <linux/pci.h>
14#include <linux/dma-mapping.h>
15#include <linux/pagemap.h>
16#include <linux/sched.h>
17#include <linux/slab.h>
18#include <linux/dmapool.h>
19#include <linux/mempool.h>
20#include <linux/spinlock.h>
21#include <linux/kthread.h>
22#include <linux/interrupt.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/in.h>
26#include <linux/ip.h>
27#include <linux/ipv6.h>
28#include <net/ipv6.h>
29#include <linux/tcp.h>
30#include <linux/udp.h>
31#include <linux/if_arp.h>
32#include <linux/if_ether.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/skbuff.h>
37#include <linux/rtnetlink.h>
38#include <linux/if_vlan.h>
c4e84bde
RM		 39#include <linux/delay.h>
40#include <linux/mm.h>
41#include <linux/vmalloc.h>
b7c6bfb7 42#include <net/ip6_checksum.h>
c4e84bde
RM		 43
44#include "qlge.h"
45
46char qlge_driver_name[] = DRV_NAME;
47const char qlge_driver_version[] = DRV_VERSION;
48
49MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50MODULE_DESCRIPTION(DRV_STRING " ");
51MODULE_LICENSE("GPL");
52MODULE_VERSION(DRV_VERSION);
53
54static const u32 default_msg =
55 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
56/* NETIF_MSG_TIMER | */
57 NETIF_MSG_IFDOWN |
58 NETIF_MSG_IFUP |
59 NETIF_MSG_RX_ERR |
60 NETIF_MSG_TX_ERR |
4974097a
RM		 61/* NETIF_MSG_TX_QUEUED | */
62/* NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
c4e84bde
RM		 63/* NETIF_MSG_PKTDATA | */
64 NETIF_MSG_HW | NETIF_MSG_WOL | 0;
65
66static int debug = 0x00007fff; /* defaults above */
67module_param(debug, int, 0);
68MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
69
70#define MSIX_IRQ 0
71#define MSI_IRQ 1
72#define LEG_IRQ 2
73static int irq_type = MSIX_IRQ;
74module_param(irq_type, int, MSIX_IRQ);
75MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
76
77static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
b0c2aadf 78 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
c4e84bde
RM		 79 /* required last entry */
80 {0,}
81};
82
83MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
84
85/* This hardware semaphore causes exclusive access to
86 * resources shared between the NIC driver, MPI firmware,
87 * FCOE firmware and the FC driver.
88 */
89static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
90{
91 u32 sem_bits = 0;
92
93 switch (sem_mask) {
94 case SEM_XGMAC0_MASK:
95 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
96 break;
97 case SEM_XGMAC1_MASK:
98 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
99 break;
100 case SEM_ICB_MASK:
101 sem_bits = SEM_SET << SEM_ICB_SHIFT;
102 break;
103 case SEM_MAC_ADDR_MASK:
104 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
105 break;
106 case SEM_FLASH_MASK:
107 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
108 break;
109 case SEM_PROBE_MASK:
110 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
111 break;
112 case SEM_RT_IDX_MASK:
113 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
114 break;
115 case SEM_PROC_REG_MASK:
116 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
117 break;
118 default:
119 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
120 return -EINVAL;
121 }
122
123 ql_write32(qdev, SEM, sem_bits | sem_mask);
124 return !(ql_read32(qdev, SEM) & sem_bits);
125}
126
127int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
128{
0857e9d7 129 unsigned int wait_count = 30;
c4e84bde
RM		 130 do {
131 if (!ql_sem_trylock(qdev, sem_mask))
132 return 0;
0857e9d7
RM		 133 udelay(100);
134 } while (--wait_count);
c4e84bde
RM		 135 return -ETIMEDOUT;
136}
137
138void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
139{
140 ql_write32(qdev, SEM, sem_mask);
141 ql_read32(qdev, SEM); /* flush */
142}
143
144/* This function waits for a specific bit to come ready
145 * in a given register. It is used mostly by the initialize
146 * process, but is also used in kernel thread API such as
147 * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
148 */
149int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
150{
151 u32 temp;
152 int count = UDELAY_COUNT;
153
154 while (count) {
155 temp = ql_read32(qdev, reg);
156
157 /* check for errors */
158 if (temp & err_bit) {
159 QPRINTK(qdev, PROBE, ALERT,
160 "register 0x%.08x access error, value = 0x%.08x!.\n",
161 reg, temp);
162 return -EIO;
163 } else if (temp & bit)
164 return 0;
165 udelay(UDELAY_DELAY);
166 count--;
167 }
168 QPRINTK(qdev, PROBE, ALERT,
169 "Timed out waiting for reg %x to come ready.\n", reg);
170 return -ETIMEDOUT;
171}
172
173/* The CFG register is used to download TX and RX control blocks
174 * to the chip. This function waits for an operation to complete.
175 */
176static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
177{
178 int count = UDELAY_COUNT;
179 u32 temp;
180
181 while (count) {
182 temp = ql_read32(qdev, CFG);
183 if (temp & CFG_LE)
184 return -EIO;
185 if (!(temp & bit))
186 return 0;
187 udelay(UDELAY_DELAY);
188 count--;
189 }
190 return -ETIMEDOUT;
191}
192
193
194/* Used to issue init control blocks to hw. Maps control block,
195 * sets address, triggers download, waits for completion.
196 */
197int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
198 u16 q_id)
199{
200 u64 map;
201 int status = 0;
202 int direction;
203 u32 mask;
204 u32 value;
205
206 direction =
207 (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
208 PCI_DMA_FROMDEVICE;
209
210 map = pci_map_single(qdev->pdev, ptr, size, direction);
211 if (pci_dma_mapping_error(qdev->pdev, map)) {
212 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
213 return -ENOMEM;
214 }
215
216 status = ql_wait_cfg(qdev, bit);
217 if (status) {
218 QPRINTK(qdev, IFUP, ERR,
219 "Timed out waiting for CFG to come ready.\n");
220 goto exit;
221 }
222
223 status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
224 if (status)
225 goto exit;
226 ql_write32(qdev, ICB_L, (u32) map);
227 ql_write32(qdev, ICB_H, (u32) (map >> 32));
228 ql_sem_unlock(qdev, SEM_ICB_MASK); /* does flush too */
229
230 mask = CFG_Q_MASK | (bit << 16);
231 value = bit | (q_id << CFG_Q_SHIFT);
232 ql_write32(qdev, CFG, (mask | value));
233
234 /*
235 * Wait for the bit to clear after signaling hw.
236 */
237 status = ql_wait_cfg(qdev, bit);
238exit:
239 pci_unmap_single(qdev->pdev, map, size, direction);
240 return status;
241}
242
243/* Get a specific MAC address from the CAM. Used for debug and reg dump. */
244int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
245 u32 *value)
246{
247 u32 offset = 0;
248 int status;
249
c4e84bde
RM		 250 switch (type) {
251 case MAC_ADDR_TYPE_MULTI_MAC:
252 case MAC_ADDR_TYPE_CAM_MAC:
253 {
254 status =
255 ql_wait_reg_rdy(qdev,
939678f8 256 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 257 if (status)
258 goto exit;
259 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
260 (index << MAC_ADDR_IDX_SHIFT) | /* index */
261 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
262 status =
263 ql_wait_reg_rdy(qdev,
939678f8 264 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
c4e84bde
RM		 265 if (status)
266 goto exit;
267 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
268 status =
269 ql_wait_reg_rdy(qdev,
939678f8 270 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 271 if (status)
272 goto exit;
273 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
274 (index << MAC_ADDR_IDX_SHIFT) | /* index */
275 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
276 status =
277 ql_wait_reg_rdy(qdev,
939678f8 278 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
c4e84bde
RM		 279 if (status)
280 goto exit;
281 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
282 if (type == MAC_ADDR_TYPE_CAM_MAC) {
283 status =
284 ql_wait_reg_rdy(qdev,
939678f8 285 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 286 if (status)
287 goto exit;
288 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
289 (index << MAC_ADDR_IDX_SHIFT) | /* index */
290 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
291 status =
292 ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
939678f8 293 MAC_ADDR_MR, 0);
c4e84bde
RM		 294 if (status)
295 goto exit;
296 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
297 }
298 break;
299 }
300 case MAC_ADDR_TYPE_VLAN:
301 case MAC_ADDR_TYPE_MULTI_FLTR:
302 default:
303 QPRINTK(qdev, IFUP, CRIT,
304 "Address type %d not yet supported.\n", type);
305 status = -EPERM;
306 }
307exit:
c4e84bde
RM		 308 return status;
309}
310
311/* Set up a MAC, multicast or VLAN address for the
312 * inbound frame matching.
313 */
314static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
315 u16 index)
316{
317 u32 offset = 0;
318 int status = 0;
319
c4e84bde
RM		 320 switch (type) {
321 case MAC_ADDR_TYPE_MULTI_MAC:
322 case MAC_ADDR_TYPE_CAM_MAC:
323 {
324 u32 cam_output;
325 u32 upper = (addr[0] << 8) | addr[1];
326 u32 lower =
327 (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
328 (addr[5]);
329
4974097a 330 QPRINTK(qdev, IFUP, DEBUG,
7c510e4b 331 "Adding %s address %pM"
c4e84bde
RM		 332 " at index %d in the CAM.\n",
333 ((type ==
334 MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
7c510e4b 335 "UNICAST"), addr, index);
c4e84bde
RM		 336
337 status =
338 ql_wait_reg_rdy(qdev,
939678f8 339 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 340 if (status)
341 goto exit;
342 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
343 (index << MAC_ADDR_IDX_SHIFT) | /* index */
344 type); /* type */
345 ql_write32(qdev, MAC_ADDR_DATA, lower);
346 status =
347 ql_wait_reg_rdy(qdev,
939678f8 348 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 349 if (status)
350 goto exit;
351 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
352 (index << MAC_ADDR_IDX_SHIFT) | /* index */
353 type); /* type */
354 ql_write32(qdev, MAC_ADDR_DATA, upper);
355 status =
356 ql_wait_reg_rdy(qdev,
939678f8 357 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 358 if (status)
359 goto exit;
360 ql_write32(qdev, MAC_ADDR_IDX, (offset) | /* offset */
361 (index << MAC_ADDR_IDX_SHIFT) | /* index */
362 type); /* type */
363 /* This field should also include the queue id
364 and possibly the function id. Right now we hardcode
365 the route field to NIC core.
366 */
367 if (type == MAC_ADDR_TYPE_CAM_MAC) {
368 cam_output = (CAM_OUT_ROUTE_NIC |
369 (qdev->
370 func << CAM_OUT_FUNC_SHIFT) |
371 (qdev->
372 rss_ring_first_cq_id <<
373 CAM_OUT_CQ_ID_SHIFT));
374 if (qdev->vlgrp)
375 cam_output |= CAM_OUT_RV;
376 /* route to NIC core */
377 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
378 }
379 break;
380 }
381 case MAC_ADDR_TYPE_VLAN:
382 {
383 u32 enable_bit = *((u32 *) &addr[0]);
384 /* For VLAN, the addr actually holds a bit that
385 * either enables or disables the vlan id we are
386 * addressing. It's either MAC_ADDR_E on or off.
387 * That's bit-27 we're talking about.
388 */
389 QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
390 (enable_bit ? "Adding" : "Removing"),
391 index, (enable_bit ? "to" : "from"));
392
393 status =
394 ql_wait_reg_rdy(qdev,
939678f8 395 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 396 if (status)
397 goto exit;
398 ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
399 (index << MAC_ADDR_IDX_SHIFT) | /* index */
400 type | /* type */
401 enable_bit); /* enable/disable */
402 break;
403 }
404 case MAC_ADDR_TYPE_MULTI_FLTR:
405 default:
406 QPRINTK(qdev, IFUP, CRIT,
407 "Address type %d not yet supported.\n", type);
408 status = -EPERM;
409 }
410exit:
c4e84bde
RM		 411 return status;
412}
413
414/* Get a specific frame routing value from the CAM.
415 * Used for debug and reg dump.
416 */
417int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
418{
419 int status = 0;
420
939678f8 421 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
c4e84bde
RM		 422 if (status)
423 goto exit;
424
425 ql_write32(qdev, RT_IDX,
426 RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
939678f8 427 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
c4e84bde
RM		 428 if (status)
429 goto exit;
430 *value = ql_read32(qdev, RT_DATA);
431exit:
c4e84bde
RM		 432 return status;
433}
434
435/* The NIC function for this chip has 16 routing indexes. Each one can be used
436 * to route different frame types to various inbound queues. We send broadcast/
437 * multicast/error frames to the default queue for slow handling,
438 * and CAM hit/RSS frames to the fast handling queues.
439 */
440static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
441 int enable)
442{
8587ea35 443 int status = -EINVAL; /* Return error if no mask match. */
c4e84bde
RM		 444 u32 value = 0;
445
c4e84bde
RM		 446 QPRINTK(qdev, IFUP, DEBUG,
447 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
448 (enable ? "Adding" : "Removing"),
449 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
450 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
451 ((index ==
452 RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
453 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
454 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
455 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
456 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
457 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
458 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
459 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
460 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
461 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
462 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
463 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
464 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
465 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
466 (enable ? "to" : "from"));
467
468 switch (mask) {
469 case RT_IDX_CAM_HIT:
470 {
471 value = RT_IDX_DST_CAM_Q | /* dest */
472 RT_IDX_TYPE_NICQ | /* type */
473 (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
474 break;
475 }
476 case RT_IDX_VALID: /* Promiscuous Mode frames. */
477 {
478 value = RT_IDX_DST_DFLT_Q | /* dest */
479 RT_IDX_TYPE_NICQ | /* type */
480 (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
481 break;
482 }
483 case RT_IDX_ERR: /* Pass up MAC,IP,TCP/UDP error frames. */
484 {
485 value = RT_IDX_DST_DFLT_Q | /* dest */
486 RT_IDX_TYPE_NICQ | /* type */
487 (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
488 break;
489 }
490 case RT_IDX_BCAST: /* Pass up Broadcast frames to default Q. */
491 {
492 value = RT_IDX_DST_DFLT_Q | /* dest */
493 RT_IDX_TYPE_NICQ | /* type */
494 (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
495 break;
496 }
497 case RT_IDX_MCAST: /* Pass up All Multicast frames. */
498 {
499 value = RT_IDX_DST_CAM_Q | /* dest */
500 RT_IDX_TYPE_NICQ | /* type */
501 (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
502 break;
503 }
504 case RT_IDX_MCAST_MATCH: /* Pass up matched Multicast frames. */
505 {
506 value = RT_IDX_DST_CAM_Q | /* dest */
507 RT_IDX_TYPE_NICQ | /* type */
508 (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
509 break;
510 }
511 case RT_IDX_RSS_MATCH: /* Pass up matched RSS frames. */
512 {
513 value = RT_IDX_DST_RSS | /* dest */
514 RT_IDX_TYPE_NICQ | /* type */
515 (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
516 break;
517 }
518 case 0: /* Clear the E-bit on an entry. */
519 {
520 value = RT_IDX_DST_DFLT_Q | /* dest */
521 RT_IDX_TYPE_NICQ | /* type */
522 (index << RT_IDX_IDX_SHIFT);/* index */
523 break;
524 }
525 default:
526 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
527 mask);
528 status = -EPERM;
529 goto exit;
530 }
531
532 if (value) {
533 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
534 if (status)
535 goto exit;
536 value |= (enable ? RT_IDX_E : 0);
537 ql_write32(qdev, RT_IDX, value);
538 ql_write32(qdev, RT_DATA, enable ? mask : 0);
539 }
540exit:
c4e84bde
RM		 541 return status;
542}
543
544static void ql_enable_interrupts(struct ql_adapter *qdev)
545{
546 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
547}
548
549static void ql_disable_interrupts(struct ql_adapter *qdev)
550{
551 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
552}
553
554/* If we're running with multiple MSI-X vectors then we enable on the fly.
555 * Otherwise, we may have multiple outstanding workers and don't want to
556 * enable until the last one finishes. In this case, the irq_cnt gets
557 * incremented everytime we queue a worker and decremented everytime
558 * a worker finishes. Once it hits zero we enable the interrupt.
559 */
bb0d215c 560u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
c4e84bde 561{
bb0d215c
RM		 562 u32 var = 0;
563 unsigned long hw_flags = 0;
564 struct intr_context *ctx = qdev->intr_context + intr;
565
566 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
567 /* Always enable if we're MSIX multi interrupts and
568 * it's not the default (zeroeth) interrupt.
569 */
c4e84bde 570 ql_write32(qdev, INTR_EN,
bb0d215c
RM		 571 ctx->intr_en_mask);
572 var = ql_read32(qdev, STS);
573 return var;
c4e84bde 574 }
bb0d215c
RM		 575
576 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
577 if (atomic_dec_and_test(&ctx->irq_cnt)) {
578 ql_write32(qdev, INTR_EN,
579 ctx->intr_en_mask);
580 var = ql_read32(qdev, STS);
581 }
582 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
583 return var;
c4e84bde
RM		 584}
585
586static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
587{
588 u32 var = 0;
bb0d215c
RM		 589 unsigned long hw_flags;
590 struct intr_context *ctx;
c4e84bde 591
bb0d215c
RM		 592 /* HW disables for us if we're MSIX multi interrupts and
593 * it's not the default (zeroeth) interrupt.
594 */
595 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
596 return 0;
597
598 ctx = qdev->intr_context + intr;
599 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
600 if (!atomic_read(&ctx->irq_cnt)) {
c4e84bde 601 ql_write32(qdev, INTR_EN,
bb0d215c 602 ctx->intr_dis_mask);
c4e84bde
RM		 603 var = ql_read32(qdev, STS);
604 }
bb0d215c
RM		 605 atomic_inc(&ctx->irq_cnt);
606 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
c4e84bde
RM		 607 return var;
608}
609
610static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
611{
612 int i;
613 for (i = 0; i < qdev->intr_count; i++) {
614 /* The enable call does a atomic_dec_and_test
615 * and enables only if the result is zero.
616 * So we precharge it here.
617 */
bb0d215c
RM		 618 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
619 i == 0))
620 atomic_set(&qdev->intr_context[i].irq_cnt, 1);
c4e84bde
RM		 621 ql_enable_completion_interrupt(qdev, i);
622 }
623
624}
625
b0c2aadf
RM		 626static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
627{
628 int status, i;
629 u16 csum = 0;
630 __le16 *flash = (__le16 *)&qdev->flash;
631
632 status = strncmp((char *)&qdev->flash, str, 4);
633 if (status) {
634 QPRINTK(qdev, IFUP, ERR, "Invalid flash signature.\n");
635 return status;
636 }
637
638 for (i = 0; i < size; i++)
639 csum += le16_to_cpu(*flash++);
640
641 if (csum)
642 QPRINTK(qdev, IFUP, ERR,
643 "Invalid flash checksum, csum = 0x%.04x.\n", csum);
644
645 return csum;
646}
647
26351479 648static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
c4e84bde
RM		 649{
650 int status = 0;
651 /* wait for reg to come ready */
652 status = ql_wait_reg_rdy(qdev,
653 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
654 if (status)
655 goto exit;
656 /* set up for reg read */
657 ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
658 /* wait for reg to come ready */
659 status = ql_wait_reg_rdy(qdev,
660 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
661 if (status)
662 goto exit;
26351479
RM		 663 /* This data is stored on flash as an array of
664 * __le32. Since ql_read32() returns cpu endian
665 * we need to swap it back.
666 */
667 *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
c4e84bde
RM		 668exit:
669 return status;
670}
671
b0c2aadf 672static int ql_get_8012_flash_params(struct ql_adapter *qdev)
c4e84bde
RM		 673{
674 int i;
675 int status;
26351479 676 __le32 *p = (__le32 *)&qdev->flash;
e78f5fa7 677 u32 offset = 0;
b0c2aadf 678 u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
e78f5fa7
RM		 679
680 /* Second function's parameters follow the first
681 * function's.
682 */
683 if (qdev->func)
b0c2aadf 684 offset = size;
c4e84bde
RM		 685
686 if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
687 return -ETIMEDOUT;
688
b0c2aadf 689 for (i = 0; i < size; i++, p++) {
e78f5fa7 690 status = ql_read_flash_word(qdev, i+offset, p);
c4e84bde
RM		 691 if (status) {
692 QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
693 goto exit;
694 }
695
696 }
b0c2aadf
RM		 697
698 status = ql_validate_flash(qdev,
699 sizeof(struct flash_params_8012) / sizeof(u16),
700 "8012");
701 if (status) {
702 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
703 status = -EINVAL;
704 goto exit;
705 }
706
707 if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
708 status = -EINVAL;
709 goto exit;
710 }
711
712 memcpy(qdev->ndev->dev_addr,
713 qdev->flash.flash_params_8012.mac_addr,
714 qdev->ndev->addr_len);
715
c4e84bde
RM		 716exit:
717 ql_sem_unlock(qdev, SEM_FLASH_MASK);
718 return status;
719}
720
721/* xgmac register are located behind the xgmac_addr and xgmac_data
722 * register pair. Each read/write requires us to wait for the ready
723 * bit before reading/writing the data.
724 */
725static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
726{
727 int status;
728 /* wait for reg to come ready */
729 status = ql_wait_reg_rdy(qdev,
730 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
731 if (status)
732 return status;
733 /* write the data to the data reg */
734 ql_write32(qdev, XGMAC_DATA, data);
735 /* trigger the write */
736 ql_write32(qdev, XGMAC_ADDR, reg);
737 return status;
738}
739
740/* xgmac register are located behind the xgmac_addr and xgmac_data
741 * register pair. Each read/write requires us to wait for the ready
742 * bit before reading/writing the data.
743 */
744int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
745{
746 int status = 0;
747 /* wait for reg to come ready */
748 status = ql_wait_reg_rdy(qdev,
749 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
750 if (status)
751 goto exit;
752 /* set up for reg read */
753 ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
754 /* wait for reg to come ready */
755 status = ql_wait_reg_rdy(qdev,
756 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
757 if (status)
758 goto exit;
759 /* get the data */
760 *data = ql_read32(qdev, XGMAC_DATA);
761exit:
762 return status;
763}
764
765/* This is used for reading the 64-bit statistics regs. */
766int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
767{
768 int status = 0;
769 u32 hi = 0;
770 u32 lo = 0;
771
772 status = ql_read_xgmac_reg(qdev, reg, &lo);
773 if (status)
774 goto exit;
775
776 status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
777 if (status)
778 goto exit;
779
780 *data = (u64) lo | ((u64) hi << 32);
781
782exit:
783 return status;
784}
785
786/* Take the MAC Core out of reset.
787 * Enable statistics counting.
788 * Take the transmitter/receiver out of reset.
789 * This functionality may be done in the MPI firmware at a
790 * later date.
791 */
b0c2aadf 792static int ql_8012_port_initialize(struct ql_adapter *qdev)
c4e84bde
RM		 793{
794 int status = 0;
795 u32 data;
796
797 if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
798 /* Another function has the semaphore, so
799 * wait for the port init bit to come ready.
800 */
801 QPRINTK(qdev, LINK, INFO,
802 "Another function has the semaphore, so wait for the port init bit to come ready.\n");
803 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
804 if (status) {
805 QPRINTK(qdev, LINK, CRIT,
806 "Port initialize timed out.\n");
807 }
808 return status;
809 }
810
811 QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
812 /* Set the core reset. */
813 status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
814 if (status)
815 goto end;
816 data |= GLOBAL_CFG_RESET;
817 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
818 if (status)
819 goto end;
820
821 /* Clear the core reset and turn on jumbo for receiver. */
822 data &= ~GLOBAL_CFG_RESET; /* Clear core reset. */
823 data |= GLOBAL_CFG_JUMBO; /* Turn on jumbo. */
824 data |= GLOBAL_CFG_TX_STAT_EN;
825 data |= GLOBAL_CFG_RX_STAT_EN;
826 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
827 if (status)
828 goto end;
829
830 /* Enable transmitter, and clear it's reset. */
831 status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
832 if (status)
833 goto end;
834 data &= ~TX_CFG_RESET; /* Clear the TX MAC reset. */
835 data |= TX_CFG_EN; /* Enable the transmitter. */
836 status = ql_write_xgmac_reg(qdev, TX_CFG, data);
837 if (status)
838 goto end;
839
840 /* Enable receiver and clear it's reset. */
841 status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
842 if (status)
843 goto end;
844 data &= ~RX_CFG_RESET; /* Clear the RX MAC reset. */
845 data |= RX_CFG_EN; /* Enable the receiver. */
846 status = ql_write_xgmac_reg(qdev, RX_CFG, data);
847 if (status)
848 goto end;
849
850 /* Turn on jumbo. */
851 status =
852 ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
853 if (status)
854 goto end;
855 status =
856 ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
857 if (status)
858 goto end;
859
860 /* Signal to the world that the port is enabled. */
861 ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
862end:
863 ql_sem_unlock(qdev, qdev->xg_sem_mask);
864 return status;
865}
866
867/* Get the next large buffer. */
8668ae92 868static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
c4e84bde
RM		 869{
870 struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
871 rx_ring->lbq_curr_idx++;
872 if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
873 rx_ring->lbq_curr_idx = 0;
874 rx_ring->lbq_free_cnt++;
875 return lbq_desc;
876}
877
878/* Get the next small buffer. */
8668ae92 879static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
c4e84bde
RM		 880{
881 struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
882 rx_ring->sbq_curr_idx++;
883 if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
884 rx_ring->sbq_curr_idx = 0;
885 rx_ring->sbq_free_cnt++;
886 return sbq_desc;
887}
888
889/* Update an rx ring index. */
890static void ql_update_cq(struct rx_ring *rx_ring)
891{
892 rx_ring->cnsmr_idx++;
893 rx_ring->curr_entry++;
894 if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
895 rx_ring->cnsmr_idx = 0;
896 rx_ring->curr_entry = rx_ring->cq_base;
897 }
898}
899
900static void ql_write_cq_idx(struct rx_ring *rx_ring)
901{
902 ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
903}
904
905/* Process (refill) a large buffer queue. */
906static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
907{
49f2186d
RM		 908 u32 clean_idx = rx_ring->lbq_clean_idx;
909 u32 start_idx = clean_idx;
c4e84bde 910 struct bq_desc *lbq_desc;
c4e84bde
RM		 911 u64 map;
912 int i;
913
914 while (rx_ring->lbq_free_cnt > 16) {
915 for (i = 0; i < 16; i++) {
916 QPRINTK(qdev, RX_STATUS, DEBUG,
917 "lbq: try cleaning clean_idx = %d.\n",
918 clean_idx);
919 lbq_desc = &rx_ring->lbq[clean_idx];
c4e84bde
RM		 920 if (lbq_desc->p.lbq_page == NULL) {
921 QPRINTK(qdev, RX_STATUS, DEBUG,
922 "lbq: getting new page for index %d.\n",
923 lbq_desc->index);
924 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
925 if (lbq_desc->p.lbq_page == NULL) {
79d2b29e 926 rx_ring->lbq_clean_idx = clean_idx;
c4e84bde
RM		 927 QPRINTK(qdev, RX_STATUS, ERR,
928 "Couldn't get a page.\n");
929 return;
930 }
931 map = pci_map_page(qdev->pdev,
932 lbq_desc->p.lbq_page,
933 0, PAGE_SIZE,
934 PCI_DMA_FROMDEVICE);
935 if (pci_dma_mapping_error(qdev->pdev, map)) {
79d2b29e 936 rx_ring->lbq_clean_idx = clean_idx;
f2603c2c
RM		 937 put_page(lbq_desc->p.lbq_page);
938 lbq_desc->p.lbq_page = NULL;
c4e84bde
RM		 939 QPRINTK(qdev, RX_STATUS, ERR,
940 "PCI mapping failed.\n");
941 return;
942 }
943 pci_unmap_addr_set(lbq_desc, mapaddr, map);
944 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
2c9a0d41 945 *lbq_desc->addr = cpu_to_le64(map);
c4e84bde
RM		 946 }
947 clean_idx++;
948 if (clean_idx == rx_ring->lbq_len)
949 clean_idx = 0;
950 }
951
952 rx_ring->lbq_clean_idx = clean_idx;
953 rx_ring->lbq_prod_idx += 16;
954 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
955 rx_ring->lbq_prod_idx = 0;
49f2186d
RM		 956 rx_ring->lbq_free_cnt -= 16;
957 }
958
959 if (start_idx != clean_idx) {
c4e84bde
RM		 960 QPRINTK(qdev, RX_STATUS, DEBUG,
961 "lbq: updating prod idx = %d.\n",
962 rx_ring->lbq_prod_idx);
963 ql_write_db_reg(rx_ring->lbq_prod_idx,
964 rx_ring->lbq_prod_idx_db_reg);
c4e84bde
RM		 965 }
966}
967
968/* Process (refill) a small buffer queue. */
969static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
970{
49f2186d
RM		 971 u32 clean_idx = rx_ring->sbq_clean_idx;
972 u32 start_idx = clean_idx;
c4e84bde 973 struct bq_desc *sbq_desc;
c4e84bde
RM		 974 u64 map;
975 int i;
976
977 while (rx_ring->sbq_free_cnt > 16) {
978 for (i = 0; i < 16; i++) {
979 sbq_desc = &rx_ring->sbq[clean_idx];
980 QPRINTK(qdev, RX_STATUS, DEBUG,
981 "sbq: try cleaning clean_idx = %d.\n",
982 clean_idx);
c4e84bde
RM		 983 if (sbq_desc->p.skb == NULL) {
984 QPRINTK(qdev, RX_STATUS, DEBUG,
985 "sbq: getting new skb for index %d.\n",
986 sbq_desc->index);
987 sbq_desc->p.skb =
988 netdev_alloc_skb(qdev->ndev,
989 rx_ring->sbq_buf_size);
990 if (sbq_desc->p.skb == NULL) {
991 QPRINTK(qdev, PROBE, ERR,
992 "Couldn't get an skb.\n");
993 rx_ring->sbq_clean_idx = clean_idx;
994 return;
995 }
996 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
997 map = pci_map_single(qdev->pdev,
998 sbq_desc->p.skb->data,
999 rx_ring->sbq_buf_size /
1000 2, PCI_DMA_FROMDEVICE);
c907a35a
RM		 1001 if (pci_dma_mapping_error(qdev->pdev, map)) {
1002 QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
1003 rx_ring->sbq_clean_idx = clean_idx;
06a3d510
RM		 1004 dev_kfree_skb_any(sbq_desc->p.skb);
1005 sbq_desc->p.skb = NULL;
c907a35a
RM		 1006 return;
1007 }
c4e84bde
RM		 1008 pci_unmap_addr_set(sbq_desc, mapaddr, map);
1009 pci_unmap_len_set(sbq_desc, maplen,
1010 rx_ring->sbq_buf_size / 2);
2c9a0d41 1011 *sbq_desc->addr = cpu_to_le64(map);
c4e84bde
RM		 1012 }
1013
1014 clean_idx++;
1015 if (clean_idx == rx_ring->sbq_len)
1016 clean_idx = 0;
1017 }
1018 rx_ring->sbq_clean_idx = clean_idx;
1019 rx_ring->sbq_prod_idx += 16;
1020 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
1021 rx_ring->sbq_prod_idx = 0;
49f2186d
RM		 1022 rx_ring->sbq_free_cnt -= 16;
1023 }
1024
1025 if (start_idx != clean_idx) {
c4e84bde
RM		 1026 QPRINTK(qdev, RX_STATUS, DEBUG,
1027 "sbq: updating prod idx = %d.\n",
1028 rx_ring->sbq_prod_idx);
1029 ql_write_db_reg(rx_ring->sbq_prod_idx,
1030 rx_ring->sbq_prod_idx_db_reg);
c4e84bde
RM		 1031 }
1032}
1033
1034static void ql_update_buffer_queues(struct ql_adapter *qdev,
1035 struct rx_ring *rx_ring)
1036{
1037 ql_update_sbq(qdev, rx_ring);
1038 ql_update_lbq(qdev, rx_ring);
1039}
1040
1041/* Unmaps tx buffers. Can be called from send() if a pci mapping
1042 * fails at some stage, or from the interrupt when a tx completes.
1043 */
1044static void ql_unmap_send(struct ql_adapter *qdev,
1045 struct tx_ring_desc *tx_ring_desc, int mapped)
1046{
1047 int i;
1048 for (i = 0; i < mapped; i++) {
1049 if (i == 0 || (i == 7 && mapped > 7)) {
1050 /*
1051 * Unmap the skb->data area, or the
1052 * external sglist (AKA the Outbound
1053 * Address List (OAL)).
1054 * If its the zeroeth element, then it's
1055 * the skb->data area. If it's the 7th
1056 * element and there is more than 6 frags,
1057 * then its an OAL.
1058 */
1059 if (i == 7) {
1060 QPRINTK(qdev, TX_DONE, DEBUG,
1061 "unmapping OAL area.\n");
1062 }
1063 pci_unmap_single(qdev->pdev,
1064 pci_unmap_addr(&tx_ring_desc->map[i],
1065 mapaddr),
1066 pci_unmap_len(&tx_ring_desc->map[i],
1067 maplen),
1068 PCI_DMA_TODEVICE);
1069 } else {
1070 QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1071 i);
1072 pci_unmap_page(qdev->pdev,
1073 pci_unmap_addr(&tx_ring_desc->map[i],
1074 mapaddr),
1075 pci_unmap_len(&tx_ring_desc->map[i],
1076 maplen), PCI_DMA_TODEVICE);
1077 }
1078 }
1079
1080}
1081
1082/* Map the buffers for this transmit. This will return
1083 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1084 */
1085static int ql_map_send(struct ql_adapter *qdev,
1086 struct ob_mac_iocb_req *mac_iocb_ptr,
1087 struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1088{
1089 int len = skb_headlen(skb);
1090 dma_addr_t map;
1091 int frag_idx, err, map_idx = 0;
1092 struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1093 int frag_cnt = skb_shinfo(skb)->nr_frags;
1094
1095 if (frag_cnt) {
1096 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1097 }
1098 /*
1099 * Map the skb buffer first.
1100 */
1101 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1102
1103 err = pci_dma_mapping_error(qdev->pdev, map);
1104 if (err) {
1105 QPRINTK(qdev, TX_QUEUED, ERR,
1106 "PCI mapping failed with error: %d\n", err);
1107
1108 return NETDEV_TX_BUSY;
1109 }
1110
1111 tbd->len = cpu_to_le32(len);
1112 tbd->addr = cpu_to_le64(map);
1113 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1114 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1115 map_idx++;
1116
1117 /*
1118 * This loop fills the remainder of the 8 address descriptors
1119 * in the IOCB. If there are more than 7 fragments, then the
1120 * eighth address desc will point to an external list (OAL).
1121 * When this happens, the remainder of the frags will be stored
1122 * in this list.
1123 */
1124 for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1125 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1126 tbd++;
1127 if (frag_idx == 6 && frag_cnt > 7) {
1128 /* Let's tack on an sglist.
1129 * Our control block will now
1130 * look like this:
1131 * iocb->seg[0] = skb->data
1132 * iocb->seg[1] = frag[0]
1133 * iocb->seg[2] = frag[1]
1134 * iocb->seg[3] = frag[2]
1135 * iocb->seg[4] = frag[3]
1136 * iocb->seg[5] = frag[4]
1137 * iocb->seg[6] = frag[5]
1138 * iocb->seg[7] = ptr to OAL (external sglist)
1139 * oal->seg[0] = frag[6]
1140 * oal->seg[1] = frag[7]
1141 * oal->seg[2] = frag[8]
1142 * oal->seg[3] = frag[9]
1143 * oal->seg[4] = frag[10]
1144 * etc...
1145 */
1146 /* Tack on the OAL in the eighth segment of IOCB. */
1147 map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1148 sizeof(struct oal),
1149 PCI_DMA_TODEVICE);
1150 err = pci_dma_mapping_error(qdev->pdev, map);
1151 if (err) {
1152 QPRINTK(qdev, TX_QUEUED, ERR,
1153 "PCI mapping outbound address list with error: %d\n",
1154 err);
1155 goto map_error;
1156 }
1157
1158 tbd->addr = cpu_to_le64(map);
1159 /*
1160 * The length is the number of fragments
1161 * that remain to be mapped times the length
1162 * of our sglist (OAL).
1163 */
1164 tbd->len =
1165 cpu_to_le32((sizeof(struct tx_buf_desc) *
1166 (frag_cnt - frag_idx)) | TX_DESC_C);
1167 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1168 map);
1169 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1170 sizeof(struct oal));
1171 tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1172 map_idx++;
1173 }
1174
1175 map =
1176 pci_map_page(qdev->pdev, frag->page,
1177 frag->page_offset, frag->size,
1178 PCI_DMA_TODEVICE);
1179
1180 err = pci_dma_mapping_error(qdev->pdev, map);
1181 if (err) {
1182 QPRINTK(qdev, TX_QUEUED, ERR,
1183 "PCI mapping frags failed with error: %d.\n",
1184 err);
1185 goto map_error;
1186 }
1187
1188 tbd->addr = cpu_to_le64(map);
1189 tbd->len = cpu_to_le32(frag->size);
1190 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1191 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1192 frag->size);
1193
1194 }
1195 /* Save the number of segments we've mapped. */
1196 tx_ring_desc->map_cnt = map_idx;
1197 /* Terminate the last segment. */
1198 tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1199 return NETDEV_TX_OK;
1200
1201map_error:
1202 /*
1203 * If the first frag mapping failed, then i will be zero.
1204 * This causes the unmap of the skb->data area. Otherwise
1205 * we pass in the number of frags that mapped successfully
1206 * so they can be umapped.
1207 */
1208 ql_unmap_send(qdev, tx_ring_desc, map_idx);
1209 return NETDEV_TX_BUSY;
1210}
1211
8668ae92 1212static void ql_realign_skb(struct sk_buff *skb, int len)
c4e84bde
RM		 1213{
1214 void *temp_addr = skb->data;
1215
1216 /* Undo the skb_reserve(skb,32) we did before
1217 * giving to hardware, and realign data on
1218 * a 2-byte boundary.
1219 */
1220 skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1221 skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1222 skb_copy_to_linear_data(skb, temp_addr,
1223 (unsigned int)len);
1224}
1225
1226/*
1227 * This function builds an skb for the given inbound
1228 * completion. It will be rewritten for readability in the near
1229 * future, but for not it works well.
1230 */
1231static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1232 struct rx_ring *rx_ring,
1233 struct ib_mac_iocb_rsp *ib_mac_rsp)
1234{
1235 struct bq_desc *lbq_desc;
1236 struct bq_desc *sbq_desc;
1237 struct sk_buff *skb = NULL;
1238 u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1239 u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1240
1241 /*
1242 * Handle the header buffer if present.
1243 */
1244 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1245 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1246 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1247 /*
1248 * Headers fit nicely into a small buffer.
1249 */
1250 sbq_desc = ql_get_curr_sbuf(rx_ring);
1251 pci_unmap_single(qdev->pdev,
1252 pci_unmap_addr(sbq_desc, mapaddr),
1253 pci_unmap_len(sbq_desc, maplen),
1254 PCI_DMA_FROMDEVICE);
1255 skb = sbq_desc->p.skb;
1256 ql_realign_skb(skb, hdr_len);
1257 skb_put(skb, hdr_len);
1258 sbq_desc->p.skb = NULL;
1259 }
1260
1261 /*
1262 * Handle the data buffer(s).
1263 */
1264 if (unlikely(!length)) { /* Is there data too? */
1265 QPRINTK(qdev, RX_STATUS, DEBUG,
1266 "No Data buffer in this packet.\n");
1267 return skb;
1268 }
1269
1270 if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1271 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1272 QPRINTK(qdev, RX_STATUS, DEBUG,
1273 "Headers in small, data of %d bytes in small, combine them.\n", length);
1274 /*
1275 * Data is less than small buffer size so it's
1276 * stuffed in a small buffer.
1277 * For this case we append the data
1278 * from the "data" small buffer to the "header" small
1279 * buffer.
1280 */
1281 sbq_desc = ql_get_curr_sbuf(rx_ring);
1282 pci_dma_sync_single_for_cpu(qdev->pdev,
1283 pci_unmap_addr
1284 (sbq_desc, mapaddr),
1285 pci_unmap_len
1286 (sbq_desc, maplen),
1287 PCI_DMA_FROMDEVICE);
1288 memcpy(skb_put(skb, length),
1289 sbq_desc->p.skb->data, length);
1290 pci_dma_sync_single_for_device(qdev->pdev,
1291 pci_unmap_addr
1292 (sbq_desc,
1293 mapaddr),
1294 pci_unmap_len
1295 (sbq_desc,
1296 maplen),
1297 PCI_DMA_FROMDEVICE);
1298 } else {
1299 QPRINTK(qdev, RX_STATUS, DEBUG,
1300 "%d bytes in a single small buffer.\n", length);
1301 sbq_desc = ql_get_curr_sbuf(rx_ring);
1302 skb = sbq_desc->p.skb;
1303 ql_realign_skb(skb, length);
1304 skb_put(skb, length);
1305 pci_unmap_single(qdev->pdev,
1306 pci_unmap_addr(sbq_desc,
1307 mapaddr),
1308 pci_unmap_len(sbq_desc,
1309 maplen),
1310 PCI_DMA_FROMDEVICE);
1311 sbq_desc->p.skb = NULL;
1312 }
1313 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1314 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1315 QPRINTK(qdev, RX_STATUS, DEBUG,
1316 "Header in small, %d bytes in large. Chain large to small!\n", length);
1317 /*
1318 * The data is in a single large buffer. We
1319 * chain it to the header buffer's skb and let
1320 * it rip.
1321 */
1322 lbq_desc = ql_get_curr_lbuf(rx_ring);
1323 pci_unmap_page(qdev->pdev,
1324 pci_unmap_addr(lbq_desc,
1325 mapaddr),
1326 pci_unmap_len(lbq_desc, maplen),
1327 PCI_DMA_FROMDEVICE);
1328 QPRINTK(qdev, RX_STATUS, DEBUG,
1329 "Chaining page to skb.\n");
1330 skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1331 0, length);
1332 skb->len += length;
1333 skb->data_len += length;
1334 skb->truesize += length;
1335 lbq_desc->p.lbq_page = NULL;
1336 } else {
1337 /*
1338 * The headers and data are in a single large buffer. We
1339 * copy it to a new skb and let it go. This can happen with
1340 * jumbo mtu on a non-TCP/UDP frame.
1341 */
1342 lbq_desc = ql_get_curr_lbuf(rx_ring);
1343 skb = netdev_alloc_skb(qdev->ndev, length);
1344 if (skb == NULL) {
1345 QPRINTK(qdev, PROBE, DEBUG,
1346 "No skb available, drop the packet.\n");
1347 return NULL;
1348 }
4055c7d4
RM		 1349 pci_unmap_page(qdev->pdev,
1350 pci_unmap_addr(lbq_desc,
1351 mapaddr),
1352 pci_unmap_len(lbq_desc, maplen),
1353 PCI_DMA_FROMDEVICE);
c4e84bde
RM		 1354 skb_reserve(skb, NET_IP_ALIGN);
1355 QPRINTK(qdev, RX_STATUS, DEBUG,
1356 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1357 skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1358 0, length);
1359 skb->len += length;
1360 skb->data_len += length;
1361 skb->truesize += length;
1362 length -= length;
1363 lbq_desc->p.lbq_page = NULL;
1364 __pskb_pull_tail(skb,
1365 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1366 VLAN_ETH_HLEN : ETH_HLEN);
1367 }
1368 } else {
1369 /*
1370 * The data is in a chain of large buffers
1371 * pointed to by a small buffer. We loop
1372 * thru and chain them to the our small header
1373 * buffer's skb.
1374 * frags: There are 18 max frags and our small
1375 * buffer will hold 32 of them. The thing is,
1376 * we'll use 3 max for our 9000 byte jumbo
1377 * frames. If the MTU goes up we could
1378 * eventually be in trouble.
1379 */
1380 int size, offset, i = 0;
2c9a0d41 1381 __le64 *bq, bq_array[8];
c4e84bde
RM		 1382 sbq_desc = ql_get_curr_sbuf(rx_ring);
1383 pci_unmap_single(qdev->pdev,
1384 pci_unmap_addr(sbq_desc, mapaddr),
1385 pci_unmap_len(sbq_desc, maplen),
1386 PCI_DMA_FROMDEVICE);
1387 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1388 /*
1389 * This is an non TCP/UDP IP frame, so
1390 * the headers aren't split into a small
1391 * buffer. We have to use the small buffer
1392 * that contains our sg list as our skb to
1393 * send upstairs. Copy the sg list here to
1394 * a local buffer and use it to find the
1395 * pages to chain.
1396 */
1397 QPRINTK(qdev, RX_STATUS, DEBUG,
1398 "%d bytes of headers & data in chain of large.\n", length);
1399 skb = sbq_desc->p.skb;
1400 bq = &bq_array[0];
1401 memcpy(bq, skb->data, sizeof(bq_array));
1402 sbq_desc->p.skb = NULL;
1403 skb_reserve(skb, NET_IP_ALIGN);
1404 } else {
1405 QPRINTK(qdev, RX_STATUS, DEBUG,
1406 "Headers in small, %d bytes of data in chain of large.\n", length);
2c9a0d41 1407 bq = (__le64 *)sbq_desc->p.skb->data;
c4e84bde
RM		 1408 }
1409 while (length > 0) {
1410 lbq_desc = ql_get_curr_lbuf(rx_ring);
c4e84bde
RM		 1411 pci_unmap_page(qdev->pdev,
1412 pci_unmap_addr(lbq_desc,
1413 mapaddr),
1414 pci_unmap_len(lbq_desc,
1415 maplen),
1416 PCI_DMA_FROMDEVICE);
1417 size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1418 offset = 0;
1419
1420 QPRINTK(qdev, RX_STATUS, DEBUG,
1421 "Adding page %d to skb for %d bytes.\n",
1422 i, size);
1423 skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1424 offset, size);
1425 skb->len += size;
1426 skb->data_len += size;
1427 skb->truesize += size;
1428 length -= size;
1429 lbq_desc->p.lbq_page = NULL;
1430 bq++;
1431 i++;
1432 }
1433 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1434 VLAN_ETH_HLEN : ETH_HLEN);
1435 }
1436 return skb;
1437}
1438
1439/* Process an inbound completion from an rx ring. */
1440static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1441 struct rx_ring *rx_ring,
1442 struct ib_mac_iocb_rsp *ib_mac_rsp)
1443{
1444 struct net_device *ndev = qdev->ndev;
1445 struct sk_buff *skb = NULL;
1446
1447 QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1448
1449 skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1450 if (unlikely(!skb)) {
1451 QPRINTK(qdev, RX_STATUS, DEBUG,
1452 "No skb available, drop packet.\n");
1453 return;
1454 }
1455
1456 prefetch(skb->data);
1457 skb->dev = ndev;
1458 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1459 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1460 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1461 IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1462 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1463 IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1464 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1465 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1466 }
1467 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1468 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1469 }
1470 if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) {
1471 QPRINTK(qdev, RX_STATUS, ERR,
1472 "Bad checksum for this %s packet.\n",
1473 ((ib_mac_rsp->
1474 flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP"));
1475 skb->ip_summed = CHECKSUM_NONE;
1476 } else if (qdev->rx_csum &&
1477 ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ||
1478 ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1479 !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) {
1480 QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n");
1481 skb->ip_summed = CHECKSUM_UNNECESSARY;
1482 }
1483 qdev->stats.rx_packets++;
1484 qdev->stats.rx_bytes += skb->len;
1485 skb->protocol = eth_type_trans(skb, ndev);
0c8dfc83 1486 skb_record_rx_queue(skb, rx_ring - &qdev->rx_ring[0]);
c4e84bde
RM		 1487 if (qdev->vlgrp && (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)) {
1488 QPRINTK(qdev, RX_STATUS, DEBUG,
1489 "Passing a VLAN packet upstream.\n");
7a9deb66 1490 vlan_hwaccel_receive_skb(skb, qdev->vlgrp,
c4e84bde
RM		 1491 le16_to_cpu(ib_mac_rsp->vlan_id));
1492 } else {
1493 QPRINTK(qdev, RX_STATUS, DEBUG,
1494 "Passing a normal packet upstream.\n");
7a9deb66 1495 netif_receive_skb(skb);
c4e84bde 1496 }
c4e84bde
RM		 1497}
1498
1499/* Process an outbound completion from an rx ring. */
1500static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1501 struct ob_mac_iocb_rsp *mac_rsp)
1502{
1503 struct tx_ring *tx_ring;
1504 struct tx_ring_desc *tx_ring_desc;
1505
1506 QL_DUMP_OB_MAC_RSP(mac_rsp);
1507 tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1508 tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1509 ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1510 qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1511 qdev->stats.tx_packets++;
1512 dev_kfree_skb(tx_ring_desc->skb);
1513 tx_ring_desc->skb = NULL;
1514
1515 if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1516 OB_MAC_IOCB_RSP_S |
1517 OB_MAC_IOCB_RSP_L |
1518 OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1519 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1520 QPRINTK(qdev, TX_DONE, WARNING,
1521 "Total descriptor length did not match transfer length.\n");
1522 }
1523 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1524 QPRINTK(qdev, TX_DONE, WARNING,
1525 "Frame too short to be legal, not sent.\n");
1526 }
1527 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1528 QPRINTK(qdev, TX_DONE, WARNING,
1529 "Frame too long, but sent anyway.\n");
1530 }
1531 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1532 QPRINTK(qdev, TX_DONE, WARNING,
1533 "PCI backplane error. Frame not sent.\n");
1534 }
1535 }
1536 atomic_inc(&tx_ring->tx_count);
1537}
1538
1539/* Fire up a handler to reset the MPI processor. */
1540void ql_queue_fw_error(struct ql_adapter *qdev)
1541{
1542 netif_stop_queue(qdev->ndev);
1543 netif_carrier_off(qdev->ndev);
1544 queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1545}
1546
1547void ql_queue_asic_error(struct ql_adapter *qdev)
1548{
1549 netif_stop_queue(qdev->ndev);
1550 netif_carrier_off(qdev->ndev);
1551 ql_disable_interrupts(qdev);
6497b607
RM		 1552 /* Clear adapter up bit to signal the recovery
1553 * process that it shouldn't kill the reset worker
1554 * thread
1555 */
1556 clear_bit(QL_ADAPTER_UP, &qdev->flags);
c4e84bde
RM		 1557 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1558}
1559
1560static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1561 struct ib_ae_iocb_rsp *ib_ae_rsp)
1562{
1563 switch (ib_ae_rsp->event) {
1564 case MGMT_ERR_EVENT:
1565 QPRINTK(qdev, RX_ERR, ERR,
1566 "Management Processor Fatal Error.\n");
1567 ql_queue_fw_error(qdev);
1568 return;
1569
1570 case CAM_LOOKUP_ERR_EVENT:
1571 QPRINTK(qdev, LINK, ERR,
1572 "Multiple CAM hits lookup occurred.\n");
1573 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1574 ql_queue_asic_error(qdev);
1575 return;
1576
1577 case SOFT_ECC_ERROR_EVENT:
1578 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1579 ql_queue_asic_error(qdev);
1580 break;
1581
1582 case PCI_ERR_ANON_BUF_RD:
1583 QPRINTK(qdev, RX_ERR, ERR,
1584 "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1585 ib_ae_rsp->q_id);
1586 ql_queue_asic_error(qdev);
1587 break;
1588
1589 default:
1590 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1591 ib_ae_rsp->event);
1592 ql_queue_asic_error(qdev);
1593 break;
1594 }
1595}
1596
1597static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1598{
1599 struct ql_adapter *qdev = rx_ring->qdev;
ba7cd3ba 1600 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 1601 struct ob_mac_iocb_rsp *net_rsp = NULL;
1602 int count = 0;
1603
1604 /* While there are entries in the completion queue. */
1605 while (prod != rx_ring->cnsmr_idx) {
1606
1607 QPRINTK(qdev, RX_STATUS, DEBUG,
1608 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1609 prod, rx_ring->cnsmr_idx);
1610
1611 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1612 rmb();
1613 switch (net_rsp->opcode) {
1614
1615 case OPCODE_OB_MAC_TSO_IOCB:
1616 case OPCODE_OB_MAC_IOCB:
1617 ql_process_mac_tx_intr(qdev, net_rsp);
1618 break;
1619 default:
1620 QPRINTK(qdev, RX_STATUS, DEBUG,
1621 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1622 net_rsp->opcode);
1623 }
1624 count++;
1625 ql_update_cq(rx_ring);
ba7cd3ba 1626 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 1627 }
1628 ql_write_cq_idx(rx_ring);
1629 if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
1630 struct tx_ring *tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1631 if (atomic_read(&tx_ring->queue_stopped) &&
1632 (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1633 /*
1634 * The queue got stopped because the tx_ring was full.
1635 * Wake it up, because it's now at least 25% empty.
1636 */
1637 netif_wake_queue(qdev->ndev);
1638 }
1639
1640 return count;
1641}
1642
1643static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1644{
1645 struct ql_adapter *qdev = rx_ring->qdev;
ba7cd3ba 1646 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 1647 struct ql_net_rsp_iocb *net_rsp;
1648 int count = 0;
1649
1650 /* While there are entries in the completion queue. */
1651 while (prod != rx_ring->cnsmr_idx) {
1652
1653 QPRINTK(qdev, RX_STATUS, DEBUG,
1654 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1655 prod, rx_ring->cnsmr_idx);
1656
1657 net_rsp = rx_ring->curr_entry;
1658 rmb();
1659 switch (net_rsp->opcode) {
1660 case OPCODE_IB_MAC_IOCB:
1661 ql_process_mac_rx_intr(qdev, rx_ring,
1662 (struct ib_mac_iocb_rsp *)
1663 net_rsp);
1664 break;
1665
1666 case OPCODE_IB_AE_IOCB:
1667 ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1668 net_rsp);
1669 break;
1670 default:
1671 {
1672 QPRINTK(qdev, RX_STATUS, DEBUG,
1673 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1674 net_rsp->opcode);
1675 }
1676 }
1677 count++;
1678 ql_update_cq(rx_ring);
ba7cd3ba 1679 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 1680 if (count == budget)
1681 break;
1682 }
1683 ql_update_buffer_queues(qdev, rx_ring);
1684 ql_write_cq_idx(rx_ring);
1685 return count;
1686}
1687
1688static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1689{
1690 struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1691 struct ql_adapter *qdev = rx_ring->qdev;
1692 int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1693
1694 QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1695 rx_ring->cq_id);
1696
1697 if (work_done < budget) {
288379f0 1698 __napi_complete(napi);
c4e84bde
RM		 1699 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1700 }
1701 return work_done;
1702}
1703
1704static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1705{
1706 struct ql_adapter *qdev = netdev_priv(ndev);
1707
1708 qdev->vlgrp = grp;
1709 if (grp) {
1710 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1711 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1712 NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1713 } else {
1714 QPRINTK(qdev, IFUP, DEBUG,
1715 "Turning off VLAN in NIC_RCV_CFG.\n");
1716 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1717 }
1718}
1719
1720static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1721{
1722 struct ql_adapter *qdev = netdev_priv(ndev);
1723 u32 enable_bit = MAC_ADDR_E;
cc288f54 1724 int status;
c4e84bde 1725
cc288f54
RM		 1726 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1727 if (status)
1728 return;
c4e84bde
RM		 1729 spin_lock(&qdev->hw_lock);
1730 if (ql_set_mac_addr_reg
1731 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1732 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1733 }
1734 spin_unlock(&qdev->hw_lock);
cc288f54 1735 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
c4e84bde
RM		 1736}
1737
1738static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1739{
1740 struct ql_adapter *qdev = netdev_priv(ndev);
1741 u32 enable_bit = 0;
cc288f54
RM		 1742 int status;
1743
1744 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1745 if (status)
1746 return;
c4e84bde
RM		 1747
1748 spin_lock(&qdev->hw_lock);
1749 if (ql_set_mac_addr_reg
1750 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1751 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1752 }
1753 spin_unlock(&qdev->hw_lock);
cc288f54 1754 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
c4e84bde
RM		 1755
1756}
1757
1758/* Worker thread to process a given rx_ring that is dedicated
1759 * to outbound completions.
1760 */
1761static void ql_tx_clean(struct work_struct *work)
1762{
1763 struct rx_ring *rx_ring =
1764 container_of(work, struct rx_ring, rx_work.work);
1765 ql_clean_outbound_rx_ring(rx_ring);
1766 ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1767
1768}
1769
1770/* Worker thread to process a given rx_ring that is dedicated
1771 * to inbound completions.
1772 */
1773static void ql_rx_clean(struct work_struct *work)
1774{
1775 struct rx_ring *rx_ring =
1776 container_of(work, struct rx_ring, rx_work.work);
1777 ql_clean_inbound_rx_ring(rx_ring, 64);
1778 ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1779}
1780
1781/* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1782static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1783{
1784 struct rx_ring *rx_ring = dev_id;
1785 queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1786 &rx_ring->rx_work, 0);
1787 return IRQ_HANDLED;
1788}
1789
1790/* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1791static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1792{
1793 struct rx_ring *rx_ring = dev_id;
288379f0 1794 napi_schedule(&rx_ring->napi);
c4e84bde
RM		 1795 return IRQ_HANDLED;
1796}
1797
c4e84bde
RM		 1798/* This handles a fatal error, MPI activity, and the default
1799 * rx_ring in an MSI-X multiple vector environment.
1800 * In MSI/Legacy environment it also process the rest of
1801 * the rx_rings.
1802 */
1803static irqreturn_t qlge_isr(int irq, void *dev_id)
1804{
1805 struct rx_ring *rx_ring = dev_id;
1806 struct ql_adapter *qdev = rx_ring->qdev;
1807 struct intr_context *intr_context = &qdev->intr_context[0];
1808 u32 var;
1809 int i;
1810 int work_done = 0;
1811
bb0d215c
RM		 1812 spin_lock(&qdev->hw_lock);
1813 if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1814 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1815 spin_unlock(&qdev->hw_lock);
1816 return IRQ_NONE;
c4e84bde 1817 }
bb0d215c 1818 spin_unlock(&qdev->hw_lock);
c4e84bde 1819
bb0d215c 1820 var = ql_disable_completion_interrupt(qdev, intr_context->intr);
c4e84bde
RM		 1821
1822 /*
1823 * Check for fatal error.
1824 */
1825 if (var & STS_FE) {
1826 ql_queue_asic_error(qdev);
1827 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1828 var = ql_read32(qdev, ERR_STS);
1829 QPRINTK(qdev, INTR, ERR,
1830 "Resetting chip. Error Status Register = 0x%x\n", var);
1831 return IRQ_HANDLED;
1832 }
1833
1834 /*
1835 * Check MPI processor activity.
1836 */
1837 if (var & STS_PI) {
1838 /*
1839 * We've got an async event or mailbox completion.
1840 * Handle it and clear the source of the interrupt.
1841 */
1842 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1843 ql_disable_completion_interrupt(qdev, intr_context->intr);
1844 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1845 &qdev->mpi_work, 0);
1846 work_done++;
1847 }
1848
1849 /*
1850 * Check the default queue and wake handler if active.
1851 */
1852 rx_ring = &qdev->rx_ring[0];
ba7cd3ba 1853 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
c4e84bde
RM		 1854 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1855 ql_disable_completion_interrupt(qdev, intr_context->intr);
1856 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1857 &rx_ring->rx_work, 0);
1858 work_done++;
1859 }
1860
1861 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1862 /*
1863 * Start the DPC for each active queue.
1864 */
1865 for (i = 1; i < qdev->rx_ring_count; i++) {
1866 rx_ring = &qdev->rx_ring[i];
ba7cd3ba 1867 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
c4e84bde
RM		 1868 rx_ring->cnsmr_idx) {
1869 QPRINTK(qdev, INTR, INFO,
1870 "Waking handler for rx_ring[%d].\n", i);
1871 ql_disable_completion_interrupt(qdev,
1872 intr_context->
1873 intr);
1874 if (i < qdev->rss_ring_first_cq_id)
1875 queue_delayed_work_on(rx_ring->cpu,
1876 qdev->q_workqueue,
1877 &rx_ring->rx_work,
1878 0);
1879 else
288379f0 1880 napi_schedule(&rx_ring->napi);
c4e84bde
RM		 1881 work_done++;
1882 }
1883 }
1884 }
bb0d215c 1885 ql_enable_completion_interrupt(qdev, intr_context->intr);
c4e84bde
RM		 1886 return work_done ? IRQ_HANDLED : IRQ_NONE;
1887}
1888
1889static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1890{
1891
1892 if (skb_is_gso(skb)) {
1893 int err;
1894 if (skb_header_cloned(skb)) {
1895 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1896 if (err)
1897 return err;
1898 }
1899
1900 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1901 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1902 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1903 mac_iocb_ptr->total_hdrs_len =
1904 cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1905 mac_iocb_ptr->net_trans_offset =
1906 cpu_to_le16(skb_network_offset(skb) |
1907 skb_transport_offset(skb)
1908 << OB_MAC_TRANSPORT_HDR_SHIFT);
1909 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1910 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1911 if (likely(skb->protocol == htons(ETH_P_IP))) {
1912 struct iphdr *iph = ip_hdr(skb);
1913 iph->check = 0;
1914 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1915 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1916 iph->daddr, 0,
1917 IPPROTO_TCP,
1918 0);
1919 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1920 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
1921 tcp_hdr(skb)->check =
1922 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1923 &ipv6_hdr(skb)->daddr,
1924 0, IPPROTO_TCP, 0);
1925 }
1926 return 1;
1927 }
1928 return 0;
1929}
1930
1931static void ql_hw_csum_setup(struct sk_buff *skb,
1932 struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1933{
1934 int len;
1935 struct iphdr *iph = ip_hdr(skb);
fd2df4f7 1936 __sum16 *check;
c4e84bde
RM		 1937 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1938 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1939 mac_iocb_ptr->net_trans_offset =
1940 cpu_to_le16(skb_network_offset(skb) |
1941 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
1942
1943 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1944 len = (ntohs(iph->tot_len) - (iph->ihl << 2));
1945 if (likely(iph->protocol == IPPROTO_TCP)) {
1946 check = &(tcp_hdr(skb)->check);
1947 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
1948 mac_iocb_ptr->total_hdrs_len =
1949 cpu_to_le16(skb_transport_offset(skb) +
1950 (tcp_hdr(skb)->doff << 2));
1951 } else {
1952 check = &(udp_hdr(skb)->check);
1953 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
1954 mac_iocb_ptr->total_hdrs_len =
1955 cpu_to_le16(skb_transport_offset(skb) +
1956 sizeof(struct udphdr));
1957 }
1958 *check = ~csum_tcpudp_magic(iph->saddr,
1959 iph->daddr, len, iph->protocol, 0);
1960}
1961
1962static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
1963{
1964 struct tx_ring_desc *tx_ring_desc;
1965 struct ob_mac_iocb_req *mac_iocb_ptr;
1966 struct ql_adapter *qdev = netdev_priv(ndev);
1967 int tso;
1968 struct tx_ring *tx_ring;
1969 u32 tx_ring_idx = (u32) QL_TXQ_IDX(qdev, skb);
1970
1971 tx_ring = &qdev->tx_ring[tx_ring_idx];
1972
1973 if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
1974 QPRINTK(qdev, TX_QUEUED, INFO,
1975 "%s: shutting down tx queue %d du to lack of resources.\n",
1976 __func__, tx_ring_idx);
1977 netif_stop_queue(ndev);
1978 atomic_inc(&tx_ring->queue_stopped);
1979 return NETDEV_TX_BUSY;
1980 }
1981 tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
1982 mac_iocb_ptr = tx_ring_desc->queue_entry;
1983 memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
c4e84bde
RM		 1984
1985 mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
1986 mac_iocb_ptr->tid = tx_ring_desc->index;
1987 /* We use the upper 32-bits to store the tx queue for this IO.
1988 * When we get the completion we can use it to establish the context.
1989 */
1990 mac_iocb_ptr->txq_idx = tx_ring_idx;
1991 tx_ring_desc->skb = skb;
1992
1993 mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
1994
1995 if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
1996 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
1997 vlan_tx_tag_get(skb));
1998 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
1999 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
2000 }
2001 tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2002 if (tso < 0) {
2003 dev_kfree_skb_any(skb);
2004 return NETDEV_TX_OK;
2005 } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2006 ql_hw_csum_setup(skb,
2007 (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2008 }
0d979f74
RM		 2009 if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
2010 NETDEV_TX_OK) {
2011 QPRINTK(qdev, TX_QUEUED, ERR,
2012 "Could not map the segments.\n");
2013 return NETDEV_TX_BUSY;
2014 }
c4e84bde
RM		 2015 QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
2016 tx_ring->prod_idx++;
2017 if (tx_ring->prod_idx == tx_ring->wq_len)
2018 tx_ring->prod_idx = 0;
2019 wmb();
2020
2021 ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
2022 ndev->trans_start = jiffies;
2023 QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
2024 tx_ring->prod_idx, skb->len);
2025
2026 atomic_dec(&tx_ring->tx_count);
2027 return NETDEV_TX_OK;
2028}
2029
2030static void ql_free_shadow_space(struct ql_adapter *qdev)
2031{
2032 if (qdev->rx_ring_shadow_reg_area) {
2033 pci_free_consistent(qdev->pdev,
2034 PAGE_SIZE,
2035 qdev->rx_ring_shadow_reg_area,
2036 qdev->rx_ring_shadow_reg_dma);
2037 qdev->rx_ring_shadow_reg_area = NULL;
2038 }
2039 if (qdev->tx_ring_shadow_reg_area) {
2040 pci_free_consistent(qdev->pdev,
2041 PAGE_SIZE,
2042 qdev->tx_ring_shadow_reg_area,
2043 qdev->tx_ring_shadow_reg_dma);
2044 qdev->tx_ring_shadow_reg_area = NULL;
2045 }
2046}
2047
2048static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2049{
2050 qdev->rx_ring_shadow_reg_area =
2051 pci_alloc_consistent(qdev->pdev,
2052 PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2053 if (qdev->rx_ring_shadow_reg_area == NULL) {
2054 QPRINTK(qdev, IFUP, ERR,
2055 "Allocation of RX shadow space failed.\n");
2056 return -ENOMEM;
2057 }
2058 qdev->tx_ring_shadow_reg_area =
2059 pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2060 &qdev->tx_ring_shadow_reg_dma);
2061 if (qdev->tx_ring_shadow_reg_area == NULL) {
2062 QPRINTK(qdev, IFUP, ERR,
2063 "Allocation of TX shadow space failed.\n");
2064 goto err_wqp_sh_area;
2065 }
2066 return 0;
2067
2068err_wqp_sh_area:
2069 pci_free_consistent(qdev->pdev,
2070 PAGE_SIZE,
2071 qdev->rx_ring_shadow_reg_area,
2072 qdev->rx_ring_shadow_reg_dma);
2073 return -ENOMEM;
2074}
2075
2076static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2077{
2078 struct tx_ring_desc *tx_ring_desc;
2079 int i;
2080 struct ob_mac_iocb_req *mac_iocb_ptr;
2081
2082 mac_iocb_ptr = tx_ring->wq_base;
2083 tx_ring_desc = tx_ring->q;
2084 for (i = 0; i < tx_ring->wq_len; i++) {
2085 tx_ring_desc->index = i;
2086 tx_ring_desc->skb = NULL;
2087 tx_ring_desc->queue_entry = mac_iocb_ptr;
2088 mac_iocb_ptr++;
2089 tx_ring_desc++;
2090 }
2091 atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2092 atomic_set(&tx_ring->queue_stopped, 0);
2093}
2094
2095static void ql_free_tx_resources(struct ql_adapter *qdev,
2096 struct tx_ring *tx_ring)
2097{
2098 if (tx_ring->wq_base) {
2099 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2100 tx_ring->wq_base, tx_ring->wq_base_dma);
2101 tx_ring->wq_base = NULL;
2102 }
2103 kfree(tx_ring->q);
2104 tx_ring->q = NULL;
2105}
2106
2107static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2108 struct tx_ring *tx_ring)
2109{
2110 tx_ring->wq_base =
2111 pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2112 &tx_ring->wq_base_dma);
2113
2114 if ((tx_ring->wq_base == NULL)
2115 || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2116 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2117 return -ENOMEM;
2118 }
2119 tx_ring->q =
2120 kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2121 if (tx_ring->q == NULL)
2122 goto err;
2123
2124 return 0;
2125err:
2126 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2127 tx_ring->wq_base, tx_ring->wq_base_dma);
2128 return -ENOMEM;
2129}
2130
8668ae92 2131static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
c4e84bde
RM		 2132{
2133 int i;
2134 struct bq_desc *lbq_desc;
2135
2136 for (i = 0; i < rx_ring->lbq_len; i++) {
2137 lbq_desc = &rx_ring->lbq[i];
2138 if (lbq_desc->p.lbq_page) {
2139 pci_unmap_page(qdev->pdev,
2140 pci_unmap_addr(lbq_desc, mapaddr),
2141 pci_unmap_len(lbq_desc, maplen),
2142 PCI_DMA_FROMDEVICE);
2143
2144 put_page(lbq_desc->p.lbq_page);
2145 lbq_desc->p.lbq_page = NULL;
2146 }
c4e84bde
RM		 2147 }
2148}
2149
8668ae92 2150static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
c4e84bde
RM		 2151{
2152 int i;
2153 struct bq_desc *sbq_desc;
2154
2155 for (i = 0; i < rx_ring->sbq_len; i++) {
2156 sbq_desc = &rx_ring->sbq[i];
2157 if (sbq_desc == NULL) {
2158 QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2159 return;
2160 }
2161 if (sbq_desc->p.skb) {
2162 pci_unmap_single(qdev->pdev,
2163 pci_unmap_addr(sbq_desc, mapaddr),
2164 pci_unmap_len(sbq_desc, maplen),
2165 PCI_DMA_FROMDEVICE);
2166 dev_kfree_skb(sbq_desc->p.skb);
2167 sbq_desc->p.skb = NULL;
2168 }
c4e84bde
RM		 2169 }
2170}
2171
4545a3f2
RM		 2172/* Free all large and small rx buffers associated
2173 * with the completion queues for this device.
2174 */
2175static void ql_free_rx_buffers(struct ql_adapter *qdev)
2176{
2177 int i;
2178 struct rx_ring *rx_ring;
2179
2180 for (i = 0; i < qdev->rx_ring_count; i++) {
2181 rx_ring = &qdev->rx_ring[i];
2182 if (rx_ring->lbq)
2183 ql_free_lbq_buffers(qdev, rx_ring);
2184 if (rx_ring->sbq)
2185 ql_free_sbq_buffers(qdev, rx_ring);
2186 }
2187}
2188
2189static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
2190{
2191 struct rx_ring *rx_ring;
2192 int i;
2193
2194 for (i = 0; i < qdev->rx_ring_count; i++) {
2195 rx_ring = &qdev->rx_ring[i];
2196 if (rx_ring->type != TX_Q)
2197 ql_update_buffer_queues(qdev, rx_ring);
2198 }
2199}
2200
2201static void ql_init_lbq_ring(struct ql_adapter *qdev,
2202 struct rx_ring *rx_ring)
2203{
2204 int i;
2205 struct bq_desc *lbq_desc;
2206 __le64 *bq = rx_ring->lbq_base;
2207
2208 memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
2209 for (i = 0; i < rx_ring->lbq_len; i++) {
2210 lbq_desc = &rx_ring->lbq[i];
2211 memset(lbq_desc, 0, sizeof(*lbq_desc));
2212 lbq_desc->index = i;
2213 lbq_desc->addr = bq;
2214 bq++;
2215 }
2216}
2217
2218static void ql_init_sbq_ring(struct ql_adapter *qdev,
c4e84bde
RM		 2219 struct rx_ring *rx_ring)
2220{
2221 int i;
2222 struct bq_desc *sbq_desc;
2c9a0d41 2223 __le64 *bq = rx_ring->sbq_base;
c4e84bde 2224
4545a3f2 2225 memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
c4e84bde
RM		 2226 for (i = 0; i < rx_ring->sbq_len; i++) {
2227 sbq_desc = &rx_ring->sbq[i];
4545a3f2 2228 memset(sbq_desc, 0, sizeof(*sbq_desc));
c4e84bde 2229 sbq_desc->index = i;
2c9a0d41 2230 sbq_desc->addr = bq;
c4e84bde
RM		 2231 bq++;
2232 }
c4e84bde
RM		 2233}
2234
2235static void ql_free_rx_resources(struct ql_adapter *qdev,
2236 struct rx_ring *rx_ring)
2237{
c4e84bde
RM		 2238 /* Free the small buffer queue. */
2239 if (rx_ring->sbq_base) {
2240 pci_free_consistent(qdev->pdev,
2241 rx_ring->sbq_size,
2242 rx_ring->sbq_base, rx_ring->sbq_base_dma);
2243 rx_ring->sbq_base = NULL;
2244 }
2245
2246 /* Free the small buffer queue control blocks. */
2247 kfree(rx_ring->sbq);
2248 rx_ring->sbq = NULL;
2249
2250 /* Free the large buffer queue. */
2251 if (rx_ring->lbq_base) {
2252 pci_free_consistent(qdev->pdev,
2253 rx_ring->lbq_size,
2254 rx_ring->lbq_base, rx_ring->lbq_base_dma);
2255 rx_ring->lbq_base = NULL;
2256 }
2257
2258 /* Free the large buffer queue control blocks. */
2259 kfree(rx_ring->lbq);
2260 rx_ring->lbq = NULL;
2261
2262 /* Free the rx queue. */
2263 if (rx_ring->cq_base) {
2264 pci_free_consistent(qdev->pdev,
2265 rx_ring->cq_size,
2266 rx_ring->cq_base, rx_ring->cq_base_dma);
2267 rx_ring->cq_base = NULL;
2268 }
2269}
2270
2271/* Allocate queues and buffers for this completions queue based
2272 * on the values in the parameter structure. */
2273static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2274 struct rx_ring *rx_ring)
2275{
2276
2277 /*
2278 * Allocate the completion queue for this rx_ring.
2279 */
2280 rx_ring->cq_base =
2281 pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2282 &rx_ring->cq_base_dma);
2283
2284 if (rx_ring->cq_base == NULL) {
2285 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2286 return -ENOMEM;
2287 }
2288
2289 if (rx_ring->sbq_len) {
2290 /*
2291 * Allocate small buffer queue.
2292 */
2293 rx_ring->sbq_base =
2294 pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2295 &rx_ring->sbq_base_dma);
2296
2297 if (rx_ring->sbq_base == NULL) {
2298 QPRINTK(qdev, IFUP, ERR,
2299 "Small buffer queue allocation failed.\n");
2300 goto err_mem;
2301 }
2302
2303 /*
2304 * Allocate small buffer queue control blocks.
2305 */
2306 rx_ring->sbq =
2307 kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2308 GFP_KERNEL);
2309 if (rx_ring->sbq == NULL) {
2310 QPRINTK(qdev, IFUP, ERR,
2311 "Small buffer queue control block allocation failed.\n");
2312 goto err_mem;
2313 }
2314
4545a3f2 2315 ql_init_sbq_ring(qdev, rx_ring);
c4e84bde
RM		 2316 }
2317
2318 if (rx_ring->lbq_len) {
2319 /*
2320 * Allocate large buffer queue.
2321 */
2322 rx_ring->lbq_base =
2323 pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2324 &rx_ring->lbq_base_dma);
2325
2326 if (rx_ring->lbq_base == NULL) {
2327 QPRINTK(qdev, IFUP, ERR,
2328 "Large buffer queue allocation failed.\n");
2329 goto err_mem;
2330 }
2331 /*
2332 * Allocate large buffer queue control blocks.
2333 */
2334 rx_ring->lbq =
2335 kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2336 GFP_KERNEL);
2337 if (rx_ring->lbq == NULL) {
2338 QPRINTK(qdev, IFUP, ERR,
2339 "Large buffer queue control block allocation failed.\n");
2340 goto err_mem;
2341 }
2342
4545a3f2 2343 ql_init_lbq_ring(qdev, rx_ring);
c4e84bde
RM		 2344 }
2345
2346 return 0;
2347
2348err_mem:
2349 ql_free_rx_resources(qdev, rx_ring);
2350 return -ENOMEM;
2351}
2352
2353static void ql_tx_ring_clean(struct ql_adapter *qdev)
2354{
2355 struct tx_ring *tx_ring;
2356 struct tx_ring_desc *tx_ring_desc;
2357 int i, j;
2358
2359 /*
2360 * Loop through all queues and free
2361 * any resources.
2362 */
2363 for (j = 0; j < qdev->tx_ring_count; j++) {
2364 tx_ring = &qdev->tx_ring[j];
2365 for (i = 0; i < tx_ring->wq_len; i++) {
2366 tx_ring_desc = &tx_ring->q[i];
2367 if (tx_ring_desc && tx_ring_desc->skb) {
2368 QPRINTK(qdev, IFDOWN, ERR,
2369 "Freeing lost SKB %p, from queue %d, index %d.\n",
2370 tx_ring_desc->skb, j,
2371 tx_ring_desc->index);
2372 ql_unmap_send(qdev, tx_ring_desc,
2373 tx_ring_desc->map_cnt);
2374 dev_kfree_skb(tx_ring_desc->skb);
2375 tx_ring_desc->skb = NULL;
2376 }
2377 }
2378 }
2379}
2380
c4e84bde
RM		 2381static void ql_free_mem_resources(struct ql_adapter *qdev)
2382{
2383 int i;
2384
2385 for (i = 0; i < qdev->tx_ring_count; i++)
2386 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2387 for (i = 0; i < qdev->rx_ring_count; i++)
2388 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2389 ql_free_shadow_space(qdev);
2390}
2391
2392static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2393{
2394 int i;
2395
2396 /* Allocate space for our shadow registers and such. */
2397 if (ql_alloc_shadow_space(qdev))
2398 return -ENOMEM;
2399
2400 for (i = 0; i < qdev->rx_ring_count; i++) {
2401 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2402 QPRINTK(qdev, IFUP, ERR,
2403 "RX resource allocation failed.\n");
2404 goto err_mem;
2405 }
2406 }
2407 /* Allocate tx queue resources */
2408 for (i = 0; i < qdev->tx_ring_count; i++) {
2409 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2410 QPRINTK(qdev, IFUP, ERR,
2411 "TX resource allocation failed.\n");
2412 goto err_mem;
2413 }
2414 }
2415 return 0;
2416
2417err_mem:
2418 ql_free_mem_resources(qdev);
2419 return -ENOMEM;
2420}
2421
2422/* Set up the rx ring control block and pass it to the chip.
2423 * The control block is defined as
2424 * "Completion Queue Initialization Control Block", or cqicb.
2425 */
2426static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2427{
2428 struct cqicb *cqicb = &rx_ring->cqicb;
2429 void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2430 (rx_ring->cq_id * sizeof(u64) * 4);
2431 u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2432 (rx_ring->cq_id * sizeof(u64) * 4);
2433 void __iomem *doorbell_area =
2434 qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2435 int err = 0;
2436 u16 bq_len;
2437
2438 /* Set up the shadow registers for this ring. */
2439 rx_ring->prod_idx_sh_reg = shadow_reg;
2440 rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2441 shadow_reg += sizeof(u64);
2442 shadow_reg_dma += sizeof(u64);
2443 rx_ring->lbq_base_indirect = shadow_reg;
2444 rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2445 shadow_reg += sizeof(u64);
2446 shadow_reg_dma += sizeof(u64);
2447 rx_ring->sbq_base_indirect = shadow_reg;
2448 rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2449
2450 /* PCI doorbell mem area + 0x00 for consumer index register */
8668ae92 2451 rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
c4e84bde
RM		 2452 rx_ring->cnsmr_idx = 0;
2453 rx_ring->curr_entry = rx_ring->cq_base;
2454
2455 /* PCI doorbell mem area + 0x04 for valid register */
2456 rx_ring->valid_db_reg = doorbell_area + 0x04;
2457
2458 /* PCI doorbell mem area + 0x18 for large buffer consumer */
8668ae92 2459 rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
c4e84bde
RM		 2460
2461 /* PCI doorbell mem area + 0x1c */
8668ae92 2462 rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
c4e84bde
RM		 2463
2464 memset((void *)cqicb, 0, sizeof(struct cqicb));
2465 cqicb->msix_vect = rx_ring->irq;
2466
459caf5a
RM		 2467 bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2468 cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
c4e84bde 2469
97345524 2470 cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
c4e84bde 2471
97345524 2472 cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
c4e84bde
RM		 2473
2474 /*
2475 * Set up the control block load flags.
2476 */
2477 cqicb->flags = FLAGS_LC | /* Load queue base address */
2478 FLAGS_LV | /* Load MSI-X vector */
2479 FLAGS_LI; /* Load irq delay values */
2480 if (rx_ring->lbq_len) {
2481 cqicb->flags |= FLAGS_LL; /* Load lbq values */
2482 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
97345524
RM		 2483 cqicb->lbq_addr =
2484 cpu_to_le64(rx_ring->lbq_base_indirect_dma);
459caf5a
RM		 2485 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2486 (u16) rx_ring->lbq_buf_size;
2487 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2488 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2489 (u16) rx_ring->lbq_len;
c4e84bde 2490 cqicb->lbq_len = cpu_to_le16(bq_len);
4545a3f2 2491 rx_ring->lbq_prod_idx = 0;
c4e84bde 2492 rx_ring->lbq_curr_idx = 0;
4545a3f2
RM		 2493 rx_ring->lbq_clean_idx = 0;
2494 rx_ring->lbq_free_cnt = rx_ring->lbq_len;
c4e84bde
RM		 2495 }
2496 if (rx_ring->sbq_len) {
2497 cqicb->flags |= FLAGS_LS; /* Load sbq values */
2498 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
97345524
RM		 2499 cqicb->sbq_addr =
2500 cpu_to_le64(rx_ring->sbq_base_indirect_dma);
c4e84bde
RM		 2501 cqicb->sbq_buf_size =
2502 cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
459caf5a
RM		 2503 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2504 (u16) rx_ring->sbq_len;
c4e84bde 2505 cqicb->sbq_len = cpu_to_le16(bq_len);
4545a3f2 2506 rx_ring->sbq_prod_idx = 0;
c4e84bde 2507 rx_ring->sbq_curr_idx = 0;
4545a3f2
RM		 2508 rx_ring->sbq_clean_idx = 0;
2509 rx_ring->sbq_free_cnt = rx_ring->sbq_len;
c4e84bde
RM		 2510 }
2511 switch (rx_ring->type) {
2512 case TX_Q:
2513 /* If there's only one interrupt, then we use
2514 * worker threads to process the outbound
2515 * completion handling rx_rings. We do this so
2516 * they can be run on multiple CPUs. There is
2517 * room to play with this more where we would only
2518 * run in a worker if there are more than x number
2519 * of outbound completions on the queue and more
2520 * than one queue active. Some threshold that
2521 * would indicate a benefit in spite of the cost
2522 * of a context switch.
2523 * If there's more than one interrupt, then the
2524 * outbound completions are processed in the ISR.
2525 */
2526 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2527 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2528 else {
2529 /* With all debug warnings on we see a WARN_ON message
2530 * when we free the skb in the interrupt context.
2531 */
2532 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2533 }
2534 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2535 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2536 break;
2537 case DEFAULT_Q:
2538 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2539 cqicb->irq_delay = 0;
2540 cqicb->pkt_delay = 0;
2541 break;
2542 case RX_Q:
2543 /* Inbound completion handling rx_rings run in
2544 * separate NAPI contexts.
2545 */
2546 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2547 64);
2548 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2549 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2550 break;
2551 default:
2552 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2553 rx_ring->type);
2554 }
4974097a 2555 QPRINTK(qdev, IFUP, DEBUG, "Initializing rx work queue.\n");
c4e84bde
RM		 2556 err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2557 CFG_LCQ, rx_ring->cq_id);
2558 if (err) {
2559 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2560 return err;
2561 }
c4e84bde
RM		 2562 return err;
2563}
2564
2565static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2566{
2567 struct wqicb *wqicb = (struct wqicb *)tx_ring;
2568 void __iomem *doorbell_area =
2569 qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2570 void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2571 (tx_ring->wq_id * sizeof(u64));
2572 u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2573 (tx_ring->wq_id * sizeof(u64));
2574 int err = 0;
2575
2576 /*
2577 * Assign doorbell registers for this tx_ring.
2578 */
2579 /* TX PCI doorbell mem area for tx producer index */
8668ae92 2580 tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
c4e84bde
RM		 2581 tx_ring->prod_idx = 0;
2582 /* TX PCI doorbell mem area + 0x04 */
2583 tx_ring->valid_db_reg = doorbell_area + 0x04;
2584
2585 /*
2586 * Assign shadow registers for this tx_ring.
2587 */
2588 tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2589 tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2590
2591 wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2592 wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2593 Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2594 wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2595 wqicb->rid = 0;
97345524 2596 wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
c4e84bde 2597
97345524 2598 wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
c4e84bde
RM		 2599
2600 ql_init_tx_ring(qdev, tx_ring);
2601
2602 err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2603 (u16) tx_ring->wq_id);
2604 if (err) {
2605 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2606 return err;
2607 }
4974097a 2608 QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded WQICB.\n");
c4e84bde
RM		 2609 return err;
2610}
2611
2612static void ql_disable_msix(struct ql_adapter *qdev)
2613{
2614 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2615 pci_disable_msix(qdev->pdev);
2616 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2617 kfree(qdev->msi_x_entry);
2618 qdev->msi_x_entry = NULL;
2619 } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2620 pci_disable_msi(qdev->pdev);
2621 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2622 }
2623}
2624
2625static void ql_enable_msix(struct ql_adapter *qdev)
2626{
2627 int i;
2628
2629 qdev->intr_count = 1;
2630 /* Get the MSIX vectors. */
2631 if (irq_type == MSIX_IRQ) {
2632 /* Try to alloc space for the msix struct,
2633 * if it fails then go to MSI/legacy.
2634 */
2635 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2636 sizeof(struct msix_entry),
2637 GFP_KERNEL);
2638 if (!qdev->msi_x_entry) {
2639 irq_type = MSI_IRQ;
2640 goto msi;
2641 }
2642
2643 for (i = 0; i < qdev->rx_ring_count; i++)
2644 qdev->msi_x_entry[i].entry = i;
2645
2646 if (!pci_enable_msix
2647 (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2648 set_bit(QL_MSIX_ENABLED, &qdev->flags);
2649 qdev->intr_count = qdev->rx_ring_count;
4974097a 2650 QPRINTK(qdev, IFUP, DEBUG,
c4e84bde
RM		 2651 "MSI-X Enabled, got %d vectors.\n",
2652 qdev->intr_count);
2653 return;
2654 } else {
2655 kfree(qdev->msi_x_entry);
2656 qdev->msi_x_entry = NULL;
2657 QPRINTK(qdev, IFUP, WARNING,
2658 "MSI-X Enable failed, trying MSI.\n");
2659 irq_type = MSI_IRQ;
2660 }
2661 }
2662msi:
2663 if (irq_type == MSI_IRQ) {
2664 if (!pci_enable_msi(qdev->pdev)) {
2665 set_bit(QL_MSI_ENABLED, &qdev->flags);
2666 QPRINTK(qdev, IFUP, INFO,
2667 "Running with MSI interrupts.\n");
2668 return;
2669 }
2670 }
2671 irq_type = LEG_IRQ;
c4e84bde
RM		 2672 QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2673}
2674
2675/*
2676 * Here we build the intr_context structures based on
2677 * our rx_ring count and intr vector count.
2678 * The intr_context structure is used to hook each vector
2679 * to possibly different handlers.
2680 */
2681static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2682{
2683 int i = 0;
2684 struct intr_context *intr_context = &qdev->intr_context[0];
2685
2686 ql_enable_msix(qdev);
2687
2688 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2689 /* Each rx_ring has it's
2690 * own intr_context since we have separate
2691 * vectors for each queue.
2692 * This only true when MSI-X is enabled.
2693 */
2694 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2695 qdev->rx_ring[i].irq = i;
2696 intr_context->intr = i;
2697 intr_context->qdev = qdev;
2698 /*
2699 * We set up each vectors enable/disable/read bits so
2700 * there's no bit/mask calculations in the critical path.
2701 */
2702 intr_context->intr_en_mask =
2703 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2704 INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2705 | i;
2706 intr_context->intr_dis_mask =
2707 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2708 INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2709 INTR_EN_IHD | i;
2710 intr_context->intr_read_mask =
2711 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2712 INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2713 i;
2714
2715 if (i == 0) {
2716 /*
2717 * Default queue handles bcast/mcast plus
2718 * async events. Needs buffers.
2719 */
2720 intr_context->handler = qlge_isr;
2721 sprintf(intr_context->name, "%s-default-queue",
2722 qdev->ndev->name);
2723 } else if (i < qdev->rss_ring_first_cq_id) {
2724 /*
2725 * Outbound queue is for outbound completions only.
2726 */
2727 intr_context->handler = qlge_msix_tx_isr;
c224969e 2728 sprintf(intr_context->name, "%s-tx-%d",
c4e84bde
RM		 2729 qdev->ndev->name, i);
2730 } else {
2731 /*
2732 * Inbound queues handle unicast frames only.
2733 */
2734 intr_context->handler = qlge_msix_rx_isr;
c224969e 2735 sprintf(intr_context->name, "%s-rx-%d",
c4e84bde
RM		 2736 qdev->ndev->name, i);
2737 }
2738 }
2739 } else {
2740 /*
2741 * All rx_rings use the same intr_context since
2742 * there is only one vector.
2743 */
2744 intr_context->intr = 0;
2745 intr_context->qdev = qdev;
2746 /*
2747 * We set up each vectors enable/disable/read bits so
2748 * there's no bit/mask calculations in the critical path.
2749 */
2750 intr_context->intr_en_mask =
2751 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2752 intr_context->intr_dis_mask =
2753 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2754 INTR_EN_TYPE_DISABLE;
2755 intr_context->intr_read_mask =
2756 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2757 /*
2758 * Single interrupt means one handler for all rings.
2759 */
2760 intr_context->handler = qlge_isr;
2761 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2762 for (i = 0; i < qdev->rx_ring_count; i++)
2763 qdev->rx_ring[i].irq = 0;
2764 }
2765}
2766
2767static void ql_free_irq(struct ql_adapter *qdev)
2768{
2769 int i;
2770 struct intr_context *intr_context = &qdev->intr_context[0];
2771
2772 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2773 if (intr_context->hooked) {
2774 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2775 free_irq(qdev->msi_x_entry[i].vector,
2776 &qdev->rx_ring[i]);
4974097a 2777 QPRINTK(qdev, IFDOWN, DEBUG,
c4e84bde
RM		 2778 "freeing msix interrupt %d.\n", i);
2779 } else {
2780 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
4974097a 2781 QPRINTK(qdev, IFDOWN, DEBUG,
c4e84bde
RM		 2782 "freeing msi interrupt %d.\n", i);
2783 }
2784 }
2785 }
2786 ql_disable_msix(qdev);
2787}
2788
2789static int ql_request_irq(struct ql_adapter *qdev)
2790{
2791 int i;
2792 int status = 0;
2793 struct pci_dev *pdev = qdev->pdev;
2794 struct intr_context *intr_context = &qdev->intr_context[0];
2795
2796 ql_resolve_queues_to_irqs(qdev);
2797
2798 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2799 atomic_set(&intr_context->irq_cnt, 0);
2800 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2801 status = request_irq(qdev->msi_x_entry[i].vector,
2802 intr_context->handler,
2803 0,
2804 intr_context->name,
2805 &qdev->rx_ring[i]);
2806 if (status) {
2807 QPRINTK(qdev, IFUP, ERR,
2808 "Failed request for MSIX interrupt %d.\n",
2809 i);
2810 goto err_irq;
2811 } else {
4974097a 2812 QPRINTK(qdev, IFUP, DEBUG,
c4e84bde
RM		 2813 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2814 i,
2815 qdev->rx_ring[i].type ==
2816 DEFAULT_Q ? "DEFAULT_Q" : "",
2817 qdev->rx_ring[i].type ==
2818 TX_Q ? "TX_Q" : "",
2819 qdev->rx_ring[i].type ==
2820 RX_Q ? "RX_Q" : "", intr_context->name);
2821 }
2822 } else {
2823 QPRINTK(qdev, IFUP, DEBUG,
2824 "trying msi or legacy interrupts.\n");
2825 QPRINTK(qdev, IFUP, DEBUG,
2826 "%s: irq = %d.\n", __func__, pdev->irq);
2827 QPRINTK(qdev, IFUP, DEBUG,
2828 "%s: context->name = %s.\n", __func__,
2829 intr_context->name);
2830 QPRINTK(qdev, IFUP, DEBUG,
2831 "%s: dev_id = 0x%p.\n", __func__,
2832 &qdev->rx_ring[0]);
2833 status =
2834 request_irq(pdev->irq, qlge_isr,
2835 test_bit(QL_MSI_ENABLED,
2836 &qdev->
2837 flags) ? 0 : IRQF_SHARED,
2838 intr_context->name, &qdev->rx_ring[0]);
2839 if (status)
2840 goto err_irq;
2841
2842 QPRINTK(qdev, IFUP, ERR,
2843 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2844 i,
2845 qdev->rx_ring[0].type ==
2846 DEFAULT_Q ? "DEFAULT_Q" : "",
2847 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2848 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2849 intr_context->name);
2850 }
2851 intr_context->hooked = 1;
2852 }
2853 return status;
2854err_irq:
2855 QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2856 ql_free_irq(qdev);
2857 return status;
2858}
2859
2860static int ql_start_rss(struct ql_adapter *qdev)
2861{
2862 struct ricb *ricb = &qdev->ricb;
2863 int status = 0;
2864 int i;
2865 u8 *hash_id = (u8 *) ricb->hash_cq_id;
2866
2867 memset((void *)ricb, 0, sizeof(ricb));
2868
2869 ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2870 ricb->flags =
2871 (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2872 RSS_RT6);
2873 ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2874
2875 /*
2876 * Fill out the Indirection Table.
2877 */
def48b6e
RM		 2878 for (i = 0; i < 256; i++)
2879 hash_id[i] = i & (qdev->rss_ring_count - 1);
c4e84bde
RM		 2880
2881 /*
2882 * Random values for the IPv6 and IPv4 Hash Keys.
2883 */
2884 get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2885 get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2886
4974097a 2887 QPRINTK(qdev, IFUP, DEBUG, "Initializing RSS.\n");
c4e84bde
RM		 2888
2889 status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2890 if (status) {
2891 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2892 return status;
2893 }
4974097a 2894 QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded RICB.\n");
c4e84bde
RM		 2895 return status;
2896}
2897
2898/* Initialize the frame-to-queue routing. */
2899static int ql_route_initialize(struct ql_adapter *qdev)
2900{
2901 int status = 0;
2902 int i;
2903
8587ea35
RM		 2904 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
2905 if (status)
2906 return status;
2907
c4e84bde
RM		 2908 /* Clear all the entries in the routing table. */
2909 for (i = 0; i < 16; i++) {
2910 status = ql_set_routing_reg(qdev, i, 0, 0);
2911 if (status) {
2912 QPRINTK(qdev, IFUP, ERR,
2913 "Failed to init routing register for CAM packets.\n");
8587ea35 2914 goto exit;
c4e84bde
RM		 2915 }
2916 }
2917
2918 status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
2919 if (status) {
2920 QPRINTK(qdev, IFUP, ERR,
2921 "Failed to init routing register for error packets.\n");
8587ea35 2922 goto exit;
c4e84bde
RM		 2923 }
2924 status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
2925 if (status) {
2926 QPRINTK(qdev, IFUP, ERR,
2927 "Failed to init routing register for broadcast packets.\n");
8587ea35 2928 goto exit;
c4e84bde
RM		 2929 }
2930 /* If we have more than one inbound queue, then turn on RSS in the
2931 * routing block.
2932 */
2933 if (qdev->rss_ring_count > 1) {
2934 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
2935 RT_IDX_RSS_MATCH, 1);
2936 if (status) {
2937 QPRINTK(qdev, IFUP, ERR,
2938 "Failed to init routing register for MATCH RSS packets.\n");
8587ea35 2939 goto exit;
c4e84bde
RM		 2940 }
2941 }
2942
2943 status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
2944 RT_IDX_CAM_HIT, 1);
8587ea35 2945 if (status)
c4e84bde
RM		 2946 QPRINTK(qdev, IFUP, ERR,
2947 "Failed to init routing register for CAM packets.\n");
8587ea35
RM		 2948exit:
2949 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
c4e84bde
RM		 2950 return status;
2951}
2952
bb58b5b6
RM		 2953static int ql_cam_route_initialize(struct ql_adapter *qdev)
2954{
2955 int status;
2956
cc288f54
RM		 2957 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
2958 if (status)
2959 return status;
bb58b5b6
RM		 2960 status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
2961 MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
cc288f54 2962 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
bb58b5b6
RM		 2963 if (status) {
2964 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
2965 return status;
2966 }
2967
2968 status = ql_route_initialize(qdev);
2969 if (status)
2970 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
2971
2972 return status;
2973}
2974
c4e84bde
RM		 2975static int ql_adapter_initialize(struct ql_adapter *qdev)
2976{
2977 u32 value, mask;
2978 int i;
2979 int status = 0;
2980
2981 /*
2982 * Set up the System register to halt on errors.
2983 */
2984 value = SYS_EFE | SYS_FAE;
2985 mask = value << 16;
2986 ql_write32(qdev, SYS, mask | value);
2987
2988 /* Set the default queue. */
2989 value = NIC_RCV_CFG_DFQ;
2990 mask = NIC_RCV_CFG_DFQ_MASK;
2991 ql_write32(qdev, NIC_RCV_CFG, (mask | value));
2992
2993 /* Set the MPI interrupt to enabled. */
2994 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
2995
2996 /* Enable the function, set pagesize, enable error checking. */
2997 value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
2998 FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
2999
3000 /* Set/clear header splitting. */
3001 mask = FSC_VM_PAGESIZE_MASK |
3002 FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3003 ql_write32(qdev, FSC, mask | value);
3004
3005 ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3006 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3007
3008 /* Start up the rx queues. */
3009 for (i = 0; i < qdev->rx_ring_count; i++) {
3010 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3011 if (status) {
3012 QPRINTK(qdev, IFUP, ERR,
3013 "Failed to start rx ring[%d].\n", i);
3014 return status;
3015 }
3016 }
3017
3018 /* If there is more than one inbound completion queue
3019 * then download a RICB to configure RSS.
3020 */
3021 if (qdev->rss_ring_count > 1) {
3022 status = ql_start_rss(qdev);
3023 if (status) {
3024 QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3025 return status;
3026 }
3027 }
3028
3029 /* Start up the tx queues. */
3030 for (i = 0; i < qdev->tx_ring_count; i++) {
3031 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3032 if (status) {
3033 QPRINTK(qdev, IFUP, ERR,
3034 "Failed to start tx ring[%d].\n", i);
3035 return status;
3036 }
3037 }
3038
b0c2aadf
RM		 3039 /* Initialize the port and set the max framesize. */
3040 status = qdev->nic_ops->port_initialize(qdev);
3041 if (status) {
3042 QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3043 return status;
3044 }
c4e84bde 3045
bb58b5b6
RM		 3046 /* Set up the MAC address and frame routing filter. */
3047 status = ql_cam_route_initialize(qdev);
c4e84bde 3048 if (status) {
bb58b5b6
RM		 3049 QPRINTK(qdev, IFUP, ERR,
3050 "Failed to init CAM/Routing tables.\n");
c4e84bde
RM		 3051 return status;
3052 }
3053
3054 /* Start NAPI for the RSS queues. */
3055 for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
4974097a 3056 QPRINTK(qdev, IFUP, DEBUG, "Enabling NAPI for rx_ring[%d].\n",
c4e84bde
RM		 3057 i);
3058 napi_enable(&qdev->rx_ring[i].napi);
3059 }
3060
3061 return status;
3062}
3063
3064/* Issue soft reset to chip. */
3065static int ql_adapter_reset(struct ql_adapter *qdev)
3066{
3067 u32 value;
3068 int max_wait_time;
3069 int status = 0;
3070 int resetCnt = 0;
3071
3072#define MAX_RESET_CNT 1
3073issueReset:
3074 resetCnt++;
3075 QPRINTK(qdev, IFDOWN, DEBUG, "Issue soft reset to chip.\n");
3076 ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3077 /* Wait for reset to complete. */
3078 max_wait_time = 3;
3079 QPRINTK(qdev, IFDOWN, DEBUG, "Wait %d seconds for reset to complete.\n",
3080 max_wait_time);
3081 do {
3082 value = ql_read32(qdev, RST_FO);
3083 if ((value & RST_FO_FR) == 0)
3084 break;
3085
3086 ssleep(1);
3087 } while ((--max_wait_time));
3088 if (value & RST_FO_FR) {
3089 QPRINTK(qdev, IFDOWN, ERR,
3090 "Stuck in SoftReset: FSC_SR:0x%08x\n", value);
3091 if (resetCnt < MAX_RESET_CNT)
3092 goto issueReset;
3093 }
3094 if (max_wait_time == 0) {
3095 status = -ETIMEDOUT;
3096 QPRINTK(qdev, IFDOWN, ERR,
3097 "ETIMEOUT!!! errored out of resetting the chip!\n");
3098 }
3099
3100 return status;
3101}
3102
3103static void ql_display_dev_info(struct net_device *ndev)
3104{
3105 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3106
3107 QPRINTK(qdev, PROBE, INFO,
3108 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3109 "XG Roll = %d, XG Rev = %d.\n",
3110 qdev->func,
3111 qdev->chip_rev_id & 0x0000000f,
3112 qdev->chip_rev_id >> 4 & 0x0000000f,
3113 qdev->chip_rev_id >> 8 & 0x0000000f,
3114 qdev->chip_rev_id >> 12 & 0x0000000f);
7c510e4b 3115 QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
c4e84bde
RM		 3116}
3117
3118static int ql_adapter_down(struct ql_adapter *qdev)
3119{
3120 struct net_device *ndev = qdev->ndev;
3121 int i, status = 0;
3122 struct rx_ring *rx_ring;
3123
3124 netif_stop_queue(ndev);
3125 netif_carrier_off(ndev);
3126
6497b607
RM		 3127 /* Don't kill the reset worker thread if we
3128 * are in the process of recovery.
3129 */
3130 if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3131 cancel_delayed_work_sync(&qdev->asic_reset_work);
c4e84bde
RM		 3132 cancel_delayed_work_sync(&qdev->mpi_reset_work);
3133 cancel_delayed_work_sync(&qdev->mpi_work);
3134
3135 /* The default queue at index 0 is always processed in
3136 * a workqueue.
3137 */
3138 cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3139
3140 /* The rest of the rx_rings are processed in
3141 * a workqueue only if it's a single interrupt
3142 * environment (MSI/Legacy).
3143 */
c062076c 3144 for (i = 1; i < qdev->rx_ring_count; i++) {
c4e84bde
RM		 3145 rx_ring = &qdev->rx_ring[i];
3146 /* Only the RSS rings use NAPI on multi irq
3147 * environment. Outbound completion processing
3148 * is done in interrupt context.
3149 */
3150 if (i >= qdev->rss_ring_first_cq_id) {
3151 napi_disable(&rx_ring->napi);
3152 } else {
3153 cancel_delayed_work_sync(&rx_ring->rx_work);
3154 }
3155 }
3156
3157 clear_bit(QL_ADAPTER_UP, &qdev->flags);
3158
3159 ql_disable_interrupts(qdev);
3160
3161 ql_tx_ring_clean(qdev);
3162
4545a3f2 3163 ql_free_rx_buffers(qdev);
c4e84bde
RM		 3164 spin_lock(&qdev->hw_lock);
3165 status = ql_adapter_reset(qdev);
3166 if (status)
3167 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3168 qdev->func);
3169 spin_unlock(&qdev->hw_lock);
3170 return status;
3171}
3172
3173static int ql_adapter_up(struct ql_adapter *qdev)
3174{
3175 int err = 0;
3176
3177 spin_lock(&qdev->hw_lock);
3178 err = ql_adapter_initialize(qdev);
3179 if (err) {
3180 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3181 spin_unlock(&qdev->hw_lock);
3182 goto err_init;
3183 }
3184 spin_unlock(&qdev->hw_lock);
3185 set_bit(QL_ADAPTER_UP, &qdev->flags);
4545a3f2 3186 ql_alloc_rx_buffers(qdev);
c4e84bde
RM		 3187 ql_enable_interrupts(qdev);
3188 ql_enable_all_completion_interrupts(qdev);
3189 if ((ql_read32(qdev, STS) & qdev->port_init)) {
3190 netif_carrier_on(qdev->ndev);
3191 netif_start_queue(qdev->ndev);
3192 }
3193
3194 return 0;
3195err_init:
3196 ql_adapter_reset(qdev);
3197 return err;
3198}
3199
3200static int ql_cycle_adapter(struct ql_adapter *qdev)
3201{
3202 int status;
3203
3204 status = ql_adapter_down(qdev);
3205 if (status)
3206 goto error;
3207
3208 status = ql_adapter_up(qdev);
3209 if (status)
3210 goto error;
3211
3212 return status;
3213error:
3214 QPRINTK(qdev, IFUP, ALERT,
3215 "Driver up/down cycle failed, closing device\n");
3216 rtnl_lock();
3217 dev_close(qdev->ndev);
3218 rtnl_unlock();
3219 return status;
3220}
3221
3222static void ql_release_adapter_resources(struct ql_adapter *qdev)
3223{
3224 ql_free_mem_resources(qdev);
3225 ql_free_irq(qdev);
3226}
3227
3228static int ql_get_adapter_resources(struct ql_adapter *qdev)
3229{
3230 int status = 0;
3231
3232 if (ql_alloc_mem_resources(qdev)) {
3233 QPRINTK(qdev, IFUP, ERR, "Unable to allocate memory.\n");
3234 return -ENOMEM;
3235 }
3236 status = ql_request_irq(qdev);
3237 if (status)
3238 goto err_irq;
3239 return status;
3240err_irq:
3241 ql_free_mem_resources(qdev);
3242 return status;
3243}
3244
3245static int qlge_close(struct net_device *ndev)
3246{
3247 struct ql_adapter *qdev = netdev_priv(ndev);
3248
3249 /*
3250 * Wait for device to recover from a reset.
3251 * (Rarely happens, but possible.)
3252 */
3253 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3254 msleep(1);
3255 ql_adapter_down(qdev);
3256 ql_release_adapter_resources(qdev);
c4e84bde
RM		 3257 return 0;
3258}
3259
3260static int ql_configure_rings(struct ql_adapter *qdev)
3261{
3262 int i;
3263 struct rx_ring *rx_ring;
3264 struct tx_ring *tx_ring;
3265 int cpu_cnt = num_online_cpus();
3266
3267 /*
3268 * For each processor present we allocate one
3269 * rx_ring for outbound completions, and one
3270 * rx_ring for inbound completions. Plus there is
3271 * always the one default queue. For the CPU
3272 * counts we end up with the following rx_rings:
3273 * rx_ring count =
3274 * one default queue +
3275 * (CPU count * outbound completion rx_ring) +
3276 * (CPU count * inbound (RSS) completion rx_ring)
3277 * To keep it simple we limit the total number of
3278 * queues to < 32, so we truncate CPU to 8.
3279 * This limitation can be removed when requested.
3280 */
3281
683d46a9
RM		 3282 if (cpu_cnt > MAX_CPUS)
3283 cpu_cnt = MAX_CPUS;
c4e84bde
RM		 3284
3285 /*
3286 * rx_ring[0] is always the default queue.
3287 */
3288 /* Allocate outbound completion ring for each CPU. */
3289 qdev->tx_ring_count = cpu_cnt;
3290 /* Allocate inbound completion (RSS) ring for each CPU. */
3291 qdev->rss_ring_count = cpu_cnt;
3292 /* cq_id for the first inbound ring handler. */
3293 qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3294 /*
3295 * qdev->rx_ring_count:
3296 * Total number of rx_rings. This includes the one
3297 * default queue, a number of outbound completion
3298 * handler rx_rings, and the number of inbound
3299 * completion handler rx_rings.
3300 */
3301 qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3302
c4e84bde
RM		 3303 for (i = 0; i < qdev->tx_ring_count; i++) {
3304 tx_ring = &qdev->tx_ring[i];
3305 memset((void *)tx_ring, 0, sizeof(tx_ring));
3306 tx_ring->qdev = qdev;
3307 tx_ring->wq_id = i;
3308 tx_ring->wq_len = qdev->tx_ring_size;
3309 tx_ring->wq_size =
3310 tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3311
3312 /*
3313 * The completion queue ID for the tx rings start
3314 * immediately after the default Q ID, which is zero.
3315 */
3316 tx_ring->cq_id = i + 1;
3317 }
3318
3319 for (i = 0; i < qdev->rx_ring_count; i++) {
3320 rx_ring = &qdev->rx_ring[i];
3321 memset((void *)rx_ring, 0, sizeof(rx_ring));
3322 rx_ring->qdev = qdev;
3323 rx_ring->cq_id = i;
3324 rx_ring->cpu = i % cpu_cnt; /* CPU to run handler on. */
3325 if (i == 0) { /* Default queue at index 0. */
3326 /*
3327 * Default queue handles bcast/mcast plus
3328 * async events. Needs buffers.
3329 */
3330 rx_ring->cq_len = qdev->rx_ring_size;
3331 rx_ring->cq_size =
3332 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3333 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3334 rx_ring->lbq_size =
2c9a0d41 3335 rx_ring->lbq_len * sizeof(__le64);
c4e84bde
RM		 3336 rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3337 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3338 rx_ring->sbq_size =
2c9a0d41 3339 rx_ring->sbq_len * sizeof(__le64);
c4e84bde
RM		 3340 rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3341 rx_ring->type = DEFAULT_Q;
3342 } else if (i < qdev->rss_ring_first_cq_id) {
3343 /*
3344 * Outbound queue handles outbound completions only.
3345 */
3346 /* outbound cq is same size as tx_ring it services. */
3347 rx_ring->cq_len = qdev->tx_ring_size;
3348 rx_ring->cq_size =
3349 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3350 rx_ring->lbq_len = 0;
3351 rx_ring->lbq_size = 0;
3352 rx_ring->lbq_buf_size = 0;
3353 rx_ring->sbq_len = 0;
3354 rx_ring->sbq_size = 0;
3355 rx_ring->sbq_buf_size = 0;
3356 rx_ring->type = TX_Q;
3357 } else { /* Inbound completions (RSS) queues */
3358 /*
3359 * Inbound queues handle unicast frames only.
3360 */
3361 rx_ring->cq_len = qdev->rx_ring_size;
3362 rx_ring->cq_size =
3363 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3364 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3365 rx_ring->lbq_size =
2c9a0d41 3366 rx_ring->lbq_len * sizeof(__le64);
c4e84bde
RM		 3367 rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3368 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3369 rx_ring->sbq_size =
2c9a0d41 3370 rx_ring->sbq_len * sizeof(__le64);
c4e84bde
RM		 3371 rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3372 rx_ring->type = RX_Q;
3373 }
3374 }
3375 return 0;
3376}
3377
3378static int qlge_open(struct net_device *ndev)
3379{
3380 int err = 0;
3381 struct ql_adapter *qdev = netdev_priv(ndev);
3382
3383 err = ql_configure_rings(qdev);
3384 if (err)
3385 return err;
3386
3387 err = ql_get_adapter_resources(qdev);
3388 if (err)
3389 goto error_up;
3390
3391 err = ql_adapter_up(qdev);
3392 if (err)
3393 goto error_up;
3394
3395 return err;
3396
3397error_up:
3398 ql_release_adapter_resources(qdev);
c4e84bde
RM		 3399 return err;
3400}
3401
3402static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3403{
3404 struct ql_adapter *qdev = netdev_priv(ndev);
3405
3406 if (ndev->mtu == 1500 && new_mtu == 9000) {
3407 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3408 } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3409 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3410 } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3411 (ndev->mtu == 9000 && new_mtu == 9000)) {
3412 return 0;
3413 } else
3414 return -EINVAL;
3415 ndev->mtu = new_mtu;
3416 return 0;
3417}
3418
3419static struct net_device_stats *qlge_get_stats(struct net_device
3420 *ndev)
3421{
3422 struct ql_adapter *qdev = netdev_priv(ndev);
3423 return &qdev->stats;
3424}
3425
3426static void qlge_set_multicast_list(struct net_device *ndev)
3427{
3428 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3429 struct dev_mc_list *mc_ptr;
cc288f54 3430 int i, status;
c4e84bde 3431
cc288f54
RM		 3432 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3433 if (status)
3434 return;
c4e84bde
RM		 3435 spin_lock(&qdev->hw_lock);
3436 /*
3437 * Set or clear promiscuous mode if a
3438 * transition is taking place.
3439 */
3440 if (ndev->flags & IFF_PROMISC) {
3441 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3442 if (ql_set_routing_reg
3443 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3444 QPRINTK(qdev, HW, ERR,
3445 "Failed to set promiscous mode.\n");
3446 } else {
3447 set_bit(QL_PROMISCUOUS, &qdev->flags);
3448 }
3449 }
3450 } else {
3451 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3452 if (ql_set_routing_reg
3453 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3454 QPRINTK(qdev, HW, ERR,
3455 "Failed to clear promiscous mode.\n");
3456 } else {
3457 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3458 }
3459 }
3460 }
3461
3462 /*
3463 * Set or clear all multicast mode if a
3464 * transition is taking place.
3465 */
3466 if ((ndev->flags & IFF_ALLMULTI) ||
3467 (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3468 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3469 if (ql_set_routing_reg
3470 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3471 QPRINTK(qdev, HW, ERR,
3472 "Failed to set all-multi mode.\n");
3473 } else {
3474 set_bit(QL_ALLMULTI, &qdev->flags);
3475 }
3476 }
3477 } else {
3478 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3479 if (ql_set_routing_reg
3480 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3481 QPRINTK(qdev, HW, ERR,
3482 "Failed to clear all-multi mode.\n");
3483 } else {
3484 clear_bit(QL_ALLMULTI, &qdev->flags);
3485 }
3486 }
3487 }
3488
3489 if (ndev->mc_count) {
cc288f54
RM		 3490 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3491 if (status)
3492 goto exit;
c4e84bde
RM		 3493 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3494 i++, mc_ptr = mc_ptr->next)
3495 if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3496 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3497 QPRINTK(qdev, HW, ERR,
3498 "Failed to loadmulticast address.\n");
cc288f54 3499 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
c4e84bde
RM		 3500 goto exit;
3501 }
cc288f54 3502 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
c4e84bde
RM		 3503 if (ql_set_routing_reg
3504 (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3505 QPRINTK(qdev, HW, ERR,
3506 "Failed to set multicast match mode.\n");
3507 } else {
3508 set_bit(QL_ALLMULTI, &qdev->flags);
3509 }
3510 }
3511exit:
3512 spin_unlock(&qdev->hw_lock);
8587ea35 3513 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
c4e84bde
RM		 3514}
3515
3516static int qlge_set_mac_address(struct net_device *ndev, void *p)
3517{
3518 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3519 struct sockaddr *addr = p;
cc288f54 3520 int status;
c4e84bde
RM		 3521
3522 if (netif_running(ndev))
3523 return -EBUSY;
3524
3525 if (!is_valid_ether_addr(addr->sa_data))
3526 return -EADDRNOTAVAIL;
3527 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3528
cc288f54
RM		 3529 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3530 if (status)
3531 return status;
c4e84bde 3532 spin_lock(&qdev->hw_lock);
cc288f54
RM		 3533 status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3534 MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
c4e84bde 3535 spin_unlock(&qdev->hw_lock);
cc288f54
RM		 3536 if (status)
3537 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3538 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3539 return status;
c4e84bde
RM		 3540}
3541
3542static void qlge_tx_timeout(struct net_device *ndev)
3543{
3544 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
6497b607 3545 ql_queue_asic_error(qdev);
c4e84bde
RM		 3546}
3547
3548static void ql_asic_reset_work(struct work_struct *work)
3549{
3550 struct ql_adapter *qdev =
3551 container_of(work, struct ql_adapter, asic_reset_work.work);
3552 ql_cycle_adapter(qdev);
3553}
3554
b0c2aadf
RM		 3555static struct nic_operations qla8012_nic_ops = {
3556 .get_flash = ql_get_8012_flash_params,
3557 .port_initialize = ql_8012_port_initialize,
3558};
3559
3560
c4e84bde
RM		 3561static void ql_get_board_info(struct ql_adapter *qdev)
3562{
3563 qdev->func =
3564 (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3565 if (qdev->func) {
3566 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3567 qdev->port_link_up = STS_PL1;
3568 qdev->port_init = STS_PI1;
3569 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3570 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3571 } else {
3572 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3573 qdev->port_link_up = STS_PL0;
3574 qdev->port_init = STS_PI0;
3575 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3576 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3577 }
3578 qdev->chip_rev_id = ql_read32(qdev, REV_ID);
b0c2aadf
RM		 3579 qdev->device_id = qdev->pdev->device;
3580 if (qdev->device_id == QLGE_DEVICE_ID_8012)
3581 qdev->nic_ops = &qla8012_nic_ops;
c4e84bde
RM		 3582}
3583
3584static void ql_release_all(struct pci_dev *pdev)
3585{
3586 struct net_device *ndev = pci_get_drvdata(pdev);
3587 struct ql_adapter *qdev = netdev_priv(ndev);
3588
3589 if (qdev->workqueue) {
3590 destroy_workqueue(qdev->workqueue);
3591 qdev->workqueue = NULL;
3592 }
3593 if (qdev->q_workqueue) {
3594 destroy_workqueue(qdev->q_workqueue);
3595 qdev->q_workqueue = NULL;
3596 }
3597 if (qdev->reg_base)
8668ae92 3598 iounmap(qdev->reg_base);
c4e84bde
RM		 3599 if (qdev->doorbell_area)
3600 iounmap(qdev->doorbell_area);
3601 pci_release_regions(pdev);
3602 pci_set_drvdata(pdev, NULL);
3603}
3604
3605static int __devinit ql_init_device(struct pci_dev *pdev,
3606 struct net_device *ndev, int cards_found)
3607{
3608 struct ql_adapter *qdev = netdev_priv(ndev);
3609 int pos, err = 0;
3610 u16 val16;
3611
3612 memset((void *)qdev, 0, sizeof(qdev));
3613 err = pci_enable_device(pdev);
3614 if (err) {
3615 dev_err(&pdev->dev, "PCI device enable failed.\n");
3616 return err;
3617 }
3618
3619 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3620 if (pos <= 0) {
3621 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3622 "aborting.\n");
3623 goto err_out;
3624 } else {
3625 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3626 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3627 val16 |= (PCI_EXP_DEVCTL_CERE |
3628 PCI_EXP_DEVCTL_NFERE |
3629 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3630 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3631 }
3632
3633 err = pci_request_regions(pdev, DRV_NAME);
3634 if (err) {
3635 dev_err(&pdev->dev, "PCI region request failed.\n");
3636 goto err_out;
3637 }
3638
3639 pci_set_master(pdev);
3640 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3641 set_bit(QL_DMA64, &qdev->flags);
3642 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3643 } else {
3644 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3645 if (!err)
3646 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3647 }
3648
3649 if (err) {
3650 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3651 goto err_out;
3652 }
3653
3654 pci_set_drvdata(pdev, ndev);
3655 qdev->reg_base =
3656 ioremap_nocache(pci_resource_start(pdev, 1),
3657 pci_resource_len(pdev, 1));
3658 if (!qdev->reg_base) {
3659 dev_err(&pdev->dev, "Register mapping failed.\n");
3660 err = -ENOMEM;
3661 goto err_out;
3662 }
3663
3664 qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3665 qdev->doorbell_area =
3666 ioremap_nocache(pci_resource_start(pdev, 3),
3667 pci_resource_len(pdev, 3));
3668 if (!qdev->doorbell_area) {
3669 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3670 err = -ENOMEM;
3671 goto err_out;
3672 }
3673
c4e84bde
RM		 3674 qdev->ndev = ndev;
3675 qdev->pdev = pdev;
b0c2aadf 3676 ql_get_board_info(qdev);
c4e84bde
RM		 3677 qdev->msg_enable = netif_msg_init(debug, default_msg);
3678 spin_lock_init(&qdev->hw_lock);
3679 spin_lock_init(&qdev->stats_lock);
3680
3681 /* make sure the EEPROM is good */
b0c2aadf 3682 err = qdev->nic_ops->get_flash(qdev);
c4e84bde
RM		 3683 if (err) {
3684 dev_err(&pdev->dev, "Invalid FLASH.\n");
3685 goto err_out;
3686 }
3687
c4e84bde
RM		 3688 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3689
3690 /* Set up the default ring sizes. */
3691 qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3692 qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3693
3694 /* Set up the coalescing parameters. */
3695 qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3696 qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3697 qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3698 qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3699
3700 /*
3701 * Set up the operating parameters.
3702 */
3703 qdev->rx_csum = 1;
3704
3705 qdev->q_workqueue = create_workqueue(ndev->name);
3706 qdev->workqueue = create_singlethread_workqueue(ndev->name);
3707 INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3708 INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3709 INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
125844ea 3710 mutex_init(&qdev->mpi_mutex);
c4e84bde
RM		 3711
3712 if (!cards_found) {
3713 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3714 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3715 DRV_NAME, DRV_VERSION);
3716 }
3717 return 0;
3718err_out:
3719 ql_release_all(pdev);
3720 pci_disable_device(pdev);
3721 return err;
3722}
3723
25ed7849
SH		 3724
3725static const struct net_device_ops qlge_netdev_ops = {
3726 .ndo_open = qlge_open,
3727 .ndo_stop = qlge_close,
3728 .ndo_start_xmit = qlge_send,
3729 .ndo_change_mtu = qlge_change_mtu,
3730 .ndo_get_stats = qlge_get_stats,
3731 .ndo_set_multicast_list = qlge_set_multicast_list,
3732 .ndo_set_mac_address = qlge_set_mac_address,
3733 .ndo_validate_addr = eth_validate_addr,
3734 .ndo_tx_timeout = qlge_tx_timeout,
3735 .ndo_vlan_rx_register = ql_vlan_rx_register,
3736 .ndo_vlan_rx_add_vid = ql_vlan_rx_add_vid,
3737 .ndo_vlan_rx_kill_vid = ql_vlan_rx_kill_vid,
3738};
3739
c4e84bde
RM		 3740static int __devinit qlge_probe(struct pci_dev *pdev,
3741 const struct pci_device_id *pci_entry)
3742{
3743 struct net_device *ndev = NULL;
3744 struct ql_adapter *qdev = NULL;
3745 static int cards_found = 0;
3746 int err = 0;
3747
3748 ndev = alloc_etherdev(sizeof(struct ql_adapter));
3749 if (!ndev)
3750 return -ENOMEM;
3751
3752 err = ql_init_device(pdev, ndev, cards_found);
3753 if (err < 0) {
3754 free_netdev(ndev);
3755 return err;
3756 }
3757
3758 qdev = netdev_priv(ndev);
3759 SET_NETDEV_DEV(ndev, &pdev->dev);
3760 ndev->features = (0
3761 | NETIF_F_IP_CSUM
3762 | NETIF_F_SG
3763 | NETIF_F_TSO
3764 | NETIF_F_TSO6
3765 | NETIF_F_TSO_ECN
3766 | NETIF_F_HW_VLAN_TX
3767 | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3768
3769 if (test_bit(QL_DMA64, &qdev->flags))
3770 ndev->features |= NETIF_F_HIGHDMA;
3771
3772 /*
3773 * Set up net_device structure.
3774 */
3775 ndev->tx_queue_len = qdev->tx_ring_size;
3776 ndev->irq = pdev->irq;
25ed7849
SH		 3777
3778 ndev->netdev_ops = &qlge_netdev_ops;
c4e84bde 3779 SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
c4e84bde 3780 ndev->watchdog_timeo = 10 * HZ;
25ed7849 3781
c4e84bde
RM		 3782 err = register_netdev(ndev);
3783 if (err) {
3784 dev_err(&pdev->dev, "net device registration failed.\n");
3785 ql_release_all(pdev);
3786 pci_disable_device(pdev);
3787 return err;
3788 }
3789 netif_carrier_off(ndev);
3790 netif_stop_queue(ndev);
3791 ql_display_dev_info(ndev);
3792 cards_found++;
3793 return 0;
3794}
3795
3796static void __devexit qlge_remove(struct pci_dev *pdev)
3797{
3798 struct net_device *ndev = pci_get_drvdata(pdev);
3799 unregister_netdev(ndev);
3800 ql_release_all(pdev);
3801 pci_disable_device(pdev);
3802 free_netdev(ndev);
3803}
3804
3805/*
3806 * This callback is called by the PCI subsystem whenever
3807 * a PCI bus error is detected.
3808 */
3809static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3810 enum pci_channel_state state)
3811{
3812 struct net_device *ndev = pci_get_drvdata(pdev);
3813 struct ql_adapter *qdev = netdev_priv(ndev);
3814
3815 if (netif_running(ndev))
3816 ql_adapter_down(qdev);
3817
3818 pci_disable_device(pdev);
3819
3820 /* Request a slot reset. */
3821 return PCI_ERS_RESULT_NEED_RESET;
3822}
3823
3824/*
3825 * This callback is called after the PCI buss has been reset.
3826 * Basically, this tries to restart the card from scratch.
3827 * This is a shortened version of the device probe/discovery code,
3828 * it resembles the first-half of the () routine.
3829 */
3830static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3831{
3832 struct net_device *ndev = pci_get_drvdata(pdev);
3833 struct ql_adapter *qdev = netdev_priv(ndev);
3834
3835 if (pci_enable_device(pdev)) {
3836 QPRINTK(qdev, IFUP, ERR,
3837 "Cannot re-enable PCI device after reset.\n");
3838 return PCI_ERS_RESULT_DISCONNECT;
3839 }
3840
3841 pci_set_master(pdev);
3842
3843 netif_carrier_off(ndev);
3844 netif_stop_queue(ndev);
3845 ql_adapter_reset(qdev);
3846
3847 /* Make sure the EEPROM is good */
3848 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3849
3850 if (!is_valid_ether_addr(ndev->perm_addr)) {
3851 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3852 return PCI_ERS_RESULT_DISCONNECT;
3853 }
3854
3855 return PCI_ERS_RESULT_RECOVERED;
3856}
3857
3858static void qlge_io_resume(struct pci_dev *pdev)
3859{
3860 struct net_device *ndev = pci_get_drvdata(pdev);
3861 struct ql_adapter *qdev = netdev_priv(ndev);
3862
3863 pci_set_master(pdev);
3864
3865 if (netif_running(ndev)) {
3866 if (ql_adapter_up(qdev)) {
3867 QPRINTK(qdev, IFUP, ERR,
3868 "Device initialization failed after reset.\n");
3869 return;
3870 }
3871 }
3872
3873 netif_device_attach(ndev);
3874}
3875
3876static struct pci_error_handlers qlge_err_handler = {
3877 .error_detected = qlge_io_error_detected,
3878 .slot_reset = qlge_io_slot_reset,
3879 .resume = qlge_io_resume,
3880};
3881
3882static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3883{
3884 struct net_device *ndev = pci_get_drvdata(pdev);
3885 struct ql_adapter *qdev = netdev_priv(ndev);
0047e5d2 3886 int err, i;
c4e84bde
RM		 3887
3888 netif_device_detach(ndev);
3889
3890 if (netif_running(ndev)) {
3891 err = ql_adapter_down(qdev);
3892 if (!err)
3893 return err;
3894 }
3895
0047e5d2
RM		 3896 for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
3897 netif_napi_del(&qdev->rx_ring[i].napi);
3898
c4e84bde
RM		 3899 err = pci_save_state(pdev);
3900 if (err)
3901 return err;
3902
3903 pci_disable_device(pdev);
3904
3905 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3906
3907 return 0;
3908}
3909
04da2cf9 3910#ifdef CONFIG_PM
c4e84bde
RM		 3911static int qlge_resume(struct pci_dev *pdev)
3912{
3913 struct net_device *ndev = pci_get_drvdata(pdev);
3914 struct ql_adapter *qdev = netdev_priv(ndev);
3915 int err;
3916
3917 pci_set_power_state(pdev, PCI_D0);
3918 pci_restore_state(pdev);
3919 err = pci_enable_device(pdev);
3920 if (err) {
3921 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
3922 return err;
3923 }
3924 pci_set_master(pdev);
3925
3926 pci_enable_wake(pdev, PCI_D3hot, 0);
3927 pci_enable_wake(pdev, PCI_D3cold, 0);
3928
3929 if (netif_running(ndev)) {
3930 err = ql_adapter_up(qdev);
3931 if (err)
3932 return err;
3933 }
3934
3935 netif_device_attach(ndev);
3936
3937 return 0;
3938}
04da2cf9 3939#endif /* CONFIG_PM */
c4e84bde
RM		 3940
3941static void qlge_shutdown(struct pci_dev *pdev)
3942{
3943 qlge_suspend(pdev, PMSG_SUSPEND);
3944}
3945
3946static struct pci_driver qlge_driver = {
3947 .name = DRV_NAME,
3948 .id_table = qlge_pci_tbl,
3949 .probe = qlge_probe,
3950 .remove = __devexit_p(qlge_remove),
3951#ifdef CONFIG_PM
3952 .suspend = qlge_suspend,
3953 .resume = qlge_resume,
3954#endif
3955 .shutdown = qlge_shutdown,
3956 .err_handler = &qlge_err_handler
3957};
3958
3959static int __init qlge_init_module(void)
3960{
3961 return pci_register_driver(&qlge_driver);
3962}
3963
3964static void __exit qlge_exit(void)
3965{
3966 pci_unregister_driver(&qlge_driver);
3967}
3968
3969module_init(qlge_init_module);
3970module_exit(qlge_exit);
Linux kernel - Deliverables
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