projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
fs_enet: Don't call phy_mii_ioctl() in atomic context.
[deliverable/linux.git] / drivers / net / r6040.c
CommitLineData
7a47dd7a
SW		 1/*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
5ac5d616 6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7a47dd7a
SW		 7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23*/
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/version.h>
28#include <linux/moduleparam.h>
29#include <linux/string.h>
30#include <linux/timer.h>
31#include <linux/errno.h>
32#include <linux/ioport.h>
33#include <linux/slab.h>
34#include <linux/interrupt.h>
35#include <linux/pci.h>
36#include <linux/netdevice.h>
37#include <linux/etherdevice.h>
38#include <linux/skbuff.h>
39#include <linux/init.h>
40#include <linux/delay.h>
41#include <linux/mii.h>
42#include <linux/ethtool.h>
43#include <linux/crc32.h>
44#include <linux/spinlock.h>
092427be
JG		 45#include <linux/bitops.h>
46#include <linux/io.h>
47#include <linux/irq.h>
48#include <linux/uaccess.h>
7a47dd7a
SW		 49
50#include <asm/processor.h>
7a47dd7a
SW		 51
52#define DRV_NAME "r6040"
53#define DRV_VERSION "0.16"
54#define DRV_RELDATE "10Nov2007"
55
56/* PHY CHIP Address */
57#define PHY1_ADDR 1 /* For MAC1 */
58#define PHY2_ADDR 2 /* For MAC2 */
59#define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
60#define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
61
62/* Time in jiffies before concluding the transmitter is hung. */
5ac5d616 63#define TX_TIMEOUT (6000 * HZ / 1000)
7a47dd7a
SW		 64
65/* RDC MAC I/O Size */
66#define R6040_IO_SIZE 256
67
68/* MAX RDC MAC */
69#define MAX_MAC 2
70
71/* MAC registers */
72#define MCR0 0x00 /* Control register 0 */
73#define MCR1 0x04 /* Control register 1 */
74#define MAC_RST 0x0001 /* Reset the MAC */
75#define MBCR 0x08 /* Bus control */
76#define MT_ICR 0x0C /* TX interrupt control */
77#define MR_ICR 0x10 /* RX interrupt control */
78#define MTPR 0x14 /* TX poll command register */
79#define MR_BSR 0x18 /* RX buffer size */
80#define MR_DCR 0x1A /* RX descriptor control */
81#define MLSR 0x1C /* Last status */
82#define MMDIO 0x20 /* MDIO control register */
83#define MDIO_WRITE 0x4000 /* MDIO write */
84#define MDIO_READ 0x2000 /* MDIO read */
85#define MMRD 0x24 /* MDIO read data register */
86#define MMWD 0x28 /* MDIO write data register */
87#define MTD_SA0 0x2C /* TX descriptor start address 0 */
88#define MTD_SA1 0x30 /* TX descriptor start address 1 */
89#define MRD_SA0 0x34 /* RX descriptor start address 0 */
90#define MRD_SA1 0x38 /* RX descriptor start address 1 */
91#define MISR 0x3C /* Status register */
92#define MIER 0x40 /* INT enable register */
93#define MSK_INT 0x0000 /* Mask off interrupts */
94#define ME_CISR 0x44 /* Event counter INT status */
95#define ME_CIER 0x48 /* Event counter INT enable */
96#define MR_CNT 0x50 /* Successfully received packet counter */
97#define ME_CNT0 0x52 /* Event counter 0 */
98#define ME_CNT1 0x54 /* Event counter 1 */
99#define ME_CNT2 0x56 /* Event counter 2 */
100#define ME_CNT3 0x58 /* Event counter 3 */
101#define MT_CNT 0x5A /* Successfully transmit packet counter */
102#define ME_CNT4 0x5C /* Event counter 4 */
103#define MP_CNT 0x5E /* Pause frame counter register */
104#define MAR0 0x60 /* Hash table 0 */
105#define MAR1 0x62 /* Hash table 1 */
106#define MAR2 0x64 /* Hash table 2 */
107#define MAR3 0x66 /* Hash table 3 */
108#define MID_0L 0x68 /* Multicast address MID0 Low */
109#define MID_0M 0x6A /* Multicast address MID0 Medium */
110#define MID_0H 0x6C /* Multicast address MID0 High */
111#define MID_1L 0x70 /* MID1 Low */
112#define MID_1M 0x72 /* MID1 Medium */
113#define MID_1H 0x74 /* MID1 High */
114#define MID_2L 0x78 /* MID2 Low */
115#define MID_2M 0x7A /* MID2 Medium */
116#define MID_2H 0x7C /* MID2 High */
117#define MID_3L 0x80 /* MID3 Low */
118#define MID_3M 0x82 /* MID3 Medium */
119#define MID_3H 0x84 /* MID3 High */
120#define PHY_CC 0x88 /* PHY status change configuration register */
121#define PHY_ST 0x8A /* PHY status register */
122#define MAC_SM 0xAC /* MAC status machine */
123#define MAC_ID 0xBE /* Identifier register */
124
125#define TX_DCNT 0x80 /* TX descriptor count */
126#define RX_DCNT 0x80 /* RX descriptor count */
127#define MAX_BUF_SIZE 0x600
6c323103
FR		 128#define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
129#define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
7a47dd7a
SW		 130#define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
131#define MCAST_MAX 4 /* Max number multicast addresses to filter */
132
133/* PHY settings */
134#define ICPLUS_PHY_ID 0x0243
135
136MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
137 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
138 "Florian Fainelli <florian@openwrt.org>");
139MODULE_LICENSE("GPL");
140MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
141
142#define RX_INT 0x0001
143#define TX_INT 0x0010
144#define RX_NO_DESC_INT 0x0002
145#define INT_MASK (RX_INT | TX_INT)
146
147struct r6040_descriptor {
148 u16 status, len; /* 0-3 */
149 __le32 buf; /* 4-7 */
150 __le32 ndesc; /* 8-B */
151 u32 rev1; /* C-F */
152 char *vbufp; /* 10-13 */
153 struct r6040_descriptor *vndescp; /* 14-17 */
154 struct sk_buff *skb_ptr; /* 18-1B */
155 u32 rev2; /* 1C-1F */
156} __attribute__((aligned(32)));
157
158struct r6040_private {
159 spinlock_t lock; /* driver lock */
160 struct timer_list timer;
161 struct pci_dev *pdev;
162 struct r6040_descriptor *rx_insert_ptr;
163 struct r6040_descriptor *rx_remove_ptr;
164 struct r6040_descriptor *tx_insert_ptr;
165 struct r6040_descriptor *tx_remove_ptr;
6c323103
FR		 166 struct r6040_descriptor *rx_ring;
167 struct r6040_descriptor *tx_ring;
168 dma_addr_t rx_ring_dma;
169 dma_addr_t tx_ring_dma;
7a47dd7a
SW		 170 u16 tx_free_desc, rx_free_desc, phy_addr, phy_mode;
171 u16 mcr0, mcr1;
7a47dd7a
SW		 172 u16 switch_sig;
173 struct net_device *dev;
174 struct mii_if_info mii_if;
175 struct napi_struct napi;
7a47dd7a
SW		 176 void __iomem *base;
177};
178
179static char version[] __devinitdata = KERN_INFO DRV_NAME
180 ": RDC R6040 NAPI net driver,"
181 "version "DRV_VERSION " (" DRV_RELDATE ")\n";
182
092427be 183static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
7a47dd7a
SW		 184
185/* Read a word data from PHY Chip */
186static int phy_read(void __iomem *ioaddr, int phy_addr, int reg)
187{
188 int limit = 2048;
189 u16 cmd;
190
191 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
192 /* Wait for the read bit to be cleared */
193 while (limit--) {
194 cmd = ioread16(ioaddr + MMDIO);
195 if (cmd & MDIO_READ)
196 break;
197 }
198
199 return ioread16(ioaddr + MMRD);
200}
201
202/* Write a word data from PHY Chip */
203static void phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
204{
205 int limit = 2048;
206 u16 cmd;
207
208 iowrite16(val, ioaddr + MMWD);
209 /* Write the command to the MDIO bus */
210 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
211 /* Wait for the write bit to be cleared */
212 while (limit--) {
213 cmd = ioread16(ioaddr + MMDIO);
214 if (cmd & MDIO_WRITE)
215 break;
216 }
217}
218
219static int mdio_read(struct net_device *dev, int mii_id, int reg)
220{
221 struct r6040_private *lp = netdev_priv(dev);
222 void __iomem *ioaddr = lp->base;
223
224 return (phy_read(ioaddr, lp->phy_addr, reg));
225}
226
227static void mdio_write(struct net_device *dev, int mii_id, int reg, int val)
228{
229 struct r6040_private *lp = netdev_priv(dev);
230 void __iomem *ioaddr = lp->base;
231
232 phy_write(ioaddr, lp->phy_addr, reg, val);
233}
234
b4f1255d
FF		 235static void r6040_free_txbufs(struct net_device *dev)
236{
237 struct r6040_private *lp = netdev_priv(dev);
238 int i;
239
240 for (i = 0; i < TX_DCNT; i++) {
241 if (lp->tx_insert_ptr->skb_ptr) {
242 pci_unmap_single(lp->pdev, lp->tx_insert_ptr->buf,
243 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
244 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
245 lp->rx_insert_ptr->skb_ptr = NULL;
246 }
247 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
248 }
249}
250
251static void r6040_free_rxbufs(struct net_device *dev)
252{
253 struct r6040_private *lp = netdev_priv(dev);
254 int i;
255
256 for (i = 0; i < RX_DCNT; i++) {
257 if (lp->rx_insert_ptr->skb_ptr) {
258 pci_unmap_single(lp->pdev, lp->rx_insert_ptr->buf,
259 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
260 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
261 lp->rx_insert_ptr->skb_ptr = NULL;
262 }
263 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
264 }
265}
266
b4f1255d
FF		 267static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
268 dma_addr_t desc_dma, int size)
269{
270 struct r6040_descriptor *desc = desc_ring;
271 dma_addr_t mapping = desc_dma;
272
273 while (size-- > 0) {
274 mapping += sizeof(sizeof(*desc));
275 desc->ndesc = cpu_to_le32(mapping);
276 desc->vndescp = desc + 1;
277 desc++;
278 }
279 desc--;
280 desc->ndesc = cpu_to_le32(desc_dma);
281 desc->vndescp = desc_ring;
282}
283
7a47dd7a
SW		 284/* Allocate skb buffer for rx descriptor */
285static void rx_buf_alloc(struct r6040_private *lp, struct net_device *dev)
286{
287 struct r6040_descriptor *descptr;
288 void __iomem *ioaddr = lp->base;
289
290 descptr = lp->rx_insert_ptr;
291 while (lp->rx_free_desc < RX_DCNT) {
ec6d2d45 292 descptr->skb_ptr = netdev_alloc_skb(dev, MAX_BUF_SIZE);
7a47dd7a
SW		 293
294 if (!descptr->skb_ptr)
295 break;
296 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
5125a786 297 descptr->skb_ptr->data,
7a47dd7a
SW		 298 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
299 descptr->status = 0x8000;
300 descptr = descptr->vndescp;
301 lp->rx_free_desc++;
302 /* Trigger RX DMA */
303 iowrite16(lp->mcr0 | 0x0002, ioaddr);
304 }
305 lp->rx_insert_ptr = descptr;
306}
307
b4f1255d
FF		 308static void r6040_alloc_txbufs(struct net_device *dev)
309{
310 struct r6040_private *lp = netdev_priv(dev);
311 void __iomem *ioaddr = lp->base;
312
313 lp->tx_free_desc = TX_DCNT;
314
315 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
316 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
317
318 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
319 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
320}
321
322static void r6040_alloc_rxbufs(struct net_device *dev)
323{
324 struct r6040_private *lp = netdev_priv(dev);
325 void __iomem *ioaddr = lp->base;
326
327 lp->rx_free_desc = 0;
328
329 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
330 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
331
332 rx_buf_alloc(lp, dev);
333
334 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
335 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
336}
7a47dd7a 337
106adf3c
FF		 338static void r6040_tx_timeout(struct net_device *dev)
339{
340 struct r6040_private *priv = netdev_priv(dev);
341 void __iomem *ioaddr = priv->base;
342
343 printk(KERN_WARNING "%s: transmit timed out, status %4.4x, PHY status "
344 "%4.4x\n",
345 dev->name, ioread16(ioaddr + MIER),
346 mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
347
348 disable_irq(dev->irq);
349 napi_disable(&priv->napi);
350 spin_lock(&priv->lock);
351 /* Clear all descriptors */
352 r6040_free_txbufs(dev);
353 r6040_free_rxbufs(dev);
354 r6040_alloc_txbufs(dev);
355 r6040_alloc_rxbufs(dev);
356
357 /* Reset MAC */
358 iowrite16(MAC_RST, ioaddr + MCR1);
359 spin_unlock(&priv->lock);
360 enable_irq(dev->irq);
361
362 dev->stats.tx_errors++;
363 netif_wake_queue(dev);
364}
365
7a47dd7a
SW		 366static struct net_device_stats *r6040_get_stats(struct net_device *dev)
367{
368 struct r6040_private *priv = netdev_priv(dev);
369 void __iomem *ioaddr = priv->base;
370 unsigned long flags;
371
372 spin_lock_irqsave(&priv->lock, flags);
d248fd77
FF		 373 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
374 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
7a47dd7a
SW		 375 spin_unlock_irqrestore(&priv->lock, flags);
376
d248fd77 377 return &dev->stats;
7a47dd7a
SW		 378}
379
380/* Stop RDC MAC and Free the allocated resource */
381static void r6040_down(struct net_device *dev)
382{
383 struct r6040_private *lp = netdev_priv(dev);
384 void __iomem *ioaddr = lp->base;
6c323103 385 struct pci_dev *pdev = lp->pdev;
7a47dd7a
SW		 386 int limit = 2048;
387 u16 *adrp;
388 u16 cmd;
389
390 /* Stop MAC */
391 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
392 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
393 while (limit--) {
394 cmd = ioread16(ioaddr + MCR1);
395 if (cmd & 0x1)
396 break;
397 }
398
399 /* Restore MAC Address to MIDx */
400 adrp = (u16 *) dev->dev_addr;
401 iowrite16(adrp[0], ioaddr + MID_0L);
402 iowrite16(adrp[1], ioaddr + MID_0M);
403 iowrite16(adrp[2], ioaddr + MID_0H);
404 free_irq(dev->irq, dev);
b4f1255d 405
7a47dd7a 406 /* Free RX buffer */
b4f1255d 407 r6040_free_rxbufs(dev);
7a47dd7a
SW		 408
409 /* Free TX buffer */
b4f1255d 410 r6040_free_txbufs(dev);
7a47dd7a
SW		 411
412 /* Free Descriptor memory */
6c323103
FR		 413 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
414 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
7a47dd7a
SW		 415}
416
5ac5d616 417static int r6040_close(struct net_device *dev)
7a47dd7a
SW		 418{
419 struct r6040_private *lp = netdev_priv(dev);
420
421 /* deleted timer */
422 del_timer_sync(&lp->timer);
423
424 spin_lock_irq(&lp->lock);
425 netif_stop_queue(dev);
426 r6040_down(dev);
427 spin_unlock_irq(&lp->lock);
428
429 return 0;
430}
431
432/* Status of PHY CHIP */
433static int phy_mode_chk(struct net_device *dev)
434{
435 struct r6040_private *lp = netdev_priv(dev);
436 void __iomem *ioaddr = lp->base;
437 int phy_dat;
438
439 /* PHY Link Status Check */
440 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
441 if (!(phy_dat & 0x4))
442 phy_dat = 0x8000; /* Link Failed, full duplex */
443
444 /* PHY Chip Auto-Negotiation Status */
445 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
446 if (phy_dat & 0x0020) {
447 /* Auto Negotiation Mode */
448 phy_dat = phy_read(ioaddr, lp->phy_addr, 5);
449 phy_dat &= phy_read(ioaddr, lp->phy_addr, 4);
450 if (phy_dat & 0x140)
451 /* Force full duplex */
452 phy_dat = 0x8000;
453 else
454 phy_dat = 0;
455 } else {
456 /* Force Mode */
457 phy_dat = phy_read(ioaddr, lp->phy_addr, 0);
458 if (phy_dat & 0x100)
459 phy_dat = 0x8000;
460 else
461 phy_dat = 0x0000;
462 }
463
464 return phy_dat;
465};
466
467static void r6040_set_carrier(struct mii_if_info *mii)
468{
469 if (phy_mode_chk(mii->dev)) {
470 /* autoneg is off: Link is always assumed to be up */
471 if (!netif_carrier_ok(mii->dev))
472 netif_carrier_on(mii->dev);
473 } else
474 phy_mode_chk(mii->dev);
475}
476
477static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
478{
479 struct r6040_private *lp = netdev_priv(dev);
5ac5d616 480 struct mii_ioctl_data *data = if_mii(rq);
7a47dd7a
SW		 481 int rc;
482
483 if (!netif_running(dev))
484 return -EINVAL;
485 spin_lock_irq(&lp->lock);
486 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
487 spin_unlock_irq(&lp->lock);
488 r6040_set_carrier(&lp->mii_if);
489 return rc;
490}
491
492static int r6040_rx(struct net_device *dev, int limit)
493{
494 struct r6040_private *priv = netdev_priv(dev);
495 int count;
496 void __iomem *ioaddr = priv->base;
497 u16 err;
498
499 for (count = 0; count < limit; ++count) {
500 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
501 struct sk_buff *skb_ptr;
502
503 /* Disable RX interrupt */
504 iowrite16(ioread16(ioaddr + MIER) & (~RX_INT), ioaddr + MIER);
505 descptr = priv->rx_remove_ptr;
506
507 /* Check for errors */
508 err = ioread16(ioaddr + MLSR);
d248fd77
FF		 509 if (err & 0x0400)
510 dev->stats.rx_errors++;
7a47dd7a 511 /* RX FIFO over-run */
d248fd77
FF		 512 if (err & 0x8000)
513 dev->stats.rx_fifo_errors++;
7a47dd7a 514 /* RX descriptor unavailable */
d248fd77
FF		 515 if (err & 0x0080)
516 dev->stats.rx_frame_errors++;
7a47dd7a 517 /* Received packet with length over buffer lenght */
d248fd77
FF		 518 if (err & 0x0020)
519 dev->stats.rx_over_errors++;
7a47dd7a 520 /* Received packet with too long or short */
d248fd77
FF		 521 if (err & (0x0010 | 0x0008))
522 dev->stats.rx_length_errors++;
7a47dd7a
SW		 523 /* Received packet with CRC errors */
524 if (err & 0x0004) {
525 spin_lock(&priv->lock);
d248fd77 526 dev->stats.rx_crc_errors++;
7a47dd7a
SW		 527 spin_unlock(&priv->lock);
528 }
529
530 while (priv->rx_free_desc) {
531 /* No RX packet */
532 if (descptr->status & 0x8000)
533 break;
534 skb_ptr = descptr->skb_ptr;
535 if (!skb_ptr) {
536 printk(KERN_ERR "%s: Inconsistent RX"
537 "descriptor chain\n",
538 dev->name);
539 break;
540 }
541 descptr->skb_ptr = NULL;
542 skb_ptr->dev = priv->dev;
543 /* Do not count the CRC */
544 skb_put(skb_ptr, descptr->len - 4);
545 pci_unmap_single(priv->pdev, descptr->buf,
546 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
547 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
548 /* Send to upper layer */
549 netif_receive_skb(skb_ptr);
550 dev->last_rx = jiffies;
d248fd77
FF		 551 dev->stats.rx_packets++;
552 dev->stats.rx_bytes += descptr->len;
7a47dd7a
SW		 553 /* To next descriptor */
554 descptr = descptr->vndescp;
555 priv->rx_free_desc--;
556 }
557 priv->rx_remove_ptr = descptr;
558 }
559 /* Allocate new RX buffer */
560 if (priv->rx_free_desc < RX_DCNT)
561 rx_buf_alloc(priv, priv->dev);
562
563 return count;
564}
565
566static void r6040_tx(struct net_device *dev)
567{
568 struct r6040_private *priv = netdev_priv(dev);
569 struct r6040_descriptor *descptr;
570 void __iomem *ioaddr = priv->base;
571 struct sk_buff *skb_ptr;
572 u16 err;
573
574 spin_lock(&priv->lock);
575 descptr = priv->tx_remove_ptr;
576 while (priv->tx_free_desc < TX_DCNT) {
577 /* Check for errors */
578 err = ioread16(ioaddr + MLSR);
579
d248fd77
FF		 580 if (err & 0x0200)
581 dev->stats.rx_fifo_errors++;
582 if (err & (0x2000 | 0x4000))
583 dev->stats.tx_carrier_errors++;
7a47dd7a
SW		 584
585 if (descptr->status & 0x8000)
ec6d2d45 586 break; /* Not complete */
7a47dd7a
SW		 587 skb_ptr = descptr->skb_ptr;
588 pci_unmap_single(priv->pdev, descptr->buf,
589 skb_ptr->len, PCI_DMA_TODEVICE);
590 /* Free buffer */
591 dev_kfree_skb_irq(skb_ptr);
592 descptr->skb_ptr = NULL;
593 /* To next descriptor */
594 descptr = descptr->vndescp;
595 priv->tx_free_desc++;
596 }
597 priv->tx_remove_ptr = descptr;
598
599 if (priv->tx_free_desc)
600 netif_wake_queue(dev);
601 spin_unlock(&priv->lock);
602}
603
604static int r6040_poll(struct napi_struct *napi, int budget)
605{
606 struct r6040_private *priv =
607 container_of(napi, struct r6040_private, napi);
608 struct net_device *dev = priv->dev;
609 void __iomem *ioaddr = priv->base;
610 int work_done;
611
612 work_done = r6040_rx(dev, budget);
613
614 if (work_done < budget) {
615 netif_rx_complete(dev, napi);
616 /* Enable RX interrupt */
617 iowrite16(ioread16(ioaddr + MIER) | RX_INT, ioaddr + MIER);
618 }
619 return work_done;
620}
621
622/* The RDC interrupt handler. */
623static irqreturn_t r6040_interrupt(int irq, void *dev_id)
624{
625 struct net_device *dev = dev_id;
626 struct r6040_private *lp = netdev_priv(dev);
627 void __iomem *ioaddr = lp->base;
628 u16 status;
7a47dd7a
SW		 629
630 /* Mask off RDC MAC interrupt */
631 iowrite16(MSK_INT, ioaddr + MIER);
632 /* Read MISR status and clear */
633 status = ioread16(ioaddr + MISR);
634
635 if (status == 0x0000 || status == 0xffff)
636 return IRQ_NONE;
637
638 /* RX interrupt request */
639 if (status & 0x01) {
640 netif_rx_schedule(dev, &lp->napi);
641 iowrite16(TX_INT, ioaddr + MIER);
642 }
643
644 /* TX interrupt request */
645 if (status & 0x10)
646 r6040_tx(dev);
647
ec6d2d45 648 return IRQ_HANDLED;
7a47dd7a
SW		 649}
650
651#ifdef CONFIG_NET_POLL_CONTROLLER
652static void r6040_poll_controller(struct net_device *dev)
653{
654 disable_irq(dev->irq);
5ac5d616 655 r6040_interrupt(dev->irq, dev);
7a47dd7a
SW		 656 enable_irq(dev->irq);
657}
658#endif
659
7a47dd7a
SW		 660/* Init RDC MAC */
661static void r6040_up(struct net_device *dev)
662{
663 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a 664 void __iomem *ioaddr = lp->base;
7a47dd7a 665
b4f1255d
FF		 666 /* Initialise and alloc RX/TX buffers */
667 r6040_alloc_txbufs(dev);
668 r6040_alloc_rxbufs(dev);
7a47dd7a
SW		 669
670 /* Buffer Size Register */
671 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
672 /* Read the PHY ID */
673 lp->switch_sig = phy_read(ioaddr, 0, 2);
674
675 if (lp->switch_sig == ICPLUS_PHY_ID) {
676 phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
677 lp->phy_mode = 0x8000;
678 } else {
679 /* PHY Mode Check */
680 phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
681 phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
682
683 if (PHY_MODE == 0x3100)
684 lp->phy_mode = phy_mode_chk(dev);
685 else
686 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
687 }
688 /* MAC Bus Control Register */
689 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
690
691 /* MAC TX/RX Enable */
692 lp->mcr0 |= lp->phy_mode;
693 iowrite16(lp->mcr0, ioaddr);
694
695 /* set interrupt waiting time and packet numbers */
696 iowrite16(0x0F06, ioaddr + MT_ICR);
697 iowrite16(0x0F06, ioaddr + MR_ICR);
698
699 /* improve performance (by RDC guys) */
700 phy_write(ioaddr, 30, 17, (phy_read(ioaddr, 30, 17) | 0x4000));
701 phy_write(ioaddr, 30, 17, ~((~phy_read(ioaddr, 30, 17)) | 0x2000));
702 phy_write(ioaddr, 0, 19, 0x0000);
703 phy_write(ioaddr, 0, 30, 0x01F0);
704
705 /* Interrupt Mask Register */
706 iowrite16(INT_MASK, ioaddr + MIER);
707}
708
709/*
710 A periodic timer routine
711 Polling PHY Chip Link Status
712*/
713static void r6040_timer(unsigned long data)
714{
715 struct net_device *dev = (struct net_device *)data;
e6a9ea10 716 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a
SW		 717 void __iomem *ioaddr = lp->base;
718 u16 phy_mode;
719
720 /* Polling PHY Chip Status */
721 if (PHY_MODE == 0x3100)
722 phy_mode = phy_mode_chk(dev);
723 else
724 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
725
726 if (phy_mode != lp->phy_mode) {
727 lp->phy_mode = phy_mode;
728 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
729 iowrite16(lp->mcr0, ioaddr);
730 printk(KERN_INFO "Link Change %x \n", ioread16(ioaddr));
731 }
732
733 /* Timer active again */
106adf3c 734 mod_timer(&lp->timer, jiffies + round_jiffies(HZ));
7a47dd7a
SW		 735}
736
737/* Read/set MAC address routines */
738static void r6040_mac_address(struct net_device *dev)
739{
740 struct r6040_private *lp = netdev_priv(dev);
741 void __iomem *ioaddr = lp->base;
742 u16 *adrp;
743
744 /* MAC operation register */
745 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
746 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
747 iowrite16(0, ioaddr + MAC_SM);
748 udelay(5000);
749
750 /* Restore MAC Address */
751 adrp = (u16 *) dev->dev_addr;
752 iowrite16(adrp[0], ioaddr + MID_0L);
753 iowrite16(adrp[1], ioaddr + MID_0M);
754 iowrite16(adrp[2], ioaddr + MID_0H);
755}
756
5ac5d616 757static int r6040_open(struct net_device *dev)
7a47dd7a 758{
5ac5d616 759 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a
SW		 760 int ret;
761
762 /* Request IRQ and Register interrupt handler */
763 ret = request_irq(dev->irq, &r6040_interrupt,
764 IRQF_SHARED, dev->name, dev);
765 if (ret)
766 return ret;
767
768 /* Set MAC address */
769 r6040_mac_address(dev);
770
771 /* Allocate Descriptor memory */
6c323103
FR		 772 lp->rx_ring =
773 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
774 if (!lp->rx_ring)
7a47dd7a
SW		 775 return -ENOMEM;
776
6c323103
FR		 777 lp->tx_ring =
778 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
779 if (!lp->tx_ring) {
780 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
781 lp->rx_ring_dma);
782 return -ENOMEM;
783 }
784
7a47dd7a
SW		 785 r6040_up(dev);
786
787 napi_enable(&lp->napi);
788 netif_start_queue(dev);
789
106adf3c
FF		 790 /* set and active a timer process */
791 setup_timer(&lp->timer, r6040_timer, (unsigned long) dev);
792 if (lp->switch_sig != ICPLUS_PHY_ID)
793 mod_timer(&lp->timer, jiffies + HZ);
7a47dd7a
SW		 794 return 0;
795}
796
5ac5d616 797static int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
7a47dd7a
SW		 798{
799 struct r6040_private *lp = netdev_priv(dev);
800 struct r6040_descriptor *descptr;
801 void __iomem *ioaddr = lp->base;
802 unsigned long flags;
092427be 803 int ret = NETDEV_TX_OK;
7a47dd7a
SW		 804
805 /* Critical Section */
806 spin_lock_irqsave(&lp->lock, flags);
807
808 /* TX resource check */
809 if (!lp->tx_free_desc) {
810 spin_unlock_irqrestore(&lp->lock, flags);
092427be 811 netif_stop_queue(dev);
7a47dd7a 812 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
092427be 813 ret = NETDEV_TX_BUSY;
7a47dd7a
SW		 814 return ret;
815 }
816
817 /* Statistic Counter */
818 dev->stats.tx_packets++;
819 dev->stats.tx_bytes += skb->len;
820 /* Set TX descriptor & Transmit it */
821 lp->tx_free_desc--;
822 descptr = lp->tx_insert_ptr;
823 if (skb->len < MISR)
824 descptr->len = MISR;
825 else
826 descptr->len = skb->len;
827
828 descptr->skb_ptr = skb;
829 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
830 skb->data, skb->len, PCI_DMA_TODEVICE));
831 descptr->status = 0x8000;
832 /* Trigger the MAC to check the TX descriptor */
833 iowrite16(0x01, ioaddr + MTPR);
834 lp->tx_insert_ptr = descptr->vndescp;
835
836 /* If no tx resource, stop */
837 if (!lp->tx_free_desc)
838 netif_stop_queue(dev);
839
840 dev->trans_start = jiffies;
841 spin_unlock_irqrestore(&lp->lock, flags);
842 return ret;
843}
844
5ac5d616 845static void r6040_multicast_list(struct net_device *dev)
7a47dd7a
SW		 846{
847 struct r6040_private *lp = netdev_priv(dev);
848 void __iomem *ioaddr = lp->base;
849 u16 *adrp;
850 u16 reg;
851 unsigned long flags;
852 struct dev_mc_list *dmi = dev->mc_list;
853 int i;
854
855 /* MAC Address */
856 adrp = (u16 *)dev->dev_addr;
857 iowrite16(adrp[0], ioaddr + MID_0L);
858 iowrite16(adrp[1], ioaddr + MID_0M);
859 iowrite16(adrp[2], ioaddr + MID_0H);
860
861 /* Promiscous Mode */
862 spin_lock_irqsave(&lp->lock, flags);
863
864 /* Clear AMCP & PROM bits */
865 reg = ioread16(ioaddr) & ~0x0120;
866 if (dev->flags & IFF_PROMISC) {
867 reg |= 0x0020;
868 lp->mcr0 |= 0x0020;
869 }
870 /* Too many multicast addresses
871 * accept all traffic */
872 else if ((dev->mc_count > MCAST_MAX)
873 || (dev->flags & IFF_ALLMULTI))
874 reg |= 0x0020;
875
876 iowrite16(reg, ioaddr);
877 spin_unlock_irqrestore(&lp->lock, flags);
878
879 /* Build the hash table */
880 if (dev->mc_count > MCAST_MAX) {
881 u16 hash_table[4];
882 u32 crc;
883
884 for (i = 0; i < 4; i++)
885 hash_table[i] = 0;
886
887 for (i = 0; i < dev->mc_count; i++) {
888 char *addrs = dmi->dmi_addr;
889
890 dmi = dmi->next;
891
892 if (!(*addrs & 1))
893 continue;
894
895 crc = ether_crc_le(6, addrs);
896 crc >>= 26;
897 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
898 }
899 /* Write the index of the hash table */
900 for (i = 0; i < 4; i++)
901 iowrite16(hash_table[i] << 14, ioaddr + MCR1);
902 /* Fill the MAC hash tables with their values */
903 iowrite16(hash_table[0], ioaddr + MAR0);
904 iowrite16(hash_table[1], ioaddr + MAR1);
905 iowrite16(hash_table[2], ioaddr + MAR2);
906 iowrite16(hash_table[3], ioaddr + MAR3);
907 }
908 /* Multicast Address 1~4 case */
909 for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
910 adrp = (u16 *)dmi->dmi_addr;
911 iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
912 iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
913 iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
914 dmi = dmi->next;
915 }
916 for (i = dev->mc_count; i < MCAST_MAX; i++) {
917 iowrite16(0xffff, ioaddr + MID_0L + 8*i);
918 iowrite16(0xffff, ioaddr + MID_0M + 8*i);
919 iowrite16(0xffff, ioaddr + MID_0H + 8*i);
920 }
921}
922
923static void netdev_get_drvinfo(struct net_device *dev,
924 struct ethtool_drvinfo *info)
925{
926 struct r6040_private *rp = netdev_priv(dev);
927
928 strcpy(info->driver, DRV_NAME);
929 strcpy(info->version, DRV_VERSION);
930 strcpy(info->bus_info, pci_name(rp->pdev));
931}
932
933static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
934{
935 struct r6040_private *rp = netdev_priv(dev);
936 int rc;
937
938 spin_lock_irq(&rp->lock);
939 rc = mii_ethtool_gset(&rp->mii_if, cmd);
092427be 940 spin_unlock_irq(&rp->lock);
7a47dd7a
SW		 941
942 return rc;
943}
944
945static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
946{
947 struct r6040_private *rp = netdev_priv(dev);
948 int rc;
949
950 spin_lock_irq(&rp->lock);
951 rc = mii_ethtool_sset(&rp->mii_if, cmd);
952 spin_unlock_irq(&rp->lock);
953 r6040_set_carrier(&rp->mii_if);
954
955 return rc;
956}
957
958static u32 netdev_get_link(struct net_device *dev)
959{
960 struct r6040_private *rp = netdev_priv(dev);
961
962 return mii_link_ok(&rp->mii_if);
963}
964
965static struct ethtool_ops netdev_ethtool_ops = {
966 .get_drvinfo = netdev_get_drvinfo,
967 .get_settings = netdev_get_settings,
968 .set_settings = netdev_set_settings,
969 .get_link = netdev_get_link,
970};
971
7a47dd7a
SW		 972static int __devinit r6040_init_one(struct pci_dev *pdev,
973 const struct pci_device_id *ent)
974{
975 struct net_device *dev;
976 struct r6040_private *lp;
977 void __iomem *ioaddr;
978 int err, io_size = R6040_IO_SIZE;
979 static int card_idx = -1;
980 int bar = 0;
981 long pioaddr;
982 u16 *adrp;
983
984 printk(KERN_INFO "%s\n", version);
985
986 err = pci_enable_device(pdev);
987 if (err)
988 return err;
989
990 /* this should always be supported */
991 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
992 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
993 "not supported by the card\n");
994 return -ENODEV;
995 }
092427be
JG		 996 if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
997 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
998 "not supported by the card\n");
999 return -ENODEV;
1000 }
7a47dd7a
SW		 1001
1002 /* IO Size check */
1003 if (pci_resource_len(pdev, 0) < io_size) {
1004 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
1005 return -EIO;
1006 }
1007
1008 pioaddr = pci_resource_start(pdev, 0); /* IO map base address */
1009 pci_set_master(pdev);
1010
1011 dev = alloc_etherdev(sizeof(struct r6040_private));
1012 if (!dev) {
1013 printk(KERN_ERR "Failed to allocate etherdev\n");
1014 return -ENOMEM;
1015 }
1016 SET_NETDEV_DEV(dev, &pdev->dev);
1017 lp = netdev_priv(dev);
1018 lp->pdev = pdev;
1019
1020 if (pci_request_regions(pdev, DRV_NAME)) {
1021 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
1022 err = -ENODEV;
1023 goto err_out_disable;
1024 }
1025
1026 ioaddr = pci_iomap(pdev, bar, io_size);
1027 if (!ioaddr) {
1028 printk(KERN_ERR "ioremap failed for device %s\n",
1029 pci_name(pdev));
1030 return -EIO;
1031 }
1032
1033 /* Init system & device */
7a47dd7a
SW		 1034 lp->base = ioaddr;
1035 dev->irq = pdev->irq;
1036
1037 spin_lock_init(&lp->lock);
1038 pci_set_drvdata(pdev, dev);
1039
1040 /* Set MAC address */
1041 card_idx++;
1042
1043 adrp = (u16 *)dev->dev_addr;
1044 adrp[0] = ioread16(ioaddr + MID_0L);
1045 adrp[1] = ioread16(ioaddr + MID_0M);
1046 adrp[2] = ioread16(ioaddr + MID_0H);
1047
1048 /* Link new device into r6040_root_dev */
1049 lp->pdev = pdev;
1050
1051 /* Init RDC private data */
1052 lp->mcr0 = 0x1002;
1053 lp->phy_addr = phy_table[card_idx];
1054 lp->switch_sig = 0;
1055
1056 /* The RDC-specific entries in the device structure. */
1057 dev->open = &r6040_open;
1058 dev->hard_start_xmit = &r6040_start_xmit;
1059 dev->stop = &r6040_close;
1060 dev->get_stats = r6040_get_stats;
1061 dev->set_multicast_list = &r6040_multicast_list;
1062 dev->do_ioctl = &r6040_ioctl;
1063 dev->ethtool_ops = &netdev_ethtool_ops;
1064 dev->tx_timeout = &r6040_tx_timeout;
1065 dev->watchdog_timeo = TX_TIMEOUT;
1066#ifdef CONFIG_NET_POLL_CONTROLLER
1067 dev->poll_controller = r6040_poll_controller;
1068#endif
1069 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1070 lp->mii_if.dev = dev;
1071 lp->mii_if.mdio_read = mdio_read;
1072 lp->mii_if.mdio_write = mdio_write;
1073 lp->mii_if.phy_id = lp->phy_addr;
1074 lp->mii_if.phy_id_mask = 0x1f;
1075 lp->mii_if.reg_num_mask = 0x1f;
1076
1077 /* Register net device. After this dev->name assign */
1078 err = register_netdev(dev);
1079 if (err) {
1080 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
1081 goto err_out_res;
1082 }
1083 return 0;
1084
1085err_out_res:
1086 pci_release_regions(pdev);
1087err_out_disable:
1088 pci_disable_device(pdev);
1089 pci_set_drvdata(pdev, NULL);
1090 free_netdev(dev);
1091
1092 return err;
1093}
1094
1095static void __devexit r6040_remove_one(struct pci_dev *pdev)
1096{
1097 struct net_device *dev = pci_get_drvdata(pdev);
1098
1099 unregister_netdev(dev);
1100 pci_release_regions(pdev);
1101 free_netdev(dev);
1102 pci_disable_device(pdev);
1103 pci_set_drvdata(pdev, NULL);
1104}
1105
1106
1107static struct pci_device_id r6040_pci_tbl[] = {
5ac5d616
FR		 1108 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1109 { 0 }
7a47dd7a
SW		 1110};
1111MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1112
1113static struct pci_driver r6040_driver = {
5ac5d616 1114 .name = DRV_NAME,
7a47dd7a
SW		 1115 .id_table = r6040_pci_tbl,
1116 .probe = r6040_init_one,
1117 .remove = __devexit_p(r6040_remove_one),
1118};
1119
1120
1121static int __init r6040_init(void)
1122{
1123 return pci_register_driver(&r6040_driver);
1124}
1125
1126
1127static void __exit r6040_cleanup(void)
1128{
1129 pci_unregister_driver(&r6040_driver);
1130}
1131
1132module_init(r6040_init);
1133module_exit(r6040_cleanup);
Linux kernel - Deliverables
This page took 0.120236 seconds and 5 git commands to generate.