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8250.c: port.lock is irq-safe
[deliverable/linux.git] / drivers / net / r6040.c
CommitLineData
7a47dd7a
SW		 1/*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
5ac5d616 6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7a47dd7a
SW		 7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23*/
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/version.h>
28#include <linux/moduleparam.h>
29#include <linux/string.h>
30#include <linux/timer.h>
31#include <linux/errno.h>
32#include <linux/ioport.h>
33#include <linux/slab.h>
34#include <linux/interrupt.h>
35#include <linux/pci.h>
36#include <linux/netdevice.h>
37#include <linux/etherdevice.h>
38#include <linux/skbuff.h>
39#include <linux/init.h>
40#include <linux/delay.h>
41#include <linux/mii.h>
42#include <linux/ethtool.h>
43#include <linux/crc32.h>
44#include <linux/spinlock.h>
092427be
JG		 45#include <linux/bitops.h>
46#include <linux/io.h>
47#include <linux/irq.h>
48#include <linux/uaccess.h>
7a47dd7a
SW		 49
50#include <asm/processor.h>
7a47dd7a
SW		 51
52#define DRV_NAME "r6040"
1de95294
FF		 53#define DRV_VERSION "0.18"
54#define DRV_RELDATE "13Jul2008"
7a47dd7a
SW		 55
56/* PHY CHIP Address */
57#define PHY1_ADDR 1 /* For MAC1 */
58#define PHY2_ADDR 2 /* For MAC2 */
59#define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
60#define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
61
62/* Time in jiffies before concluding the transmitter is hung. */
5ac5d616 63#define TX_TIMEOUT (6000 * HZ / 1000)
7a47dd7a
SW		 64
65/* RDC MAC I/O Size */
66#define R6040_IO_SIZE 256
67
68/* MAX RDC MAC */
69#define MAX_MAC 2
70
71/* MAC registers */
72#define MCR0 0x00 /* Control register 0 */
73#define MCR1 0x04 /* Control register 1 */
74#define MAC_RST 0x0001 /* Reset the MAC */
75#define MBCR 0x08 /* Bus control */
76#define MT_ICR 0x0C /* TX interrupt control */
77#define MR_ICR 0x10 /* RX interrupt control */
78#define MTPR 0x14 /* TX poll command register */
79#define MR_BSR 0x18 /* RX buffer size */
80#define MR_DCR 0x1A /* RX descriptor control */
81#define MLSR 0x1C /* Last status */
82#define MMDIO 0x20 /* MDIO control register */
83#define MDIO_WRITE 0x4000 /* MDIO write */
84#define MDIO_READ 0x2000 /* MDIO read */
85#define MMRD 0x24 /* MDIO read data register */
86#define MMWD 0x28 /* MDIO write data register */
87#define MTD_SA0 0x2C /* TX descriptor start address 0 */
88#define MTD_SA1 0x30 /* TX descriptor start address 1 */
89#define MRD_SA0 0x34 /* RX descriptor start address 0 */
90#define MRD_SA1 0x38 /* RX descriptor start address 1 */
91#define MISR 0x3C /* Status register */
92#define MIER 0x40 /* INT enable register */
93#define MSK_INT 0x0000 /* Mask off interrupts */
3d254348
FF		 94#define RX_FINISH 0x0001 /* RX finished */
95#define RX_NO_DESC 0x0002 /* No RX descriptor available */
96#define RX_FIFO_FULL 0x0004 /* RX FIFO full */
97#define RX_EARLY 0x0008 /* RX early */
98#define TX_FINISH 0x0010 /* TX finished */
99#define TX_EARLY 0x0080 /* TX early */
100#define EVENT_OVRFL 0x0100 /* Event counter overflow */
101#define LINK_CHANGED 0x0200 /* PHY link changed */
7a47dd7a
SW		 102#define ME_CISR 0x44 /* Event counter INT status */
103#define ME_CIER 0x48 /* Event counter INT enable */
104#define MR_CNT 0x50 /* Successfully received packet counter */
105#define ME_CNT0 0x52 /* Event counter 0 */
106#define ME_CNT1 0x54 /* Event counter 1 */
107#define ME_CNT2 0x56 /* Event counter 2 */
108#define ME_CNT3 0x58 /* Event counter 3 */
109#define MT_CNT 0x5A /* Successfully transmit packet counter */
110#define ME_CNT4 0x5C /* Event counter 4 */
111#define MP_CNT 0x5E /* Pause frame counter register */
112#define MAR0 0x60 /* Hash table 0 */
113#define MAR1 0x62 /* Hash table 1 */
114#define MAR2 0x64 /* Hash table 2 */
115#define MAR3 0x66 /* Hash table 3 */
116#define MID_0L 0x68 /* Multicast address MID0 Low */
117#define MID_0M 0x6A /* Multicast address MID0 Medium */
118#define MID_0H 0x6C /* Multicast address MID0 High */
119#define MID_1L 0x70 /* MID1 Low */
120#define MID_1M 0x72 /* MID1 Medium */
121#define MID_1H 0x74 /* MID1 High */
122#define MID_2L 0x78 /* MID2 Low */
123#define MID_2M 0x7A /* MID2 Medium */
124#define MID_2H 0x7C /* MID2 High */
125#define MID_3L 0x80 /* MID3 Low */
126#define MID_3M 0x82 /* MID3 Medium */
127#define MID_3H 0x84 /* MID3 High */
128#define PHY_CC 0x88 /* PHY status change configuration register */
129#define PHY_ST 0x8A /* PHY status register */
130#define MAC_SM 0xAC /* MAC status machine */
131#define MAC_ID 0xBE /* Identifier register */
132
133#define TX_DCNT 0x80 /* TX descriptor count */
134#define RX_DCNT 0x80 /* RX descriptor count */
135#define MAX_BUF_SIZE 0x600
6c323103
FR		 136#define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
137#define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
7a47dd7a
SW		 138#define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
139#define MCAST_MAX 4 /* Max number multicast addresses to filter */
140
32f565df
FF		 141/* Descriptor status */
142#define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
143#define DSC_RX_OK 0x4000 /* RX was successful */
144#define DSC_RX_ERR 0x0800 /* RX PHY error */
145#define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
146#define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
147#define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
148#define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
149#define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
150#define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
151#define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
152#define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
153#define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
154#define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
155
7a47dd7a
SW		 156/* PHY settings */
157#define ICPLUS_PHY_ID 0x0243
158
159MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
160 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
161 "Florian Fainelli <florian@openwrt.org>");
162MODULE_LICENSE("GPL");
163MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
164
3d254348 165/* RX and TX interrupts that we handle */
e24ddf3a
FF		 166#define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
167#define TX_INTS (TX_FINISH)
168#define INT_MASK (RX_INTS | TX_INTS)
7a47dd7a
SW		 169
170struct r6040_descriptor {
171 u16 status, len; /* 0-3 */
172 __le32 buf; /* 4-7 */
173 __le32 ndesc; /* 8-B */
174 u32 rev1; /* C-F */
175 char *vbufp; /* 10-13 */
176 struct r6040_descriptor *vndescp; /* 14-17 */
177 struct sk_buff *skb_ptr; /* 18-1B */
178 u32 rev2; /* 1C-1F */
179} __attribute__((aligned(32)));
180
181struct r6040_private {
182 spinlock_t lock; /* driver lock */
183 struct timer_list timer;
184 struct pci_dev *pdev;
185 struct r6040_descriptor *rx_insert_ptr;
186 struct r6040_descriptor *rx_remove_ptr;
187 struct r6040_descriptor *tx_insert_ptr;
188 struct r6040_descriptor *tx_remove_ptr;
6c323103
FR		 189 struct r6040_descriptor *rx_ring;
190 struct r6040_descriptor *tx_ring;
191 dma_addr_t rx_ring_dma;
192 dma_addr_t tx_ring_dma;
9ca28dc4 193 u16 tx_free_desc, phy_addr, phy_mode;
7a47dd7a 194 u16 mcr0, mcr1;
7a47dd7a
SW		 195 u16 switch_sig;
196 struct net_device *dev;
197 struct mii_if_info mii_if;
198 struct napi_struct napi;
7a47dd7a
SW		 199 void __iomem *base;
200};
201
202static char version[] __devinitdata = KERN_INFO DRV_NAME
203 ": RDC R6040 NAPI net driver,"
204 "version "DRV_VERSION " (" DRV_RELDATE ")\n";
205
092427be 206static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
7a47dd7a
SW		 207
208/* Read a word data from PHY Chip */
c6e69bb9 209static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
7a47dd7a
SW		 210{
211 int limit = 2048;
212 u16 cmd;
213
214 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
215 /* Wait for the read bit to be cleared */
216 while (limit--) {
217 cmd = ioread16(ioaddr + MMDIO);
218 if (cmd & MDIO_READ)
219 break;
220 }
221
222 return ioread16(ioaddr + MMRD);
223}
224
225/* Write a word data from PHY Chip */
c6e69bb9 226static void r6040_phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
7a47dd7a
SW		 227{
228 int limit = 2048;
229 u16 cmd;
230
231 iowrite16(val, ioaddr + MMWD);
232 /* Write the command to the MDIO bus */
233 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
234 /* Wait for the write bit to be cleared */
235 while (limit--) {
236 cmd = ioread16(ioaddr + MMDIO);
237 if (cmd & MDIO_WRITE)
238 break;
239 }
240}
241
c6e69bb9 242static int r6040_mdio_read(struct net_device *dev, int mii_id, int reg)
7a47dd7a
SW		 243{
244 struct r6040_private *lp = netdev_priv(dev);
245 void __iomem *ioaddr = lp->base;
246
c6e69bb9 247 return (r6040_phy_read(ioaddr, lp->phy_addr, reg));
7a47dd7a
SW		 248}
249
c6e69bb9 250static void r6040_mdio_write(struct net_device *dev, int mii_id, int reg, int val)
7a47dd7a
SW		 251{
252 struct r6040_private *lp = netdev_priv(dev);
253 void __iomem *ioaddr = lp->base;
254
c6e69bb9 255 r6040_phy_write(ioaddr, lp->phy_addr, reg, val);
7a47dd7a
SW		 256}
257
b4f1255d
FF		 258static void r6040_free_txbufs(struct net_device *dev)
259{
260 struct r6040_private *lp = netdev_priv(dev);
261 int i;
262
263 for (i = 0; i < TX_DCNT; i++) {
264 if (lp->tx_insert_ptr->skb_ptr) {
ed773b4a
AV		 265 pci_unmap_single(lp->pdev,
266 le32_to_cpu(lp->tx_insert_ptr->buf),
b4f1255d
FF		 267 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
268 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
269 lp->rx_insert_ptr->skb_ptr = NULL;
270 }
271 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
272 }
273}
274
275static void r6040_free_rxbufs(struct net_device *dev)
276{
277 struct r6040_private *lp = netdev_priv(dev);
278 int i;
279
280 for (i = 0; i < RX_DCNT; i++) {
281 if (lp->rx_insert_ptr->skb_ptr) {
ed773b4a
AV		 282 pci_unmap_single(lp->pdev,
283 le32_to_cpu(lp->rx_insert_ptr->buf),
b4f1255d
FF		 284 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
285 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
286 lp->rx_insert_ptr->skb_ptr = NULL;
287 }
288 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
289 }
290}
291
b4f1255d
FF		 292static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
293 dma_addr_t desc_dma, int size)
294{
295 struct r6040_descriptor *desc = desc_ring;
296 dma_addr_t mapping = desc_dma;
297
298 while (size-- > 0) {
3f6602ad 299 mapping += sizeof(*desc);
b4f1255d
FF		 300 desc->ndesc = cpu_to_le32(mapping);
301 desc->vndescp = desc + 1;
302 desc++;
303 }
304 desc--;
305 desc->ndesc = cpu_to_le32(desc_dma);
306 desc->vndescp = desc_ring;
307}
308
3d463419 309static void r6040_init_txbufs(struct net_device *dev)
b4f1255d
FF		 310{
311 struct r6040_private *lp = netdev_priv(dev);
b4f1255d
FF		 312
313 lp->tx_free_desc = TX_DCNT;
314
315 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
316 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
b4f1255d
FF		 317}
318
3d463419 319static int r6040_alloc_rxbufs(struct net_device *dev)
b4f1255d
FF		 320{
321 struct r6040_private *lp = netdev_priv(dev);
3d463419
FF		 322 struct r6040_descriptor *desc;
323 struct sk_buff *skb;
324 int rc;
b4f1255d
FF		 325
326 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
327 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
328
3d463419
FF		 329 /* Allocate skbs for the rx descriptors */
330 desc = lp->rx_ring;
331 do {
332 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
333 if (!skb) {
334 printk(KERN_ERR "%s: failed to alloc skb for rx\n", dev->name);
335 rc = -ENOMEM;
336 goto err_exit;
337 }
338 desc->skb_ptr = skb;
339 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
340 desc->skb_ptr->data,
341 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
32f565df 342 desc->status = DSC_OWNER_MAC;
3d463419
FF		 343 desc = desc->vndescp;
344 } while (desc != lp->rx_ring);
345
346 return 0;
347
348err_exit:
349 /* Deallocate all previously allocated skbs */
350 r6040_free_rxbufs(dev);
351 return rc;
fec3a23b
FF		 352}
353
354static void r6040_init_mac_regs(struct net_device *dev)
355{
356 struct r6040_private *lp = netdev_priv(dev);
357 void __iomem *ioaddr = lp->base;
358 int limit = 2048;
359 u16 cmd;
360
361 /* Mask Off Interrupt */
362 iowrite16(MSK_INT, ioaddr + MIER);
363
364 /* Reset RDC MAC */
365 iowrite16(MAC_RST, ioaddr + MCR1);
366 while (limit--) {
367 cmd = ioread16(ioaddr + MCR1);
368 if (cmd & 0x1)
369 break;
370 }
371 /* Reset internal state machine */
372 iowrite16(2, ioaddr + MAC_SM);
373 iowrite16(0, ioaddr + MAC_SM);
374 udelay(5000);
375
376 /* MAC Bus Control Register */
377 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
378
379 /* Buffer Size Register */
380 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
381
382 /* Write TX ring start address */
383 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
384 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
b4f1255d 385
fec3a23b 386 /* Write RX ring start address */
b4f1255d
FF		 387 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
388 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
fec3a23b
FF		 389
390 /* Set interrupt waiting time and packet numbers */
31718ded
FF		 391 iowrite16(0, ioaddr + MT_ICR);
392 iowrite16(0, ioaddr + MR_ICR);
fec3a23b
FF		 393
394 /* Enable interrupts */
395 iowrite16(INT_MASK, ioaddr + MIER);
396
397 /* Enable TX and RX */
398 iowrite16(lp->mcr0 | 0x0002, ioaddr);
399
400 /* Let TX poll the descriptors
401 * we may got called by r6040_tx_timeout which has left
402 * some unsent tx buffers */
403 iowrite16(0x01, ioaddr + MTPR);
b4f1255d 404}
7a47dd7a 405
106adf3c
FF		 406static void r6040_tx_timeout(struct net_device *dev)
407{
408 struct r6040_private *priv = netdev_priv(dev);
409 void __iomem *ioaddr = priv->base;
410
fec3a23b
FF		 411 printk(KERN_WARNING "%s: transmit timed out, int enable %4.4x "
412 "status %4.4x, PHY status %4.4x\n",
106adf3c 413 dev->name, ioread16(ioaddr + MIER),
fec3a23b 414 ioread16(ioaddr + MISR),
c6e69bb9 415 r6040_mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
106adf3c 416
106adf3c 417 dev->stats.tx_errors++;
fec3a23b
FF		 418
419 /* Reset MAC and re-init all registers */
420 r6040_init_mac_regs(dev);
106adf3c
FF		 421}
422
7a47dd7a
SW		 423static struct net_device_stats *r6040_get_stats(struct net_device *dev)
424{
425 struct r6040_private *priv = netdev_priv(dev);
426 void __iomem *ioaddr = priv->base;
427 unsigned long flags;
428
429 spin_lock_irqsave(&priv->lock, flags);
d248fd77
FF		 430 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
431 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
7a47dd7a
SW		 432 spin_unlock_irqrestore(&priv->lock, flags);
433
d248fd77 434 return &dev->stats;
7a47dd7a
SW		 435}
436
437/* Stop RDC MAC and Free the allocated resource */
438static void r6040_down(struct net_device *dev)
439{
440 struct r6040_private *lp = netdev_priv(dev);
441 void __iomem *ioaddr = lp->base;
6c323103 442 struct pci_dev *pdev = lp->pdev;
7a47dd7a
SW		 443 int limit = 2048;
444 u16 *adrp;
445 u16 cmd;
446
447 /* Stop MAC */
448 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
449 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
450 while (limit--) {
451 cmd = ioread16(ioaddr + MCR1);
452 if (cmd & 0x1)
453 break;
454 }
455
456 /* Restore MAC Address to MIDx */
457 adrp = (u16 *) dev->dev_addr;
458 iowrite16(adrp[0], ioaddr + MID_0L);
459 iowrite16(adrp[1], ioaddr + MID_0M);
460 iowrite16(adrp[2], ioaddr + MID_0H);
461 free_irq(dev->irq, dev);
b4f1255d 462
7a47dd7a 463 /* Free RX buffer */
b4f1255d 464 r6040_free_rxbufs(dev);
7a47dd7a
SW		 465
466 /* Free TX buffer */
b4f1255d 467 r6040_free_txbufs(dev);
7a47dd7a
SW		 468
469 /* Free Descriptor memory */
6c323103
FR		 470 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
471 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
7a47dd7a
SW		 472}
473
5ac5d616 474static int r6040_close(struct net_device *dev)
7a47dd7a
SW		 475{
476 struct r6040_private *lp = netdev_priv(dev);
477
478 /* deleted timer */
479 del_timer_sync(&lp->timer);
480
481 spin_lock_irq(&lp->lock);
129cf9a7 482 napi_disable(&lp->napi);
7a47dd7a
SW		 483 netif_stop_queue(dev);
484 r6040_down(dev);
485 spin_unlock_irq(&lp->lock);
486
487 return 0;
488}
489
490/* Status of PHY CHIP */
c6e69bb9 491static int r6040_phy_mode_chk(struct net_device *dev)
7a47dd7a
SW		 492{
493 struct r6040_private *lp = netdev_priv(dev);
494 void __iomem *ioaddr = lp->base;
495 int phy_dat;
496
497 /* PHY Link Status Check */
c6e69bb9 498 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
7a47dd7a
SW		 499 if (!(phy_dat & 0x4))
500 phy_dat = 0x8000; /* Link Failed, full duplex */
501
502 /* PHY Chip Auto-Negotiation Status */
c6e69bb9 503 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
7a47dd7a
SW		 504 if (phy_dat & 0x0020) {
505 /* Auto Negotiation Mode */
c6e69bb9
FF		 506 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 5);
507 phy_dat &= r6040_phy_read(ioaddr, lp->phy_addr, 4);
7a47dd7a
SW		 508 if (phy_dat & 0x140)
509 /* Force full duplex */
510 phy_dat = 0x8000;
511 else
512 phy_dat = 0;
513 } else {
514 /* Force Mode */
c6e69bb9 515 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 0);
7a47dd7a
SW		 516 if (phy_dat & 0x100)
517 phy_dat = 0x8000;
518 else
519 phy_dat = 0x0000;
520 }
521
522 return phy_dat;
523};
524
525static void r6040_set_carrier(struct mii_if_info *mii)
526{
c6e69bb9 527 if (r6040_phy_mode_chk(mii->dev)) {
7a47dd7a
SW		 528 /* autoneg is off: Link is always assumed to be up */
529 if (!netif_carrier_ok(mii->dev))
530 netif_carrier_on(mii->dev);
531 } else
c6e69bb9 532 r6040_phy_mode_chk(mii->dev);
7a47dd7a
SW		 533}
534
535static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
536{
537 struct r6040_private *lp = netdev_priv(dev);
5ac5d616 538 struct mii_ioctl_data *data = if_mii(rq);
7a47dd7a
SW		 539 int rc;
540
541 if (!netif_running(dev))
542 return -EINVAL;
543 spin_lock_irq(&lp->lock);
544 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
545 spin_unlock_irq(&lp->lock);
546 r6040_set_carrier(&lp->mii_if);
547 return rc;
548}
549
550static int r6040_rx(struct net_device *dev, int limit)
551{
552 struct r6040_private *priv = netdev_priv(dev);
9ca28dc4
FF		 553 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
554 struct sk_buff *skb_ptr, *new_skb;
555 int count = 0;
7a47dd7a
SW		 556 u16 err;
557
9ca28dc4 558 /* Limit not reached and the descriptor belongs to the CPU */
32f565df 559 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
9ca28dc4
FF		 560 /* Read the descriptor status */
561 err = descptr->status;
562 /* Global error status set */
32f565df 563 if (err & DSC_RX_ERR) {
9ca28dc4 564 /* RX dribble */
32f565df 565 if (err & DSC_RX_ERR_DRI)
9ca28dc4
FF		 566 dev->stats.rx_frame_errors++;
567 /* Buffer lenght exceeded */
32f565df 568 if (err & DSC_RX_ERR_BUF)
9ca28dc4
FF		 569 dev->stats.rx_length_errors++;
570 /* Packet too long */
32f565df 571 if (err & DSC_RX_ERR_LONG)
9ca28dc4
FF		 572 dev->stats.rx_length_errors++;
573 /* Packet < 64 bytes */
32f565df 574 if (err & DSC_RX_ERR_RUNT)
9ca28dc4
FF		 575 dev->stats.rx_length_errors++;
576 /* CRC error */
32f565df 577 if (err & DSC_RX_ERR_CRC) {
9ca28dc4
FF		 578 spin_lock(&priv->lock);
579 dev->stats.rx_crc_errors++;
580 spin_unlock(&priv->lock);
7a47dd7a 581 }
9ca28dc4
FF		 582 goto next_descr;
583 }
584
585 /* Packet successfully received */
586 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
587 if (!new_skb) {
588 dev->stats.rx_dropped++;
589 goto next_descr;
7a47dd7a 590 }
9ca28dc4
FF		 591 skb_ptr = descptr->skb_ptr;
592 skb_ptr->dev = priv->dev;
593
594 /* Do not count the CRC */
595 skb_put(skb_ptr, descptr->len - 4);
596 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
597 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
598 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
599
600 /* Send to upper layer */
601 netif_receive_skb(skb_ptr);
602 dev->last_rx = jiffies;
603 dev->stats.rx_packets++;
604 dev->stats.rx_bytes += descptr->len - 4;
605
606 /* put new skb into descriptor */
607 descptr->skb_ptr = new_skb;
608 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
609 descptr->skb_ptr->data,
610 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
611
612next_descr:
613 /* put the descriptor back to the MAC */
32f565df 614 descptr->status = DSC_OWNER_MAC;
9ca28dc4
FF		 615 descptr = descptr->vndescp;
616 count++;
7a47dd7a 617 }
9ca28dc4 618 priv->rx_remove_ptr = descptr;
7a47dd7a
SW		 619
620 return count;
621}
622
623static void r6040_tx(struct net_device *dev)
624{
625 struct r6040_private *priv = netdev_priv(dev);
626 struct r6040_descriptor *descptr;
627 void __iomem *ioaddr = priv->base;
628 struct sk_buff *skb_ptr;
629 u16 err;
630
631 spin_lock(&priv->lock);
632 descptr = priv->tx_remove_ptr;
633 while (priv->tx_free_desc < TX_DCNT) {
634 /* Check for errors */
635 err = ioread16(ioaddr + MLSR);
636
d248fd77
FF		 637 if (err & 0x0200)
638 dev->stats.rx_fifo_errors++;
639 if (err & (0x2000 | 0x4000))
640 dev->stats.tx_carrier_errors++;
7a47dd7a 641
32f565df 642 if (descptr->status & DSC_OWNER_MAC)
ec6d2d45 643 break; /* Not complete */
7a47dd7a 644 skb_ptr = descptr->skb_ptr;
ed773b4a 645 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
7a47dd7a
SW		 646 skb_ptr->len, PCI_DMA_TODEVICE);
647 /* Free buffer */
648 dev_kfree_skb_irq(skb_ptr);
649 descptr->skb_ptr = NULL;
650 /* To next descriptor */
651 descptr = descptr->vndescp;
652 priv->tx_free_desc++;
653 }
654 priv->tx_remove_ptr = descptr;
655
656 if (priv->tx_free_desc)
657 netif_wake_queue(dev);
658 spin_unlock(&priv->lock);
659}
660
661static int r6040_poll(struct napi_struct *napi, int budget)
662{
663 struct r6040_private *priv =
664 container_of(napi, struct r6040_private, napi);
665 struct net_device *dev = priv->dev;
666 void __iomem *ioaddr = priv->base;
667 int work_done;
668
669 work_done = r6040_rx(dev, budget);
670
671 if (work_done < budget) {
672 netif_rx_complete(dev, napi);
673 /* Enable RX interrupt */
e24ddf3a 674 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
7a47dd7a
SW		 675 }
676 return work_done;
677}
678
679/* The RDC interrupt handler. */
680static irqreturn_t r6040_interrupt(int irq, void *dev_id)
681{
682 struct net_device *dev = dev_id;
683 struct r6040_private *lp = netdev_priv(dev);
684 void __iomem *ioaddr = lp->base;
685 u16 status;
7a47dd7a
SW		 686
687 /* Mask off RDC MAC interrupt */
688 iowrite16(MSK_INT, ioaddr + MIER);
689 /* Read MISR status and clear */
690 status = ioread16(ioaddr + MISR);
691
692 if (status == 0x0000 || status == 0xffff)
693 return IRQ_NONE;
694
695 /* RX interrupt request */
e24ddf3a
FF		 696 if (status & RX_INTS) {
697 if (status & RX_NO_DESC) {
698 /* RX descriptor unavailable */
699 dev->stats.rx_dropped++;
700 dev->stats.rx_missed_errors++;
701 }
702 if (status & RX_FIFO_FULL)
703 dev->stats.rx_fifo_errors++;
704
3d254348 705 /* Mask off RX interrupt */
e24ddf3a 706 iowrite16(ioread16(ioaddr + MIER) & ~RX_INTS, ioaddr + MIER);
7a47dd7a 707 netif_rx_schedule(dev, &lp->napi);
7a47dd7a
SW		 708 }
709
710 /* TX interrupt request */
e24ddf3a 711 if (status & TX_INTS)
7a47dd7a
SW		 712 r6040_tx(dev);
713
ec6d2d45 714 return IRQ_HANDLED;
7a47dd7a
SW		 715}
716
717#ifdef CONFIG_NET_POLL_CONTROLLER
718static void r6040_poll_controller(struct net_device *dev)
719{
720 disable_irq(dev->irq);
5ac5d616 721 r6040_interrupt(dev->irq, dev);
7a47dd7a
SW		 722 enable_irq(dev->irq);
723}
724#endif
725
7a47dd7a 726/* Init RDC MAC */
3d463419 727static int r6040_up(struct net_device *dev)
7a47dd7a
SW		 728{
729 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a 730 void __iomem *ioaddr = lp->base;
3d463419 731 int ret;
7a47dd7a 732
b4f1255d 733 /* Initialise and alloc RX/TX buffers */
3d463419
FF		 734 r6040_init_txbufs(dev);
735 ret = r6040_alloc_rxbufs(dev);
736 if (ret)
737 return ret;
7a47dd7a 738
7a47dd7a 739 /* Read the PHY ID */
c6e69bb9 740 lp->switch_sig = r6040_phy_read(ioaddr, 0, 2);
7a47dd7a
SW		 741
742 if (lp->switch_sig == ICPLUS_PHY_ID) {
c6e69bb9 743 r6040_phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
7a47dd7a
SW		 744 lp->phy_mode = 0x8000;
745 } else {
746 /* PHY Mode Check */
c6e69bb9
FF		 747 r6040_phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
748 r6040_phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
7a47dd7a
SW		 749
750 if (PHY_MODE == 0x3100)
c6e69bb9 751 lp->phy_mode = r6040_phy_mode_chk(dev);
7a47dd7a
SW		 752 else
753 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
754 }
7a47dd7a 755
fec3a23b 756 /* Set duplex mode */
7a47dd7a 757 lp->mcr0 |= lp->phy_mode;
7a47dd7a
SW		 758
759 /* improve performance (by RDC guys) */
c6e69bb9
FF		 760 r6040_phy_write(ioaddr, 30, 17, (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
761 r6040_phy_write(ioaddr, 30, 17, ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
762 r6040_phy_write(ioaddr, 0, 19, 0x0000);
763 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
7a47dd7a 764
fec3a23b
FF		 765 /* Initialize all MAC registers */
766 r6040_init_mac_regs(dev);
3d463419
FF		 767
768 return 0;
7a47dd7a
SW		 769}
770
771/*
772 A periodic timer routine
773 Polling PHY Chip Link Status
774*/
775static void r6040_timer(unsigned long data)
776{
777 struct net_device *dev = (struct net_device *)data;
e6a9ea10 778 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a
SW		 779 void __iomem *ioaddr = lp->base;
780 u16 phy_mode;
781
782 /* Polling PHY Chip Status */
783 if (PHY_MODE == 0x3100)
c6e69bb9 784 phy_mode = r6040_phy_mode_chk(dev);
7a47dd7a
SW		 785 else
786 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
787
788 if (phy_mode != lp->phy_mode) {
789 lp->phy_mode = phy_mode;
790 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
791 iowrite16(lp->mcr0, ioaddr);
792 printk(KERN_INFO "Link Change %x \n", ioread16(ioaddr));
793 }
794
795 /* Timer active again */
208aefa2 796 mod_timer(&lp->timer, round_jiffies(jiffies + HZ));
7a47dd7a
SW		 797}
798
799/* Read/set MAC address routines */
800static void r6040_mac_address(struct net_device *dev)
801{
802 struct r6040_private *lp = netdev_priv(dev);
803 void __iomem *ioaddr = lp->base;
804 u16 *adrp;
805
806 /* MAC operation register */
807 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
808 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
809 iowrite16(0, ioaddr + MAC_SM);
810 udelay(5000);
811
812 /* Restore MAC Address */
813 adrp = (u16 *) dev->dev_addr;
814 iowrite16(adrp[0], ioaddr + MID_0L);
815 iowrite16(adrp[1], ioaddr + MID_0M);
816 iowrite16(adrp[2], ioaddr + MID_0H);
817}
818
5ac5d616 819static int r6040_open(struct net_device *dev)
7a47dd7a 820{
5ac5d616 821 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a
SW		 822 int ret;
823
824 /* Request IRQ and Register interrupt handler */
825 ret = request_irq(dev->irq, &r6040_interrupt,
826 IRQF_SHARED, dev->name, dev);
827 if (ret)
828 return ret;
829
830 /* Set MAC address */
831 r6040_mac_address(dev);
832
833 /* Allocate Descriptor memory */
6c323103
FR		 834 lp->rx_ring =
835 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
836 if (!lp->rx_ring)
7a47dd7a
SW		 837 return -ENOMEM;
838
6c323103
FR		 839 lp->tx_ring =
840 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
841 if (!lp->tx_ring) {
842 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
843 lp->rx_ring_dma);
844 return -ENOMEM;
845 }
846
3d463419
FF		 847 ret = r6040_up(dev);
848 if (ret) {
849 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
850 lp->tx_ring_dma);
851 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
852 lp->rx_ring_dma);
853 return ret;
854 }
7a47dd7a
SW		 855
856 napi_enable(&lp->napi);
857 netif_start_queue(dev);
858
106adf3c
FF		 859 /* set and active a timer process */
860 setup_timer(&lp->timer, r6040_timer, (unsigned long) dev);
861 if (lp->switch_sig != ICPLUS_PHY_ID)
862 mod_timer(&lp->timer, jiffies + HZ);
7a47dd7a
SW		 863 return 0;
864}
865
5ac5d616 866static int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
7a47dd7a
SW		 867{
868 struct r6040_private *lp = netdev_priv(dev);
869 struct r6040_descriptor *descptr;
870 void __iomem *ioaddr = lp->base;
871 unsigned long flags;
092427be 872 int ret = NETDEV_TX_OK;
7a47dd7a
SW		 873
874 /* Critical Section */
875 spin_lock_irqsave(&lp->lock, flags);
876
877 /* TX resource check */
878 if (!lp->tx_free_desc) {
879 spin_unlock_irqrestore(&lp->lock, flags);
092427be 880 netif_stop_queue(dev);
7a47dd7a 881 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
092427be 882 ret = NETDEV_TX_BUSY;
7a47dd7a
SW		 883 return ret;
884 }
885
886 /* Statistic Counter */
887 dev->stats.tx_packets++;
888 dev->stats.tx_bytes += skb->len;
889 /* Set TX descriptor & Transmit it */
890 lp->tx_free_desc--;
891 descptr = lp->tx_insert_ptr;
892 if (skb->len < MISR)
893 descptr->len = MISR;
894 else
895 descptr->len = skb->len;
896
897 descptr->skb_ptr = skb;
898 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
899 skb->data, skb->len, PCI_DMA_TODEVICE));
32f565df 900 descptr->status = DSC_OWNER_MAC;
7a47dd7a
SW		 901 /* Trigger the MAC to check the TX descriptor */
902 iowrite16(0x01, ioaddr + MTPR);
903 lp->tx_insert_ptr = descptr->vndescp;
904
905 /* If no tx resource, stop */
906 if (!lp->tx_free_desc)
907 netif_stop_queue(dev);
908
909 dev->trans_start = jiffies;
910 spin_unlock_irqrestore(&lp->lock, flags);
911 return ret;
912}
913
5ac5d616 914static void r6040_multicast_list(struct net_device *dev)
7a47dd7a
SW		 915{
916 struct r6040_private *lp = netdev_priv(dev);
917 void __iomem *ioaddr = lp->base;
918 u16 *adrp;
919 u16 reg;
920 unsigned long flags;
921 struct dev_mc_list *dmi = dev->mc_list;
922 int i;
923
924 /* MAC Address */
925 adrp = (u16 *)dev->dev_addr;
926 iowrite16(adrp[0], ioaddr + MID_0L);
927 iowrite16(adrp[1], ioaddr + MID_0M);
928 iowrite16(adrp[2], ioaddr + MID_0H);
929
930 /* Promiscous Mode */
931 spin_lock_irqsave(&lp->lock, flags);
932
933 /* Clear AMCP & PROM bits */
934 reg = ioread16(ioaddr) & ~0x0120;
935 if (dev->flags & IFF_PROMISC) {
936 reg |= 0x0020;
937 lp->mcr0 |= 0x0020;
938 }
939 /* Too many multicast addresses
940 * accept all traffic */
941 else if ((dev->mc_count > MCAST_MAX)
942 || (dev->flags & IFF_ALLMULTI))
943 reg |= 0x0020;
944
945 iowrite16(reg, ioaddr);
946 spin_unlock_irqrestore(&lp->lock, flags);
947
948 /* Build the hash table */
949 if (dev->mc_count > MCAST_MAX) {
950 u16 hash_table[4];
951 u32 crc;
952
953 for (i = 0; i < 4; i++)
954 hash_table[i] = 0;
955
956 for (i = 0; i < dev->mc_count; i++) {
957 char *addrs = dmi->dmi_addr;
958
959 dmi = dmi->next;
960
961 if (!(*addrs & 1))
962 continue;
963
964 crc = ether_crc_le(6, addrs);
965 crc >>= 26;
966 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
967 }
968 /* Write the index of the hash table */
969 for (i = 0; i < 4; i++)
970 iowrite16(hash_table[i] << 14, ioaddr + MCR1);
971 /* Fill the MAC hash tables with their values */
972 iowrite16(hash_table[0], ioaddr + MAR0);
973 iowrite16(hash_table[1], ioaddr + MAR1);
974 iowrite16(hash_table[2], ioaddr + MAR2);
975 iowrite16(hash_table[3], ioaddr + MAR3);
976 }
977 /* Multicast Address 1~4 case */
978 for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
979 adrp = (u16 *)dmi->dmi_addr;
980 iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
981 iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
982 iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
983 dmi = dmi->next;
984 }
985 for (i = dev->mc_count; i < MCAST_MAX; i++) {
986 iowrite16(0xffff, ioaddr + MID_0L + 8*i);
987 iowrite16(0xffff, ioaddr + MID_0M + 8*i);
988 iowrite16(0xffff, ioaddr + MID_0H + 8*i);
989 }
990}
991
992static void netdev_get_drvinfo(struct net_device *dev,
993 struct ethtool_drvinfo *info)
994{
995 struct r6040_private *rp = netdev_priv(dev);
996
997 strcpy(info->driver, DRV_NAME);
998 strcpy(info->version, DRV_VERSION);
999 strcpy(info->bus_info, pci_name(rp->pdev));
1000}
1001
1002static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1003{
1004 struct r6040_private *rp = netdev_priv(dev);
1005 int rc;
1006
1007 spin_lock_irq(&rp->lock);
1008 rc = mii_ethtool_gset(&rp->mii_if, cmd);
092427be 1009 spin_unlock_irq(&rp->lock);
7a47dd7a
SW		 1010
1011 return rc;
1012}
1013
1014static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1015{
1016 struct r6040_private *rp = netdev_priv(dev);
1017 int rc;
1018
1019 spin_lock_irq(&rp->lock);
1020 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1021 spin_unlock_irq(&rp->lock);
1022 r6040_set_carrier(&rp->mii_if);
1023
1024 return rc;
1025}
1026
1027static u32 netdev_get_link(struct net_device *dev)
1028{
1029 struct r6040_private *rp = netdev_priv(dev);
1030
1031 return mii_link_ok(&rp->mii_if);
1032}
1033
1034static struct ethtool_ops netdev_ethtool_ops = {
1035 .get_drvinfo = netdev_get_drvinfo,
1036 .get_settings = netdev_get_settings,
1037 .set_settings = netdev_set_settings,
1038 .get_link = netdev_get_link,
1039};
1040
7a47dd7a
SW		 1041static int __devinit r6040_init_one(struct pci_dev *pdev,
1042 const struct pci_device_id *ent)
1043{
1044 struct net_device *dev;
1045 struct r6040_private *lp;
1046 void __iomem *ioaddr;
1047 int err, io_size = R6040_IO_SIZE;
1048 static int card_idx = -1;
1049 int bar = 0;
1050 long pioaddr;
1051 u16 *adrp;
1052
1053 printk(KERN_INFO "%s\n", version);
1054
1055 err = pci_enable_device(pdev);
1056 if (err)
b0e45390 1057 goto err_out;
7a47dd7a
SW		 1058
1059 /* this should always be supported */
b0e45390
FF		 1060 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1061 if (err) {
7a47dd7a
SW		 1062 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1063 "not supported by the card\n");
b0e45390 1064 goto err_out;
7a47dd7a 1065 }
b0e45390
FF		 1066 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1067 if (err) {
092427be
JG		 1068 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1069 "not supported by the card\n");
b0e45390 1070 goto err_out;
092427be 1071 }
7a47dd7a
SW		 1072
1073 /* IO Size check */
1074 if (pci_resource_len(pdev, 0) < io_size) {
b0e45390
FF		 1075 printk(KERN_ERR DRV_NAME "Insufficient PCI resources, aborting\n");
1076 err = -EIO;
1077 goto err_out;
7a47dd7a
SW		 1078 }
1079
1080 pioaddr = pci_resource_start(pdev, 0); /* IO map base address */
1081 pci_set_master(pdev);
1082
1083 dev = alloc_etherdev(sizeof(struct r6040_private));
1084 if (!dev) {
b0e45390
FF		 1085 printk(KERN_ERR DRV_NAME "Failed to allocate etherdev\n");
1086 err = -ENOMEM;
1087 goto err_out;
7a47dd7a
SW		 1088 }
1089 SET_NETDEV_DEV(dev, &pdev->dev);
1090 lp = netdev_priv(dev);
7a47dd7a 1091
b0e45390
FF		 1092 err = pci_request_regions(pdev, DRV_NAME);
1093
1094 if (err) {
7a47dd7a 1095 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
b0e45390 1096 goto err_out_free_dev;
7a47dd7a
SW		 1097 }
1098
1099 ioaddr = pci_iomap(pdev, bar, io_size);
1100 if (!ioaddr) {
1101 printk(KERN_ERR "ioremap failed for device %s\n",
1102 pci_name(pdev));
b0e45390
FF		 1103 err = -EIO;
1104 goto err_out_free_res;
7a47dd7a
SW		 1105 }
1106
1107 /* Init system & device */
7a47dd7a
SW		 1108 lp->base = ioaddr;
1109 dev->irq = pdev->irq;
1110
1111 spin_lock_init(&lp->lock);
1112 pci_set_drvdata(pdev, dev);
1113
1114 /* Set MAC address */
1115 card_idx++;
1116
1117 adrp = (u16 *)dev->dev_addr;
1118 adrp[0] = ioread16(ioaddr + MID_0L);
1119 adrp[1] = ioread16(ioaddr + MID_0M);
1120 adrp[2] = ioread16(ioaddr + MID_0H);
1121
1122 /* Link new device into r6040_root_dev */
1123 lp->pdev = pdev;
129cf9a7 1124 lp->dev = dev;
7a47dd7a
SW		 1125
1126 /* Init RDC private data */
1127 lp->mcr0 = 0x1002;
1128 lp->phy_addr = phy_table[card_idx];
1129 lp->switch_sig = 0;
1130
1131 /* The RDC-specific entries in the device structure. */
1132 dev->open = &r6040_open;
1133 dev->hard_start_xmit = &r6040_start_xmit;
1134 dev->stop = &r6040_close;
1135 dev->get_stats = r6040_get_stats;
1136 dev->set_multicast_list = &r6040_multicast_list;
1137 dev->do_ioctl = &r6040_ioctl;
1138 dev->ethtool_ops = &netdev_ethtool_ops;
1139 dev->tx_timeout = &r6040_tx_timeout;
1140 dev->watchdog_timeo = TX_TIMEOUT;
1141#ifdef CONFIG_NET_POLL_CONTROLLER
1142 dev->poll_controller = r6040_poll_controller;
1143#endif
1144 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1145 lp->mii_if.dev = dev;
c6e69bb9
FF		 1146 lp->mii_if.mdio_read = r6040_mdio_read;
1147 lp->mii_if.mdio_write = r6040_mdio_write;
7a47dd7a
SW		 1148 lp->mii_if.phy_id = lp->phy_addr;
1149 lp->mii_if.phy_id_mask = 0x1f;
1150 lp->mii_if.reg_num_mask = 0x1f;
1151
1152 /* Register net device. After this dev->name assign */
1153 err = register_netdev(dev);
1154 if (err) {
1155 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
b0e45390 1156 goto err_out_unmap;
7a47dd7a
SW		 1157 }
1158 return 0;
1159
b0e45390
FF		 1160err_out_unmap:
1161 pci_iounmap(pdev, ioaddr);
1162err_out_free_res:
7a47dd7a 1163 pci_release_regions(pdev);
b0e45390 1164err_out_free_dev:
7a47dd7a 1165 free_netdev(dev);
b0e45390 1166err_out:
7a47dd7a
SW		 1167 return err;
1168}
1169
1170static void __devexit r6040_remove_one(struct pci_dev *pdev)
1171{
1172 struct net_device *dev = pci_get_drvdata(pdev);
1173
1174 unregister_netdev(dev);
1175 pci_release_regions(pdev);
1176 free_netdev(dev);
1177 pci_disable_device(pdev);
1178 pci_set_drvdata(pdev, NULL);
1179}
1180
1181
1182static struct pci_device_id r6040_pci_tbl[] = {
5ac5d616
FR		 1183 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1184 { 0 }
7a47dd7a
SW		 1185};
1186MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1187
1188static struct pci_driver r6040_driver = {
5ac5d616 1189 .name = DRV_NAME,
7a47dd7a
SW		 1190 .id_table = r6040_pci_tbl,
1191 .probe = r6040_init_one,
1192 .remove = __devexit_p(r6040_remove_one),
1193};
1194
1195
1196static int __init r6040_init(void)
1197{
1198 return pci_register_driver(&r6040_driver);
1199}
1200
1201
1202static void __exit r6040_cleanup(void)
1203{
1204 pci_unregister_driver(&r6040_driver);
1205}
1206
1207module_init(r6040_init);
1208module_exit(r6040_cleanup);
Linux kernel - Deliverables
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