projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
r6040: fix all checkpatch errors and warnings
[deliverable/linux.git] / drivers / net / r6040.c
CommitLineData
7a47dd7a
SW		 1/*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
5ac5d616 6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7a47dd7a
SW		 7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23*/
24
25#include <linux/kernel.h>
26#include <linux/module.h>
7a47dd7a
SW		 27#include <linux/moduleparam.h>
28#include <linux/string.h>
29#include <linux/timer.h>
30#include <linux/errno.h>
31#include <linux/ioport.h>
7a47dd7a
SW		 32#include <linux/interrupt.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/skbuff.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/mii.h>
40#include <linux/ethtool.h>
41#include <linux/crc32.h>
42#include <linux/spinlock.h>
092427be
JG		 43#include <linux/bitops.h>
44#include <linux/io.h>
45#include <linux/irq.h>
46#include <linux/uaccess.h>
3831861b 47#include <linux/phy.h>
7a47dd7a
SW		 48
49#include <asm/processor.h>
7a47dd7a
SW		 50
51#define DRV_NAME "r6040"
92c4bbfa
FF		 52#define DRV_VERSION "0.26"
53#define DRV_RELDATE "30May2010"
7a47dd7a
SW		 54
55/* PHY CHIP Address */
56#define PHY1_ADDR 1 /* For MAC1 */
2a30ca8b 57#define PHY2_ADDR 3 /* For MAC2 */
7a47dd7a
SW		 58#define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
59#define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
60
61/* Time in jiffies before concluding the transmitter is hung. */
5ac5d616 62#define TX_TIMEOUT (6000 * HZ / 1000)
7a47dd7a
SW		 63
64/* RDC MAC I/O Size */
65#define R6040_IO_SIZE 256
66
67/* MAX RDC MAC */
68#define MAX_MAC 2
69
70/* MAC registers */
71#define MCR0 0x00 /* Control register 0 */
72#define MCR1 0x04 /* Control register 1 */
73#define MAC_RST 0x0001 /* Reset the MAC */
74#define MBCR 0x08 /* Bus control */
75#define MT_ICR 0x0C /* TX interrupt control */
76#define MR_ICR 0x10 /* RX interrupt control */
77#define MTPR 0x14 /* TX poll command register */
78#define MR_BSR 0x18 /* RX buffer size */
79#define MR_DCR 0x1A /* RX descriptor control */
80#define MLSR 0x1C /* Last status */
81#define MMDIO 0x20 /* MDIO control register */
82#define MDIO_WRITE 0x4000 /* MDIO write */
83#define MDIO_READ 0x2000 /* MDIO read */
84#define MMRD 0x24 /* MDIO read data register */
85#define MMWD 0x28 /* MDIO write data register */
86#define MTD_SA0 0x2C /* TX descriptor start address 0 */
87#define MTD_SA1 0x30 /* TX descriptor start address 1 */
88#define MRD_SA0 0x34 /* RX descriptor start address 0 */
89#define MRD_SA1 0x38 /* RX descriptor start address 1 */
90#define MISR 0x3C /* Status register */
91#define MIER 0x40 /* INT enable register */
92#define MSK_INT 0x0000 /* Mask off interrupts */
3d254348
FF		 93#define RX_FINISH 0x0001 /* RX finished */
94#define RX_NO_DESC 0x0002 /* No RX descriptor available */
95#define RX_FIFO_FULL 0x0004 /* RX FIFO full */
96#define RX_EARLY 0x0008 /* RX early */
97#define TX_FINISH 0x0010 /* TX finished */
98#define TX_EARLY 0x0080 /* TX early */
99#define EVENT_OVRFL 0x0100 /* Event counter overflow */
100#define LINK_CHANGED 0x0200 /* PHY link changed */
7a47dd7a
SW		 101#define ME_CISR 0x44 /* Event counter INT status */
102#define ME_CIER 0x48 /* Event counter INT enable */
103#define MR_CNT 0x50 /* Successfully received packet counter */
104#define ME_CNT0 0x52 /* Event counter 0 */
105#define ME_CNT1 0x54 /* Event counter 1 */
106#define ME_CNT2 0x56 /* Event counter 2 */
107#define ME_CNT3 0x58 /* Event counter 3 */
108#define MT_CNT 0x5A /* Successfully transmit packet counter */
109#define ME_CNT4 0x5C /* Event counter 4 */
110#define MP_CNT 0x5E /* Pause frame counter register */
111#define MAR0 0x60 /* Hash table 0 */
112#define MAR1 0x62 /* Hash table 1 */
113#define MAR2 0x64 /* Hash table 2 */
114#define MAR3 0x66 /* Hash table 3 */
115#define MID_0L 0x68 /* Multicast address MID0 Low */
116#define MID_0M 0x6A /* Multicast address MID0 Medium */
117#define MID_0H 0x6C /* Multicast address MID0 High */
118#define MID_1L 0x70 /* MID1 Low */
119#define MID_1M 0x72 /* MID1 Medium */
120#define MID_1H 0x74 /* MID1 High */
121#define MID_2L 0x78 /* MID2 Low */
122#define MID_2M 0x7A /* MID2 Medium */
123#define MID_2H 0x7C /* MID2 High */
124#define MID_3L 0x80 /* MID3 Low */
125#define MID_3M 0x82 /* MID3 Medium */
126#define MID_3H 0x84 /* MID3 High */
127#define PHY_CC 0x88 /* PHY status change configuration register */
128#define PHY_ST 0x8A /* PHY status register */
129#define MAC_SM 0xAC /* MAC status machine */
130#define MAC_ID 0xBE /* Identifier register */
131
132#define TX_DCNT 0x80 /* TX descriptor count */
133#define RX_DCNT 0x80 /* RX descriptor count */
134#define MAX_BUF_SIZE 0x600
6c323103
FR		 135#define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
136#define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
7a47dd7a 137#define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
3bcf8229 138#define MCAST_MAX 3 /* Max number multicast addresses to filter */
7a47dd7a 139
32f565df
FF		 140/* Descriptor status */
141#define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
142#define DSC_RX_OK 0x4000 /* RX was successful */
143#define DSC_RX_ERR 0x0800 /* RX PHY error */
144#define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
145#define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
146#define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
147#define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
148#define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
149#define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
150#define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
151#define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
152#define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
153#define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
154
7a47dd7a
SW		 155/* PHY settings */
156#define ICPLUS_PHY_ID 0x0243
157
158MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
159 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
160 "Florian Fainelli <florian@openwrt.org>");
161MODULE_LICENSE("GPL");
162MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
bc4de260 163MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
7a47dd7a 164
3d254348 165/* RX and TX interrupts that we handle */
e24ddf3a
FF		 166#define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
167#define TX_INTS (TX_FINISH)
168#define INT_MASK (RX_INTS | TX_INTS)
7a47dd7a
SW		 169
170struct r6040_descriptor {
171 u16 status, len; /* 0-3 */
172 __le32 buf; /* 4-7 */
173 __le32 ndesc; /* 8-B */
174 u32 rev1; /* C-F */
175 char *vbufp; /* 10-13 */
176 struct r6040_descriptor *vndescp; /* 14-17 */
177 struct sk_buff *skb_ptr; /* 18-1B */
178 u32 rev2; /* 1C-1F */
179} __attribute__((aligned(32)));
180
181struct r6040_private {
182 spinlock_t lock; /* driver lock */
7a47dd7a
SW		 183 struct pci_dev *pdev;
184 struct r6040_descriptor *rx_insert_ptr;
185 struct r6040_descriptor *rx_remove_ptr;
186 struct r6040_descriptor *tx_insert_ptr;
187 struct r6040_descriptor *tx_remove_ptr;
6c323103
FR		 188 struct r6040_descriptor *rx_ring;
189 struct r6040_descriptor *tx_ring;
190 dma_addr_t rx_ring_dma;
191 dma_addr_t tx_ring_dma;
3831861b 192 u16 tx_free_desc, phy_addr;
7a47dd7a 193 u16 mcr0, mcr1;
7a47dd7a 194 struct net_device *dev;
3831861b 195 struct mii_bus *mii_bus;
7a47dd7a 196 struct napi_struct napi;
7a47dd7a 197 void __iomem *base;
3831861b
FF		 198 struct phy_device *phydev;
199 int old_link;
200 int old_duplex;
7a47dd7a
SW		 201};
202
2154c704 203static char version[] __devinitdata = DRV_NAME
7a47dd7a 204 ": RDC R6040 NAPI net driver,"
9a48ce84 205 "version "DRV_VERSION " (" DRV_RELDATE ")";
7a47dd7a 206
092427be 207static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
7a47dd7a
SW		 208
209/* Read a word data from PHY Chip */
c6e69bb9 210static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
7a47dd7a
SW		 211{
212 int limit = 2048;
213 u16 cmd;
214
215 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
216 /* Wait for the read bit to be cleared */
217 while (limit--) {
218 cmd = ioread16(ioaddr + MMDIO);
11e5e8f5 219 if (!(cmd & MDIO_READ))
7a47dd7a
SW		 220 break;
221 }
222
223 return ioread16(ioaddr + MMRD);
224}
225
226/* Write a word data from PHY Chip */
2154c704
FF		 227static void r6040_phy_write(void __iomem *ioaddr,
228 int phy_addr, int reg, u16 val)
7a47dd7a
SW		 229{
230 int limit = 2048;
231 u16 cmd;
232
233 iowrite16(val, ioaddr + MMWD);
234 /* Write the command to the MDIO bus */
235 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
236 /* Wait for the write bit to be cleared */
237 while (limit--) {
238 cmd = ioread16(ioaddr + MMDIO);
11e5e8f5 239 if (!(cmd & MDIO_WRITE))
7a47dd7a
SW		 240 break;
241 }
242}
243
3831861b 244static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg)
7a47dd7a 245{
3831861b 246 struct net_device *dev = bus->priv;
7a47dd7a
SW		 247 struct r6040_private *lp = netdev_priv(dev);
248 void __iomem *ioaddr = lp->base;
249
3831861b 250 return r6040_phy_read(ioaddr, phy_addr, reg);
7a47dd7a
SW		 251}
252
3831861b
FF		 253static int r6040_mdiobus_write(struct mii_bus *bus, int phy_addr,
254 int reg, u16 value)
7a47dd7a 255{
3831861b 256 struct net_device *dev = bus->priv;
7a47dd7a
SW		 257 struct r6040_private *lp = netdev_priv(dev);
258 void __iomem *ioaddr = lp->base;
259
3831861b
FF		 260 r6040_phy_write(ioaddr, phy_addr, reg, value);
261
262 return 0;
263}
264
265static int r6040_mdiobus_reset(struct mii_bus *bus)
266{
267 return 0;
7a47dd7a
SW		 268}
269
b4f1255d
FF		 270static void r6040_free_txbufs(struct net_device *dev)
271{
272 struct r6040_private *lp = netdev_priv(dev);
273 int i;
274
275 for (i = 0; i < TX_DCNT; i++) {
276 if (lp->tx_insert_ptr->skb_ptr) {
ed773b4a
AV		 277 pci_unmap_single(lp->pdev,
278 le32_to_cpu(lp->tx_insert_ptr->buf),
b4f1255d
FF		 279 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
280 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
3b060be0 281 lp->tx_insert_ptr->skb_ptr = NULL;
b4f1255d
FF		 282 }
283 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
284 }
285}
286
287static void r6040_free_rxbufs(struct net_device *dev)
288{
289 struct r6040_private *lp = netdev_priv(dev);
290 int i;
291
292 for (i = 0; i < RX_DCNT; i++) {
293 if (lp->rx_insert_ptr->skb_ptr) {
ed773b4a
AV		 294 pci_unmap_single(lp->pdev,
295 le32_to_cpu(lp->rx_insert_ptr->buf),
b4f1255d
FF		 296 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
297 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
298 lp->rx_insert_ptr->skb_ptr = NULL;
299 }
300 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
301 }
302}
303
b4f1255d
FF		 304static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
305 dma_addr_t desc_dma, int size)
306{
307 struct r6040_descriptor *desc = desc_ring;
308 dma_addr_t mapping = desc_dma;
309
310 while (size-- > 0) {
3f6602ad 311 mapping += sizeof(*desc);
b4f1255d
FF		 312 desc->ndesc = cpu_to_le32(mapping);
313 desc->vndescp = desc + 1;
314 desc++;
315 }
316 desc--;
317 desc->ndesc = cpu_to_le32(desc_dma);
318 desc->vndescp = desc_ring;
319}
320
3d463419 321static void r6040_init_txbufs(struct net_device *dev)
b4f1255d
FF		 322{
323 struct r6040_private *lp = netdev_priv(dev);
b4f1255d
FF		 324
325 lp->tx_free_desc = TX_DCNT;
326
327 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
328 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
b4f1255d
FF		 329}
330
3d463419 331static int r6040_alloc_rxbufs(struct net_device *dev)
b4f1255d
FF		 332{
333 struct r6040_private *lp = netdev_priv(dev);
3d463419
FF		 334 struct r6040_descriptor *desc;
335 struct sk_buff *skb;
336 int rc;
b4f1255d
FF		 337
338 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
339 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
340
3d463419
FF		 341 /* Allocate skbs for the rx descriptors */
342 desc = lp->rx_ring;
343 do {
344 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
345 if (!skb) {
7d53b809 346 netdev_err(dev, "failed to alloc skb for rx\n");
3d463419
FF		 347 rc = -ENOMEM;
348 goto err_exit;
349 }
350 desc->skb_ptr = skb;
351 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
2154c704
FF		 352 desc->skb_ptr->data,
353 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
32f565df 354 desc->status = DSC_OWNER_MAC;
3d463419
FF		 355 desc = desc->vndescp;
356 } while (desc != lp->rx_ring);
357
358 return 0;
359
360err_exit:
361 /* Deallocate all previously allocated skbs */
362 r6040_free_rxbufs(dev);
363 return rc;
fec3a23b
FF		 364}
365
366static void r6040_init_mac_regs(struct net_device *dev)
367{
368 struct r6040_private *lp = netdev_priv(dev);
369 void __iomem *ioaddr = lp->base;
370 int limit = 2048;
371 u16 cmd;
372
373 /* Mask Off Interrupt */
374 iowrite16(MSK_INT, ioaddr + MIER);
375
376 /* Reset RDC MAC */
377 iowrite16(MAC_RST, ioaddr + MCR1);
378 while (limit--) {
379 cmd = ioread16(ioaddr + MCR1);
380 if (cmd & 0x1)
381 break;
382 }
383 /* Reset internal state machine */
384 iowrite16(2, ioaddr + MAC_SM);
385 iowrite16(0, ioaddr + MAC_SM);
c1d69937 386 mdelay(5);
fec3a23b
FF		 387
388 /* MAC Bus Control Register */
389 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
390
391 /* Buffer Size Register */
392 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
393
394 /* Write TX ring start address */
395 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
396 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
b4f1255d 397
fec3a23b 398 /* Write RX ring start address */
b4f1255d
FF		 399 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
400 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
fec3a23b
FF		 401
402 /* Set interrupt waiting time and packet numbers */
31718ded
FF		 403 iowrite16(0, ioaddr + MT_ICR);
404 iowrite16(0, ioaddr + MR_ICR);
fec3a23b
FF		 405
406 /* Enable interrupts */
407 iowrite16(INT_MASK, ioaddr + MIER);
408
409 /* Enable TX and RX */
410 iowrite16(lp->mcr0 | 0x0002, ioaddr);
411
412 /* Let TX poll the descriptors
413 * we may got called by r6040_tx_timeout which has left
414 * some unsent tx buffers */
415 iowrite16(0x01, ioaddr + MTPR);
b4f1255d 416}
7a47dd7a 417
106adf3c
FF		 418static void r6040_tx_timeout(struct net_device *dev)
419{
420 struct r6040_private *priv = netdev_priv(dev);
421 void __iomem *ioaddr = priv->base;
422
7d53b809 423 netdev_warn(dev, "transmit timed out, int enable %4.4x "
3831861b 424 "status %4.4x\n",
7d53b809 425 ioread16(ioaddr + MIER),
3831861b 426 ioread16(ioaddr + MISR));
106adf3c 427
106adf3c 428 dev->stats.tx_errors++;
fec3a23b
FF		 429
430 /* Reset MAC and re-init all registers */
431 r6040_init_mac_regs(dev);
106adf3c
FF		 432}
433
7a47dd7a
SW		 434static struct net_device_stats *r6040_get_stats(struct net_device *dev)
435{
436 struct r6040_private *priv = netdev_priv(dev);
437 void __iomem *ioaddr = priv->base;
438 unsigned long flags;
439
440 spin_lock_irqsave(&priv->lock, flags);
d248fd77
FF		 441 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
442 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
7a47dd7a
SW		 443 spin_unlock_irqrestore(&priv->lock, flags);
444
d248fd77 445 return &dev->stats;
7a47dd7a
SW		 446}
447
448/* Stop RDC MAC and Free the allocated resource */
449static void r6040_down(struct net_device *dev)
450{
451 struct r6040_private *lp = netdev_priv(dev);
452 void __iomem *ioaddr = lp->base;
7a47dd7a
SW		 453 int limit = 2048;
454 u16 *adrp;
455 u16 cmd;
456
457 /* Stop MAC */
458 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
459 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
460 while (limit--) {
461 cmd = ioread16(ioaddr + MCR1);
462 if (cmd & 0x1)
463 break;
464 }
465
466 /* Restore MAC Address to MIDx */
467 adrp = (u16 *) dev->dev_addr;
468 iowrite16(adrp[0], ioaddr + MID_0L);
469 iowrite16(adrp[1], ioaddr + MID_0M);
470 iowrite16(adrp[2], ioaddr + MID_0H);
7a47dd7a
SW		 471}
472
5ac5d616 473static int r6040_close(struct net_device *dev)
7a47dd7a
SW		 474{
475 struct r6040_private *lp = netdev_priv(dev);
58854c6b 476 struct pci_dev *pdev = lp->pdev;
7a47dd7a 477
7a47dd7a 478 spin_lock_irq(&lp->lock);
129cf9a7 479 napi_disable(&lp->napi);
7a47dd7a
SW		 480 netif_stop_queue(dev);
481 r6040_down(dev);
58854c6b
FF		 482
483 free_irq(dev->irq, dev);
484
485 /* Free RX buffer */
486 r6040_free_rxbufs(dev);
487
488 /* Free TX buffer */
489 r6040_free_txbufs(dev);
490
7a47dd7a
SW		 491 spin_unlock_irq(&lp->lock);
492
58854c6b
FF		 493 /* Free Descriptor memory */
494 if (lp->rx_ring) {
2154c704
FF		 495 pci_free_consistent(pdev,
496 RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
5b5103ec 497 lp->rx_ring = NULL;
58854c6b
FF		 498 }
499
500 if (lp->tx_ring) {
2154c704
FF		 501 pci_free_consistent(pdev,
502 TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
5b5103ec 503 lp->tx_ring = NULL;
58854c6b
FF		 504 }
505
7a47dd7a
SW		 506 return 0;
507}
508
7a47dd7a
SW		 509static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
510{
511 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a 512
3831861b 513 if (!lp->phydev)
7a47dd7a 514 return -EINVAL;
3831861b 515
4cfa580e 516 return phy_mii_ioctl(lp->phydev, rq, cmd);
7a47dd7a
SW		 517}
518
519static int r6040_rx(struct net_device *dev, int limit)
520{
521 struct r6040_private *priv = netdev_priv(dev);
9ca28dc4
FF		 522 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
523 struct sk_buff *skb_ptr, *new_skb;
524 int count = 0;
7a47dd7a
SW		 525 u16 err;
526
9ca28dc4 527 /* Limit not reached and the descriptor belongs to the CPU */
32f565df 528 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
9ca28dc4
FF		 529 /* Read the descriptor status */
530 err = descptr->status;
531 /* Global error status set */
32f565df 532 if (err & DSC_RX_ERR) {
9ca28dc4 533 /* RX dribble */
32f565df 534 if (err & DSC_RX_ERR_DRI)
9ca28dc4
FF		 535 dev->stats.rx_frame_errors++;
536 /* Buffer lenght exceeded */
32f565df 537 if (err & DSC_RX_ERR_BUF)
9ca28dc4
FF		 538 dev->stats.rx_length_errors++;
539 /* Packet too long */
32f565df 540 if (err & DSC_RX_ERR_LONG)
9ca28dc4
FF		 541 dev->stats.rx_length_errors++;
542 /* Packet < 64 bytes */
32f565df 543 if (err & DSC_RX_ERR_RUNT)
9ca28dc4
FF		 544 dev->stats.rx_length_errors++;
545 /* CRC error */
32f565df 546 if (err & DSC_RX_ERR_CRC) {
9ca28dc4
FF		 547 spin_lock(&priv->lock);
548 dev->stats.rx_crc_errors++;
549 spin_unlock(&priv->lock);
7a47dd7a 550 }
9ca28dc4
FF		 551 goto next_descr;
552 }
2154c704 553
9ca28dc4
FF		 554 /* Packet successfully received */
555 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
556 if (!new_skb) {
557 dev->stats.rx_dropped++;
558 goto next_descr;
7a47dd7a 559 }
9ca28dc4
FF		 560 skb_ptr = descptr->skb_ptr;
561 skb_ptr->dev = priv->dev;
2154c704 562
9ca28dc4
FF		 563 /* Do not count the CRC */
564 skb_put(skb_ptr, descptr->len - 4);
565 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
566 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
567 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
2154c704 568
9ca28dc4
FF		 569 /* Send to upper layer */
570 netif_receive_skb(skb_ptr);
9ca28dc4
FF		 571 dev->stats.rx_packets++;
572 dev->stats.rx_bytes += descptr->len - 4;
573
574 /* put new skb into descriptor */
575 descptr->skb_ptr = new_skb;
576 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
577 descptr->skb_ptr->data,
578 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
579
580next_descr:
581 /* put the descriptor back to the MAC */
32f565df 582 descptr->status = DSC_OWNER_MAC;
9ca28dc4
FF		 583 descptr = descptr->vndescp;
584 count++;
7a47dd7a 585 }
9ca28dc4 586 priv->rx_remove_ptr = descptr;
7a47dd7a
SW		 587
588 return count;
589}
590
591static void r6040_tx(struct net_device *dev)
592{
593 struct r6040_private *priv = netdev_priv(dev);
594 struct r6040_descriptor *descptr;
595 void __iomem *ioaddr = priv->base;
596 struct sk_buff *skb_ptr;
597 u16 err;
598
599 spin_lock(&priv->lock);
600 descptr = priv->tx_remove_ptr;
601 while (priv->tx_free_desc < TX_DCNT) {
602 /* Check for errors */
603 err = ioread16(ioaddr + MLSR);
604
d248fd77
FF		 605 if (err & 0x0200)
606 dev->stats.rx_fifo_errors++;
607 if (err & (0x2000 | 0x4000))
608 dev->stats.tx_carrier_errors++;
7a47dd7a 609
32f565df 610 if (descptr->status & DSC_OWNER_MAC)
ec6d2d45 611 break; /* Not complete */
7a47dd7a 612 skb_ptr = descptr->skb_ptr;
ed773b4a 613 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
7a47dd7a
SW		 614 skb_ptr->len, PCI_DMA_TODEVICE);
615 /* Free buffer */
616 dev_kfree_skb_irq(skb_ptr);
617 descptr->skb_ptr = NULL;
618 /* To next descriptor */
619 descptr = descptr->vndescp;
620 priv->tx_free_desc++;
621 }
622 priv->tx_remove_ptr = descptr;
623
624 if (priv->tx_free_desc)
625 netif_wake_queue(dev);
626 spin_unlock(&priv->lock);
627}
628
629static int r6040_poll(struct napi_struct *napi, int budget)
630{
631 struct r6040_private *priv =
632 container_of(napi, struct r6040_private, napi);
633 struct net_device *dev = priv->dev;
634 void __iomem *ioaddr = priv->base;
635 int work_done;
636
637 work_done = r6040_rx(dev, budget);
638
639 if (work_done < budget) {
288379f0 640 napi_complete(napi);
7a47dd7a 641 /* Enable RX interrupt */
e24ddf3a 642 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
7a47dd7a
SW		 643 }
644 return work_done;
645}
646
647/* The RDC interrupt handler. */
648static irqreturn_t r6040_interrupt(int irq, void *dev_id)
649{
650 struct net_device *dev = dev_id;
651 struct r6040_private *lp = netdev_priv(dev);
652 void __iomem *ioaddr = lp->base;
3e7c469f 653 u16 misr, status;
7a47dd7a 654
3e7c469f
JC		 655 /* Save MIER */
656 misr = ioread16(ioaddr + MIER);
7a47dd7a
SW		 657 /* Mask off RDC MAC interrupt */
658 iowrite16(MSK_INT, ioaddr + MIER);
659 /* Read MISR status and clear */
660 status = ioread16(ioaddr + MISR);
661
35976d4d
FF		 662 if (status == 0x0000 || status == 0xffff) {
663 /* Restore RDC MAC interrupt */
664 iowrite16(misr, ioaddr + MIER);
7a47dd7a 665 return IRQ_NONE;
35976d4d 666 }
7a47dd7a
SW		 667
668 /* RX interrupt request */
e24ddf3a
FF		 669 if (status & RX_INTS) {
670 if (status & RX_NO_DESC) {
671 /* RX descriptor unavailable */
672 dev->stats.rx_dropped++;
673 dev->stats.rx_missed_errors++;
674 }
675 if (status & RX_FIFO_FULL)
676 dev->stats.rx_fifo_errors++;
677
3d254348 678 /* Mask off RX interrupt */
3e7c469f 679 misr &= ~RX_INTS;
288379f0 680 napi_schedule(&lp->napi);
7a47dd7a
SW		 681 }
682
683 /* TX interrupt request */
e24ddf3a 684 if (status & TX_INTS)
7a47dd7a
SW		 685 r6040_tx(dev);
686
3e7c469f
JC		 687 /* Restore RDC MAC interrupt */
688 iowrite16(misr, ioaddr + MIER);
689
ec6d2d45 690 return IRQ_HANDLED;
7a47dd7a
SW		 691}
692
693#ifdef CONFIG_NET_POLL_CONTROLLER
694static void r6040_poll_controller(struct net_device *dev)
695{
696 disable_irq(dev->irq);
5ac5d616 697 r6040_interrupt(dev->irq, dev);
7a47dd7a
SW		 698 enable_irq(dev->irq);
699}
700#endif
701
7a47dd7a 702/* Init RDC MAC */
3d463419 703static int r6040_up(struct net_device *dev)
7a47dd7a
SW		 704{
705 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a 706 void __iomem *ioaddr = lp->base;
3d463419 707 int ret;
7a47dd7a 708
b4f1255d 709 /* Initialise and alloc RX/TX buffers */
3d463419
FF		 710 r6040_init_txbufs(dev);
711 ret = r6040_alloc_rxbufs(dev);
712 if (ret)
713 return ret;
7a47dd7a 714
7a47dd7a 715 /* improve performance (by RDC guys) */
2154c704
FF		 716 r6040_phy_write(ioaddr, 30, 17,
717 (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
718 r6040_phy_write(ioaddr, 30, 17,
719 ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
c6e69bb9
FF		 720 r6040_phy_write(ioaddr, 0, 19, 0x0000);
721 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
7a47dd7a 722
fec3a23b
FF		 723 /* Initialize all MAC registers */
724 r6040_init_mac_regs(dev);
3d463419
FF		 725
726 return 0;
7a47dd7a
SW		 727}
728
7a47dd7a
SW		 729
730/* Read/set MAC address routines */
731static void r6040_mac_address(struct net_device *dev)
732{
733 struct r6040_private *lp = netdev_priv(dev);
734 void __iomem *ioaddr = lp->base;
735 u16 *adrp;
736
737 /* MAC operation register */
738 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
739 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
740 iowrite16(0, ioaddr + MAC_SM);
c1d69937 741 mdelay(5);
7a47dd7a
SW		 742
743 /* Restore MAC Address */
744 adrp = (u16 *) dev->dev_addr;
745 iowrite16(adrp[0], ioaddr + MID_0L);
746 iowrite16(adrp[1], ioaddr + MID_0M);
747 iowrite16(adrp[2], ioaddr + MID_0H);
748}
749
5ac5d616 750static int r6040_open(struct net_device *dev)
7a47dd7a 751{
5ac5d616 752 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a
SW		 753 int ret;
754
755 /* Request IRQ and Register interrupt handler */
91dcbf36 756 ret = request_irq(dev->irq, r6040_interrupt,
7a47dd7a
SW		 757 IRQF_SHARED, dev->name, dev);
758 if (ret)
759 return ret;
760
761 /* Set MAC address */
762 r6040_mac_address(dev);
763
764 /* Allocate Descriptor memory */
6c323103
FR		 765 lp->rx_ring =
766 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
767 if (!lp->rx_ring)
7a47dd7a
SW		 768 return -ENOMEM;
769
6c323103
FR		 770 lp->tx_ring =
771 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
772 if (!lp->tx_ring) {
773 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
774 lp->rx_ring_dma);
775 return -ENOMEM;
776 }
777
3d463419
FF		 778 ret = r6040_up(dev);
779 if (ret) {
780 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
781 lp->tx_ring_dma);
782 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
783 lp->rx_ring_dma);
784 return ret;
785 }
7a47dd7a
SW		 786
787 napi_enable(&lp->napi);
788 netif_start_queue(dev);
789
7a47dd7a
SW		 790 return 0;
791}
792
61357325
SH		 793static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
794 struct net_device *dev)
7a47dd7a
SW		 795{
796 struct r6040_private *lp = netdev_priv(dev);
797 struct r6040_descriptor *descptr;
798 void __iomem *ioaddr = lp->base;
799 unsigned long flags;
7a47dd7a
SW		 800
801 /* Critical Section */
802 spin_lock_irqsave(&lp->lock, flags);
803
804 /* TX resource check */
805 if (!lp->tx_free_desc) {
806 spin_unlock_irqrestore(&lp->lock, flags);
092427be 807 netif_stop_queue(dev);
7d53b809 808 netdev_err(dev, ": no tx descriptor\n");
61357325 809 return NETDEV_TX_BUSY;
7a47dd7a
SW		 810 }
811
812 /* Statistic Counter */
813 dev->stats.tx_packets++;
814 dev->stats.tx_bytes += skb->len;
815 /* Set TX descriptor & Transmit it */
816 lp->tx_free_desc--;
817 descptr = lp->tx_insert_ptr;
818 if (skb->len < MISR)
819 descptr->len = MISR;
820 else
821 descptr->len = skb->len;
822
823 descptr->skb_ptr = skb;
824 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
825 skb->data, skb->len, PCI_DMA_TODEVICE));
32f565df 826 descptr->status = DSC_OWNER_MAC;
7a47dd7a
SW		 827 /* Trigger the MAC to check the TX descriptor */
828 iowrite16(0x01, ioaddr + MTPR);
829 lp->tx_insert_ptr = descptr->vndescp;
830
831 /* If no tx resource, stop */
832 if (!lp->tx_free_desc)
833 netif_stop_queue(dev);
834
7a47dd7a 835 spin_unlock_irqrestore(&lp->lock, flags);
61357325
SH		 836
837 return NETDEV_TX_OK;
7a47dd7a
SW		 838}
839
5ac5d616 840static void r6040_multicast_list(struct net_device *dev)
7a47dd7a
SW		 841{
842 struct r6040_private *lp = netdev_priv(dev);
843 void __iomem *ioaddr = lp->base;
844 u16 *adrp;
845 u16 reg;
846 unsigned long flags;
22bedad3 847 struct netdev_hw_addr *ha;
7a47dd7a
SW		 848 int i;
849
850 /* MAC Address */
851 adrp = (u16 *)dev->dev_addr;
852 iowrite16(adrp[0], ioaddr + MID_0L);
853 iowrite16(adrp[1], ioaddr + MID_0M);
854 iowrite16(adrp[2], ioaddr + MID_0H);
855
856 /* Promiscous Mode */
857 spin_lock_irqsave(&lp->lock, flags);
858
859 /* Clear AMCP & PROM bits */
860 reg = ioread16(ioaddr) & ~0x0120;
861 if (dev->flags & IFF_PROMISC) {
862 reg |= 0x0020;
863 lp->mcr0 |= 0x0020;
864 }
865 /* Too many multicast addresses
866 * accept all traffic */
4cd24eaf
JP		 867 else if ((netdev_mc_count(dev) > MCAST_MAX) ||
868 (dev->flags & IFF_ALLMULTI))
7a47dd7a
SW		 869 reg |= 0x0020;
870
871 iowrite16(reg, ioaddr);
872 spin_unlock_irqrestore(&lp->lock, flags);
873
874 /* Build the hash table */
4cd24eaf 875 if (netdev_mc_count(dev) > MCAST_MAX) {
7a47dd7a
SW		 876 u16 hash_table[4];
877 u32 crc;
878
879 for (i = 0; i < 4; i++)
880 hash_table[i] = 0;
881
22bedad3
JP		 882 netdev_for_each_mc_addr(ha, dev) {
883 char *addrs = ha->addr;
7a47dd7a 884
7a47dd7a
SW		 885 if (!(*addrs & 1))
886 continue;
887
888 crc = ether_crc_le(6, addrs);
889 crc >>= 26;
890 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
891 }
7a47dd7a
SW		 892 /* Fill the MAC hash tables with their values */
893 iowrite16(hash_table[0], ioaddr + MAR0);
894 iowrite16(hash_table[1], ioaddr + MAR1);
895 iowrite16(hash_table[2], ioaddr + MAR2);
896 iowrite16(hash_table[3], ioaddr + MAR3);
897 }
898 /* Multicast Address 1~4 case */
f9dcbcc9 899 i = 0;
22bedad3 900 netdev_for_each_mc_addr(ha, dev) {
f9dcbcc9 901 if (i < MCAST_MAX) {
22bedad3 902 adrp = (u16 *) ha->addr;
f9dcbcc9
JP		 903 iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);
904 iowrite16(adrp[1], ioaddr + MID_1M + 8 * i);
905 iowrite16(adrp[2], ioaddr + MID_1H + 8 * i);
906 } else {
3bcf8229
FF		 907 iowrite16(0xffff, ioaddr + MID_1L + 8 * i);
908 iowrite16(0xffff, ioaddr + MID_1M + 8 * i);
909 iowrite16(0xffff, ioaddr + MID_1H + 8 * i);
f9dcbcc9
JP		 910 }
911 i++;
7a47dd7a
SW		 912 }
913}
914
915static void netdev_get_drvinfo(struct net_device *dev,
916 struct ethtool_drvinfo *info)
917{
918 struct r6040_private *rp = netdev_priv(dev);
919
920 strcpy(info->driver, DRV_NAME);
921 strcpy(info->version, DRV_VERSION);
922 strcpy(info->bus_info, pci_name(rp->pdev));
923}
924
925static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
926{
927 struct r6040_private *rp = netdev_priv(dev);
7a47dd7a 928
3831861b 929 return phy_ethtool_gset(rp->phydev, cmd);
7a47dd7a
SW		 930}
931
932static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7a47dd7a
SW		 933{
934 struct r6040_private *rp = netdev_priv(dev);
935
3831861b 936 return phy_ethtool_sset(rp->phydev, cmd);
7a47dd7a
SW		 937}
938
a7bd89cb 939static const struct ethtool_ops netdev_ethtool_ops = {
7a47dd7a
SW		 940 .get_drvinfo = netdev_get_drvinfo,
941 .get_settings = netdev_get_settings,
942 .set_settings = netdev_set_settings,
3831861b 943 .get_link = ethtool_op_get_link,
7a47dd7a
SW		 944};
945
a7bd89cb
SH		 946static const struct net_device_ops r6040_netdev_ops = {
947 .ndo_open = r6040_open,
948 .ndo_stop = r6040_close,
949 .ndo_start_xmit = r6040_start_xmit,
950 .ndo_get_stats = r6040_get_stats,
951 .ndo_set_multicast_list = r6040_multicast_list,
952 .ndo_change_mtu = eth_change_mtu,
953 .ndo_validate_addr = eth_validate_addr,
2154c704 954 .ndo_set_mac_address = eth_mac_addr,
a7bd89cb
SH		 955 .ndo_do_ioctl = r6040_ioctl,
956 .ndo_tx_timeout = r6040_tx_timeout,
957#ifdef CONFIG_NET_POLL_CONTROLLER
958 .ndo_poll_controller = r6040_poll_controller,
959#endif
960};
961
3831861b
FF		 962static void r6040_adjust_link(struct net_device *dev)
963{
964 struct r6040_private *lp = netdev_priv(dev);
965 struct phy_device *phydev = lp->phydev;
966 int status_changed = 0;
967 void __iomem *ioaddr = lp->base;
968
969 BUG_ON(!phydev);
970
971 if (lp->old_link != phydev->link) {
972 status_changed = 1;
973 lp->old_link = phydev->link;
974 }
975
976 /* reflect duplex change */
977 if (phydev->link && (lp->old_duplex != phydev->duplex)) {
978 lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? 0x8000 : 0);
979 iowrite16(lp->mcr0, ioaddr);
980
981 status_changed = 1;
982 lp->old_duplex = phydev->duplex;
983 }
984
985 if (status_changed) {
986 pr_info("%s: link %s", dev->name, phydev->link ?
987 "UP" : "DOWN");
988 if (phydev->link)
989 pr_cont(" - %d/%s", phydev->speed,
990 DUPLEX_FULL == phydev->duplex ? "full" : "half");
991 pr_cont("\n");
992 }
993}
994
995static int r6040_mii_probe(struct net_device *dev)
996{
997 struct r6040_private *lp = netdev_priv(dev);
998 struct phy_device *phydev = NULL;
999
1000 phydev = phy_find_first(lp->mii_bus);
1001 if (!phydev) {
1002 dev_err(&lp->pdev->dev, "no PHY found\n");
1003 return -ENODEV;
1004 }
1005
1006 phydev = phy_connect(dev, dev_name(&phydev->dev), &r6040_adjust_link,
1007 0, PHY_INTERFACE_MODE_MII);
1008
1009 if (IS_ERR(phydev)) {
1010 dev_err(&lp->pdev->dev, "could not attach to PHY\n");
1011 return PTR_ERR(phydev);
1012 }
1013
1014 /* mask with MAC supported features */
1015 phydev->supported &= (SUPPORTED_10baseT_Half
1016 | SUPPORTED_10baseT_Full
1017 | SUPPORTED_100baseT_Half
1018 | SUPPORTED_100baseT_Full
1019 | SUPPORTED_Autoneg
1020 | SUPPORTED_MII
1021 | SUPPORTED_TP);
1022
1023 phydev->advertising = phydev->supported;
1024 lp->phydev = phydev;
1025 lp->old_link = 0;
1026 lp->old_duplex = -1;
1027
1028 dev_info(&lp->pdev->dev, "attached PHY driver [%s] "
1029 "(mii_bus:phy_addr=%s)\n",
1030 phydev->drv->name, dev_name(&phydev->dev));
1031
1032 return 0;
1033}
1034
7a47dd7a
SW		 1035static int __devinit r6040_init_one(struct pci_dev *pdev,
1036 const struct pci_device_id *ent)
1037{
1038 struct net_device *dev;
1039 struct r6040_private *lp;
1040 void __iomem *ioaddr;
1041 int err, io_size = R6040_IO_SIZE;
1042 static int card_idx = -1;
1043 int bar = 0;
7a47dd7a 1044 u16 *adrp;
3831861b 1045 int i;
7a47dd7a 1046
2154c704 1047 pr_info("%s\n", version);
7a47dd7a
SW		 1048
1049 err = pci_enable_device(pdev);
1050 if (err)
b0e45390 1051 goto err_out;
7a47dd7a
SW		 1052
1053 /* this should always be supported */
284901a9 1054 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b0e45390 1055 if (err) {
7d53b809 1056 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
7a47dd7a 1057 "not supported by the card\n");
b0e45390 1058 goto err_out;
7a47dd7a 1059 }
284901a9 1060 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
b0e45390 1061 if (err) {
7d53b809 1062 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
092427be 1063 "not supported by the card\n");
b0e45390 1064 goto err_out;
092427be 1065 }
7a47dd7a
SW		 1066
1067 /* IO Size check */
6f5bec19 1068 if (pci_resource_len(pdev, bar) < io_size) {
7d53b809 1069 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
b0e45390
FF		 1070 err = -EIO;
1071 goto err_out;
7a47dd7a
SW		 1072 }
1073
7a47dd7a
SW		 1074 pci_set_master(pdev);
1075
1076 dev = alloc_etherdev(sizeof(struct r6040_private));
1077 if (!dev) {
7d53b809 1078 dev_err(&pdev->dev, "Failed to allocate etherdev\n");
b0e45390
FF		 1079 err = -ENOMEM;
1080 goto err_out;
7a47dd7a
SW		 1081 }
1082 SET_NETDEV_DEV(dev, &pdev->dev);
1083 lp = netdev_priv(dev);
7a47dd7a 1084
b0e45390
FF		 1085 err = pci_request_regions(pdev, DRV_NAME);
1086
1087 if (err) {
7d53b809 1088 dev_err(&pdev->dev, "Failed to request PCI regions\n");
b0e45390 1089 goto err_out_free_dev;
7a47dd7a
SW		 1090 }
1091
1092 ioaddr = pci_iomap(pdev, bar, io_size);
1093 if (!ioaddr) {
7d53b809 1094 dev_err(&pdev->dev, "ioremap failed for device\n");
b0e45390
FF		 1095 err = -EIO;
1096 goto err_out_free_res;
7a47dd7a 1097 }
84314bf9
FF		 1098 /* If PHY status change register is still set to zero it means the
1099 * bootloader didn't initialize it */
1100 if (ioread16(ioaddr + PHY_CC) == 0)
1101 iowrite16(0x9f07, ioaddr + PHY_CC);
7a47dd7a
SW		 1102
1103 /* Init system & device */
7a47dd7a
SW		 1104 lp->base = ioaddr;
1105 dev->irq = pdev->irq;
1106
1107 spin_lock_init(&lp->lock);
1108 pci_set_drvdata(pdev, dev);
1109
1110 /* Set MAC address */
1111 card_idx++;
1112
1113 adrp = (u16 *)dev->dev_addr;
1114 adrp[0] = ioread16(ioaddr + MID_0L);
1115 adrp[1] = ioread16(ioaddr + MID_0M);
1116 adrp[2] = ioread16(ioaddr + MID_0H);
1117
1d2b1a76
FF		 1118 /* Some bootloader/BIOSes do not initialize
1119 * MAC address, warn about that */
9f113618 1120 if (!(adrp[0] || adrp[1] || adrp[2])) {
2154c704
FF		 1121 netdev_warn(dev, "MAC address not initialized, "
1122 "generating random\n");
9f113618
FF		 1123 random_ether_addr(dev->dev_addr);
1124 }
1d2b1a76 1125
7a47dd7a
SW		 1126 /* Link new device into r6040_root_dev */
1127 lp->pdev = pdev;
129cf9a7 1128 lp->dev = dev;
7a47dd7a
SW		 1129
1130 /* Init RDC private data */
1131 lp->mcr0 = 0x1002;
1132 lp->phy_addr = phy_table[card_idx];
7a47dd7a
SW		 1133
1134 /* The RDC-specific entries in the device structure. */
a7bd89cb 1135 dev->netdev_ops = &r6040_netdev_ops;
7a47dd7a 1136 dev->ethtool_ops = &netdev_ethtool_ops;
7a47dd7a 1137 dev->watchdog_timeo = TX_TIMEOUT;
a7bd89cb 1138
7a47dd7a 1139 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
3831861b
FF		 1140
1141 lp->mii_bus = mdiobus_alloc();
1142 if (!lp->mii_bus) {
1143 dev_err(&pdev->dev, "mdiobus_alloc() failed\n");
e03f614a
MK		 1144 goto err_out_unmap;
1145 }
1146
3831861b
FF		 1147 lp->mii_bus->priv = dev;
1148 lp->mii_bus->read = r6040_mdiobus_read;
1149 lp->mii_bus->write = r6040_mdiobus_write;
1150 lp->mii_bus->reset = r6040_mdiobus_reset;
1151 lp->mii_bus->name = "r6040_eth_mii";
1152 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x", card_idx);
1153 lp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1154 if (!lp->mii_bus->irq) {
1155 dev_err(&pdev->dev, "mii_bus irq allocation failed\n");
1156 goto err_out_mdio;
1157 }
1158
1159 for (i = 0; i < PHY_MAX_ADDR; i++)
1160 lp->mii_bus->irq[i] = PHY_POLL;
1161
1162 err = mdiobus_register(lp->mii_bus);
1163 if (err) {
1164 dev_err(&pdev->dev, "failed to register MII bus\n");
1165 goto err_out_mdio_irq;
1166 }
1167
1168 err = r6040_mii_probe(dev);
1169 if (err) {
1170 dev_err(&pdev->dev, "failed to probe MII bus\n");
1171 goto err_out_mdio_unregister;
1172 }
1173
7a47dd7a
SW		 1174 /* Register net device. After this dev->name assign */
1175 err = register_netdev(dev);
1176 if (err) {
7d53b809 1177 dev_err(&pdev->dev, "Failed to register net device\n");
3831861b 1178 goto err_out_mdio_unregister;
7a47dd7a
SW		 1179 }
1180 return 0;
1181
3831861b
FF		 1182err_out_mdio_unregister:
1183 mdiobus_unregister(lp->mii_bus);
1184err_out_mdio_irq:
1185 kfree(lp->mii_bus->irq);
1186err_out_mdio:
1187 mdiobus_free(lp->mii_bus);
b0e45390
FF		 1188err_out_unmap:
1189 pci_iounmap(pdev, ioaddr);
1190err_out_free_res:
7a47dd7a 1191 pci_release_regions(pdev);
b0e45390 1192err_out_free_dev:
7a47dd7a 1193 free_netdev(dev);
b0e45390 1194err_out:
7a47dd7a
SW		 1195 return err;
1196}
1197
1198static void __devexit r6040_remove_one(struct pci_dev *pdev)
1199{
1200 struct net_device *dev = pci_get_drvdata(pdev);
3831861b 1201 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a
SW		 1202
1203 unregister_netdev(dev);
3831861b
FF		 1204 mdiobus_unregister(lp->mii_bus);
1205 kfree(lp->mii_bus->irq);
1206 mdiobus_free(lp->mii_bus);
7a47dd7a
SW		 1207 pci_release_regions(pdev);
1208 free_netdev(dev);
1209 pci_disable_device(pdev);
1210 pci_set_drvdata(pdev, NULL);
1211}
1212
1213
a3aa1884 1214static DEFINE_PCI_DEVICE_TABLE(r6040_pci_tbl) = {
5ac5d616
FR		 1215 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1216 { 0 }
7a47dd7a
SW		 1217};
1218MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1219
1220static struct pci_driver r6040_driver = {
5ac5d616 1221 .name = DRV_NAME,
7a47dd7a
SW		 1222 .id_table = r6040_pci_tbl,
1223 .probe = r6040_init_one,
1224 .remove = __devexit_p(r6040_remove_one),
1225};
1226
1227
1228static int __init r6040_init(void)
1229{
1230 return pci_register_driver(&r6040_driver);
1231}
1232
1233
1234static void __exit r6040_cleanup(void)
1235{
1236 pci_unregister_driver(&r6040_driver);
1237}
1238
1239module_init(r6040_init);
1240module_exit(r6040_cleanup);
Linux kernel - Deliverables
This page took 0.504868 seconds and 5 git commands to generate.