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mv643xx_eth: fix NETPOLL build
[deliverable/linux.git] / drivers / net / r6040.c
CommitLineData
7a47dd7a
SW		 1/*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
5ac5d616 6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7a47dd7a
SW		 7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23*/
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/version.h>
28#include <linux/moduleparam.h>
29#include <linux/string.h>
30#include <linux/timer.h>
31#include <linux/errno.h>
32#include <linux/ioport.h>
33#include <linux/slab.h>
34#include <linux/interrupt.h>
35#include <linux/pci.h>
36#include <linux/netdevice.h>
37#include <linux/etherdevice.h>
38#include <linux/skbuff.h>
39#include <linux/init.h>
40#include <linux/delay.h>
41#include <linux/mii.h>
42#include <linux/ethtool.h>
43#include <linux/crc32.h>
44#include <linux/spinlock.h>
092427be
JG		 45#include <linux/bitops.h>
46#include <linux/io.h>
47#include <linux/irq.h>
48#include <linux/uaccess.h>
7a47dd7a
SW		 49
50#include <asm/processor.h>
7a47dd7a
SW		 51
52#define DRV_NAME "r6040"
53#define DRV_VERSION "0.16"
54#define DRV_RELDATE "10Nov2007"
55
56/* PHY CHIP Address */
57#define PHY1_ADDR 1 /* For MAC1 */
58#define PHY2_ADDR 2 /* For MAC2 */
59#define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
60#define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
61
62/* Time in jiffies before concluding the transmitter is hung. */
5ac5d616 63#define TX_TIMEOUT (6000 * HZ / 1000)
7a47dd7a
SW		 64
65/* RDC MAC I/O Size */
66#define R6040_IO_SIZE 256
67
68/* MAX RDC MAC */
69#define MAX_MAC 2
70
71/* MAC registers */
72#define MCR0 0x00 /* Control register 0 */
73#define MCR1 0x04 /* Control register 1 */
74#define MAC_RST 0x0001 /* Reset the MAC */
75#define MBCR 0x08 /* Bus control */
76#define MT_ICR 0x0C /* TX interrupt control */
77#define MR_ICR 0x10 /* RX interrupt control */
78#define MTPR 0x14 /* TX poll command register */
79#define MR_BSR 0x18 /* RX buffer size */
80#define MR_DCR 0x1A /* RX descriptor control */
81#define MLSR 0x1C /* Last status */
82#define MMDIO 0x20 /* MDIO control register */
83#define MDIO_WRITE 0x4000 /* MDIO write */
84#define MDIO_READ 0x2000 /* MDIO read */
85#define MMRD 0x24 /* MDIO read data register */
86#define MMWD 0x28 /* MDIO write data register */
87#define MTD_SA0 0x2C /* TX descriptor start address 0 */
88#define MTD_SA1 0x30 /* TX descriptor start address 1 */
89#define MRD_SA0 0x34 /* RX descriptor start address 0 */
90#define MRD_SA1 0x38 /* RX descriptor start address 1 */
91#define MISR 0x3C /* Status register */
92#define MIER 0x40 /* INT enable register */
93#define MSK_INT 0x0000 /* Mask off interrupts */
3d254348
FF		 94#define RX_FINISH 0x0001 /* RX finished */
95#define RX_NO_DESC 0x0002 /* No RX descriptor available */
96#define RX_FIFO_FULL 0x0004 /* RX FIFO full */
97#define RX_EARLY 0x0008 /* RX early */
98#define TX_FINISH 0x0010 /* TX finished */
99#define TX_EARLY 0x0080 /* TX early */
100#define EVENT_OVRFL 0x0100 /* Event counter overflow */
101#define LINK_CHANGED 0x0200 /* PHY link changed */
7a47dd7a
SW		 102#define ME_CISR 0x44 /* Event counter INT status */
103#define ME_CIER 0x48 /* Event counter INT enable */
104#define MR_CNT 0x50 /* Successfully received packet counter */
105#define ME_CNT0 0x52 /* Event counter 0 */
106#define ME_CNT1 0x54 /* Event counter 1 */
107#define ME_CNT2 0x56 /* Event counter 2 */
108#define ME_CNT3 0x58 /* Event counter 3 */
109#define MT_CNT 0x5A /* Successfully transmit packet counter */
110#define ME_CNT4 0x5C /* Event counter 4 */
111#define MP_CNT 0x5E /* Pause frame counter register */
112#define MAR0 0x60 /* Hash table 0 */
113#define MAR1 0x62 /* Hash table 1 */
114#define MAR2 0x64 /* Hash table 2 */
115#define MAR3 0x66 /* Hash table 3 */
116#define MID_0L 0x68 /* Multicast address MID0 Low */
117#define MID_0M 0x6A /* Multicast address MID0 Medium */
118#define MID_0H 0x6C /* Multicast address MID0 High */
119#define MID_1L 0x70 /* MID1 Low */
120#define MID_1M 0x72 /* MID1 Medium */
121#define MID_1H 0x74 /* MID1 High */
122#define MID_2L 0x78 /* MID2 Low */
123#define MID_2M 0x7A /* MID2 Medium */
124#define MID_2H 0x7C /* MID2 High */
125#define MID_3L 0x80 /* MID3 Low */
126#define MID_3M 0x82 /* MID3 Medium */
127#define MID_3H 0x84 /* MID3 High */
128#define PHY_CC 0x88 /* PHY status change configuration register */
129#define PHY_ST 0x8A /* PHY status register */
130#define MAC_SM 0xAC /* MAC status machine */
131#define MAC_ID 0xBE /* Identifier register */
132
133#define TX_DCNT 0x80 /* TX descriptor count */
134#define RX_DCNT 0x80 /* RX descriptor count */
135#define MAX_BUF_SIZE 0x600
6c323103
FR		 136#define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
137#define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
7a47dd7a
SW		 138#define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
139#define MCAST_MAX 4 /* Max number multicast addresses to filter */
140
141/* PHY settings */
142#define ICPLUS_PHY_ID 0x0243
143
144MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
145 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
146 "Florian Fainelli <florian@openwrt.org>");
147MODULE_LICENSE("GPL");
148MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
149
3d254348
FF		 150/* RX and TX interrupts that we handle */
151#define RX_INT (RX_FINISH)
152#define TX_INT (TX_FINISH)
153#define INT_MASK (RX_INT | TX_INT)
7a47dd7a
SW		 154
155struct r6040_descriptor {
156 u16 status, len; /* 0-3 */
157 __le32 buf; /* 4-7 */
158 __le32 ndesc; /* 8-B */
159 u32 rev1; /* C-F */
160 char *vbufp; /* 10-13 */
161 struct r6040_descriptor *vndescp; /* 14-17 */
162 struct sk_buff *skb_ptr; /* 18-1B */
163 u32 rev2; /* 1C-1F */
164} __attribute__((aligned(32)));
165
166struct r6040_private {
167 spinlock_t lock; /* driver lock */
168 struct timer_list timer;
169 struct pci_dev *pdev;
170 struct r6040_descriptor *rx_insert_ptr;
171 struct r6040_descriptor *rx_remove_ptr;
172 struct r6040_descriptor *tx_insert_ptr;
173 struct r6040_descriptor *tx_remove_ptr;
6c323103
FR		 174 struct r6040_descriptor *rx_ring;
175 struct r6040_descriptor *tx_ring;
176 dma_addr_t rx_ring_dma;
177 dma_addr_t tx_ring_dma;
7a47dd7a
SW		 178 u16 tx_free_desc, rx_free_desc, phy_addr, phy_mode;
179 u16 mcr0, mcr1;
7a47dd7a
SW		 180 u16 switch_sig;
181 struct net_device *dev;
182 struct mii_if_info mii_if;
183 struct napi_struct napi;
7a47dd7a
SW		 184 void __iomem *base;
185};
186
187static char version[] __devinitdata = KERN_INFO DRV_NAME
188 ": RDC R6040 NAPI net driver,"
189 "version "DRV_VERSION " (" DRV_RELDATE ")\n";
190
092427be 191static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
7a47dd7a
SW		 192
193/* Read a word data from PHY Chip */
c6e69bb9 194static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
7a47dd7a
SW		 195{
196 int limit = 2048;
197 u16 cmd;
198
199 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
200 /* Wait for the read bit to be cleared */
201 while (limit--) {
202 cmd = ioread16(ioaddr + MMDIO);
203 if (cmd & MDIO_READ)
204 break;
205 }
206
207 return ioread16(ioaddr + MMRD);
208}
209
210/* Write a word data from PHY Chip */
c6e69bb9 211static void r6040_phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
7a47dd7a
SW		 212{
213 int limit = 2048;
214 u16 cmd;
215
216 iowrite16(val, ioaddr + MMWD);
217 /* Write the command to the MDIO bus */
218 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
219 /* Wait for the write bit to be cleared */
220 while (limit--) {
221 cmd = ioread16(ioaddr + MMDIO);
222 if (cmd & MDIO_WRITE)
223 break;
224 }
225}
226
c6e69bb9 227static int r6040_mdio_read(struct net_device *dev, int mii_id, int reg)
7a47dd7a
SW		 228{
229 struct r6040_private *lp = netdev_priv(dev);
230 void __iomem *ioaddr = lp->base;
231
c6e69bb9 232 return (r6040_phy_read(ioaddr, lp->phy_addr, reg));
7a47dd7a
SW		 233}
234
c6e69bb9 235static void r6040_mdio_write(struct net_device *dev, int mii_id, int reg, int val)
7a47dd7a
SW		 236{
237 struct r6040_private *lp = netdev_priv(dev);
238 void __iomem *ioaddr = lp->base;
239
c6e69bb9 240 r6040_phy_write(ioaddr, lp->phy_addr, reg, val);
7a47dd7a
SW		 241}
242
b4f1255d
FF		 243static void r6040_free_txbufs(struct net_device *dev)
244{
245 struct r6040_private *lp = netdev_priv(dev);
246 int i;
247
248 for (i = 0; i < TX_DCNT; i++) {
249 if (lp->tx_insert_ptr->skb_ptr) {
ed773b4a
AV		 250 pci_unmap_single(lp->pdev,
251 le32_to_cpu(lp->tx_insert_ptr->buf),
b4f1255d
FF		 252 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
253 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
254 lp->rx_insert_ptr->skb_ptr = NULL;
255 }
256 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
257 }
258}
259
260static void r6040_free_rxbufs(struct net_device *dev)
261{
262 struct r6040_private *lp = netdev_priv(dev);
263 int i;
264
265 for (i = 0; i < RX_DCNT; i++) {
266 if (lp->rx_insert_ptr->skb_ptr) {
ed773b4a
AV		 267 pci_unmap_single(lp->pdev,
268 le32_to_cpu(lp->rx_insert_ptr->buf),
b4f1255d
FF		 269 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
270 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
271 lp->rx_insert_ptr->skb_ptr = NULL;
272 }
273 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
274 }
275}
276
b4f1255d
FF		 277static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
278 dma_addr_t desc_dma, int size)
279{
280 struct r6040_descriptor *desc = desc_ring;
281 dma_addr_t mapping = desc_dma;
282
283 while (size-- > 0) {
3f6602ad 284 mapping += sizeof(*desc);
b4f1255d
FF		 285 desc->ndesc = cpu_to_le32(mapping);
286 desc->vndescp = desc + 1;
287 desc++;
288 }
289 desc--;
290 desc->ndesc = cpu_to_le32(desc_dma);
291 desc->vndescp = desc_ring;
292}
293
7a47dd7a 294/* Allocate skb buffer for rx descriptor */
c6e69bb9 295static void r6040_rx_buf_alloc(struct r6040_private *lp, struct net_device *dev)
7a47dd7a
SW		 296{
297 struct r6040_descriptor *descptr;
7a47dd7a
SW		 298
299 descptr = lp->rx_insert_ptr;
300 while (lp->rx_free_desc < RX_DCNT) {
ec6d2d45 301 descptr->skb_ptr = netdev_alloc_skb(dev, MAX_BUF_SIZE);
7a47dd7a
SW		 302
303 if (!descptr->skb_ptr)
304 break;
305 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
5125a786 306 descptr->skb_ptr->data,
7a47dd7a
SW		 307 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
308 descptr->status = 0x8000;
309 descptr = descptr->vndescp;
310 lp->rx_free_desc++;
7a47dd7a
SW		 311 }
312 lp->rx_insert_ptr = descptr;
313}
314
3d463419 315static void r6040_init_txbufs(struct net_device *dev)
b4f1255d
FF		 316{
317 struct r6040_private *lp = netdev_priv(dev);
b4f1255d
FF		 318
319 lp->tx_free_desc = TX_DCNT;
320
321 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
322 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
b4f1255d
FF		 323}
324
3d463419 325static int r6040_alloc_rxbufs(struct net_device *dev)
b4f1255d
FF		 326{
327 struct r6040_private *lp = netdev_priv(dev);
3d463419
FF		 328 struct r6040_descriptor *desc;
329 struct sk_buff *skb;
330 int rc;
b4f1255d
FF		 331
332 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
333 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
334
3d463419
FF		 335 /* Allocate skbs for the rx descriptors */
336 desc = lp->rx_ring;
337 do {
338 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
339 if (!skb) {
340 printk(KERN_ERR "%s: failed to alloc skb for rx\n", dev->name);
341 rc = -ENOMEM;
342 goto err_exit;
343 }
344 desc->skb_ptr = skb;
345 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
346 desc->skb_ptr->data,
347 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
348 desc->status = 0x8000;
349 desc = desc->vndescp;
350 } while (desc != lp->rx_ring);
351
352 return 0;
353
354err_exit:
355 /* Deallocate all previously allocated skbs */
356 r6040_free_rxbufs(dev);
357 return rc;
fec3a23b
FF		 358}
359
360static void r6040_init_mac_regs(struct net_device *dev)
361{
362 struct r6040_private *lp = netdev_priv(dev);
363 void __iomem *ioaddr = lp->base;
364 int limit = 2048;
365 u16 cmd;
366
367 /* Mask Off Interrupt */
368 iowrite16(MSK_INT, ioaddr + MIER);
369
370 /* Reset RDC MAC */
371 iowrite16(MAC_RST, ioaddr + MCR1);
372 while (limit--) {
373 cmd = ioread16(ioaddr + MCR1);
374 if (cmd & 0x1)
375 break;
376 }
377 /* Reset internal state machine */
378 iowrite16(2, ioaddr + MAC_SM);
379 iowrite16(0, ioaddr + MAC_SM);
380 udelay(5000);
381
382 /* MAC Bus Control Register */
383 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
384
385 /* Buffer Size Register */
386 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
387
388 /* Write TX ring start address */
389 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
390 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
b4f1255d 391
fec3a23b 392 /* Write RX ring start address */
b4f1255d
FF		 393 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
394 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
fec3a23b
FF		 395
396 /* Set interrupt waiting time and packet numbers */
397 iowrite16(0x0F06, ioaddr + MT_ICR);
398 iowrite16(0x0F06, ioaddr + MR_ICR);
399
400 /* Enable interrupts */
401 iowrite16(INT_MASK, ioaddr + MIER);
402
403 /* Enable TX and RX */
404 iowrite16(lp->mcr0 | 0x0002, ioaddr);
405
406 /* Let TX poll the descriptors
407 * we may got called by r6040_tx_timeout which has left
408 * some unsent tx buffers */
409 iowrite16(0x01, ioaddr + MTPR);
b4f1255d 410}
7a47dd7a 411
106adf3c
FF		 412static void r6040_tx_timeout(struct net_device *dev)
413{
414 struct r6040_private *priv = netdev_priv(dev);
415 void __iomem *ioaddr = priv->base;
416
fec3a23b
FF		 417 printk(KERN_WARNING "%s: transmit timed out, int enable %4.4x "
418 "status %4.4x, PHY status %4.4x\n",
106adf3c 419 dev->name, ioread16(ioaddr + MIER),
fec3a23b 420 ioread16(ioaddr + MISR),
c6e69bb9 421 r6040_mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
106adf3c 422
106adf3c 423 dev->stats.tx_errors++;
fec3a23b
FF		 424
425 /* Reset MAC and re-init all registers */
426 r6040_init_mac_regs(dev);
106adf3c
FF		 427}
428
7a47dd7a
SW		 429static struct net_device_stats *r6040_get_stats(struct net_device *dev)
430{
431 struct r6040_private *priv = netdev_priv(dev);
432 void __iomem *ioaddr = priv->base;
433 unsigned long flags;
434
435 spin_lock_irqsave(&priv->lock, flags);
d248fd77
FF		 436 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
437 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
7a47dd7a
SW		 438 spin_unlock_irqrestore(&priv->lock, flags);
439
d248fd77 440 return &dev->stats;
7a47dd7a
SW		 441}
442
443/* Stop RDC MAC and Free the allocated resource */
444static void r6040_down(struct net_device *dev)
445{
446 struct r6040_private *lp = netdev_priv(dev);
447 void __iomem *ioaddr = lp->base;
6c323103 448 struct pci_dev *pdev = lp->pdev;
7a47dd7a
SW		 449 int limit = 2048;
450 u16 *adrp;
451 u16 cmd;
452
453 /* Stop MAC */
454 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
455 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
456 while (limit--) {
457 cmd = ioread16(ioaddr + MCR1);
458 if (cmd & 0x1)
459 break;
460 }
461
462 /* Restore MAC Address to MIDx */
463 adrp = (u16 *) dev->dev_addr;
464 iowrite16(adrp[0], ioaddr + MID_0L);
465 iowrite16(adrp[1], ioaddr + MID_0M);
466 iowrite16(adrp[2], ioaddr + MID_0H);
467 free_irq(dev->irq, dev);
b4f1255d 468
7a47dd7a 469 /* Free RX buffer */
b4f1255d 470 r6040_free_rxbufs(dev);
7a47dd7a
SW		 471
472 /* Free TX buffer */
b4f1255d 473 r6040_free_txbufs(dev);
7a47dd7a
SW		 474
475 /* Free Descriptor memory */
6c323103
FR		 476 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
477 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
7a47dd7a
SW		 478}
479
5ac5d616 480static int r6040_close(struct net_device *dev)
7a47dd7a
SW		 481{
482 struct r6040_private *lp = netdev_priv(dev);
483
484 /* deleted timer */
485 del_timer_sync(&lp->timer);
486
487 spin_lock_irq(&lp->lock);
488 netif_stop_queue(dev);
489 r6040_down(dev);
490 spin_unlock_irq(&lp->lock);
491
492 return 0;
493}
494
495/* Status of PHY CHIP */
c6e69bb9 496static int r6040_phy_mode_chk(struct net_device *dev)
7a47dd7a
SW		 497{
498 struct r6040_private *lp = netdev_priv(dev);
499 void __iomem *ioaddr = lp->base;
500 int phy_dat;
501
502 /* PHY Link Status Check */
c6e69bb9 503 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
7a47dd7a
SW		 504 if (!(phy_dat & 0x4))
505 phy_dat = 0x8000; /* Link Failed, full duplex */
506
507 /* PHY Chip Auto-Negotiation Status */
c6e69bb9 508 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
7a47dd7a
SW		 509 if (phy_dat & 0x0020) {
510 /* Auto Negotiation Mode */
c6e69bb9
FF		 511 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 5);
512 phy_dat &= r6040_phy_read(ioaddr, lp->phy_addr, 4);
7a47dd7a
SW		 513 if (phy_dat & 0x140)
514 /* Force full duplex */
515 phy_dat = 0x8000;
516 else
517 phy_dat = 0;
518 } else {
519 /* Force Mode */
c6e69bb9 520 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 0);
7a47dd7a
SW		 521 if (phy_dat & 0x100)
522 phy_dat = 0x8000;
523 else
524 phy_dat = 0x0000;
525 }
526
527 return phy_dat;
528};
529
530static void r6040_set_carrier(struct mii_if_info *mii)
531{
c6e69bb9 532 if (r6040_phy_mode_chk(mii->dev)) {
7a47dd7a
SW		 533 /* autoneg is off: Link is always assumed to be up */
534 if (!netif_carrier_ok(mii->dev))
535 netif_carrier_on(mii->dev);
536 } else
c6e69bb9 537 r6040_phy_mode_chk(mii->dev);
7a47dd7a
SW		 538}
539
540static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
541{
542 struct r6040_private *lp = netdev_priv(dev);
5ac5d616 543 struct mii_ioctl_data *data = if_mii(rq);
7a47dd7a
SW		 544 int rc;
545
546 if (!netif_running(dev))
547 return -EINVAL;
548 spin_lock_irq(&lp->lock);
549 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
550 spin_unlock_irq(&lp->lock);
551 r6040_set_carrier(&lp->mii_if);
552 return rc;
553}
554
555static int r6040_rx(struct net_device *dev, int limit)
556{
557 struct r6040_private *priv = netdev_priv(dev);
558 int count;
559 void __iomem *ioaddr = priv->base;
560 u16 err;
561
562 for (count = 0; count < limit; ++count) {
563 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
564 struct sk_buff *skb_ptr;
565
7a47dd7a
SW		 566 descptr = priv->rx_remove_ptr;
567
568 /* Check for errors */
569 err = ioread16(ioaddr + MLSR);
d248fd77
FF		 570 if (err & 0x0400)
571 dev->stats.rx_errors++;
7a47dd7a 572 /* RX FIFO over-run */
d248fd77
FF		 573 if (err & 0x8000)
574 dev->stats.rx_fifo_errors++;
7a47dd7a 575 /* RX descriptor unavailable */
d248fd77
FF		 576 if (err & 0x0080)
577 dev->stats.rx_frame_errors++;
7a47dd7a 578 /* Received packet with length over buffer lenght */
d248fd77
FF		 579 if (err & 0x0020)
580 dev->stats.rx_over_errors++;
7a47dd7a 581 /* Received packet with too long or short */
d248fd77
FF		 582 if (err & (0x0010 | 0x0008))
583 dev->stats.rx_length_errors++;
7a47dd7a
SW		 584 /* Received packet with CRC errors */
585 if (err & 0x0004) {
586 spin_lock(&priv->lock);
d248fd77 587 dev->stats.rx_crc_errors++;
7a47dd7a
SW		 588 spin_unlock(&priv->lock);
589 }
590
591 while (priv->rx_free_desc) {
592 /* No RX packet */
593 if (descptr->status & 0x8000)
594 break;
595 skb_ptr = descptr->skb_ptr;
596 if (!skb_ptr) {
597 printk(KERN_ERR "%s: Inconsistent RX"
598 "descriptor chain\n",
599 dev->name);
600 break;
601 }
602 descptr->skb_ptr = NULL;
603 skb_ptr->dev = priv->dev;
604 /* Do not count the CRC */
605 skb_put(skb_ptr, descptr->len - 4);
ed773b4a 606 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
7a47dd7a
SW		 607 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
608 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
609 /* Send to upper layer */
610 netif_receive_skb(skb_ptr);
611 dev->last_rx = jiffies;
d248fd77
FF		 612 dev->stats.rx_packets++;
613 dev->stats.rx_bytes += descptr->len;
7a47dd7a
SW		 614 /* To next descriptor */
615 descptr = descptr->vndescp;
616 priv->rx_free_desc--;
617 }
618 priv->rx_remove_ptr = descptr;
619 }
620 /* Allocate new RX buffer */
621 if (priv->rx_free_desc < RX_DCNT)
c6e69bb9 622 r6040_rx_buf_alloc(priv, priv->dev);
7a47dd7a
SW		 623
624 return count;
625}
626
627static void r6040_tx(struct net_device *dev)
628{
629 struct r6040_private *priv = netdev_priv(dev);
630 struct r6040_descriptor *descptr;
631 void __iomem *ioaddr = priv->base;
632 struct sk_buff *skb_ptr;
633 u16 err;
634
635 spin_lock(&priv->lock);
636 descptr = priv->tx_remove_ptr;
637 while (priv->tx_free_desc < TX_DCNT) {
638 /* Check for errors */
639 err = ioread16(ioaddr + MLSR);
640
d248fd77
FF		 641 if (err & 0x0200)
642 dev->stats.rx_fifo_errors++;
643 if (err & (0x2000 | 0x4000))
644 dev->stats.tx_carrier_errors++;
7a47dd7a
SW		 645
646 if (descptr->status & 0x8000)
ec6d2d45 647 break; /* Not complete */
7a47dd7a 648 skb_ptr = descptr->skb_ptr;
ed773b4a 649 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
7a47dd7a
SW		 650 skb_ptr->len, PCI_DMA_TODEVICE);
651 /* Free buffer */
652 dev_kfree_skb_irq(skb_ptr);
653 descptr->skb_ptr = NULL;
654 /* To next descriptor */
655 descptr = descptr->vndescp;
656 priv->tx_free_desc++;
657 }
658 priv->tx_remove_ptr = descptr;
659
660 if (priv->tx_free_desc)
661 netif_wake_queue(dev);
662 spin_unlock(&priv->lock);
663}
664
665static int r6040_poll(struct napi_struct *napi, int budget)
666{
667 struct r6040_private *priv =
668 container_of(napi, struct r6040_private, napi);
669 struct net_device *dev = priv->dev;
670 void __iomem *ioaddr = priv->base;
671 int work_done;
672
673 work_done = r6040_rx(dev, budget);
674
675 if (work_done < budget) {
676 netif_rx_complete(dev, napi);
677 /* Enable RX interrupt */
678 iowrite16(ioread16(ioaddr + MIER) | RX_INT, ioaddr + MIER);
679 }
680 return work_done;
681}
682
683/* The RDC interrupt handler. */
684static irqreturn_t r6040_interrupt(int irq, void *dev_id)
685{
686 struct net_device *dev = dev_id;
687 struct r6040_private *lp = netdev_priv(dev);
688 void __iomem *ioaddr = lp->base;
689 u16 status;
7a47dd7a
SW		 690
691 /* Mask off RDC MAC interrupt */
692 iowrite16(MSK_INT, ioaddr + MIER);
693 /* Read MISR status and clear */
694 status = ioread16(ioaddr + MISR);
695
696 if (status == 0x0000 || status == 0xffff)
697 return IRQ_NONE;
698
699 /* RX interrupt request */
700 if (status & 0x01) {
3d254348
FF		 701 /* Mask off RX interrupt */
702 iowrite16(ioread16(ioaddr + MIER) & ~RX_INT, ioaddr + MIER);
7a47dd7a 703 netif_rx_schedule(dev, &lp->napi);
7a47dd7a
SW		 704 }
705
706 /* TX interrupt request */
707 if (status & 0x10)
708 r6040_tx(dev);
709
ec6d2d45 710 return IRQ_HANDLED;
7a47dd7a
SW		 711}
712
713#ifdef CONFIG_NET_POLL_CONTROLLER
714static void r6040_poll_controller(struct net_device *dev)
715{
716 disable_irq(dev->irq);
5ac5d616 717 r6040_interrupt(dev->irq, dev);
7a47dd7a
SW		 718 enable_irq(dev->irq);
719}
720#endif
721
7a47dd7a 722/* Init RDC MAC */
3d463419 723static int r6040_up(struct net_device *dev)
7a47dd7a
SW		 724{
725 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a 726 void __iomem *ioaddr = lp->base;
3d463419 727 int ret;
7a47dd7a 728
b4f1255d 729 /* Initialise and alloc RX/TX buffers */
3d463419
FF		 730 r6040_init_txbufs(dev);
731 ret = r6040_alloc_rxbufs(dev);
732 if (ret)
733 return ret;
7a47dd7a 734
7a47dd7a 735 /* Read the PHY ID */
c6e69bb9 736 lp->switch_sig = r6040_phy_read(ioaddr, 0, 2);
7a47dd7a
SW		 737
738 if (lp->switch_sig == ICPLUS_PHY_ID) {
c6e69bb9 739 r6040_phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
7a47dd7a
SW		 740 lp->phy_mode = 0x8000;
741 } else {
742 /* PHY Mode Check */
c6e69bb9
FF		 743 r6040_phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
744 r6040_phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
7a47dd7a
SW		 745
746 if (PHY_MODE == 0x3100)
c6e69bb9 747 lp->phy_mode = r6040_phy_mode_chk(dev);
7a47dd7a
SW		 748 else
749 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
750 }
7a47dd7a 751
fec3a23b 752 /* Set duplex mode */
7a47dd7a 753 lp->mcr0 |= lp->phy_mode;
7a47dd7a
SW		 754
755 /* improve performance (by RDC guys) */
c6e69bb9
FF		 756 r6040_phy_write(ioaddr, 30, 17, (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
757 r6040_phy_write(ioaddr, 30, 17, ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
758 r6040_phy_write(ioaddr, 0, 19, 0x0000);
759 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
7a47dd7a 760
fec3a23b
FF		 761 /* Initialize all MAC registers */
762 r6040_init_mac_regs(dev);
3d463419
FF		 763
764 return 0;
7a47dd7a
SW		 765}
766
767/*
768 A periodic timer routine
769 Polling PHY Chip Link Status
770*/
771static void r6040_timer(unsigned long data)
772{
773 struct net_device *dev = (struct net_device *)data;
e6a9ea10 774 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a
SW		 775 void __iomem *ioaddr = lp->base;
776 u16 phy_mode;
777
778 /* Polling PHY Chip Status */
779 if (PHY_MODE == 0x3100)
c6e69bb9 780 phy_mode = r6040_phy_mode_chk(dev);
7a47dd7a
SW		 781 else
782 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
783
784 if (phy_mode != lp->phy_mode) {
785 lp->phy_mode = phy_mode;
786 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
787 iowrite16(lp->mcr0, ioaddr);
788 printk(KERN_INFO "Link Change %x \n", ioread16(ioaddr));
789 }
790
791 /* Timer active again */
208aefa2 792 mod_timer(&lp->timer, round_jiffies(jiffies + HZ));
7a47dd7a
SW		 793}
794
795/* Read/set MAC address routines */
796static void r6040_mac_address(struct net_device *dev)
797{
798 struct r6040_private *lp = netdev_priv(dev);
799 void __iomem *ioaddr = lp->base;
800 u16 *adrp;
801
802 /* MAC operation register */
803 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
804 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
805 iowrite16(0, ioaddr + MAC_SM);
806 udelay(5000);
807
808 /* Restore MAC Address */
809 adrp = (u16 *) dev->dev_addr;
810 iowrite16(adrp[0], ioaddr + MID_0L);
811 iowrite16(adrp[1], ioaddr + MID_0M);
812 iowrite16(adrp[2], ioaddr + MID_0H);
813}
814
5ac5d616 815static int r6040_open(struct net_device *dev)
7a47dd7a 816{
5ac5d616 817 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a
SW		 818 int ret;
819
820 /* Request IRQ and Register interrupt handler */
821 ret = request_irq(dev->irq, &r6040_interrupt,
822 IRQF_SHARED, dev->name, dev);
823 if (ret)
824 return ret;
825
826 /* Set MAC address */
827 r6040_mac_address(dev);
828
829 /* Allocate Descriptor memory */
6c323103
FR		 830 lp->rx_ring =
831 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
832 if (!lp->rx_ring)
7a47dd7a
SW		 833 return -ENOMEM;
834
6c323103
FR		 835 lp->tx_ring =
836 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
837 if (!lp->tx_ring) {
838 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
839 lp->rx_ring_dma);
840 return -ENOMEM;
841 }
842
3d463419
FF		 843 ret = r6040_up(dev);
844 if (ret) {
845 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
846 lp->tx_ring_dma);
847 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
848 lp->rx_ring_dma);
849 return ret;
850 }
7a47dd7a
SW		 851
852 napi_enable(&lp->napi);
853 netif_start_queue(dev);
854
106adf3c
FF		 855 /* set and active a timer process */
856 setup_timer(&lp->timer, r6040_timer, (unsigned long) dev);
857 if (lp->switch_sig != ICPLUS_PHY_ID)
858 mod_timer(&lp->timer, jiffies + HZ);
7a47dd7a
SW		 859 return 0;
860}
861
5ac5d616 862static int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
7a47dd7a
SW		 863{
864 struct r6040_private *lp = netdev_priv(dev);
865 struct r6040_descriptor *descptr;
866 void __iomem *ioaddr = lp->base;
867 unsigned long flags;
092427be 868 int ret = NETDEV_TX_OK;
7a47dd7a
SW		 869
870 /* Critical Section */
871 spin_lock_irqsave(&lp->lock, flags);
872
873 /* TX resource check */
874 if (!lp->tx_free_desc) {
875 spin_unlock_irqrestore(&lp->lock, flags);
092427be 876 netif_stop_queue(dev);
7a47dd7a 877 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
092427be 878 ret = NETDEV_TX_BUSY;
7a47dd7a
SW		 879 return ret;
880 }
881
882 /* Statistic Counter */
883 dev->stats.tx_packets++;
884 dev->stats.tx_bytes += skb->len;
885 /* Set TX descriptor & Transmit it */
886 lp->tx_free_desc--;
887 descptr = lp->tx_insert_ptr;
888 if (skb->len < MISR)
889 descptr->len = MISR;
890 else
891 descptr->len = skb->len;
892
893 descptr->skb_ptr = skb;
894 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
895 skb->data, skb->len, PCI_DMA_TODEVICE));
896 descptr->status = 0x8000;
897 /* Trigger the MAC to check the TX descriptor */
898 iowrite16(0x01, ioaddr + MTPR);
899 lp->tx_insert_ptr = descptr->vndescp;
900
901 /* If no tx resource, stop */
902 if (!lp->tx_free_desc)
903 netif_stop_queue(dev);
904
905 dev->trans_start = jiffies;
906 spin_unlock_irqrestore(&lp->lock, flags);
907 return ret;
908}
909
5ac5d616 910static void r6040_multicast_list(struct net_device *dev)
7a47dd7a
SW		 911{
912 struct r6040_private *lp = netdev_priv(dev);
913 void __iomem *ioaddr = lp->base;
914 u16 *adrp;
915 u16 reg;
916 unsigned long flags;
917 struct dev_mc_list *dmi = dev->mc_list;
918 int i;
919
920 /* MAC Address */
921 adrp = (u16 *)dev->dev_addr;
922 iowrite16(adrp[0], ioaddr + MID_0L);
923 iowrite16(adrp[1], ioaddr + MID_0M);
924 iowrite16(adrp[2], ioaddr + MID_0H);
925
926 /* Promiscous Mode */
927 spin_lock_irqsave(&lp->lock, flags);
928
929 /* Clear AMCP & PROM bits */
930 reg = ioread16(ioaddr) & ~0x0120;
931 if (dev->flags & IFF_PROMISC) {
932 reg |= 0x0020;
933 lp->mcr0 |= 0x0020;
934 }
935 /* Too many multicast addresses
936 * accept all traffic */
937 else if ((dev->mc_count > MCAST_MAX)
938 || (dev->flags & IFF_ALLMULTI))
939 reg |= 0x0020;
940
941 iowrite16(reg, ioaddr);
942 spin_unlock_irqrestore(&lp->lock, flags);
943
944 /* Build the hash table */
945 if (dev->mc_count > MCAST_MAX) {
946 u16 hash_table[4];
947 u32 crc;
948
949 for (i = 0; i < 4; i++)
950 hash_table[i] = 0;
951
952 for (i = 0; i < dev->mc_count; i++) {
953 char *addrs = dmi->dmi_addr;
954
955 dmi = dmi->next;
956
957 if (!(*addrs & 1))
958 continue;
959
960 crc = ether_crc_le(6, addrs);
961 crc >>= 26;
962 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
963 }
964 /* Write the index of the hash table */
965 for (i = 0; i < 4; i++)
966 iowrite16(hash_table[i] << 14, ioaddr + MCR1);
967 /* Fill the MAC hash tables with their values */
968 iowrite16(hash_table[0], ioaddr + MAR0);
969 iowrite16(hash_table[1], ioaddr + MAR1);
970 iowrite16(hash_table[2], ioaddr + MAR2);
971 iowrite16(hash_table[3], ioaddr + MAR3);
972 }
973 /* Multicast Address 1~4 case */
974 for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
975 adrp = (u16 *)dmi->dmi_addr;
976 iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
977 iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
978 iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
979 dmi = dmi->next;
980 }
981 for (i = dev->mc_count; i < MCAST_MAX; i++) {
982 iowrite16(0xffff, ioaddr + MID_0L + 8*i);
983 iowrite16(0xffff, ioaddr + MID_0M + 8*i);
984 iowrite16(0xffff, ioaddr + MID_0H + 8*i);
985 }
986}
987
988static void netdev_get_drvinfo(struct net_device *dev,
989 struct ethtool_drvinfo *info)
990{
991 struct r6040_private *rp = netdev_priv(dev);
992
993 strcpy(info->driver, DRV_NAME);
994 strcpy(info->version, DRV_VERSION);
995 strcpy(info->bus_info, pci_name(rp->pdev));
996}
997
998static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
999{
1000 struct r6040_private *rp = netdev_priv(dev);
1001 int rc;
1002
1003 spin_lock_irq(&rp->lock);
1004 rc = mii_ethtool_gset(&rp->mii_if, cmd);
092427be 1005 spin_unlock_irq(&rp->lock);
7a47dd7a
SW		 1006
1007 return rc;
1008}
1009
1010static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1011{
1012 struct r6040_private *rp = netdev_priv(dev);
1013 int rc;
1014
1015 spin_lock_irq(&rp->lock);
1016 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1017 spin_unlock_irq(&rp->lock);
1018 r6040_set_carrier(&rp->mii_if);
1019
1020 return rc;
1021}
1022
1023static u32 netdev_get_link(struct net_device *dev)
1024{
1025 struct r6040_private *rp = netdev_priv(dev);
1026
1027 return mii_link_ok(&rp->mii_if);
1028}
1029
1030static struct ethtool_ops netdev_ethtool_ops = {
1031 .get_drvinfo = netdev_get_drvinfo,
1032 .get_settings = netdev_get_settings,
1033 .set_settings = netdev_set_settings,
1034 .get_link = netdev_get_link,
1035};
1036
7a47dd7a
SW		 1037static int __devinit r6040_init_one(struct pci_dev *pdev,
1038 const struct pci_device_id *ent)
1039{
1040 struct net_device *dev;
1041 struct r6040_private *lp;
1042 void __iomem *ioaddr;
1043 int err, io_size = R6040_IO_SIZE;
1044 static int card_idx = -1;
1045 int bar = 0;
1046 long pioaddr;
1047 u16 *adrp;
1048
1049 printk(KERN_INFO "%s\n", version);
1050
1051 err = pci_enable_device(pdev);
1052 if (err)
1053 return err;
1054
1055 /* this should always be supported */
1056 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1057 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1058 "not supported by the card\n");
1059 return -ENODEV;
1060 }
092427be
JG		 1061 if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1062 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1063 "not supported by the card\n");
1064 return -ENODEV;
1065 }
7a47dd7a
SW		 1066
1067 /* IO Size check */
1068 if (pci_resource_len(pdev, 0) < io_size) {
1069 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
1070 return -EIO;
1071 }
1072
1073 pioaddr = pci_resource_start(pdev, 0); /* IO map base address */
1074 pci_set_master(pdev);
1075
1076 dev = alloc_etherdev(sizeof(struct r6040_private));
1077 if (!dev) {
1078 printk(KERN_ERR "Failed to allocate etherdev\n");
1079 return -ENOMEM;
1080 }
1081 SET_NETDEV_DEV(dev, &pdev->dev);
1082 lp = netdev_priv(dev);
1083 lp->pdev = pdev;
3d254348 1084 lp->dev = dev;
7a47dd7a
SW		 1085
1086 if (pci_request_regions(pdev, DRV_NAME)) {
1087 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
1088 err = -ENODEV;
1089 goto err_out_disable;
1090 }
1091
1092 ioaddr = pci_iomap(pdev, bar, io_size);
1093 if (!ioaddr) {
1094 printk(KERN_ERR "ioremap failed for device %s\n",
1095 pci_name(pdev));
1096 return -EIO;
1097 }
1098
1099 /* Init system & device */
7a47dd7a
SW		 1100 lp->base = ioaddr;
1101 dev->irq = pdev->irq;
1102
1103 spin_lock_init(&lp->lock);
1104 pci_set_drvdata(pdev, dev);
1105
1106 /* Set MAC address */
1107 card_idx++;
1108
1109 adrp = (u16 *)dev->dev_addr;
1110 adrp[0] = ioread16(ioaddr + MID_0L);
1111 adrp[1] = ioread16(ioaddr + MID_0M);
1112 adrp[2] = ioread16(ioaddr + MID_0H);
1113
1114 /* Link new device into r6040_root_dev */
1115 lp->pdev = pdev;
1116
1117 /* Init RDC private data */
1118 lp->mcr0 = 0x1002;
1119 lp->phy_addr = phy_table[card_idx];
1120 lp->switch_sig = 0;
1121
1122 /* The RDC-specific entries in the device structure. */
1123 dev->open = &r6040_open;
1124 dev->hard_start_xmit = &r6040_start_xmit;
1125 dev->stop = &r6040_close;
1126 dev->get_stats = r6040_get_stats;
1127 dev->set_multicast_list = &r6040_multicast_list;
1128 dev->do_ioctl = &r6040_ioctl;
1129 dev->ethtool_ops = &netdev_ethtool_ops;
1130 dev->tx_timeout = &r6040_tx_timeout;
1131 dev->watchdog_timeo = TX_TIMEOUT;
1132#ifdef CONFIG_NET_POLL_CONTROLLER
1133 dev->poll_controller = r6040_poll_controller;
1134#endif
1135 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1136 lp->mii_if.dev = dev;
c6e69bb9
FF		 1137 lp->mii_if.mdio_read = r6040_mdio_read;
1138 lp->mii_if.mdio_write = r6040_mdio_write;
7a47dd7a
SW		 1139 lp->mii_if.phy_id = lp->phy_addr;
1140 lp->mii_if.phy_id_mask = 0x1f;
1141 lp->mii_if.reg_num_mask = 0x1f;
1142
1143 /* Register net device. After this dev->name assign */
1144 err = register_netdev(dev);
1145 if (err) {
1146 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
1147 goto err_out_res;
1148 }
1149 return 0;
1150
1151err_out_res:
1152 pci_release_regions(pdev);
1153err_out_disable:
1154 pci_disable_device(pdev);
1155 pci_set_drvdata(pdev, NULL);
1156 free_netdev(dev);
1157
1158 return err;
1159}
1160
1161static void __devexit r6040_remove_one(struct pci_dev *pdev)
1162{
1163 struct net_device *dev = pci_get_drvdata(pdev);
1164
1165 unregister_netdev(dev);
1166 pci_release_regions(pdev);
1167 free_netdev(dev);
1168 pci_disable_device(pdev);
1169 pci_set_drvdata(pdev, NULL);
1170}
1171
1172
1173static struct pci_device_id r6040_pci_tbl[] = {
5ac5d616
FR		 1174 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1175 { 0 }
7a47dd7a
SW		 1176};
1177MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1178
1179static struct pci_driver r6040_driver = {
5ac5d616 1180 .name = DRV_NAME,
7a47dd7a
SW		 1181 .id_table = r6040_pci_tbl,
1182 .probe = r6040_init_one,
1183 .remove = __devexit_p(r6040_remove_one),
1184};
1185
1186
1187static int __init r6040_init(void)
1188{
1189 return pci_register_driver(&r6040_driver);
1190}
1191
1192
1193static void __exit r6040_cleanup(void)
1194{
1195 pci_unregister_driver(&r6040_driver);
1196}
1197
1198module_init(r6040_init);
1199module_exit(r6040_cleanup);
Linux kernel - Deliverables
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