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ipsec: update MAX_AH_AUTH_LEN to support sha512
[deliverable/linux.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
1da177e4 28
99f252b0 29#include <asm/system.h>
1da177e4
LT		 30#include <asm/io.h>
31#include <asm/irq.h>
32
865c652d 33#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 34#define MODULENAME "r8169"
35#define PFX MODULENAME ": "
36
bca03d5f 37#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
39
1da177e4
LT		 40#ifdef RTL8169_DEBUG
41#define assert(expr) \
5b0384f4
FR		 42 if (!(expr)) { \
43 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 44 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 45 }
06fa7358
JP		 46#define dprintk(fmt, args...) \
47 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 48#else
49#define assert(expr) do {} while (0)
50#define dprintk(fmt, args...) do {} while (0)
51#endif /* RTL8169_DEBUG */
52
b57b7e5a 53#define R8169_MSG_DEFAULT \
f0e837d9 54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 55
1da177e4
LT		 56#define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
58
1da177e4
LT		 59/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 61static const int multicast_filter_limit = 32;
1da177e4
LT		 62
63/* MAC address length */
64#define MAC_ADDR_LEN 6
65
9c14ceaf 66#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 67#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
68#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
69#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 70#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73#define R8169_REGS_SIZE 256
74#define R8169_NAPI_WEIGHT 64
75#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77#define RX_BUF_SIZE 1536 /* Rx Buffer size */
78#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81#define RTL8169_TX_TIMEOUT (6*HZ)
82#define RTL8169_PHY_TIMEOUT (10*HZ)
83
ea8dbdd1 84#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
85#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 86#define RTL_EEPROM_SIG_ADDR 0x0000
87
1da177e4
LT		 88/* write/read MMIO register */
89#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92#define RTL_R8(reg) readb (ioaddr + (reg))
93#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 94#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 95
96enum mac_version {
f21b75e9 97 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 98 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
99 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
100 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
101 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
102 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 103 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 104 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
105 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
106 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
107 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 108 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 109 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
110 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
111 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
112 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
113 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
114 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
115 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
116 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 117 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 118 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 119 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 120 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 121 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 122 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
123 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
e6de30d6 124 RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
125 RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
1da177e4
LT		 126};
127
1da177e4
LT		 128#define _R(NAME,MAC,MASK) \
129 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
130
3c6bee1d 131static const struct {
1da177e4
LT		 132 const char *name;
133 u8 mac_version;
134 u32 RxConfigMask; /* Clears the bits supported by this chip */
135} rtl_chip_info[] = {
ba6eb6ee
FR		 136 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
137 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
138 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
139 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
140 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 141 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 142 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
143 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
144 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
149 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 150 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
151 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
152 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
154 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 155 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 156 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 157 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 158 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9 159 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
daf9df6d 160 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
161 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
e6de30d6 162 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
163 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880) // PCI-E
1da177e4
LT		 164};
165#undef _R
166
bcf0bf90
FR		 167enum cfg_version {
168 RTL_CFG_0 = 0x00,
169 RTL_CFG_1,
170 RTL_CFG_2
171};
172
07ce4064
FR		 173static void rtl_hw_start_8169(struct net_device *);
174static void rtl_hw_start_8168(struct net_device *);
175static void rtl_hw_start_8101(struct net_device *);
176
a3aa1884 177static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 178 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 179 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 180 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 181 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 182 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
183 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 184 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 185 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
186 { PCI_VENDOR_ID_LINKSYS, 0x1032,
187 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 188 { 0x0001, 0x8168,
189 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 190 {0,},
191};
192
193MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
194
6f0333b8 195static int rx_buf_sz = 16383;
4300e8c7 196static int use_dac;
b57b7e5a
SH		 197static struct {
198 u32 msg_enable;
199} debug = { -1 };
1da177e4 200
07d3f51f
FR		 201enum rtl_registers {
202 MAC0 = 0, /* Ethernet hardware address. */
773d2021 203 MAC4 = 4,
07d3f51f
FR		 204 MAR0 = 8, /* Multicast filter. */
205 CounterAddrLow = 0x10,
206 CounterAddrHigh = 0x14,
207 TxDescStartAddrLow = 0x20,
208 TxDescStartAddrHigh = 0x24,
209 TxHDescStartAddrLow = 0x28,
210 TxHDescStartAddrHigh = 0x2c,
211 FLASH = 0x30,
212 ERSR = 0x36,
213 ChipCmd = 0x37,
214 TxPoll = 0x38,
215 IntrMask = 0x3c,
216 IntrStatus = 0x3e,
217 TxConfig = 0x40,
218 RxConfig = 0x44,
219 RxMissed = 0x4c,
220 Cfg9346 = 0x50,
221 Config0 = 0x51,
222 Config1 = 0x52,
223 Config2 = 0x53,
224 Config3 = 0x54,
225 Config4 = 0x55,
226 Config5 = 0x56,
227 MultiIntr = 0x5c,
228 PHYAR = 0x60,
07d3f51f
FR		 229 PHYstatus = 0x6c,
230 RxMaxSize = 0xda,
231 CPlusCmd = 0xe0,
232 IntrMitigate = 0xe2,
233 RxDescAddrLow = 0xe4,
234 RxDescAddrHigh = 0xe8,
f0298f81 235 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
236
237#define NoEarlyTx 0x3f /* Max value : no early transmit. */
238
239 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
240
241#define TxPacketMax (8064 >> 7)
242
07d3f51f
FR		 243 FuncEvent = 0xf0,
244 FuncEventMask = 0xf4,
245 FuncPresetState = 0xf8,
246 FuncForceEvent = 0xfc,
1da177e4
LT		 247};
248
f162a5d1
FR		 249enum rtl8110_registers {
250 TBICSR = 0x64,
251 TBI_ANAR = 0x68,
252 TBI_LPAR = 0x6a,
253};
254
255enum rtl8168_8101_registers {
256 CSIDR = 0x64,
257 CSIAR = 0x68,
258#define CSIAR_FLAG 0x80000000
259#define CSIAR_WRITE_CMD 0x80000000
260#define CSIAR_BYTE_ENABLE 0x0f
261#define CSIAR_BYTE_ENABLE_SHIFT 12
262#define CSIAR_ADDR_MASK 0x0fff
065c27c1 263 PMCH = 0x6f,
f162a5d1
FR		 264 EPHYAR = 0x80,
265#define EPHYAR_FLAG 0x80000000
266#define EPHYAR_WRITE_CMD 0x80000000
267#define EPHYAR_REG_MASK 0x1f
268#define EPHYAR_REG_SHIFT 16
269#define EPHYAR_DATA_MASK 0xffff
270 DBG_REG = 0xd1,
271#define FIX_NAK_1 (1 << 4)
272#define FIX_NAK_2 (1 << 3)
daf9df6d 273 EFUSEAR = 0xdc,
274#define EFUSEAR_FLAG 0x80000000
275#define EFUSEAR_WRITE_CMD 0x80000000
276#define EFUSEAR_READ_CMD 0x00000000
277#define EFUSEAR_REG_MASK 0x03ff
278#define EFUSEAR_REG_SHIFT 8
279#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 280};
281
c0e45c1c 282enum rtl8168_registers {
b646d900 283 ERIDR = 0x70,
284 ERIAR = 0x74,
285#define ERIAR_FLAG 0x80000000
286#define ERIAR_WRITE_CMD 0x80000000
287#define ERIAR_READ_CMD 0x00000000
288#define ERIAR_ADDR_BYTE_ALIGN 4
289#define ERIAR_EXGMAC 0
290#define ERIAR_MSIX 1
291#define ERIAR_ASF 2
292#define ERIAR_TYPE_SHIFT 16
293#define ERIAR_BYTEEN 0x0f
294#define ERIAR_BYTEEN_SHIFT 12
c0e45c1c 295 EPHY_RXER_NUM = 0x7c,
296 OCPDR = 0xb0, /* OCP GPHY access */
297#define OCPDR_WRITE_CMD 0x80000000
298#define OCPDR_READ_CMD 0x00000000
299#define OCPDR_REG_MASK 0x7f
300#define OCPDR_GPHY_REG_SHIFT 16
301#define OCPDR_DATA_MASK 0xffff
302 OCPAR = 0xb4,
303#define OCPAR_FLAG 0x80000000
304#define OCPAR_GPHY_WRITE_CMD 0x8000f060
305#define OCPAR_GPHY_READ_CMD 0x0000f060
e6de30d6 306 RDSAR1 = 0xd0 /* 8168c only. Undocumented on 8168dp */
c0e45c1c 307};
308
07d3f51f 309enum rtl_register_content {
1da177e4 310 /* InterruptStatusBits */
07d3f51f
FR		 311 SYSErr = 0x8000,
312 PCSTimeout = 0x4000,
313 SWInt = 0x0100,
314 TxDescUnavail = 0x0080,
315 RxFIFOOver = 0x0040,
316 LinkChg = 0x0020,
317 RxOverflow = 0x0010,
318 TxErr = 0x0008,
319 TxOK = 0x0004,
320 RxErr = 0x0002,
321 RxOK = 0x0001,
1da177e4
LT		 322
323 /* RxStatusDesc */
9dccf611
FR		 324 RxFOVF = (1 << 23),
325 RxRWT = (1 << 22),
326 RxRES = (1 << 21),
327 RxRUNT = (1 << 20),
328 RxCRC = (1 << 19),
1da177e4
LT		 329
330 /* ChipCmdBits */
07d3f51f
FR		 331 CmdReset = 0x10,
332 CmdRxEnb = 0x08,
333 CmdTxEnb = 0x04,
334 RxBufEmpty = 0x01,
1da177e4 335
275391a4
FR		 336 /* TXPoll register p.5 */
337 HPQ = 0x80, /* Poll cmd on the high prio queue */
338 NPQ = 0x40, /* Poll cmd on the low prio queue */
339 FSWInt = 0x01, /* Forced software interrupt */
340
1da177e4 341 /* Cfg9346Bits */
07d3f51f
FR		 342 Cfg9346_Lock = 0x00,
343 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 344
345 /* rx_mode_bits */
07d3f51f
FR		 346 AcceptErr = 0x20,
347 AcceptRunt = 0x10,
348 AcceptBroadcast = 0x08,
349 AcceptMulticast = 0x04,
350 AcceptMyPhys = 0x02,
351 AcceptAllPhys = 0x01,
1da177e4
LT		 352
353 /* RxConfigBits */
07d3f51f
FR		 354 RxCfgFIFOShift = 13,
355 RxCfgDMAShift = 8,
1da177e4
LT		 356
357 /* TxConfigBits */
358 TxInterFrameGapShift = 24,
359 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
360
5d06a99f 361 /* Config1 register p.24 */
f162a5d1
FR		 362 LEDS1 = (1 << 7),
363 LEDS0 = (1 << 6),
fbac58fc 364 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 365 Speed_down = (1 << 4),
366 MEMMAP = (1 << 3),
367 IOMAP = (1 << 2),
368 VPD = (1 << 1),
5d06a99f
FR		 369 PMEnable = (1 << 0), /* Power Management Enable */
370
6dccd16b
FR		 371 /* Config2 register p. 25 */
372 PCI_Clock_66MHz = 0x01,
373 PCI_Clock_33MHz = 0x00,
374
61a4dcc2
FR		 375 /* Config3 register p.25 */
376 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
377 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 378 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 379
5d06a99f 380 /* Config5 register p.27 */
61a4dcc2
FR		 381 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
382 MWF = (1 << 5), /* Accept Multicast wakeup frame */
383 UWF = (1 << 4), /* Accept Unicast wakeup frame */
384 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 385 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
386
1da177e4
LT		 387 /* TBICSR p.28 */
388 TBIReset = 0x80000000,
389 TBILoopback = 0x40000000,
390 TBINwEnable = 0x20000000,
391 TBINwRestart = 0x10000000,
392 TBILinkOk = 0x02000000,
393 TBINwComplete = 0x01000000,
394
395 /* CPlusCmd p.31 */
f162a5d1
FR		 396 EnableBist = (1 << 15), // 8168 8101
397 Mac_dbgo_oe = (1 << 14), // 8168 8101
398 Normal_mode = (1 << 13), // unused
399 Force_half_dup = (1 << 12), // 8168 8101
400 Force_rxflow_en = (1 << 11), // 8168 8101
401 Force_txflow_en = (1 << 10), // 8168 8101
402 Cxpl_dbg_sel = (1 << 9), // 8168 8101
403 ASF = (1 << 8), // 8168 8101
404 PktCntrDisable = (1 << 7), // 8168 8101
405 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 406 RxVlan = (1 << 6),
407 RxChkSum = (1 << 5),
408 PCIDAC = (1 << 4),
409 PCIMulRW = (1 << 3),
0e485150
FR		 410 INTT_0 = 0x0000, // 8168
411 INTT_1 = 0x0001, // 8168
412 INTT_2 = 0x0002, // 8168
413 INTT_3 = 0x0003, // 8168
1da177e4
LT		 414
415 /* rtl8169_PHYstatus */
07d3f51f
FR		 416 TBI_Enable = 0x80,
417 TxFlowCtrl = 0x40,
418 RxFlowCtrl = 0x20,
419 _1000bpsF = 0x10,
420 _100bps = 0x08,
421 _10bps = 0x04,
422 LinkStatus = 0x02,
423 FullDup = 0x01,
1da177e4 424
1da177e4 425 /* _TBICSRBit */
07d3f51f 426 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 427
428 /* DumpCounterCommand */
07d3f51f 429 CounterDump = 0x8,
1da177e4
LT		 430};
431
07d3f51f 432enum desc_status_bit {
1da177e4
LT		 433 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
434 RingEnd = (1 << 30), /* End of descriptor ring */
435 FirstFrag = (1 << 29), /* First segment of a packet */
436 LastFrag = (1 << 28), /* Final segment of a packet */
437
438 /* Tx private */
439 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
440 MSSShift = 16, /* MSS value position */
441 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
442 IPCS = (1 << 18), /* Calculate IP checksum */
443 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
444 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
445 TxVlanTag = (1 << 17), /* Add VLAN tag */
446
447 /* Rx private */
448 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
449 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
450
451#define RxProtoUDP (PID1)
452#define RxProtoTCP (PID0)
453#define RxProtoIP (PID1 | PID0)
454#define RxProtoMask RxProtoIP
455
456 IPFail = (1 << 16), /* IP checksum failed */
457 UDPFail = (1 << 15), /* UDP/IP checksum failed */
458 TCPFail = (1 << 14), /* TCP/IP checksum failed */
459 RxVlanTag = (1 << 16), /* VLAN tag available */
460};
461
462#define RsvdMask 0x3fffc000
463
464struct TxDesc {
6cccd6e7
REB		 465 __le32 opts1;
466 __le32 opts2;
467 __le64 addr;
1da177e4
LT		 468};
469
470struct RxDesc {
6cccd6e7
REB		 471 __le32 opts1;
472 __le32 opts2;
473 __le64 addr;
1da177e4
LT		 474};
475
476struct ring_info {
477 struct sk_buff *skb;
478 u32 len;
479 u8 __pad[sizeof(void *) - sizeof(u32)];
480};
481
f23e7fda 482enum features {
ccdffb9a
FR		 483 RTL_FEATURE_WOL = (1 << 0),
484 RTL_FEATURE_MSI = (1 << 1),
485 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 486};
487
355423d0
IV		 488struct rtl8169_counters {
489 __le64 tx_packets;
490 __le64 rx_packets;
491 __le64 tx_errors;
492 __le32 rx_errors;
493 __le16 rx_missed;
494 __le16 align_errors;
495 __le32 tx_one_collision;
496 __le32 tx_multi_collision;
497 __le64 rx_unicast;
498 __le64 rx_broadcast;
499 __le32 rx_multicast;
500 __le16 tx_aborted;
501 __le16 tx_underun;
502};
503
1da177e4
LT		 504struct rtl8169_private {
505 void __iomem *mmio_addr; /* memory map physical address */
506 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 507 struct net_device *dev;
bea3348e 508 struct napi_struct napi;
1da177e4 509 spinlock_t lock; /* spin lock flag */
b57b7e5a 510 u32 msg_enable;
1da177e4
LT		 511 int chipset;
512 int mac_version;
1da177e4
LT		 513 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
514 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
515 u32 dirty_rx;
516 u32 dirty_tx;
517 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
518 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
519 dma_addr_t TxPhyAddr;
520 dma_addr_t RxPhyAddr;
6f0333b8 521 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 522 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 523 struct timer_list timer;
524 u16 cp_cmd;
0e485150
FR		 525 u16 intr_event;
526 u16 napi_event;
1da177e4 527 u16 intr_mask;
1da177e4
LT		 528 int phy_1000_ctrl_reg;
529#ifdef CONFIG_R8169_VLAN
530 struct vlan_group *vlgrp;
531#endif
c0e45c1c 532
533 struct mdio_ops {
534 void (*write)(void __iomem *, int, int);
535 int (*read)(void __iomem *, int);
536 } mdio_ops;
537
065c27c1 538 struct pll_power_ops {
539 void (*down)(struct rtl8169_private *);
540 void (*up)(struct rtl8169_private *);
541 } pll_power_ops;
542
1da177e4 543 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 544 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 545 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 546 void (*hw_start)(struct net_device *);
4da19633 547 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 548 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 549 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 550 int pcie_cap;
c4028958 551 struct delayed_work task;
f23e7fda 552 unsigned features;
ccdffb9a
FR		 553
554 struct mii_if_info mii;
355423d0 555 struct rtl8169_counters counters;
e1759441 556 u32 saved_wolopts;
1da177e4
LT		 557};
558
979b6c13 559MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 560MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 561module_param(use_dac, int, 0);
4300e8c7 562MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 563module_param_named(debug, debug.msg_enable, int, 0);
564MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 565MODULE_LICENSE("GPL");
566MODULE_VERSION(RTL8169_VERSION);
bca03d5f 567MODULE_FIRMWARE(FIRMWARE_8168D_1);
568MODULE_FIRMWARE(FIRMWARE_8168D_2);
1da177e4
LT		 569
570static int rtl8169_open(struct net_device *dev);
61357325
SH		 571static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
572 struct net_device *dev);
7d12e780 573static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 574static int rtl8169_init_ring(struct net_device *dev);
07ce4064 575static void rtl_hw_start(struct net_device *dev);
1da177e4 576static int rtl8169_close(struct net_device *dev);
07ce4064 577static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 578static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 579static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 580static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 581 void __iomem *, u32 budget);
4dcb7d33 582static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 583static void rtl8169_down(struct net_device *dev);
99f252b0 584static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 585static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 586
1da177e4 587static const unsigned int rtl8169_rx_config =
5b0384f4 588 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 589
b646d900 590static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
591{
592 void __iomem *ioaddr = tp->mmio_addr;
593 int i;
594
595 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
596 for (i = 0; i < 20; i++) {
597 udelay(100);
598 if (RTL_R32(OCPAR) & OCPAR_FLAG)
599 break;
600 }
601 return RTL_R32(OCPDR);
602}
603
604static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
605{
606 void __iomem *ioaddr = tp->mmio_addr;
607 int i;
608
609 RTL_W32(OCPDR, data);
610 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
611 for (i = 0; i < 20; i++) {
612 udelay(100);
613 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
614 break;
615 }
616}
617
618static void rtl8168_oob_notify(void __iomem *ioaddr, u8 cmd)
619{
620 int i;
621
622 RTL_W8(ERIDR, cmd);
623 RTL_W32(ERIAR, 0x800010e8);
624 msleep(2);
625 for (i = 0; i < 5; i++) {
626 udelay(100);
627 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
628 break;
629 }
630
631 ocp_write(ioaddr, 0x1, 0x30, 0x00000001);
632}
633
634#define OOB_CMD_RESET 0x00
635#define OOB_CMD_DRIVER_START 0x05
636#define OOB_CMD_DRIVER_STOP 0x06
637
638static void rtl8168_driver_start(struct rtl8169_private *tp)
639{
640 int i;
641
642 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
643
644 for (i = 0; i < 10; i++) {
645 msleep(10);
646 if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
647 break;
648 }
649}
650
651static void rtl8168_driver_stop(struct rtl8169_private *tp)
652{
653 int i;
654
655 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
656
657 for (i = 0; i < 10; i++) {
658 msleep(10);
659 if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
660 break;
661 }
662}
663
664
4da19633 665static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 666{
667 int i;
668
a6baf3af 669 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 670
2371408c 671 for (i = 20; i > 0; i--) {
07d3f51f
FR		 672 /*
673 * Check if the RTL8169 has completed writing to the specified
674 * MII register.
675 */
5b0384f4 676 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 677 break;
2371408c 678 udelay(25);
1da177e4 679 }
024a07ba 680 /*
81a95f04
TT		 681 * According to hardware specs a 20us delay is required after write
682 * complete indication, but before sending next command.
024a07ba 683 */
81a95f04 684 udelay(20);
1da177e4
LT		 685}
686
4da19633 687static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 688{
689 int i, value = -1;
690
a6baf3af 691 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 692
2371408c 693 for (i = 20; i > 0; i--) {
07d3f51f
FR		 694 /*
695 * Check if the RTL8169 has completed retrieving data from
696 * the specified MII register.
697 */
1da177e4 698 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 699 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 700 break;
701 }
2371408c 702 udelay(25);
1da177e4 703 }
81a95f04
TT		 704 /*
705 * According to hardware specs a 20us delay is required after read
706 * complete indication, but before sending next command.
707 */
708 udelay(20);
709
1da177e4
LT		 710 return value;
711}
712
c0e45c1c 713static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
714{
715 int i;
716
717 RTL_W32(OCPDR, data |
718 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
719 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
720 RTL_W32(EPHY_RXER_NUM, 0);
721
722 for (i = 0; i < 100; i++) {
723 mdelay(1);
724 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
725 break;
726 }
727}
728
729static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
730{
731 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
732 (value & OCPDR_DATA_MASK));
733}
734
735static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
736{
737 int i;
738
739 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
740
741 mdelay(1);
742 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
743 RTL_W32(EPHY_RXER_NUM, 0);
744
745 for (i = 0; i < 100; i++) {
746 mdelay(1);
747 if (RTL_R32(OCPAR) & OCPAR_FLAG)
748 break;
749 }
750
751 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
752}
753
e6de30d6 754#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
755
756static void r8168dp_2_mdio_start(void __iomem *ioaddr)
757{
758 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
759}
760
761static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
762{
763 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
764}
765
766static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
767{
768 r8168dp_2_mdio_start(ioaddr);
769
770 r8169_mdio_write(ioaddr, reg_addr, value);
771
772 r8168dp_2_mdio_stop(ioaddr);
773}
774
775static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
776{
777 int value;
778
779 r8168dp_2_mdio_start(ioaddr);
780
781 value = r8169_mdio_read(ioaddr, reg_addr);
782
783 r8168dp_2_mdio_stop(ioaddr);
784
785 return value;
786}
787
4da19633 788static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 789{
c0e45c1c 790 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 791}
792
4da19633 793static int rtl_readphy(struct rtl8169_private *tp, int location)
794{
c0e45c1c 795 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 796}
797
798static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
799{
800 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
801}
802
803static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 804{
805 int val;
806
4da19633 807 val = rtl_readphy(tp, reg_addr);
808 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 809}
810
ccdffb9a
FR		 811static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
812 int val)
813{
814 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 815
4da19633 816 rtl_writephy(tp, location, val);
ccdffb9a
FR		 817}
818
819static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
820{
821 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 822
4da19633 823 return rtl_readphy(tp, location);
ccdffb9a
FR		 824}
825
dacf8154
FR		 826static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
827{
828 unsigned int i;
829
830 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
831 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
832
833 for (i = 0; i < 100; i++) {
834 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
835 break;
836 udelay(10);
837 }
838}
839
840static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
841{
842 u16 value = 0xffff;
843 unsigned int i;
844
845 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
846
847 for (i = 0; i < 100; i++) {
848 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
849 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
850 break;
851 }
852 udelay(10);
853 }
854
855 return value;
856}
857
858static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
859{
860 unsigned int i;
861
862 RTL_W32(CSIDR, value);
863 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
864 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
865
866 for (i = 0; i < 100; i++) {
867 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
868 break;
869 udelay(10);
870 }
871}
872
873static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
874{
875 u32 value = ~0x00;
876 unsigned int i;
877
878 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
879 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
880
881 for (i = 0; i < 100; i++) {
882 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
883 value = RTL_R32(CSIDR);
884 break;
885 }
886 udelay(10);
887 }
888
889 return value;
890}
891
daf9df6d 892static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
893{
894 u8 value = 0xff;
895 unsigned int i;
896
897 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
898
899 for (i = 0; i < 300; i++) {
900 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
901 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
902 break;
903 }
904 udelay(100);
905 }
906
907 return value;
908}
909
1da177e4
LT		 910static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
911{
912 RTL_W16(IntrMask, 0x0000);
913
914 RTL_W16(IntrStatus, 0xffff);
915}
916
917static void rtl8169_asic_down(void __iomem *ioaddr)
918{
919 RTL_W8(ChipCmd, 0x00);
920 rtl8169_irq_mask_and_ack(ioaddr);
921 RTL_R16(CPlusCmd);
922}
923
4da19633 924static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 925{
4da19633 926 void __iomem *ioaddr = tp->mmio_addr;
927
1da177e4
LT		 928 return RTL_R32(TBICSR) & TBIReset;
929}
930
4da19633 931static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 932{
4da19633 933 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 934}
935
936static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
937{
938 return RTL_R32(TBICSR) & TBILinkOk;
939}
940
941static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
942{
943 return RTL_R8(PHYstatus) & LinkStatus;
944}
945
4da19633 946static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 947{
4da19633 948 void __iomem *ioaddr = tp->mmio_addr;
949
1da177e4
LT		 950 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
951}
952
4da19633 953static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 954{
955 unsigned int val;
956
4da19633 957 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
958 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 959}
960
e4fbce74 961static void __rtl8169_check_link_status(struct net_device *dev,
07d3f51f 962 struct rtl8169_private *tp,
e4fbce74
RW		 963 void __iomem *ioaddr,
964 bool pm)
1da177e4
LT		 965{
966 unsigned long flags;
967
968 spin_lock_irqsave(&tp->lock, flags);
969 if (tp->link_ok(ioaddr)) {
e1759441 970 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 971 if (pm)
972 pm_request_resume(&tp->pci_dev->dev);
1da177e4 973 netif_carrier_on(dev);
bf82c189 974 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 975 } else {
1da177e4 976 netif_carrier_off(dev);
bf82c189 977 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 978 if (pm)
979 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 980 }
1da177e4
LT		 981 spin_unlock_irqrestore(&tp->lock, flags);
982}
983
e4fbce74
RW		 984static void rtl8169_check_link_status(struct net_device *dev,
985 struct rtl8169_private *tp,
986 void __iomem *ioaddr)
987{
988 __rtl8169_check_link_status(dev, tp, ioaddr, false);
989}
990
e1759441
RW		 991#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
992
993static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 994{
61a4dcc2
FR		 995 void __iomem *ioaddr = tp->mmio_addr;
996 u8 options;
e1759441 997 u32 wolopts = 0;
61a4dcc2
FR		 998
999 options = RTL_R8(Config1);
1000 if (!(options & PMEnable))
e1759441 1001 return 0;
61a4dcc2
FR		 1002
1003 options = RTL_R8(Config3);
1004 if (options & LinkUp)
e1759441 1005 wolopts |= WAKE_PHY;
61a4dcc2 1006 if (options & MagicPacket)
e1759441 1007 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1008
1009 options = RTL_R8(Config5);
1010 if (options & UWF)
e1759441 1011 wolopts |= WAKE_UCAST;
61a4dcc2 1012 if (options & BWF)
e1759441 1013 wolopts |= WAKE_BCAST;
61a4dcc2 1014 if (options & MWF)
e1759441 1015 wolopts |= WAKE_MCAST;
61a4dcc2 1016
e1759441 1017 return wolopts;
61a4dcc2
FR		 1018}
1019
e1759441 1020static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1021{
1022 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1023
1024 spin_lock_irq(&tp->lock);
1025
1026 wol->supported = WAKE_ANY;
1027 wol->wolopts = __rtl8169_get_wol(tp);
1028
1029 spin_unlock_irq(&tp->lock);
1030}
1031
1032static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1033{
61a4dcc2 1034 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1035 unsigned int i;
350f7596 1036 static const struct {
61a4dcc2
FR		 1037 u32 opt;
1038 u16 reg;
1039 u8 mask;
1040 } cfg[] = {
1041 { WAKE_ANY, Config1, PMEnable },
1042 { WAKE_PHY, Config3, LinkUp },
1043 { WAKE_MAGIC, Config3, MagicPacket },
1044 { WAKE_UCAST, Config5, UWF },
1045 { WAKE_BCAST, Config5, BWF },
1046 { WAKE_MCAST, Config5, MWF },
1047 { WAKE_ANY, Config5, LanWake }
1048 };
1049
61a4dcc2
FR		 1050 RTL_W8(Cfg9346, Cfg9346_Unlock);
1051
1052 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1053 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1054 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1055 options |= cfg[i].mask;
1056 RTL_W8(cfg[i].reg, options);
1057 }
1058
1059 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1060}
1061
1062static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1063{
1064 struct rtl8169_private *tp = netdev_priv(dev);
1065
1066 spin_lock_irq(&tp->lock);
61a4dcc2 1067
f23e7fda
FR		 1068 if (wol->wolopts)
1069 tp->features |= RTL_FEATURE_WOL;
1070 else
1071 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1072 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1073 spin_unlock_irq(&tp->lock);
1074
ea80907f 1075 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1076
61a4dcc2
FR		 1077 return 0;
1078}
1079
1da177e4
LT		 1080static void rtl8169_get_drvinfo(struct net_device *dev,
1081 struct ethtool_drvinfo *info)
1082{
1083 struct rtl8169_private *tp = netdev_priv(dev);
1084
1085 strcpy(info->driver, MODULENAME);
1086 strcpy(info->version, RTL8169_VERSION);
1087 strcpy(info->bus_info, pci_name(tp->pci_dev));
1088}
1089
1090static int rtl8169_get_regs_len(struct net_device *dev)
1091{
1092 return R8169_REGS_SIZE;
1093}
1094
1095static int rtl8169_set_speed_tbi(struct net_device *dev,
1096 u8 autoneg, u16 speed, u8 duplex)
1097{
1098 struct rtl8169_private *tp = netdev_priv(dev);
1099 void __iomem *ioaddr = tp->mmio_addr;
1100 int ret = 0;
1101 u32 reg;
1102
1103 reg = RTL_R32(TBICSR);
1104 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1105 (duplex == DUPLEX_FULL)) {
1106 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1107 } else if (autoneg == AUTONEG_ENABLE)
1108 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1109 else {
bf82c189
JP		 1110 netif_warn(tp, link, dev,
1111 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1112 ret = -EOPNOTSUPP;
1113 }
1114
1115 return ret;
1116}
1117
1118static int rtl8169_set_speed_xmii(struct net_device *dev,
1119 u8 autoneg, u16 speed, u8 duplex)
1120{
1121 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1122 int giga_ctrl, bmcr;
1da177e4
LT		 1123
1124 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1125 int auto_nego;
1126
4da19633 1127 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
64e4bfb4
FR		 1128 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1129 ADVERTISE_100HALF | ADVERTISE_100FULL);
3577aa1b 1130 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1131
4da19633 1132 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1133 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1134
3577aa1b 1135 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1136 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1137 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1138 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1139 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1140 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1141 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1142 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1143 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
1144 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
bf82c189
JP		 1145 } else {
1146 netif_info(tp, link, dev,
1147 "PHY does not support 1000Mbps\n");
bcf0bf90 1148 }
1da177e4 1149
3577aa1b 1150 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1151
1152 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
1153 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
1154 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
1155 /*
1156 * Wake up the PHY.
1157 * Vendor specific (0x1f) and reserved (0x0e) MII
1158 * registers.
1159 */
4da19633 1160 rtl_writephy(tp, 0x1f, 0x0000);
1161 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1162 }
1163
4da19633 1164 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1165 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1166 } else {
1167 giga_ctrl = 0;
1168
1169 if (speed == SPEED_10)
1170 bmcr = 0;
1171 else if (speed == SPEED_100)
1172 bmcr = BMCR_SPEED100;
1173 else
1174 return -EINVAL;
1175
1176 if (duplex == DUPLEX_FULL)
1177 bmcr |= BMCR_FULLDPLX;
623a1593 1178
4da19633 1179 rtl_writephy(tp, 0x1f, 0x0000);
2584fbc3
RS		 1180 }
1181
1da177e4
LT		 1182 tp->phy_1000_ctrl_reg = giga_ctrl;
1183
4da19633 1184 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1185
1186 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1187 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1188 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1189 rtl_writephy(tp, 0x17, 0x2138);
1190 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1191 } else {
4da19633 1192 rtl_writephy(tp, 0x17, 0x2108);
1193 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1194 }
1195 }
1196
1da177e4
LT		 1197 return 0;
1198}
1199
1200static int rtl8169_set_speed(struct net_device *dev,
1201 u8 autoneg, u16 speed, u8 duplex)
1202{
1203 struct rtl8169_private *tp = netdev_priv(dev);
1204 int ret;
1205
1206 ret = tp->set_speed(dev, autoneg, speed, duplex);
1207
64e4bfb4 1208 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1209 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1210
1211 return ret;
1212}
1213
1214static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1215{
1216 struct rtl8169_private *tp = netdev_priv(dev);
1217 unsigned long flags;
1218 int ret;
1219
1220 spin_lock_irqsave(&tp->lock, flags);
1221 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1222 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1223
1da177e4
LT		 1224 return ret;
1225}
1226
1227static u32 rtl8169_get_rx_csum(struct net_device *dev)
1228{
1229 struct rtl8169_private *tp = netdev_priv(dev);
1230
1231 return tp->cp_cmd & RxChkSum;
1232}
1233
1234static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1235{
1236 struct rtl8169_private *tp = netdev_priv(dev);
1237 void __iomem *ioaddr = tp->mmio_addr;
1238 unsigned long flags;
1239
1240 spin_lock_irqsave(&tp->lock, flags);
1241
1242 if (data)
1243 tp->cp_cmd |= RxChkSum;
1244 else
1245 tp->cp_cmd &= ~RxChkSum;
1246
1247 RTL_W16(CPlusCmd, tp->cp_cmd);
1248 RTL_R16(CPlusCmd);
1249
1250 spin_unlock_irqrestore(&tp->lock, flags);
1251
1252 return 0;
1253}
1254
1255#ifdef CONFIG_R8169_VLAN
1256
1257static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1258 struct sk_buff *skb)
1259{
eab6d18d 1260 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1261 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1262}
1263
1264static void rtl8169_vlan_rx_register(struct net_device *dev,
1265 struct vlan_group *grp)
1266{
1267 struct rtl8169_private *tp = netdev_priv(dev);
1268 void __iomem *ioaddr = tp->mmio_addr;
1269 unsigned long flags;
1270
1271 spin_lock_irqsave(&tp->lock, flags);
1272 tp->vlgrp = grp;
05af2142
SW		 1273 /*
1274 * Do not disable RxVlan on 8110SCd.
1275 */
1276 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1da177e4
LT		 1277 tp->cp_cmd |= RxVlan;
1278 else
1279 tp->cp_cmd &= ~RxVlan;
1280 RTL_W16(CPlusCmd, tp->cp_cmd);
1281 RTL_R16(CPlusCmd);
1282 spin_unlock_irqrestore(&tp->lock, flags);
1283}
1284
1da177e4 1285static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1286 struct sk_buff *skb, int polling)
1da177e4
LT		 1287{
1288 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1289 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1290 int ret;
1291
865c652d 1292 if (vlgrp && (opts2 & RxVlanTag)) {
2edae08e
ED		 1293 u16 vtag = swab16(opts2 & 0xffff);
1294
1295 if (likely(polling))
1296 vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1297 else
1298 __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1da177e4
LT		 1299 ret = 0;
1300 } else
1301 ret = -1;
1302 desc->opts2 = 0;
1303 return ret;
1304}
1305
1306#else /* !CONFIG_R8169_VLAN */
1307
1308static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1309 struct sk_buff *skb)
1310{
1311 return 0;
1312}
1313
1314static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1315 struct sk_buff *skb, int polling)
1da177e4
LT		 1316{
1317 return -1;
1318}
1319
1320#endif
1321
ccdffb9a 1322static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1323{
1324 struct rtl8169_private *tp = netdev_priv(dev);
1325 void __iomem *ioaddr = tp->mmio_addr;
1326 u32 status;
1327
1328 cmd->supported =
1329 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1330 cmd->port = PORT_FIBRE;
1331 cmd->transceiver = XCVR_INTERNAL;
1332
1333 status = RTL_R32(TBICSR);
1334 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1335 cmd->autoneg = !!(status & TBINwEnable);
1336
1337 cmd->speed = SPEED_1000;
1338 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1339
1340 return 0;
1da177e4
LT		 1341}
1342
ccdffb9a 1343static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1344{
1345 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1346
1347 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1348}
1349
1350static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1351{
1352 struct rtl8169_private *tp = netdev_priv(dev);
1353 unsigned long flags;
ccdffb9a 1354 int rc;
1da177e4
LT		 1355
1356 spin_lock_irqsave(&tp->lock, flags);
1357
ccdffb9a 1358 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1359
1360 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1361 return rc;
1da177e4
LT		 1362}
1363
1364static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1365 void *p)
1366{
5b0384f4
FR		 1367 struct rtl8169_private *tp = netdev_priv(dev);
1368 unsigned long flags;
1da177e4 1369
5b0384f4
FR		 1370 if (regs->len > R8169_REGS_SIZE)
1371 regs->len = R8169_REGS_SIZE;
1da177e4 1372
5b0384f4
FR		 1373 spin_lock_irqsave(&tp->lock, flags);
1374 memcpy_fromio(p, tp->mmio_addr, regs->len);
1375 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1376}
1377
b57b7e5a
SH		 1378static u32 rtl8169_get_msglevel(struct net_device *dev)
1379{
1380 struct rtl8169_private *tp = netdev_priv(dev);
1381
1382 return tp->msg_enable;
1383}
1384
1385static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1386{
1387 struct rtl8169_private *tp = netdev_priv(dev);
1388
1389 tp->msg_enable = value;
1390}
1391
d4a3a0fc
SH		 1392static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1393 "tx_packets",
1394 "rx_packets",
1395 "tx_errors",
1396 "rx_errors",
1397 "rx_missed",
1398 "align_errors",
1399 "tx_single_collisions",
1400 "tx_multi_collisions",
1401 "unicast",
1402 "broadcast",
1403 "multicast",
1404 "tx_aborted",
1405 "tx_underrun",
1406};
1407
b9f2c044 1408static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1409{
b9f2c044
JG		 1410 switch (sset) {
1411 case ETH_SS_STATS:
1412 return ARRAY_SIZE(rtl8169_gstrings);
1413 default:
1414 return -EOPNOTSUPP;
1415 }
d4a3a0fc
SH		 1416}
1417
355423d0 1418static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1419{
1420 struct rtl8169_private *tp = netdev_priv(dev);
1421 void __iomem *ioaddr = tp->mmio_addr;
1422 struct rtl8169_counters *counters;
1423 dma_addr_t paddr;
1424 u32 cmd;
355423d0 1425 int wait = 1000;
48addcc9 1426 struct device *d = &tp->pci_dev->dev;
d4a3a0fc 1427
355423d0
IV		 1428 /*
1429 * Some chips are unable to dump tally counters when the receiver
1430 * is disabled.
1431 */
1432 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1433 return;
d4a3a0fc 1434
48addcc9 1435 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1436 if (!counters)
1437 return;
1438
1439 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1440 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1441 RTL_W32(CounterAddrLow, cmd);
1442 RTL_W32(CounterAddrLow, cmd | CounterDump);
1443
355423d0
IV		 1444 while (wait--) {
1445 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1446 /* copy updated counters */
1447 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1448 break;
355423d0
IV		 1449 }
1450 udelay(10);
d4a3a0fc
SH		 1451 }
1452
1453 RTL_W32(CounterAddrLow, 0);
1454 RTL_W32(CounterAddrHigh, 0);
1455
48addcc9 1456 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1457}
1458
355423d0
IV		 1459static void rtl8169_get_ethtool_stats(struct net_device *dev,
1460 struct ethtool_stats *stats, u64 *data)
1461{
1462 struct rtl8169_private *tp = netdev_priv(dev);
1463
1464 ASSERT_RTNL();
1465
1466 rtl8169_update_counters(dev);
1467
1468 data[0] = le64_to_cpu(tp->counters.tx_packets);
1469 data[1] = le64_to_cpu(tp->counters.rx_packets);
1470 data[2] = le64_to_cpu(tp->counters.tx_errors);
1471 data[3] = le32_to_cpu(tp->counters.rx_errors);
1472 data[4] = le16_to_cpu(tp->counters.rx_missed);
1473 data[5] = le16_to_cpu(tp->counters.align_errors);
1474 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1475 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1476 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1477 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1478 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1479 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1480 data[12] = le16_to_cpu(tp->counters.tx_underun);
1481}
1482
d4a3a0fc
SH		 1483static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1484{
1485 switch(stringset) {
1486 case ETH_SS_STATS:
1487 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1488 break;
1489 }
1490}
1491
7282d491 1492static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1493 .get_drvinfo = rtl8169_get_drvinfo,
1494 .get_regs_len = rtl8169_get_regs_len,
1495 .get_link = ethtool_op_get_link,
1496 .get_settings = rtl8169_get_settings,
1497 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1498 .get_msglevel = rtl8169_get_msglevel,
1499 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1500 .get_rx_csum = rtl8169_get_rx_csum,
1501 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1502 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1503 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1504 .set_tso = ethtool_op_set_tso,
1505 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1506 .get_wol = rtl8169_get_wol,
1507 .set_wol = rtl8169_set_wol,
d4a3a0fc 1508 .get_strings = rtl8169_get_strings,
b9f2c044 1509 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1510 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1511};
1512
07d3f51f
FR		 1513static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1514 void __iomem *ioaddr)
1da177e4 1515{
0e485150
FR		 1516 /*
1517 * The driver currently handles the 8168Bf and the 8168Be identically
1518 * but they can be identified more specifically through the test below
1519 * if needed:
1520 *
1521 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1522 *
1523 * Same thing for the 8101Eb and the 8101Ec:
1524 *
1525 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1526 */
350f7596 1527 static const struct {
1da177e4 1528 u32 mask;
e3cf0cc0 1529 u32 val;
1da177e4
LT		 1530 int mac_version;
1531 } mac_info[] = {
5b538df9 1532 /* 8168D family. */
daf9df6d 1533 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1534 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1535 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1536
e6de30d6 1537 /* 8168DP family. */
1538 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1539 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1540
ef808d50 1541 /* 8168C family. */
17c99297 1542 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1543 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1544 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1545 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1546 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1547 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1548 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1549 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1550 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1551
1552 /* 8168B family. */
1553 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1554 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1555 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1556 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1557
1558 /* 8101 family. */
2857ffb7
FR		 1559 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1560 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1561 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1562 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1563 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1564 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1565 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1566 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1567 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1568 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1569 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1570 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1571 /* FIXME: where did these entries come from ? -- FR */
1572 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1573 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1574
1575 /* 8110 family. */
1576 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1577 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1578 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1579 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1580 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1581 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1582
f21b75e9
JD		 1583 /* Catch-all */
1584 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1585 }, *p = mac_info;
1586 u32 reg;
1587
e3cf0cc0
FR		 1588 reg = RTL_R32(TxConfig);
1589 while ((reg & p->mask) != p->val)
1da177e4
LT		 1590 p++;
1591 tp->mac_version = p->mac_version;
1592}
1593
1594static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1595{
bcf0bf90 1596 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1597}
1598
867763c1
FR		 1599struct phy_reg {
1600 u16 reg;
1601 u16 val;
1602};
1603
4da19633 1604static void rtl_writephy_batch(struct rtl8169_private *tp,
1605 const struct phy_reg *regs, int len)
867763c1
FR		 1606{
1607 while (len-- > 0) {
4da19633 1608 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1609 regs++;
1610 }
1611}
1612
bca03d5f 1613#define PHY_READ 0x00000000
1614#define PHY_DATA_OR 0x10000000
1615#define PHY_DATA_AND 0x20000000
1616#define PHY_BJMPN 0x30000000
1617#define PHY_READ_EFUSE 0x40000000
1618#define PHY_READ_MAC_BYTE 0x50000000
1619#define PHY_WRITE_MAC_BYTE 0x60000000
1620#define PHY_CLEAR_READCOUNT 0x70000000
1621#define PHY_WRITE 0x80000000
1622#define PHY_READCOUNT_EQ_SKIP 0x90000000
1623#define PHY_COMP_EQ_SKIPN 0xa0000000
1624#define PHY_COMP_NEQ_SKIPN 0xb0000000
1625#define PHY_WRITE_PREVIOUS 0xc0000000
1626#define PHY_SKIPN 0xd0000000
1627#define PHY_DELAY_MS 0xe0000000
1628#define PHY_WRITE_ERI_WORD 0xf0000000
1629
1630static void
1631rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1632{
bca03d5f 1633 __le32 *phytable = (__le32 *)fw->data;
1634 struct net_device *dev = tp->dev;
42b82dc1 1635 size_t index, fw_size = fw->size / sizeof(*phytable);
1636 u32 predata, count;
bca03d5f 1637
1638 if (fw->size % sizeof(*phytable)) {
1639 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1640 return;
1641 }
1642
42b82dc1 1643 for (index = 0; index < fw_size; index++) {
1644 u32 action = le32_to_cpu(phytable[index]);
1645 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 1646
42b82dc1 1647 switch(action & 0xf0000000) {
1648 case PHY_READ:
1649 case PHY_DATA_OR:
1650 case PHY_DATA_AND:
1651 case PHY_READ_EFUSE:
1652 case PHY_CLEAR_READCOUNT:
1653 case PHY_WRITE:
1654 case PHY_WRITE_PREVIOUS:
1655 case PHY_DELAY_MS:
1656 break;
1657
1658 case PHY_BJMPN:
1659 if (regno > index) {
1660 netif_err(tp, probe, tp->dev,
1661 "Out of range of firmware\n");
1662 return;
1663 }
1664 break;
1665 case PHY_READCOUNT_EQ_SKIP:
1666 if (index + 2 >= fw_size) {
1667 netif_err(tp, probe, tp->dev,
1668 "Out of range of firmware\n");
1669 return;
1670 }
1671 break;
1672 case PHY_COMP_EQ_SKIPN:
1673 case PHY_COMP_NEQ_SKIPN:
1674 case PHY_SKIPN:
1675 if (index + 1 + regno >= fw_size) {
1676 netif_err(tp, probe, tp->dev,
1677 "Out of range of firmware\n");
1678 return;
1679 }
bca03d5f 1680 break;
1681
42b82dc1 1682 case PHY_READ_MAC_BYTE:
1683 case PHY_WRITE_MAC_BYTE:
1684 case PHY_WRITE_ERI_WORD:
1685 default:
1686 netif_err(tp, probe, tp->dev,
1687 "Invalid action 0x%08x\n", action);
bca03d5f 1688 return;
1689 }
1690 }
1691
42b82dc1 1692 predata = 0;
1693 count = 0;
1694
1695 for (index = 0; index < fw_size; ) {
1696 u32 action = le32_to_cpu(phytable[index]);
bca03d5f 1697 u32 data = action & 0x0000ffff;
42b82dc1 1698 u32 regno = (action & 0x0fff0000) >> 16;
1699
1700 if (!action)
1701 break;
bca03d5f 1702
1703 switch(action & 0xf0000000) {
42b82dc1 1704 case PHY_READ:
1705 predata = rtl_readphy(tp, regno);
1706 count++;
1707 index++;
1708 break;
1709 case PHY_DATA_OR:
1710 predata |= data;
1711 index++;
1712 break;
1713 case PHY_DATA_AND:
1714 predata &= data;
1715 index++;
1716 break;
1717 case PHY_BJMPN:
1718 index -= regno;
1719 break;
1720 case PHY_READ_EFUSE:
1721 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1722 index++;
1723 break;
1724 case PHY_CLEAR_READCOUNT:
1725 count = 0;
1726 index++;
1727 break;
bca03d5f 1728 case PHY_WRITE:
42b82dc1 1729 rtl_writephy(tp, regno, data);
1730 index++;
1731 break;
1732 case PHY_READCOUNT_EQ_SKIP:
1733 if (count == data)
1734 index += 2;
1735 else
1736 index += 1;
bca03d5f 1737 break;
42b82dc1 1738 case PHY_COMP_EQ_SKIPN:
1739 if (predata == data)
1740 index += regno;
1741 index++;
1742 break;
1743 case PHY_COMP_NEQ_SKIPN:
1744 if (predata != data)
1745 index += regno;
1746 index++;
1747 break;
1748 case PHY_WRITE_PREVIOUS:
1749 rtl_writephy(tp, regno, predata);
1750 index++;
1751 break;
1752 case PHY_SKIPN:
1753 index += regno + 1;
1754 break;
1755 case PHY_DELAY_MS:
1756 mdelay(data);
1757 index++;
1758 break;
1759
1760 case PHY_READ_MAC_BYTE:
1761 case PHY_WRITE_MAC_BYTE:
1762 case PHY_WRITE_ERI_WORD:
bca03d5f 1763 default:
1764 BUG();
1765 }
1766 }
1767}
1768
4da19633 1769static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 1770{
350f7596 1771 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1772 { 0x1f, 0x0001 },
1773 { 0x06, 0x006e },
1774 { 0x08, 0x0708 },
1775 { 0x15, 0x4000 },
1776 { 0x18, 0x65c7 },
1da177e4 1777
0b9b571d 1778 { 0x1f, 0x0001 },
1779 { 0x03, 0x00a1 },
1780 { 0x02, 0x0008 },
1781 { 0x01, 0x0120 },
1782 { 0x00, 0x1000 },
1783 { 0x04, 0x0800 },
1784 { 0x04, 0x0000 },
1da177e4 1785
0b9b571d 1786 { 0x03, 0xff41 },
1787 { 0x02, 0xdf60 },
1788 { 0x01, 0x0140 },
1789 { 0x00, 0x0077 },
1790 { 0x04, 0x7800 },
1791 { 0x04, 0x7000 },
1792
1793 { 0x03, 0x802f },
1794 { 0x02, 0x4f02 },
1795 { 0x01, 0x0409 },
1796 { 0x00, 0xf0f9 },
1797 { 0x04, 0x9800 },
1798 { 0x04, 0x9000 },
1799
1800 { 0x03, 0xdf01 },
1801 { 0x02, 0xdf20 },
1802 { 0x01, 0xff95 },
1803 { 0x00, 0xba00 },
1804 { 0x04, 0xa800 },
1805 { 0x04, 0xa000 },
1806
1807 { 0x03, 0xff41 },
1808 { 0x02, 0xdf20 },
1809 { 0x01, 0x0140 },
1810 { 0x00, 0x00bb },
1811 { 0x04, 0xb800 },
1812 { 0x04, 0xb000 },
1813
1814 { 0x03, 0xdf41 },
1815 { 0x02, 0xdc60 },
1816 { 0x01, 0x6340 },
1817 { 0x00, 0x007d },
1818 { 0x04, 0xd800 },
1819 { 0x04, 0xd000 },
1820
1821 { 0x03, 0xdf01 },
1822 { 0x02, 0xdf20 },
1823 { 0x01, 0x100a },
1824 { 0x00, 0xa0ff },
1825 { 0x04, 0xf800 },
1826 { 0x04, 0xf000 },
1827
1828 { 0x1f, 0x0000 },
1829 { 0x0b, 0x0000 },
1830 { 0x00, 0x9200 }
1831 };
1da177e4 1832
4da19633 1833 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1834}
1835
4da19633 1836static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 1837{
350f7596 1838 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1839 { 0x1f, 0x0002 },
1840 { 0x01, 0x90d0 },
1841 { 0x1f, 0x0000 }
1842 };
1843
4da19633 1844 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1845}
1846
4da19633 1847static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 1848{
1849 struct pci_dev *pdev = tp->pci_dev;
1850 u16 vendor_id, device_id;
1851
1852 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1853 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1854
1855 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1856 return;
1857
4da19633 1858 rtl_writephy(tp, 0x1f, 0x0001);
1859 rtl_writephy(tp, 0x10, 0xf01b);
1860 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 1861}
1862
4da19633 1863static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 1864{
350f7596 1865 static const struct phy_reg phy_reg_init[] = {
2e955856 1866 { 0x1f, 0x0001 },
1867 { 0x04, 0x0000 },
1868 { 0x03, 0x00a1 },
1869 { 0x02, 0x0008 },
1870 { 0x01, 0x0120 },
1871 { 0x00, 0x1000 },
1872 { 0x04, 0x0800 },
1873 { 0x04, 0x9000 },
1874 { 0x03, 0x802f },
1875 { 0x02, 0x4f02 },
1876 { 0x01, 0x0409 },
1877 { 0x00, 0xf099 },
1878 { 0x04, 0x9800 },
1879 { 0x04, 0xa000 },
1880 { 0x03, 0xdf01 },
1881 { 0x02, 0xdf20 },
1882 { 0x01, 0xff95 },
1883 { 0x00, 0xba00 },
1884 { 0x04, 0xa800 },
1885 { 0x04, 0xf000 },
1886 { 0x03, 0xdf01 },
1887 { 0x02, 0xdf20 },
1888 { 0x01, 0x101a },
1889 { 0x00, 0xa0ff },
1890 { 0x04, 0xf800 },
1891 { 0x04, 0x0000 },
1892 { 0x1f, 0x0000 },
1893
1894 { 0x1f, 0x0001 },
1895 { 0x10, 0xf41b },
1896 { 0x14, 0xfb54 },
1897 { 0x18, 0xf5c7 },
1898 { 0x1f, 0x0000 },
1899
1900 { 0x1f, 0x0001 },
1901 { 0x17, 0x0cc0 },
1902 { 0x1f, 0x0000 }
1903 };
1904
4da19633 1905 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 1906
4da19633 1907 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 1908}
1909
4da19633 1910static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 1911{
350f7596 1912 static const struct phy_reg phy_reg_init[] = {
8c7006aa 1913 { 0x1f, 0x0001 },
1914 { 0x04, 0x0000 },
1915 { 0x03, 0x00a1 },
1916 { 0x02, 0x0008 },
1917 { 0x01, 0x0120 },
1918 { 0x00, 0x1000 },
1919 { 0x04, 0x0800 },
1920 { 0x04, 0x9000 },
1921 { 0x03, 0x802f },
1922 { 0x02, 0x4f02 },
1923 { 0x01, 0x0409 },
1924 { 0x00, 0xf099 },
1925 { 0x04, 0x9800 },
1926 { 0x04, 0xa000 },
1927 { 0x03, 0xdf01 },
1928 { 0x02, 0xdf20 },
1929 { 0x01, 0xff95 },
1930 { 0x00, 0xba00 },
1931 { 0x04, 0xa800 },
1932 { 0x04, 0xf000 },
1933 { 0x03, 0xdf01 },
1934 { 0x02, 0xdf20 },
1935 { 0x01, 0x101a },
1936 { 0x00, 0xa0ff },
1937 { 0x04, 0xf800 },
1938 { 0x04, 0x0000 },
1939 { 0x1f, 0x0000 },
1940
1941 { 0x1f, 0x0001 },
1942 { 0x0b, 0x8480 },
1943 { 0x1f, 0x0000 },
1944
1945 { 0x1f, 0x0001 },
1946 { 0x18, 0x67c7 },
1947 { 0x04, 0x2000 },
1948 { 0x03, 0x002f },
1949 { 0x02, 0x4360 },
1950 { 0x01, 0x0109 },
1951 { 0x00, 0x3022 },
1952 { 0x04, 0x2800 },
1953 { 0x1f, 0x0000 },
1954
1955 { 0x1f, 0x0001 },
1956 { 0x17, 0x0cc0 },
1957 { 0x1f, 0x0000 }
1958 };
1959
4da19633 1960 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 1961}
1962
4da19633 1963static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 1964{
350f7596 1965 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1966 { 0x10, 0xf41b },
1967 { 0x1f, 0x0000 }
1968 };
1969
4da19633 1970 rtl_writephy(tp, 0x1f, 0x0001);
1971 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 1972
4da19633 1973 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 1974}
1975
4da19633 1976static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 1977{
350f7596 1978 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1979 { 0x1f, 0x0001 },
1980 { 0x10, 0xf41b },
1981 { 0x1f, 0x0000 }
1982 };
1983
4da19633 1984 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 1985}
1986
4da19633 1987static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 1988{
350f7596 1989 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 1990 { 0x1f, 0x0000 },
1991 { 0x1d, 0x0f00 },
1992 { 0x1f, 0x0002 },
1993 { 0x0c, 0x1ec8 },
1994 { 0x1f, 0x0000 }
1995 };
1996
4da19633 1997 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 1998}
1999
4da19633 2000static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2001{
350f7596 2002 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2003 { 0x1f, 0x0001 },
2004 { 0x1d, 0x3d98 },
2005 { 0x1f, 0x0000 }
2006 };
2007
4da19633 2008 rtl_writephy(tp, 0x1f, 0x0000);
2009 rtl_patchphy(tp, 0x14, 1 << 5);
2010 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2011
4da19633 2012 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2013}
2014
4da19633 2015static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2016{
350f7596 2017 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2018 { 0x1f, 0x0001 },
2019 { 0x12, 0x2300 },
867763c1
FR		 2020 { 0x1f, 0x0002 },
2021 { 0x00, 0x88d4 },
2022 { 0x01, 0x82b1 },
2023 { 0x03, 0x7002 },
2024 { 0x08, 0x9e30 },
2025 { 0x09, 0x01f0 },
2026 { 0x0a, 0x5500 },
2027 { 0x0c, 0x00c8 },
2028 { 0x1f, 0x0003 },
2029 { 0x12, 0xc096 },
2030 { 0x16, 0x000a },
f50d4275
FR		 2031 { 0x1f, 0x0000 },
2032 { 0x1f, 0x0000 },
2033 { 0x09, 0x2000 },
2034 { 0x09, 0x0000 }
867763c1
FR		 2035 };
2036
4da19633 2037 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2038
4da19633 2039 rtl_patchphy(tp, 0x14, 1 << 5);
2040 rtl_patchphy(tp, 0x0d, 1 << 5);
2041 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2042}
2043
4da19633 2044static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2045{
350f7596 2046 static const struct phy_reg phy_reg_init[] = {
f50d4275 2047 { 0x1f, 0x0001 },
7da97ec9 2048 { 0x12, 0x2300 },
f50d4275
FR		 2049 { 0x03, 0x802f },
2050 { 0x02, 0x4f02 },
2051 { 0x01, 0x0409 },
2052 { 0x00, 0xf099 },
2053 { 0x04, 0x9800 },
2054 { 0x04, 0x9000 },
2055 { 0x1d, 0x3d98 },
7da97ec9
FR		 2056 { 0x1f, 0x0002 },
2057 { 0x0c, 0x7eb8 },
f50d4275
FR		 2058 { 0x06, 0x0761 },
2059 { 0x1f, 0x0003 },
2060 { 0x16, 0x0f0a },
7da97ec9
FR		 2061 { 0x1f, 0x0000 }
2062 };
2063
4da19633 2064 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2065
4da19633 2066 rtl_patchphy(tp, 0x16, 1 << 0);
2067 rtl_patchphy(tp, 0x14, 1 << 5);
2068 rtl_patchphy(tp, 0x0d, 1 << 5);
2069 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2070}
2071
4da19633 2072static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2073{
350f7596 2074 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2075 { 0x1f, 0x0001 },
2076 { 0x12, 0x2300 },
2077 { 0x1d, 0x3d98 },
2078 { 0x1f, 0x0002 },
2079 { 0x0c, 0x7eb8 },
2080 { 0x06, 0x5461 },
2081 { 0x1f, 0x0003 },
2082 { 0x16, 0x0f0a },
2083 { 0x1f, 0x0000 }
2084 };
2085
4da19633 2086 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2087
4da19633 2088 rtl_patchphy(tp, 0x16, 1 << 0);
2089 rtl_patchphy(tp, 0x14, 1 << 5);
2090 rtl_patchphy(tp, 0x0d, 1 << 5);
2091 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2092}
2093
4da19633 2094static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2095{
4da19633 2096 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2097}
2098
bca03d5f 2099static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2100{
350f7596 2101 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2102 /* Channel Estimation */
5b538df9 2103 { 0x1f, 0x0001 },
daf9df6d 2104 { 0x06, 0x4064 },
2105 { 0x07, 0x2863 },
2106 { 0x08, 0x059c },
2107 { 0x09, 0x26b4 },
2108 { 0x0a, 0x6a19 },
2109 { 0x0b, 0xdcc8 },
2110 { 0x10, 0xf06d },
2111 { 0x14, 0x7f68 },
2112 { 0x18, 0x7fd9 },
2113 { 0x1c, 0xf0ff },
2114 { 0x1d, 0x3d9c },
5b538df9 2115 { 0x1f, 0x0003 },
daf9df6d 2116 { 0x12, 0xf49f },
2117 { 0x13, 0x070b },
2118 { 0x1a, 0x05ad },
bca03d5f 2119 { 0x14, 0x94c0 },
2120
2121 /*
2122 * Tx Error Issue
2123 * enhance line driver power
2124 */
5b538df9 2125 { 0x1f, 0x0002 },
daf9df6d 2126 { 0x06, 0x5561 },
2127 { 0x1f, 0x0005 },
2128 { 0x05, 0x8332 },
bca03d5f 2129 { 0x06, 0x5561 },
2130
2131 /*
2132 * Can not link to 1Gbps with bad cable
2133 * Decrease SNR threshold form 21.07dB to 19.04dB
2134 */
2135 { 0x1f, 0x0001 },
2136 { 0x17, 0x0cc0 },
daf9df6d 2137
5b538df9 2138 { 0x1f, 0x0000 },
bca03d5f 2139 { 0x0d, 0xf880 }
daf9df6d 2140 };
bca03d5f 2141 void __iomem *ioaddr = tp->mmio_addr;
2142 const struct firmware *fw;
daf9df6d 2143
4da19633 2144 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2145
bca03d5f 2146 /*
2147 * Rx Error Issue
2148 * Fine Tune Switching regulator parameter
2149 */
4da19633 2150 rtl_writephy(tp, 0x1f, 0x0002);
2151 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2152 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2153
daf9df6d 2154 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2155 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2156 { 0x1f, 0x0002 },
2157 { 0x05, 0x669a },
2158 { 0x1f, 0x0005 },
2159 { 0x05, 0x8330 },
2160 { 0x06, 0x669a },
2161 { 0x1f, 0x0002 }
2162 };
2163 int val;
2164
4da19633 2165 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2166
4da19633 2167 val = rtl_readphy(tp, 0x0d);
daf9df6d 2168
2169 if ((val & 0x00ff) != 0x006c) {
350f7596 2170 static const u32 set[] = {
daf9df6d 2171 0x0065, 0x0066, 0x0067, 0x0068,
2172 0x0069, 0x006a, 0x006b, 0x006c
2173 };
2174 int i;
2175
4da19633 2176 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2177
2178 val &= 0xff00;
2179 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2180 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2181 }
2182 } else {
350f7596 2183 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2184 { 0x1f, 0x0002 },
2185 { 0x05, 0x6662 },
2186 { 0x1f, 0x0005 },
2187 { 0x05, 0x8330 },
2188 { 0x06, 0x6662 }
2189 };
2190
4da19633 2191 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2192 }
2193
bca03d5f 2194 /* RSET couple improve */
4da19633 2195 rtl_writephy(tp, 0x1f, 0x0002);
2196 rtl_patchphy(tp, 0x0d, 0x0300);
2197 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2198
bca03d5f 2199 /* Fine tune PLL performance */
4da19633 2200 rtl_writephy(tp, 0x1f, 0x0002);
2201 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2202 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2203
4da19633 2204 rtl_writephy(tp, 0x1f, 0x0005);
2205 rtl_writephy(tp, 0x05, 0x001b);
2206 if (rtl_readphy(tp, 0x06) == 0xbf00 &&
bca03d5f 2207 request_firmware(&fw, FIRMWARE_8168D_1, &tp->pci_dev->dev) == 0) {
2208 rtl_phy_write_fw(tp, fw);
2209 release_firmware(fw);
2210 } else {
2211 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2212 }
2213
4da19633 2214 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2215}
2216
bca03d5f 2217static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2218{
350f7596 2219 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2220 /* Channel Estimation */
daf9df6d 2221 { 0x1f, 0x0001 },
2222 { 0x06, 0x4064 },
2223 { 0x07, 0x2863 },
2224 { 0x08, 0x059c },
2225 { 0x09, 0x26b4 },
2226 { 0x0a, 0x6a19 },
2227 { 0x0b, 0xdcc8 },
2228 { 0x10, 0xf06d },
2229 { 0x14, 0x7f68 },
2230 { 0x18, 0x7fd9 },
2231 { 0x1c, 0xf0ff },
2232 { 0x1d, 0x3d9c },
2233 { 0x1f, 0x0003 },
2234 { 0x12, 0xf49f },
2235 { 0x13, 0x070b },
2236 { 0x1a, 0x05ad },
2237 { 0x14, 0x94c0 },
2238
bca03d5f 2239 /*
2240 * Tx Error Issue
2241 * enhance line driver power
2242 */
daf9df6d 2243 { 0x1f, 0x0002 },
2244 { 0x06, 0x5561 },
2245 { 0x1f, 0x0005 },
2246 { 0x05, 0x8332 },
bca03d5f 2247 { 0x06, 0x5561 },
2248
2249 /*
2250 * Can not link to 1Gbps with bad cable
2251 * Decrease SNR threshold form 21.07dB to 19.04dB
2252 */
2253 { 0x1f, 0x0001 },
2254 { 0x17, 0x0cc0 },
daf9df6d 2255
2256 { 0x1f, 0x0000 },
bca03d5f 2257 { 0x0d, 0xf880 }
5b538df9 2258 };
bca03d5f 2259 void __iomem *ioaddr = tp->mmio_addr;
2260 const struct firmware *fw;
5b538df9 2261
4da19633 2262 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2263
daf9df6d 2264 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2265 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2266 { 0x1f, 0x0002 },
2267 { 0x05, 0x669a },
5b538df9 2268 { 0x1f, 0x0005 },
daf9df6d 2269 { 0x05, 0x8330 },
2270 { 0x06, 0x669a },
2271
2272 { 0x1f, 0x0002 }
2273 };
2274 int val;
2275
4da19633 2276 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2277
4da19633 2278 val = rtl_readphy(tp, 0x0d);
daf9df6d 2279 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2280 static const u32 set[] = {
daf9df6d 2281 0x0065, 0x0066, 0x0067, 0x0068,
2282 0x0069, 0x006a, 0x006b, 0x006c
2283 };
2284 int i;
2285
4da19633 2286 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2287
2288 val &= 0xff00;
2289 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2290 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2291 }
2292 } else {
350f7596 2293 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2294 { 0x1f, 0x0002 },
2295 { 0x05, 0x2642 },
5b538df9 2296 { 0x1f, 0x0005 },
daf9df6d 2297 { 0x05, 0x8330 },
2298 { 0x06, 0x2642 }
5b538df9
FR		 2299 };
2300
4da19633 2301 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2302 }
2303
bca03d5f 2304 /* Fine tune PLL performance */
4da19633 2305 rtl_writephy(tp, 0x1f, 0x0002);
2306 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2307 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2308
bca03d5f 2309 /* Switching regulator Slew rate */
4da19633 2310 rtl_writephy(tp, 0x1f, 0x0002);
2311 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2312
4da19633 2313 rtl_writephy(tp, 0x1f, 0x0005);
2314 rtl_writephy(tp, 0x05, 0x001b);
2315 if (rtl_readphy(tp, 0x06) == 0xb300 &&
bca03d5f 2316 request_firmware(&fw, FIRMWARE_8168D_2, &tp->pci_dev->dev) == 0) {
2317 rtl_phy_write_fw(tp, fw);
2318 release_firmware(fw);
2319 } else {
2320 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2321 }
2322
4da19633 2323 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2324}
2325
4da19633 2326static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2327{
350f7596 2328 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2329 { 0x1f, 0x0002 },
2330 { 0x10, 0x0008 },
2331 { 0x0d, 0x006c },
2332
2333 { 0x1f, 0x0000 },
2334 { 0x0d, 0xf880 },
2335
2336 { 0x1f, 0x0001 },
2337 { 0x17, 0x0cc0 },
2338
2339 { 0x1f, 0x0001 },
2340 { 0x0b, 0xa4d8 },
2341 { 0x09, 0x281c },
2342 { 0x07, 0x2883 },
2343 { 0x0a, 0x6b35 },
2344 { 0x1d, 0x3da4 },
2345 { 0x1c, 0xeffd },
2346 { 0x14, 0x7f52 },
2347 { 0x18, 0x7fc6 },
2348 { 0x08, 0x0601 },
2349 { 0x06, 0x4063 },
2350 { 0x10, 0xf074 },
2351 { 0x1f, 0x0003 },
2352 { 0x13, 0x0789 },
2353 { 0x12, 0xf4bd },
2354 { 0x1a, 0x04fd },
2355 { 0x14, 0x84b0 },
2356 { 0x1f, 0x0000 },
2357 { 0x00, 0x9200 },
2358
2359 { 0x1f, 0x0005 },
2360 { 0x01, 0x0340 },
2361 { 0x1f, 0x0001 },
2362 { 0x04, 0x4000 },
2363 { 0x03, 0x1d21 },
2364 { 0x02, 0x0c32 },
2365 { 0x01, 0x0200 },
2366 { 0x00, 0x5554 },
2367 { 0x04, 0x4800 },
2368 { 0x04, 0x4000 },
2369 { 0x04, 0xf000 },
2370 { 0x03, 0xdf01 },
2371 { 0x02, 0xdf20 },
2372 { 0x01, 0x101a },
2373 { 0x00, 0xa0ff },
2374 { 0x04, 0xf800 },
2375 { 0x04, 0xf000 },
2376 { 0x1f, 0x0000 },
2377
2378 { 0x1f, 0x0007 },
2379 { 0x1e, 0x0023 },
2380 { 0x16, 0x0000 },
2381 { 0x1f, 0x0000 }
2382 };
2383
4da19633 2384 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2385}
2386
e6de30d6 2387static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2388{
2389 static const struct phy_reg phy_reg_init[] = {
2390 { 0x1f, 0x0001 },
2391 { 0x17, 0x0cc0 },
2392
2393 { 0x1f, 0x0007 },
2394 { 0x1e, 0x002d },
2395 { 0x18, 0x0040 },
2396 { 0x1f, 0x0000 }
2397 };
2398
2399 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2400 rtl_patchphy(tp, 0x0d, 1 << 5);
2401}
2402
4da19633 2403static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2404{
350f7596 2405 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2406 { 0x1f, 0x0003 },
2407 { 0x08, 0x441d },
2408 { 0x01, 0x9100 },
2409 { 0x1f, 0x0000 }
2410 };
2411
4da19633 2412 rtl_writephy(tp, 0x1f, 0x0000);
2413 rtl_patchphy(tp, 0x11, 1 << 12);
2414 rtl_patchphy(tp, 0x19, 1 << 13);
2415 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2416
4da19633 2417 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2418}
2419
5615d9f1
FR		 2420static void rtl_hw_phy_config(struct net_device *dev)
2421{
2422 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2423
2424 rtl8169_print_mac_version(tp);
2425
2426 switch (tp->mac_version) {
2427 case RTL_GIGA_MAC_VER_01:
2428 break;
2429 case RTL_GIGA_MAC_VER_02:
2430 case RTL_GIGA_MAC_VER_03:
4da19633 2431 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2432 break;
2433 case RTL_GIGA_MAC_VER_04:
4da19633 2434 rtl8169sb_hw_phy_config(tp);
5615d9f1 2435 break;
2e955856 2436 case RTL_GIGA_MAC_VER_05:
4da19633 2437 rtl8169scd_hw_phy_config(tp);
2e955856 2438 break;
8c7006aa 2439 case RTL_GIGA_MAC_VER_06:
4da19633 2440 rtl8169sce_hw_phy_config(tp);
8c7006aa 2441 break;
2857ffb7
FR		 2442 case RTL_GIGA_MAC_VER_07:
2443 case RTL_GIGA_MAC_VER_08:
2444 case RTL_GIGA_MAC_VER_09:
4da19633 2445 rtl8102e_hw_phy_config(tp);
2857ffb7 2446 break;
236b8082 2447 case RTL_GIGA_MAC_VER_11:
4da19633 2448 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2449 break;
2450 case RTL_GIGA_MAC_VER_12:
4da19633 2451 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2452 break;
2453 case RTL_GIGA_MAC_VER_17:
4da19633 2454 rtl8168bef_hw_phy_config(tp);
236b8082 2455 break;
867763c1 2456 case RTL_GIGA_MAC_VER_18:
4da19633 2457 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2458 break;
2459 case RTL_GIGA_MAC_VER_19:
4da19633 2460 rtl8168c_1_hw_phy_config(tp);
867763c1 2461 break;
7da97ec9 2462 case RTL_GIGA_MAC_VER_20:
4da19633 2463 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2464 break;
197ff761 2465 case RTL_GIGA_MAC_VER_21:
4da19633 2466 rtl8168c_3_hw_phy_config(tp);
197ff761 2467 break;
6fb07058 2468 case RTL_GIGA_MAC_VER_22:
4da19633 2469 rtl8168c_4_hw_phy_config(tp);
6fb07058 2470 break;
ef3386f0 2471 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2472 case RTL_GIGA_MAC_VER_24:
4da19633 2473 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2474 break;
5b538df9 2475 case RTL_GIGA_MAC_VER_25:
bca03d5f 2476 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2477 break;
2478 case RTL_GIGA_MAC_VER_26:
bca03d5f 2479 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2480 break;
2481 case RTL_GIGA_MAC_VER_27:
4da19633 2482 rtl8168d_3_hw_phy_config(tp);
5b538df9 2483 break;
e6de30d6 2484 case RTL_GIGA_MAC_VER_28:
2485 rtl8168d_4_hw_phy_config(tp);
2486 break;
ef3386f0 2487
5615d9f1
FR		 2488 default:
2489 break;
2490 }
2491}
2492
1da177e4
LT		 2493static void rtl8169_phy_timer(unsigned long __opaque)
2494{
2495 struct net_device *dev = (struct net_device *)__opaque;
2496 struct rtl8169_private *tp = netdev_priv(dev);
2497 struct timer_list *timer = &tp->timer;
2498 void __iomem *ioaddr = tp->mmio_addr;
2499 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2500
bcf0bf90 2501 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2502
64e4bfb4 2503 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 2504 return;
2505
2506 spin_lock_irq(&tp->lock);
2507
4da19633 2508 if (tp->phy_reset_pending(tp)) {
5b0384f4 2509 /*
1da177e4
LT		 2510 * A busy loop could burn quite a few cycles on nowadays CPU.
2511 * Let's delay the execution of the timer for a few ticks.
2512 */
2513 timeout = HZ/10;
2514 goto out_mod_timer;
2515 }
2516
2517 if (tp->link_ok(ioaddr))
2518 goto out_unlock;
2519
bf82c189 2520 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 2521
4da19633 2522 tp->phy_reset_enable(tp);
1da177e4
LT		 2523
2524out_mod_timer:
2525 mod_timer(timer, jiffies + timeout);
2526out_unlock:
2527 spin_unlock_irq(&tp->lock);
2528}
2529
2530static inline void rtl8169_delete_timer(struct net_device *dev)
2531{
2532 struct rtl8169_private *tp = netdev_priv(dev);
2533 struct timer_list *timer = &tp->timer;
2534
e179bb7b 2535 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2536 return;
2537
2538 del_timer_sync(timer);
2539}
2540
2541static inline void rtl8169_request_timer(struct net_device *dev)
2542{
2543 struct rtl8169_private *tp = netdev_priv(dev);
2544 struct timer_list *timer = &tp->timer;
2545
e179bb7b 2546 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2547 return;
2548
2efa53f3 2549 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 2550}
2551
2552#ifdef CONFIG_NET_POLL_CONTROLLER
2553/*
2554 * Polling 'interrupt' - used by things like netconsole to send skbs
2555 * without having to re-enable interrupts. It's not called while
2556 * the interrupt routine is executing.
2557 */
2558static void rtl8169_netpoll(struct net_device *dev)
2559{
2560 struct rtl8169_private *tp = netdev_priv(dev);
2561 struct pci_dev *pdev = tp->pci_dev;
2562
2563 disable_irq(pdev->irq);
7d12e780 2564 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2565 enable_irq(pdev->irq);
2566}
2567#endif
2568
2569static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2570 void __iomem *ioaddr)
2571{
2572 iounmap(ioaddr);
2573 pci_release_regions(pdev);
87aeec76 2574 pci_clear_mwi(pdev);
1da177e4
LT		 2575 pci_disable_device(pdev);
2576 free_netdev(dev);
2577}
2578
bf793295
FR		 2579static void rtl8169_phy_reset(struct net_device *dev,
2580 struct rtl8169_private *tp)
2581{
07d3f51f 2582 unsigned int i;
bf793295 2583
4da19633 2584 tp->phy_reset_enable(tp);
bf793295 2585 for (i = 0; i < 100; i++) {
4da19633 2586 if (!tp->phy_reset_pending(tp))
bf793295
FR		 2587 return;
2588 msleep(1);
2589 }
bf82c189 2590 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2591}
2592
4ff96fa6
FR		 2593static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2594{
2595 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2596
5615d9f1 2597 rtl_hw_phy_config(dev);
4ff96fa6 2598
77332894
MS		 2599 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2600 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2601 RTL_W8(0x82, 0x01);
2602 }
4ff96fa6 2603
6dccd16b
FR		 2604 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2605
2606 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2607 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2608
bcf0bf90 2609 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2610 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2611 RTL_W8(0x82, 0x01);
2612 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 2613 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 2614 }
2615
bf793295
FR		 2616 rtl8169_phy_reset(dev, tp);
2617
901dda2b
FR		 2618 /*
2619 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2620 * only 8101. Don't panic.
2621 */
2622 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6 2623
bf82c189
JP		 2624 if (RTL_R8(PHYstatus) & TBI_Enable)
2625 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2626}
2627
773d2021
FR		 2628static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2629{
2630 void __iomem *ioaddr = tp->mmio_addr;
2631 u32 high;
2632 u32 low;
2633
2634 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2635 high = addr[4] | (addr[5] << 8);
2636
2637 spin_lock_irq(&tp->lock);
2638
2639 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2640
773d2021 2641 RTL_W32(MAC4, high);
908ba2bf 2642 RTL_R32(MAC4);
2643
78f1cd02 2644 RTL_W32(MAC0, low);
908ba2bf 2645 RTL_R32(MAC0);
2646
773d2021
FR		 2647 RTL_W8(Cfg9346, Cfg9346_Lock);
2648
2649 spin_unlock_irq(&tp->lock);
2650}
2651
2652static int rtl_set_mac_address(struct net_device *dev, void *p)
2653{
2654 struct rtl8169_private *tp = netdev_priv(dev);
2655 struct sockaddr *addr = p;
2656
2657 if (!is_valid_ether_addr(addr->sa_data))
2658 return -EADDRNOTAVAIL;
2659
2660 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2661
2662 rtl_rar_set(tp, dev->dev_addr);
2663
2664 return 0;
2665}
2666
5f787a1a
FR		 2667static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2668{
2669 struct rtl8169_private *tp = netdev_priv(dev);
2670 struct mii_ioctl_data *data = if_mii(ifr);
2671
8b4ab28d
FR		 2672 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2673}
5f787a1a 2674
8b4ab28d
FR		 2675static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2676{
5f787a1a
FR		 2677 switch (cmd) {
2678 case SIOCGMIIPHY:
2679 data->phy_id = 32; /* Internal PHY */
2680 return 0;
2681
2682 case SIOCGMIIREG:
4da19633 2683 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 2684 return 0;
2685
2686 case SIOCSMIIREG:
4da19633 2687 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 2688 return 0;
2689 }
2690 return -EOPNOTSUPP;
2691}
2692
8b4ab28d
FR		 2693static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2694{
2695 return -EOPNOTSUPP;
2696}
2697
0e485150
FR		 2698static const struct rtl_cfg_info {
2699 void (*hw_start)(struct net_device *);
2700 unsigned int region;
2701 unsigned int align;
2702 u16 intr_event;
2703 u16 napi_event;
ccdffb9a 2704 unsigned features;
f21b75e9 2705 u8 default_ver;
0e485150
FR		 2706} rtl_cfg_infos [] = {
2707 [RTL_CFG_0] = {
2708 .hw_start = rtl_hw_start_8169,
2709 .region = 1,
e9f63f30 2710 .align = 0,
0e485150
FR		 2711 .intr_event = SYSErr | LinkChg | RxOverflow |
2712 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2713 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2714 .features = RTL_FEATURE_GMII,
2715 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2716 },
2717 [RTL_CFG_1] = {
2718 .hw_start = rtl_hw_start_8168,
2719 .region = 2,
2720 .align = 8,
53f57357 2721 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 2722 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2723 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2724 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2725 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2726 },
2727 [RTL_CFG_2] = {
2728 .hw_start = rtl_hw_start_8101,
2729 .region = 2,
2730 .align = 8,
2731 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2732 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2733 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2734 .features = RTL_FEATURE_MSI,
2735 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2736 }
2737};
2738
fbac58fc
FR		 2739/* Cfg9346_Unlock assumed. */
2740static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2741 const struct rtl_cfg_info *cfg)
2742{
2743 unsigned msi = 0;
2744 u8 cfg2;
2745
2746 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2747 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2748 if (pci_enable_msi(pdev)) {
2749 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2750 } else {
2751 cfg2 |= MSIEnable;
2752 msi = RTL_FEATURE_MSI;
2753 }
2754 }
2755 RTL_W8(Config2, cfg2);
2756 return msi;
2757}
2758
2759static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2760{
2761 if (tp->features & RTL_FEATURE_MSI) {
2762 pci_disable_msi(pdev);
2763 tp->features &= ~RTL_FEATURE_MSI;
2764 }
2765}
2766
8b4ab28d
FR		 2767static const struct net_device_ops rtl8169_netdev_ops = {
2768 .ndo_open = rtl8169_open,
2769 .ndo_stop = rtl8169_close,
2770 .ndo_get_stats = rtl8169_get_stats,
00829823 2771 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2772 .ndo_tx_timeout = rtl8169_tx_timeout,
2773 .ndo_validate_addr = eth_validate_addr,
2774 .ndo_change_mtu = rtl8169_change_mtu,
2775 .ndo_set_mac_address = rtl_set_mac_address,
2776 .ndo_do_ioctl = rtl8169_ioctl,
2777 .ndo_set_multicast_list = rtl_set_rx_mode,
2778#ifdef CONFIG_R8169_VLAN
2779 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2780#endif
2781#ifdef CONFIG_NET_POLL_CONTROLLER
2782 .ndo_poll_controller = rtl8169_netpoll,
2783#endif
2784
2785};
2786
c0e45c1c 2787static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2788{
2789 struct mdio_ops *ops = &tp->mdio_ops;
2790
2791 switch (tp->mac_version) {
2792 case RTL_GIGA_MAC_VER_27:
2793 ops->write = r8168dp_1_mdio_write;
2794 ops->read = r8168dp_1_mdio_read;
2795 break;
e6de30d6 2796 case RTL_GIGA_MAC_VER_28:
2797 ops->write = r8168dp_2_mdio_write;
2798 ops->read = r8168dp_2_mdio_read;
2799 break;
c0e45c1c 2800 default:
2801 ops->write = r8169_mdio_write;
2802 ops->read = r8169_mdio_read;
2803 break;
2804 }
2805}
2806
065c27c1 2807static void r810x_phy_power_down(struct rtl8169_private *tp)
2808{
2809 rtl_writephy(tp, 0x1f, 0x0000);
2810 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2811}
2812
2813static void r810x_phy_power_up(struct rtl8169_private *tp)
2814{
2815 rtl_writephy(tp, 0x1f, 0x0000);
2816 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2817}
2818
2819static void r810x_pll_power_down(struct rtl8169_private *tp)
2820{
2821 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2822 rtl_writephy(tp, 0x1f, 0x0000);
2823 rtl_writephy(tp, MII_BMCR, 0x0000);
2824 return;
2825 }
2826
2827 r810x_phy_power_down(tp);
2828}
2829
2830static void r810x_pll_power_up(struct rtl8169_private *tp)
2831{
2832 r810x_phy_power_up(tp);
2833}
2834
2835static void r8168_phy_power_up(struct rtl8169_private *tp)
2836{
2837 rtl_writephy(tp, 0x1f, 0x0000);
2838 rtl_writephy(tp, 0x0e, 0x0000);
2839 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2840}
2841
2842static void r8168_phy_power_down(struct rtl8169_private *tp)
2843{
2844 rtl_writephy(tp, 0x1f, 0x0000);
2845 rtl_writephy(tp, 0x0e, 0x0200);
2846 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2847}
2848
2849static void r8168_pll_power_down(struct rtl8169_private *tp)
2850{
2851 void __iomem *ioaddr = tp->mmio_addr;
2852
2853 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2854 return;
2855
2856 if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2857 (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2858 (RTL_R16(CPlusCmd) & ASF)) {
2859 return;
2860 }
2861
2862 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2863 rtl_writephy(tp, 0x1f, 0x0000);
2864 rtl_writephy(tp, MII_BMCR, 0x0000);
2865
2866 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2867 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2868 return;
2869 }
2870
2871 r8168_phy_power_down(tp);
2872
2873 switch (tp->mac_version) {
2874 case RTL_GIGA_MAC_VER_25:
2875 case RTL_GIGA_MAC_VER_26:
2876 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2877 break;
2878 }
2879}
2880
2881static void r8168_pll_power_up(struct rtl8169_private *tp)
2882{
2883 void __iomem *ioaddr = tp->mmio_addr;
2884
2885 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2886 return;
2887
2888 switch (tp->mac_version) {
2889 case RTL_GIGA_MAC_VER_25:
2890 case RTL_GIGA_MAC_VER_26:
2891 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2892 break;
2893 }
2894
2895 r8168_phy_power_up(tp);
2896}
2897
2898static void rtl_pll_power_op(struct rtl8169_private *tp,
2899 void (*op)(struct rtl8169_private *))
2900{
2901 if (op)
2902 op(tp);
2903}
2904
2905static void rtl_pll_power_down(struct rtl8169_private *tp)
2906{
2907 rtl_pll_power_op(tp, tp->pll_power_ops.down);
2908}
2909
2910static void rtl_pll_power_up(struct rtl8169_private *tp)
2911{
2912 rtl_pll_power_op(tp, tp->pll_power_ops.up);
2913}
2914
2915static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2916{
2917 struct pll_power_ops *ops = &tp->pll_power_ops;
2918
2919 switch (tp->mac_version) {
2920 case RTL_GIGA_MAC_VER_07:
2921 case RTL_GIGA_MAC_VER_08:
2922 case RTL_GIGA_MAC_VER_09:
2923 case RTL_GIGA_MAC_VER_10:
2924 case RTL_GIGA_MAC_VER_16:
2925 ops->down = r810x_pll_power_down;
2926 ops->up = r810x_pll_power_up;
2927 break;
2928
2929 case RTL_GIGA_MAC_VER_11:
2930 case RTL_GIGA_MAC_VER_12:
2931 case RTL_GIGA_MAC_VER_17:
2932 case RTL_GIGA_MAC_VER_18:
2933 case RTL_GIGA_MAC_VER_19:
2934 case RTL_GIGA_MAC_VER_20:
2935 case RTL_GIGA_MAC_VER_21:
2936 case RTL_GIGA_MAC_VER_22:
2937 case RTL_GIGA_MAC_VER_23:
2938 case RTL_GIGA_MAC_VER_24:
2939 case RTL_GIGA_MAC_VER_25:
2940 case RTL_GIGA_MAC_VER_26:
2941 case RTL_GIGA_MAC_VER_27:
e6de30d6 2942 case RTL_GIGA_MAC_VER_28:
065c27c1 2943 ops->down = r8168_pll_power_down;
2944 ops->up = r8168_pll_power_up;
2945 break;
2946
2947 default:
2948 ops->down = NULL;
2949 ops->up = NULL;
2950 break;
2951 }
2952}
2953
1da177e4 2954static int __devinit
4ff96fa6 2955rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 2956{
0e485150
FR		 2957 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2958 const unsigned int region = cfg->region;
1da177e4 2959 struct rtl8169_private *tp;
ccdffb9a 2960 struct mii_if_info *mii;
4ff96fa6
FR		 2961 struct net_device *dev;
2962 void __iomem *ioaddr;
07d3f51f
FR		 2963 unsigned int i;
2964 int rc;
1da177e4 2965
4ff96fa6
FR		 2966 if (netif_msg_drv(&debug)) {
2967 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2968 MODULENAME, RTL8169_VERSION);
2969 }
1da177e4 2970
1da177e4 2971 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 2972 if (!dev) {
b57b7e5a 2973 if (netif_msg_drv(&debug))
9b91cf9d 2974 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 2975 rc = -ENOMEM;
2976 goto out;
1da177e4
LT		 2977 }
2978
1da177e4 2979 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 2980 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 2981 tp = netdev_priv(dev);
c4028958 2982 tp->dev = dev;
21e197f2 2983 tp->pci_dev = pdev;
b57b7e5a 2984 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 2985
ccdffb9a
FR		 2986 mii = &tp->mii;
2987 mii->dev = dev;
2988 mii->mdio_read = rtl_mdio_read;
2989 mii->mdio_write = rtl_mdio_write;
2990 mii->phy_id_mask = 0x1f;
2991 mii->reg_num_mask = 0x1f;
2992 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2993
1da177e4
LT		 2994 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2995 rc = pci_enable_device(pdev);
b57b7e5a 2996 if (rc < 0) {
bf82c189 2997 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 2998 goto err_out_free_dev_1;
1da177e4
LT		 2999 }
3000
87aeec76 3001 if (pci_set_mwi(pdev) < 0)
3002 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3003
1da177e4 3004 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3005 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3006 netif_err(tp, probe, dev,
3007 "region #%d not an MMIO resource, aborting\n",
3008 region);
1da177e4 3009 rc = -ENODEV;
87aeec76 3010 goto err_out_mwi_2;
1da177e4 3011 }
4ff96fa6 3012
1da177e4 3013 /* check for weird/broken PCI region reporting */
bcf0bf90 3014 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3015 netif_err(tp, probe, dev,
3016 "Invalid PCI region size(s), aborting\n");
1da177e4 3017 rc = -ENODEV;
87aeec76 3018 goto err_out_mwi_2;
1da177e4
LT		 3019 }
3020
3021 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3022 if (rc < 0) {
bf82c189 3023 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3024 goto err_out_mwi_2;
1da177e4
LT		 3025 }
3026
3027 tp->cp_cmd = PCIMulRW | RxChkSum;
3028
3029 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3030 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3031 tp->cp_cmd |= PCIDAC;
3032 dev->features |= NETIF_F_HIGHDMA;
3033 } else {
284901a9 3034 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3035 if (rc < 0) {
bf82c189 3036 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3037 goto err_out_free_res_3;
1da177e4
LT		 3038 }
3039 }
3040
1da177e4 3041 /* ioremap MMIO region */
bcf0bf90 3042 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3043 if (!ioaddr) {
bf82c189 3044 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3045 rc = -EIO;
87aeec76 3046 goto err_out_free_res_3;
1da177e4
LT		 3047 }
3048
4300e8c7
DM		 3049 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3050 if (!tp->pcie_cap)
3051 netif_info(tp, probe, dev, "no PCI Express capability\n");
3052
d78ad8cb 3053 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 3054
3055 /* Soft reset the chip. */
3056 RTL_W8(ChipCmd, CmdReset);
3057
3058 /* Check that the chip has finished the reset. */
07d3f51f 3059 for (i = 0; i < 100; i++) {
1da177e4
LT		 3060 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3061 break;
b518fa8e 3062 msleep_interruptible(1);
1da177e4
LT		 3063 }
3064
d78ad8cb
KW		 3065 RTL_W16(IntrStatus, 0xffff);
3066
ca52efd5 3067 pci_set_master(pdev);
3068
1da177e4
LT		 3069 /* Identify chip attached to board */
3070 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 3071
c0e45c1c 3072 rtl_init_mdio_ops(tp);
065c27c1 3073 rtl_init_pll_power_ops(tp);
c0e45c1c 3074
f21b75e9
JD		 3075 /* Use appropriate default if unknown */
3076 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
bf82c189
JP		 3077 netif_notice(tp, probe, dev,
3078 "unknown MAC, using family default\n");
f21b75e9
JD		 3079 tp->mac_version = cfg->default_ver;
3080 }
3081
1da177e4 3082 rtl8169_print_mac_version(tp);
1da177e4 3083
cee60c37 3084 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 3085 if (tp->mac_version == rtl_chip_info[i].mac_version)
3086 break;
3087 }
cee60c37 3088 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 3089 dev_err(&pdev->dev,
3090 "driver bug, MAC version not found in rtl_chip_info\n");
87aeec76 3091 goto err_out_msi_4;
1da177e4
LT		 3092 }
3093 tp->chipset = i;
3094
5d06a99f
FR		 3095 RTL_W8(Cfg9346, Cfg9346_Unlock);
3096 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3097 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3098 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3099 tp->features |= RTL_FEATURE_WOL;
3100 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3101 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3102 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3103 RTL_W8(Cfg9346, Cfg9346_Lock);
3104
66ec5d4f
FR		 3105 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3106 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3107 tp->set_speed = rtl8169_set_speed_tbi;
3108 tp->get_settings = rtl8169_gset_tbi;
3109 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3110 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3111 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3112 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 3113
64e4bfb4 3114 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 3115 } else {
3116 tp->set_speed = rtl8169_set_speed_xmii;
3117 tp->get_settings = rtl8169_gset_xmii;
3118 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3119 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3120 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3121 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3122 }
3123
df58ef51
FR		 3124 spin_lock_init(&tp->lock);
3125
738e1e69
PV		 3126 tp->mmio_addr = ioaddr;
3127
7bf6bf48 3128 /* Get MAC address */
1da177e4
LT		 3129 for (i = 0; i < MAC_ADDR_LEN; i++)
3130 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3131 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3132
1da177e4 3133 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3134 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3135 dev->irq = pdev->irq;
3136 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3137
bea3348e 3138 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 3139
3140#ifdef CONFIG_R8169_VLAN
3141 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4 3142#endif
2edae08e 3143 dev->features |= NETIF_F_GRO;
1da177e4
LT		 3144
3145 tp->intr_mask = 0xffff;
0e485150
FR		 3146 tp->hw_start = cfg->hw_start;
3147 tp->intr_event = cfg->intr_event;
3148 tp->napi_event = cfg->napi_event;
1da177e4 3149
2efa53f3
FR		 3150 init_timer(&tp->timer);
3151 tp->timer.data = (unsigned long) dev;
3152 tp->timer.function = rtl8169_phy_timer;
3153
1da177e4 3154 rc = register_netdev(dev);
4ff96fa6 3155 if (rc < 0)
87aeec76 3156 goto err_out_msi_4;
1da177e4
LT		 3157
3158 pci_set_drvdata(pdev, dev);
3159
bf82c189
JP		 3160 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3161 rtl_chip_info[tp->chipset].name,
3162 dev->base_addr, dev->dev_addr,
3163 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3164
e6de30d6 3165 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3166 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
b646d900 3167 rtl8168_driver_start(tp);
e6de30d6 3168 }
b646d900 3169
8b76ab39 3170 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3171
f3ec4f87
AS		 3172 if (pci_dev_run_wake(pdev))
3173 pm_runtime_put_noidle(&pdev->dev);
e1759441 3174
4ff96fa6
FR		 3175out:
3176 return rc;
1da177e4 3177
87aeec76 3178err_out_msi_4:
fbac58fc 3179 rtl_disable_msi(pdev, tp);
4ff96fa6 3180 iounmap(ioaddr);
87aeec76 3181err_out_free_res_3:
4ff96fa6 3182 pci_release_regions(pdev);
87aeec76 3183err_out_mwi_2:
4ff96fa6 3184 pci_clear_mwi(pdev);
4ff96fa6
FR		 3185 pci_disable_device(pdev);
3186err_out_free_dev_1:
3187 free_netdev(dev);
3188 goto out;
1da177e4
LT		 3189}
3190
07d3f51f 3191static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3192{
3193 struct net_device *dev = pci_get_drvdata(pdev);
3194 struct rtl8169_private *tp = netdev_priv(dev);
3195
e6de30d6 3196 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3197 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
b646d900 3198 rtl8168_driver_stop(tp);
e6de30d6 3199 }
b646d900 3200
23f333a2 3201 cancel_delayed_work_sync(&tp->task);
eb2a021c 3202
1da177e4 3203 unregister_netdev(dev);
cc098dc7 3204
f3ec4f87
AS		 3205 if (pci_dev_run_wake(pdev))
3206 pm_runtime_get_noresume(&pdev->dev);
e1759441 3207
cc098dc7
IV		 3208 /* restore original MAC address */
3209 rtl_rar_set(tp, dev->perm_addr);
3210
fbac58fc 3211 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3212 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3213 pci_set_drvdata(pdev, NULL);
3214}
3215
1da177e4
LT		 3216static int rtl8169_open(struct net_device *dev)
3217{
3218 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 3219 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3220 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3221 int retval = -ENOMEM;
1da177e4 3222
e1759441 3223 pm_runtime_get_sync(&pdev->dev);
1da177e4 3224
1da177e4
LT		 3225 /*
3226 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3227 * dma_alloc_coherent provides more.
1da177e4 3228 */
82553bb6
SG		 3229 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3230 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3231 if (!tp->TxDescArray)
e1759441 3232 goto err_pm_runtime_put;
1da177e4 3233
82553bb6
SG		 3234 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3235 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3236 if (!tp->RxDescArray)
99f252b0 3237 goto err_free_tx_0;
1da177e4
LT		 3238
3239 retval = rtl8169_init_ring(dev);
3240 if (retval < 0)
99f252b0 3241 goto err_free_rx_1;
1da177e4 3242
c4028958 3243 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3244
99f252b0
FR		 3245 smp_mb();
3246
fbac58fc
FR		 3247 retval = request_irq(dev->irq, rtl8169_interrupt,
3248 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3249 dev->name, dev);
3250 if (retval < 0)
3251 goto err_release_ring_2;
3252
bea3348e 3253 napi_enable(&tp->napi);
bea3348e 3254
eee3a96c 3255 rtl8169_init_phy(dev, tp);
3256
3257 /*
3258 * Pretend we are using VLANs; This bypasses a nasty bug where
3259 * Interrupts stop flowing on high load on 8110SCd controllers.
3260 */
3261 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3262 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3263
065c27c1 3264 rtl_pll_power_up(tp);
3265
07ce4064 3266 rtl_hw_start(dev);
1da177e4
LT		 3267
3268 rtl8169_request_timer(dev);
3269
e1759441
RW		 3270 tp->saved_wolopts = 0;
3271 pm_runtime_put_noidle(&pdev->dev);
3272
eee3a96c 3273 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 3274out:
3275 return retval;
3276
99f252b0
FR		 3277err_release_ring_2:
3278 rtl8169_rx_clear(tp);
3279err_free_rx_1:
82553bb6
SG		 3280 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3281 tp->RxPhyAddr);
e1759441 3282 tp->RxDescArray = NULL;
99f252b0 3283err_free_tx_0:
82553bb6
SG		 3284 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3285 tp->TxPhyAddr);
e1759441
RW		 3286 tp->TxDescArray = NULL;
3287err_pm_runtime_put:
3288 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3289 goto out;
3290}
3291
e6de30d6 3292static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3293{
e6de30d6 3294 void __iomem *ioaddr = tp->mmio_addr;
3295
1da177e4
LT		 3296 /* Disable interrupts */
3297 rtl8169_irq_mask_and_ack(ioaddr);
3298
e6de30d6 3299 if (tp->mac_version == RTL_GIGA_MAC_VER_28) {
3300 while (RTL_R8(TxPoll) & NPQ)
3301 udelay(20);
3302
3303 }
3304
1da177e4
LT		 3305 /* Reset the chipset */
3306 RTL_W8(ChipCmd, CmdReset);
3307
3308 /* PCI commit */
3309 RTL_R8(ChipCmd);
3310}
3311
7f796d83 3312static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3313{
3314 void __iomem *ioaddr = tp->mmio_addr;
3315 u32 cfg = rtl8169_rx_config;
3316
3317 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3318 RTL_W32(RxConfig, cfg);
3319
3320 /* Set DMA burst size and Interframe Gap Time */
3321 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3322 (InterFrameGap << TxInterFrameGapShift));
3323}
3324
07ce4064 3325static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3326{
3327 struct rtl8169_private *tp = netdev_priv(dev);
3328 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 3329 unsigned int i;
1da177e4
LT		 3330
3331 /* Soft reset the chip. */
3332 RTL_W8(ChipCmd, CmdReset);
3333
3334 /* Check that the chip has finished the reset. */
07d3f51f 3335 for (i = 0; i < 100; i++) {
1da177e4
LT		 3336 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3337 break;
b518fa8e 3338 msleep_interruptible(1);
1da177e4
LT		 3339 }
3340
07ce4064
FR		 3341 tp->hw_start(dev);
3342
07ce4064
FR		 3343 netif_start_queue(dev);
3344}
3345
3346
7f796d83
FR		 3347static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3348 void __iomem *ioaddr)
3349{
3350 /*
3351 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3352 * register to be written before TxDescAddrLow to work.
3353 * Switching from MMIO to I/O access fixes the issue as well.
3354 */
3355 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3356 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3357 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3358 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3359}
3360
3361static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3362{
3363 u16 cmd;
3364
3365 cmd = RTL_R16(CPlusCmd);
3366 RTL_W16(CPlusCmd, cmd);
3367 return cmd;
3368}
3369
fdd7b4c3 3370static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3371{
3372 /* Low hurts. Let's disable the filtering. */
207d6e87 3373 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3374}
3375
6dccd16b
FR		 3376static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3377{
350f7596 3378 static const struct {
6dccd16b
FR		 3379 u32 mac_version;
3380 u32 clk;
3381 u32 val;
3382 } cfg2_info [] = {
3383 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3384 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3385 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3386 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3387 }, *p = cfg2_info;
3388 unsigned int i;
3389 u32 clk;
3390
3391 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3392 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3393 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3394 RTL_W32(0x7c, p->val);
3395 break;
3396 }
3397 }
3398}
3399
07ce4064
FR		 3400static void rtl_hw_start_8169(struct net_device *dev)
3401{
3402 struct rtl8169_private *tp = netdev_priv(dev);
3403 void __iomem *ioaddr = tp->mmio_addr;
3404 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3405
9cb427b6
FR		 3406 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3407 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3408 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3409 }
3410
1da177e4 3411 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 3412 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3413 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3414 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3415 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3416 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3417
f0298f81 3418 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 3419
6f0333b8 3420 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 3421
c946b304
FR		 3422 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3423 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3424 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3425 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3426 rtl_set_rx_tx_config_registers(tp);
1da177e4 3427
7f796d83 3428 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3429
bcf0bf90
FR		 3430 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3431 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 3432 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3433 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3434 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3435 }
3436
bcf0bf90
FR		 3437 RTL_W16(CPlusCmd, tp->cp_cmd);
3438
6dccd16b
FR		 3439 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3440
1da177e4
LT		 3441 /*
3442 * Undocumented corner. Supposedly:
3443 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3444 */
3445 RTL_W16(IntrMitigate, 0x0000);
3446
7f796d83 3447 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3448
c946b304
FR		 3449 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3450 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3451 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3452 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3453 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3454 rtl_set_rx_tx_config_registers(tp);
3455 }
3456
1da177e4 3457 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3458
3459 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3460 RTL_R8(IntrMask);
1da177e4
LT		 3461
3462 RTL_W32(RxMissed, 0);
3463
07ce4064 3464 rtl_set_rx_mode(dev);
1da177e4
LT		 3465
3466 /* no early-rx interrupts */
3467 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3468
3469 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3470 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3471}
1da177e4 3472
9c14ceaf 3473static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3474{
9c14ceaf
FR		 3475 struct net_device *dev = pci_get_drvdata(pdev);
3476 struct rtl8169_private *tp = netdev_priv(dev);
3477 int cap = tp->pcie_cap;
3478
3479 if (cap) {
3480 u16 ctl;
458a9f61 3481
9c14ceaf
FR		 3482 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3483 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3484 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3485 }
458a9f61
FR		 3486}
3487
650e8d5d 3488static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 3489{
3490 u32 csi;
3491
3492 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 3493 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3494}
3495
e6de30d6 3496static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3497{
3498 rtl_csi_access_enable(ioaddr, 0x17000000);
3499}
3500
650e8d5d 3501static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3502{
3503 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 3504}
3505
3506struct ephy_info {
3507 unsigned int offset;
3508 u16 mask;
3509 u16 bits;
3510};
3511
350f7596 3512static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3513{
3514 u16 w;
3515
3516 while (len-- > 0) {
3517 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3518 rtl_ephy_write(ioaddr, e->offset, w);
3519 e++;
3520 }
3521}
3522
b726e493
FR		 3523static void rtl_disable_clock_request(struct pci_dev *pdev)
3524{
3525 struct net_device *dev = pci_get_drvdata(pdev);
3526 struct rtl8169_private *tp = netdev_priv(dev);
3527 int cap = tp->pcie_cap;
3528
3529 if (cap) {
3530 u16 ctl;
3531
3532 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3533 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3534 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3535 }
3536}
3537
e6de30d6 3538static void rtl_enable_clock_request(struct pci_dev *pdev)
3539{
3540 struct net_device *dev = pci_get_drvdata(pdev);
3541 struct rtl8169_private *tp = netdev_priv(dev);
3542 int cap = tp->pcie_cap;
3543
3544 if (cap) {
3545 u16 ctl;
3546
3547 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3548 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3549 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3550 }
3551}
3552
b726e493
FR		 3553#define R8168_CPCMD_QUIRK_MASK (\
3554 EnableBist | \
3555 Mac_dbgo_oe | \
3556 Force_half_dup | \
3557 Force_rxflow_en | \
3558 Force_txflow_en | \
3559 Cxpl_dbg_sel | \
3560 ASF | \
3561 PktCntrDisable | \
3562 Mac_dbgo_sel)
3563
219a1e9d
FR		 3564static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3565{
b726e493
FR		 3566 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3567
3568 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3569
2e68ae44
FR		 3570 rtl_tx_performance_tweak(pdev,
3571 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3572}
3573
3574static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3575{
3576 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 3577
f0298f81 3578 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 3579
3580 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3581}
3582
3583static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3584{
b726e493
FR		 3585 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3586
3587 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3588
219a1e9d 3589 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3590
3591 rtl_disable_clock_request(pdev);
3592
3593 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3594}
3595
ef3386f0 3596static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3597{
350f7596 3598 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3599 { 0x01, 0, 0x0001 },
3600 { 0x02, 0x0800, 0x1000 },
3601 { 0x03, 0, 0x0042 },
3602 { 0x06, 0x0080, 0x0000 },
3603 { 0x07, 0, 0x2000 }
3604 };
3605
650e8d5d 3606 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3607
3608 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3609
219a1e9d
FR		 3610 __rtl_hw_start_8168cp(ioaddr, pdev);
3611}
3612
ef3386f0
FR		 3613static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3614{
650e8d5d 3615 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 3616
3617 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3618
3619 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3620
3621 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3622}
3623
7f3e3d3a
FR		 3624static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3625{
650e8d5d 3626 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 3627
3628 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3629
3630 /* Magic. */
3631 RTL_W8(DBG_REG, 0x20);
3632
f0298f81 3633 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 3634
3635 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3636
3637 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3638}
3639
219a1e9d
FR		 3640static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3641{
350f7596 3642 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3643 { 0x02, 0x0800, 0x1000 },
3644 { 0x03, 0, 0x0002 },
3645 { 0x06, 0x0080, 0x0000 }
3646 };
3647
650e8d5d 3648 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3649
3650 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3651
3652 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3653
219a1e9d
FR		 3654 __rtl_hw_start_8168cp(ioaddr, pdev);
3655}
3656
3657static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3658{
350f7596 3659 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3660 { 0x01, 0, 0x0001 },
3661 { 0x03, 0x0400, 0x0220 }
3662 };
3663
650e8d5d 3664 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3665
3666 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3667
219a1e9d
FR		 3668 __rtl_hw_start_8168cp(ioaddr, pdev);
3669}
3670
197ff761
FR		 3671static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3672{
3673 rtl_hw_start_8168c_2(ioaddr, pdev);
3674}
3675
6fb07058
FR		 3676static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3677{
650e8d5d 3678 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 3679
3680 __rtl_hw_start_8168cp(ioaddr, pdev);
3681}
3682
5b538df9
FR		 3683static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3684{
650e8d5d 3685 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 3686
3687 rtl_disable_clock_request(pdev);
3688
f0298f81 3689 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 3690
3691 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3692
3693 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3694}
3695
e6de30d6 3696static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
3697{
3698 static const struct ephy_info e_info_8168d_4[] = {
3699 { 0x0b, ~0, 0x48 },
3700 { 0x19, 0x20, 0x50 },
3701 { 0x0c, ~0, 0x20 }
3702 };
3703 int i;
3704
3705 rtl_csi_access_enable_1(ioaddr);
3706
3707 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3708
3709 RTL_W8(MaxTxPacketSize, TxPacketMax);
3710
3711 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
3712 const struct ephy_info *e = e_info_8168d_4 + i;
3713 u16 w;
3714
3715 w = rtl_ephy_read(ioaddr, e->offset);
3716 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
3717 }
3718
3719 rtl_enable_clock_request(pdev);
3720}
3721
07ce4064
FR		 3722static void rtl_hw_start_8168(struct net_device *dev)
3723{
2dd99530
FR		 3724 struct rtl8169_private *tp = netdev_priv(dev);
3725 void __iomem *ioaddr = tp->mmio_addr;
0e485150 3726 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 3727
3728 RTL_W8(Cfg9346, Cfg9346_Unlock);
3729
f0298f81 3730 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 3731
6f0333b8 3732 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 3733
0e485150 3734 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 3735
3736 RTL_W16(CPlusCmd, tp->cp_cmd);
3737
0e485150 3738 RTL_W16(IntrMitigate, 0x5151);
2dd99530 3739
0e485150
FR		 3740 /* Work around for RxFIFO overflow. */
3741 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3742 tp->intr_event |= RxFIFOOver | PCSTimeout;
3743 tp->intr_event &= ~RxOverflow;
3744 }
3745
3746 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 3747
b8363901
FR		 3748 rtl_set_rx_mode(dev);
3749
3750 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3751 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 3752
3753 RTL_R8(IntrMask);
3754
219a1e9d
FR		 3755 switch (tp->mac_version) {
3756 case RTL_GIGA_MAC_VER_11:
3757 rtl_hw_start_8168bb(ioaddr, pdev);
3758 break;
3759
3760 case RTL_GIGA_MAC_VER_12:
3761 case RTL_GIGA_MAC_VER_17:
3762 rtl_hw_start_8168bef(ioaddr, pdev);
3763 break;
3764
3765 case RTL_GIGA_MAC_VER_18:
ef3386f0 3766 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 3767 break;
3768
3769 case RTL_GIGA_MAC_VER_19:
3770 rtl_hw_start_8168c_1(ioaddr, pdev);
3771 break;
3772
3773 case RTL_GIGA_MAC_VER_20:
3774 rtl_hw_start_8168c_2(ioaddr, pdev);
3775 break;
3776
197ff761
FR		 3777 case RTL_GIGA_MAC_VER_21:
3778 rtl_hw_start_8168c_3(ioaddr, pdev);
3779 break;
3780
6fb07058
FR		 3781 case RTL_GIGA_MAC_VER_22:
3782 rtl_hw_start_8168c_4(ioaddr, pdev);
3783 break;
3784
ef3386f0
FR		 3785 case RTL_GIGA_MAC_VER_23:
3786 rtl_hw_start_8168cp_2(ioaddr, pdev);
3787 break;
3788
7f3e3d3a
FR		 3789 case RTL_GIGA_MAC_VER_24:
3790 rtl_hw_start_8168cp_3(ioaddr, pdev);
3791 break;
3792
5b538df9 3793 case RTL_GIGA_MAC_VER_25:
daf9df6d 3794 case RTL_GIGA_MAC_VER_26:
3795 case RTL_GIGA_MAC_VER_27:
5b538df9
FR		 3796 rtl_hw_start_8168d(ioaddr, pdev);
3797 break;
3798
e6de30d6 3799 case RTL_GIGA_MAC_VER_28:
3800 rtl_hw_start_8168d_4(ioaddr, pdev);
3801 break;
3802
219a1e9d
FR		 3803 default:
3804 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3805 dev->name, tp->mac_version);
3806 break;
3807 }
2dd99530 3808
0e485150
FR		 3809 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3810
b8363901
FR		 3811 RTL_W8(Cfg9346, Cfg9346_Lock);
3812
2dd99530 3813 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 3814
0e485150 3815 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3816}
1da177e4 3817
2857ffb7
FR		 3818#define R810X_CPCMD_QUIRK_MASK (\
3819 EnableBist | \
3820 Mac_dbgo_oe | \
3821 Force_half_dup | \
5edcc537 3822 Force_rxflow_en | \
2857ffb7
FR		 3823 Force_txflow_en | \
3824 Cxpl_dbg_sel | \
3825 ASF | \
3826 PktCntrDisable | \
3827 PCIDAC | \
3828 PCIMulRW)
3829
3830static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3831{
350f7596 3832 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 3833 { 0x01, 0, 0x6e65 },
3834 { 0x02, 0, 0x091f },
3835 { 0x03, 0, 0xc2f9 },
3836 { 0x06, 0, 0xafb5 },
3837 { 0x07, 0, 0x0e00 },
3838 { 0x19, 0, 0xec80 },
3839 { 0x01, 0, 0x2e65 },
3840 { 0x01, 0, 0x6e65 }
3841 };
3842 u8 cfg1;
3843
650e8d5d 3844 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 3845
3846 RTL_W8(DBG_REG, FIX_NAK_1);
3847
3848 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3849
3850 RTL_W8(Config1,
3851 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3852 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3853
3854 cfg1 = RTL_R8(Config1);
3855 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3856 RTL_W8(Config1, cfg1 & ~LEDS0);
3857
3858 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3859
3860 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3861}
3862
3863static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3864{
650e8d5d 3865 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 3866
3867 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3868
3869 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3870 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3871
3872 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3873}
3874
3875static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3876{
3877 rtl_hw_start_8102e_2(ioaddr, pdev);
3878
3879 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3880}
3881
07ce4064
FR		 3882static void rtl_hw_start_8101(struct net_device *dev)
3883{
cdf1a608
FR		 3884 struct rtl8169_private *tp = netdev_priv(dev);
3885 void __iomem *ioaddr = tp->mmio_addr;
3886 struct pci_dev *pdev = tp->pci_dev;
3887
e3cf0cc0
FR		 3888 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3889 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 3890 int cap = tp->pcie_cap;
3891
3892 if (cap) {
3893 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3894 PCI_EXP_DEVCTL_NOSNOOP_EN);
3895 }
cdf1a608
FR		 3896 }
3897
2857ffb7
FR		 3898 switch (tp->mac_version) {
3899 case RTL_GIGA_MAC_VER_07:
3900 rtl_hw_start_8102e_1(ioaddr, pdev);
3901 break;
3902
3903 case RTL_GIGA_MAC_VER_08:
3904 rtl_hw_start_8102e_3(ioaddr, pdev);
3905 break;
3906
3907 case RTL_GIGA_MAC_VER_09:
3908 rtl_hw_start_8102e_2(ioaddr, pdev);
3909 break;
cdf1a608
FR		 3910 }
3911
3912 RTL_W8(Cfg9346, Cfg9346_Unlock);
3913
f0298f81 3914 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 3915
6f0333b8 3916 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608
FR		 3917
3918 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3919
3920 RTL_W16(CPlusCmd, tp->cp_cmd);
3921
3922 RTL_W16(IntrMitigate, 0x0000);
3923
3924 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3925
3926 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3927 rtl_set_rx_tx_config_registers(tp);
3928
3929 RTL_W8(Cfg9346, Cfg9346_Lock);
3930
3931 RTL_R8(IntrMask);
3932
cdf1a608
FR		 3933 rtl_set_rx_mode(dev);
3934
0e485150
FR		 3935 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3936
cdf1a608 3937 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 3938
0e485150 3939 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3940}
3941
3942static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3943{
1da177e4
LT		 3944 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3945 return -EINVAL;
3946
3947 dev->mtu = new_mtu;
323bb685 3948 return 0;
1da177e4
LT		 3949}
3950
3951static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3952{
95e0918d 3953 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 3954 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3955}
3956
6f0333b8
ED		 3957static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3958 void **data_buff, struct RxDesc *desc)
1da177e4 3959{
48addcc9 3960 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 3961 DMA_FROM_DEVICE);
48addcc9 3962
6f0333b8
ED		 3963 kfree(*data_buff);
3964 *data_buff = NULL;
1da177e4
LT		 3965 rtl8169_make_unusable_by_asic(desc);
3966}
3967
3968static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3969{
3970 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3971
3972 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3973}
3974
3975static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3976 u32 rx_buf_sz)
3977{
3978 desc->addr = cpu_to_le64(mapping);
3979 wmb();
3980 rtl8169_mark_to_asic(desc, rx_buf_sz);
3981}
3982
6f0333b8
ED		 3983static inline void *rtl8169_align(void *data)
3984{
3985 return (void *)ALIGN((long)data, 16);
3986}
3987
0ecbe1ca
SG		 3988static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3989 struct RxDesc *desc)
1da177e4 3990{
6f0333b8 3991 void *data;
1da177e4 3992 dma_addr_t mapping;
48addcc9 3993 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 3994 struct net_device *dev = tp->dev;
6f0333b8 3995 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 3996
6f0333b8
ED		 3997 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
3998 if (!data)
3999 return NULL;
e9f63f30 4000
6f0333b8
ED		 4001 if (rtl8169_align(data) != data) {
4002 kfree(data);
4003 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4004 if (!data)
4005 return NULL;
4006 }
3eafe507 4007
48addcc9 4008 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 4009 DMA_FROM_DEVICE);
d827d86b
SG		 4010 if (unlikely(dma_mapping_error(d, mapping))) {
4011 if (net_ratelimit())
4012 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 4013 goto err_out;
d827d86b 4014 }
1da177e4
LT		 4015
4016 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4017 return data;
3eafe507
SG		 4018
4019err_out:
4020 kfree(data);
4021 return NULL;
1da177e4
LT		 4022}
4023
4024static void rtl8169_rx_clear(struct rtl8169_private *tp)
4025{
07d3f51f 4026 unsigned int i;
1da177e4
LT		 4027
4028 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4029 if (tp->Rx_databuff[i]) {
4030 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4031 tp->RxDescArray + i);
4032 }
4033 }
4034}
4035
0ecbe1ca 4036static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4037{
0ecbe1ca
SG		 4038 desc->opts1 |= cpu_to_le32(RingEnd);
4039}
5b0384f4 4040
0ecbe1ca
SG		 4041static int rtl8169_rx_fill(struct rtl8169_private *tp)
4042{
4043 unsigned int i;
1da177e4 4044
0ecbe1ca
SG		 4045 for (i = 0; i < NUM_RX_DESC; i++) {
4046 void *data;
4ae47c2d 4047
6f0333b8 4048 if (tp->Rx_databuff[i])
1da177e4 4049 continue;
bcf0bf90 4050
0ecbe1ca 4051 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4052 if (!data) {
4053 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4054 goto err_out;
6f0333b8
ED		 4055 }
4056 tp->Rx_databuff[i] = data;
1da177e4 4057 }
1da177e4 4058
0ecbe1ca
SG		 4059 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4060 return 0;
4061
4062err_out:
4063 rtl8169_rx_clear(tp);
4064 return -ENOMEM;
1da177e4
LT		 4065}
4066
4067static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4068{
4069 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4070}
4071
4072static int rtl8169_init_ring(struct net_device *dev)
4073{
4074 struct rtl8169_private *tp = netdev_priv(dev);
4075
4076 rtl8169_init_ring_indexes(tp);
4077
4078 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4079 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4080
0ecbe1ca 4081 return rtl8169_rx_fill(tp);
1da177e4
LT		 4082}
4083
48addcc9 4084static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4085 struct TxDesc *desc)
4086{
4087 unsigned int len = tx_skb->len;
4088
48addcc9
SG		 4089 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4090
1da177e4
LT		 4091 desc->opts1 = 0x00;
4092 desc->opts2 = 0x00;
4093 desc->addr = 0x00;
4094 tx_skb->len = 0;
4095}
4096
3eafe507
SG		 4097static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4098 unsigned int n)
1da177e4
LT		 4099{
4100 unsigned int i;
4101
3eafe507
SG		 4102 for (i = 0; i < n; i++) {
4103 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4104 struct ring_info *tx_skb = tp->tx_skb + entry;
4105 unsigned int len = tx_skb->len;
4106
4107 if (len) {
4108 struct sk_buff *skb = tx_skb->skb;
4109
48addcc9 4110 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4111 tp->TxDescArray + entry);
4112 if (skb) {
cac4b22f 4113 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4114 dev_kfree_skb(skb);
4115 tx_skb->skb = NULL;
4116 }
1da177e4
LT		 4117 }
4118 }
3eafe507
SG		 4119}
4120
4121static void rtl8169_tx_clear(struct rtl8169_private *tp)
4122{
4123 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4124 tp->cur_tx = tp->dirty_tx = 0;
4125}
4126
c4028958 4127static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4128{
4129 struct rtl8169_private *tp = netdev_priv(dev);
4130
c4028958 4131 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4132 schedule_delayed_work(&tp->task, 4);
4133}
4134
4135static void rtl8169_wait_for_quiescence(struct net_device *dev)
4136{
4137 struct rtl8169_private *tp = netdev_priv(dev);
4138 void __iomem *ioaddr = tp->mmio_addr;
4139
4140 synchronize_irq(dev->irq);
4141
4142 /* Wait for any pending NAPI task to complete */
bea3348e 4143 napi_disable(&tp->napi);
1da177e4
LT		 4144
4145 rtl8169_irq_mask_and_ack(ioaddr);
4146
d1d08d12
DM		 4147 tp->intr_mask = 0xffff;
4148 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4149 napi_enable(&tp->napi);
1da177e4
LT		 4150}
4151
c4028958 4152static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4153{
c4028958
DH		 4154 struct rtl8169_private *tp =
4155 container_of(work, struct rtl8169_private, task.work);
4156 struct net_device *dev = tp->dev;
1da177e4
LT		 4157 int ret;
4158
eb2a021c
FR		 4159 rtnl_lock();
4160
4161 if (!netif_running(dev))
4162 goto out_unlock;
4163
4164 rtl8169_wait_for_quiescence(dev);
4165 rtl8169_close(dev);
1da177e4
LT		 4166
4167 ret = rtl8169_open(dev);
4168 if (unlikely(ret < 0)) {
bf82c189
JP		 4169 if (net_ratelimit())
4170 netif_err(tp, drv, dev,
4171 "reinit failure (status = %d). Rescheduling\n",
4172 ret);
1da177e4
LT		 4173 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4174 }
eb2a021c
FR		 4175
4176out_unlock:
4177 rtnl_unlock();
1da177e4
LT		 4178}
4179
c4028958 4180static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4181{
c4028958
DH		 4182 struct rtl8169_private *tp =
4183 container_of(work, struct rtl8169_private, task.work);
4184 struct net_device *dev = tp->dev;
1da177e4 4185
eb2a021c
FR		 4186 rtnl_lock();
4187
1da177e4 4188 if (!netif_running(dev))
eb2a021c 4189 goto out_unlock;
1da177e4
LT		 4190
4191 rtl8169_wait_for_quiescence(dev);
4192
bea3348e 4193 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 4194 rtl8169_tx_clear(tp);
4195
4196 if (tp->dirty_rx == tp->cur_rx) {
4197 rtl8169_init_ring_indexes(tp);
07ce4064 4198 rtl_hw_start(dev);
1da177e4 4199 netif_wake_queue(dev);
cebf8cc7 4200 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 4201 } else {
bf82c189
JP		 4202 if (net_ratelimit())
4203 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
1da177e4
LT		 4204 rtl8169_schedule_work(dev, rtl8169_reset_task);
4205 }
eb2a021c
FR		 4206
4207out_unlock:
4208 rtnl_unlock();
1da177e4
LT		 4209}
4210
4211static void rtl8169_tx_timeout(struct net_device *dev)
4212{
4213 struct rtl8169_private *tp = netdev_priv(dev);
4214
e6de30d6 4215 rtl8169_hw_reset(tp);
1da177e4
LT		 4216
4217 /* Let's wait a bit while any (async) irq lands on */
4218 rtl8169_schedule_work(dev, rtl8169_reset_task);
4219}
4220
4221static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4222 u32 opts1)
4223{
4224 struct skb_shared_info *info = skb_shinfo(skb);
4225 unsigned int cur_frag, entry;
a6343afb 4226 struct TxDesc * uninitialized_var(txd);
48addcc9 4227 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4228
4229 entry = tp->cur_tx;
4230 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4231 skb_frag_t *frag = info->frags + cur_frag;
4232 dma_addr_t mapping;
4233 u32 status, len;
4234 void *addr;
4235
4236 entry = (entry + 1) % NUM_TX_DESC;
4237
4238 txd = tp->TxDescArray + entry;
4239 len = frag->size;
4240 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 4241 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 4242 if (unlikely(dma_mapping_error(d, mapping))) {
4243 if (net_ratelimit())
4244 netif_err(tp, drv, tp->dev,
4245 "Failed to map TX fragments DMA!\n");
3eafe507 4246 goto err_out;
d827d86b 4247 }
1da177e4
LT		 4248
4249 /* anti gcc 2.95.3 bugware (sic) */
4250 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4251
4252 txd->opts1 = cpu_to_le32(status);
4253 txd->addr = cpu_to_le64(mapping);
4254
4255 tp->tx_skb[entry].len = len;
4256 }
4257
4258 if (cur_frag) {
4259 tp->tx_skb[entry].skb = skb;
4260 txd->opts1 |= cpu_to_le32(LastFrag);
4261 }
4262
4263 return cur_frag;
3eafe507
SG		 4264
4265err_out:
4266 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4267 return -EIO;
1da177e4
LT		 4268}
4269
4270static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4271{
4272 if (dev->features & NETIF_F_TSO) {
7967168c 4273 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 4274
4275 if (mss)
4276 return LargeSend | ((mss & MSSMask) << MSSShift);
4277 }
84fa7933 4278 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4279 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4280
4281 if (ip->protocol == IPPROTO_TCP)
4282 return IPCS | TCPCS;
4283 else if (ip->protocol == IPPROTO_UDP)
4284 return IPCS | UDPCS;
4285 WARN_ON(1); /* we need a WARN() */
4286 }
4287 return 0;
4288}
4289
61357325
SH		 4290static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4291 struct net_device *dev)
1da177e4
LT		 4292{
4293 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 4294 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 4295 struct TxDesc *txd = tp->TxDescArray + entry;
4296 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 4297 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4298 dma_addr_t mapping;
4299 u32 status, len;
4300 u32 opts1;
3eafe507 4301 int frags;
5b0384f4 4302
1da177e4 4303 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4304 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 4305 goto err_stop_0;
1da177e4
LT		 4306 }
4307
4308 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 4309 goto err_stop_0;
4310
4311 len = skb_headlen(skb);
48addcc9 4312 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 4313 if (unlikely(dma_mapping_error(d, mapping))) {
4314 if (net_ratelimit())
4315 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 4316 goto err_dma_0;
d827d86b 4317 }
3eafe507
SG		 4318
4319 tp->tx_skb[entry].len = len;
4320 txd->addr = cpu_to_le64(mapping);
4321 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
1da177e4
LT		 4322
4323 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4324
4325 frags = rtl8169_xmit_frags(tp, skb, opts1);
3eafe507
SG		 4326 if (frags < 0)
4327 goto err_dma_1;
4328 else if (frags)
1da177e4 4329 opts1 |= FirstFrag;
3eafe507 4330 else {
1da177e4
LT		 4331 opts1 |= FirstFrag | LastFrag;
4332 tp->tx_skb[entry].skb = skb;
4333 }
4334
1da177e4
LT		 4335 wmb();
4336
4337 /* anti gcc 2.95.3 bugware (sic) */
4338 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4339 txd->opts1 = cpu_to_le32(status);
4340
1da177e4
LT		 4341 tp->cur_tx += frags + 1;
4342
4c020a96 4343 wmb();
1da177e4 4344
275391a4 4345 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 4346
4347 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4348 netif_stop_queue(dev);
4349 smp_rmb();
4350 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4351 netif_wake_queue(dev);
4352 }
4353
61357325 4354 return NETDEV_TX_OK;
1da177e4 4355
3eafe507 4356err_dma_1:
48addcc9 4357 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 4358err_dma_0:
4359 dev_kfree_skb(skb);
4360 dev->stats.tx_dropped++;
4361 return NETDEV_TX_OK;
4362
4363err_stop_0:
1da177e4 4364 netif_stop_queue(dev);
cebf8cc7 4365 dev->stats.tx_dropped++;
61357325 4366 return NETDEV_TX_BUSY;
1da177e4
LT		 4367}
4368
4369static void rtl8169_pcierr_interrupt(struct net_device *dev)
4370{
4371 struct rtl8169_private *tp = netdev_priv(dev);
4372 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 4373 u16 pci_status, pci_cmd;
4374
4375 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4376 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4377
bf82c189
JP		 4378 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4379 pci_cmd, pci_status);
1da177e4
LT		 4380
4381 /*
4382 * The recovery sequence below admits a very elaborated explanation:
4383 * - it seems to work;
d03902b8
FR		 4384 * - I did not see what else could be done;
4385 * - it makes iop3xx happy.
1da177e4
LT		 4386 *
4387 * Feel free to adjust to your needs.
4388 */
a27993f3 4389 if (pdev->broken_parity_status)
d03902b8
FR		 4390 pci_cmd &= ~PCI_COMMAND_PARITY;
4391 else
4392 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4393
4394 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4395
4396 pci_write_config_word(pdev, PCI_STATUS,
4397 pci_status & (PCI_STATUS_DETECTED_PARITY |
4398 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4399 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4400
4401 /* The infamous DAC f*ckup only happens at boot time */
4402 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 4403 void __iomem *ioaddr = tp->mmio_addr;
4404
bf82c189 4405 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4406 tp->cp_cmd &= ~PCIDAC;
4407 RTL_W16(CPlusCmd, tp->cp_cmd);
4408 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4409 }
4410
e6de30d6 4411 rtl8169_hw_reset(tp);
d03902b8
FR		 4412
4413 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4414}
4415
07d3f51f
FR		 4416static void rtl8169_tx_interrupt(struct net_device *dev,
4417 struct rtl8169_private *tp,
4418 void __iomem *ioaddr)
1da177e4
LT		 4419{
4420 unsigned int dirty_tx, tx_left;
4421
1da177e4
LT		 4422 dirty_tx = tp->dirty_tx;
4423 smp_rmb();
4424 tx_left = tp->cur_tx - dirty_tx;
4425
4426 while (tx_left > 0) {
4427 unsigned int entry = dirty_tx % NUM_TX_DESC;
4428 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 4429 u32 status;
4430
4431 rmb();
4432 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4433 if (status & DescOwn)
4434 break;
4435
48addcc9
SG		 4436 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4437 tp->TxDescArray + entry);
1da177e4 4438 if (status & LastFrag) {
cac4b22f
SG		 4439 dev->stats.tx_packets++;
4440 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 4441 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4442 tx_skb->skb = NULL;
4443 }
4444 dirty_tx++;
4445 tx_left--;
4446 }
4447
4448 if (tp->dirty_tx != dirty_tx) {
4449 tp->dirty_tx = dirty_tx;
4450 smp_wmb();
4451 if (netif_queue_stopped(dev) &&
4452 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4453 netif_wake_queue(dev);
4454 }
d78ae2dc
FR		 4455 /*
4456 * 8168 hack: TxPoll requests are lost when the Tx packets are
4457 * too close. Let's kick an extra TxPoll request when a burst
4458 * of start_xmit activity is detected (if it is not detected,
4459 * it is slow enough). -- FR
4460 */
4461 smp_rmb();
4462 if (tp->cur_tx != dirty_tx)
4463 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4464 }
4465}
4466
126fa4b9
FR		 4467static inline int rtl8169_fragmented_frame(u32 status)
4468{
4469 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4470}
4471
adea1ac7 4472static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4473{
1da177e4
LT		 4474 u32 status = opts1 & RxProtoMask;
4475
4476 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 4477 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 4478 skb->ip_summed = CHECKSUM_UNNECESSARY;
4479 else
bc8acf2c 4480 skb_checksum_none_assert(skb);
1da177e4
LT		 4481}
4482
6f0333b8
ED		 4483static struct sk_buff *rtl8169_try_rx_copy(void *data,
4484 struct rtl8169_private *tp,
4485 int pkt_size,
4486 dma_addr_t addr)
1da177e4 4487{
b449655f 4488 struct sk_buff *skb;
48addcc9 4489 struct device *d = &tp->pci_dev->dev;
b449655f 4490
6f0333b8 4491 data = rtl8169_align(data);
48addcc9 4492 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 4493 prefetch(data);
4494 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4495 if (skb)
4496 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 4497 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4498
6f0333b8 4499 return skb;
1da177e4
LT		 4500}
4501
630b943c
ED		 4502/*
4503 * Warning : rtl8169_rx_interrupt() might be called :
4504 * 1) from NAPI (softirq) context
4505 * (polling = 1 : we should call netif_receive_skb())
4506 * 2) from process context (rtl8169_reset_task())
4507 * (polling = 0 : we must call netif_rx() instead)
4508 */
07d3f51f
FR		 4509static int rtl8169_rx_interrupt(struct net_device *dev,
4510 struct rtl8169_private *tp,
bea3348e 4511 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4512{
4513 unsigned int cur_rx, rx_left;
6f0333b8 4514 unsigned int count;
630b943c 4515 int polling = (budget != ~(u32)0) ? 1 : 0;
1da177e4 4516
1da177e4
LT		 4517 cur_rx = tp->cur_rx;
4518 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4519 rx_left = min(rx_left, budget);
1da177e4 4520
4dcb7d33 4521 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4522 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4523 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4524 u32 status;
4525
4526 rmb();
126fa4b9 4527 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4528
4529 if (status & DescOwn)
4530 break;
4dcb7d33 4531 if (unlikely(status & RxRES)) {
bf82c189
JP		 4532 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4533 status);
cebf8cc7 4534 dev->stats.rx_errors++;
1da177e4 4535 if (status & (RxRWT | RxRUNT))
cebf8cc7 4536 dev->stats.rx_length_errors++;
1da177e4 4537 if (status & RxCRC)
cebf8cc7 4538 dev->stats.rx_crc_errors++;
9dccf611
FR		 4539 if (status & RxFOVF) {
4540 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4541 dev->stats.rx_fifo_errors++;
9dccf611 4542 }
6f0333b8 4543 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 4544 } else {
6f0333b8 4545 struct sk_buff *skb;
b449655f 4546 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4547 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 4548
126fa4b9
FR		 4549 /*
4550 * The driver does not support incoming fragmented
4551 * frames. They are seen as a symptom of over-mtu
4552 * sized frames.
4553 */
4554 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4555 dev->stats.rx_dropped++;
4556 dev->stats.rx_length_errors++;
6f0333b8 4557 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 4558 continue;
126fa4b9
FR		 4559 }
4560
6f0333b8
ED		 4561 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4562 tp, pkt_size, addr);
4563 rtl8169_mark_to_asic(desc, rx_buf_sz);
4564 if (!skb) {
4565 dev->stats.rx_dropped++;
4566 continue;
1da177e4
LT		 4567 }
4568
adea1ac7 4569 rtl8169_rx_csum(skb, status);
1da177e4
LT		 4570 skb_put(skb, pkt_size);
4571 skb->protocol = eth_type_trans(skb, dev);
4572
630b943c
ED		 4573 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4574 if (likely(polling))
2edae08e 4575 napi_gro_receive(&tp->napi, skb);
630b943c
ED		 4576 else
4577 netif_rx(skb);
4578 }
1da177e4 4579
cebf8cc7
FR		 4580 dev->stats.rx_bytes += pkt_size;
4581 dev->stats.rx_packets++;
1da177e4 4582 }
6dccd16b
FR		 4583
4584 /* Work around for AMD plateform. */
95e0918d 4585 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4586 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4587 desc->opts2 = 0;
4588 cur_rx++;
4589 }
1da177e4
LT		 4590 }
4591
4592 count = cur_rx - tp->cur_rx;
4593 tp->cur_rx = cur_rx;
4594
6f0333b8 4595 tp->dirty_rx += count;
1da177e4
LT		 4596
4597 return count;
4598}
4599
07d3f51f 4600static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4601{
07d3f51f 4602 struct net_device *dev = dev_instance;
1da177e4 4603 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4604 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4605 int handled = 0;
865c652d 4606 int status;
1da177e4 4607
f11a377b
DD		 4608 /* loop handling interrupts until we have no new ones or
4609 * we hit a invalid/hotplug case.
4610 */
865c652d 4611 status = RTL_R16(IntrStatus);
f11a377b
DD		 4612 while (status && status != 0xffff) {
4613 handled = 1;
1da177e4 4614
f11a377b
DD		 4615 /* Handle all of the error cases first. These will reset
4616 * the chip, so just exit the loop.
4617 */
4618 if (unlikely(!netif_running(dev))) {
4619 rtl8169_asic_down(ioaddr);
4620 break;
4621 }
1da177e4 4622
f11a377b 4623 /* Work around for rx fifo overflow */
53f57357 4624 if (unlikely(status & RxFIFOOver) &&
4625 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
f11a377b
DD		 4626 netif_stop_queue(dev);
4627 rtl8169_tx_timeout(dev);
4628 break;
4629 }
1da177e4 4630
f11a377b
DD		 4631 if (unlikely(status & SYSErr)) {
4632 rtl8169_pcierr_interrupt(dev);
4633 break;
4634 }
1da177e4 4635
f11a377b 4636 if (status & LinkChg)
e4fbce74 4637 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 4638
f11a377b
DD		 4639 /* We need to see the lastest version of tp->intr_mask to
4640 * avoid ignoring an MSI interrupt and having to wait for
4641 * another event which may never come.
4642 */
4643 smp_rmb();
4644 if (status & tp->intr_mask & tp->napi_event) {
4645 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4646 tp->intr_mask = ~tp->napi_event;
4647
4648 if (likely(napi_schedule_prep(&tp->napi)))
4649 __napi_schedule(&tp->napi);
bf82c189
JP		 4650 else
4651 netif_info(tp, intr, dev,
4652 "interrupt %04x in poll\n", status);
f11a377b 4653 }
1da177e4 4654
f11a377b
DD		 4655 /* We only get a new MSI interrupt when all active irq
4656 * sources on the chip have been acknowledged. So, ack
4657 * everything we've seen and check if new sources have become
4658 * active to avoid blocking all interrupts from the chip.
4659 */
4660 RTL_W16(IntrStatus,
4661 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4662 status = RTL_R16(IntrStatus);
865c652d 4663 }
1da177e4 4664
1da177e4
LT		 4665 return IRQ_RETVAL(handled);
4666}
4667
bea3348e 4668static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 4669{
bea3348e
SH		 4670 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4671 struct net_device *dev = tp->dev;
1da177e4 4672 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 4673 int work_done;
1da177e4 4674
bea3348e 4675 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 4676 rtl8169_tx_interrupt(dev, tp, ioaddr);
4677
bea3348e 4678 if (work_done < budget) {
288379f0 4679 napi_complete(napi);
f11a377b
DD		 4680
4681 /* We need for force the visibility of tp->intr_mask
4682 * for other CPUs, as we can loose an MSI interrupt
4683 * and potentially wait for a retransmit timeout if we don't.
4684 * The posted write to IntrMask is safe, as it will
4685 * eventually make it to the chip and we won't loose anything
4686 * until it does.
1da177e4 4687 */
f11a377b 4688 tp->intr_mask = 0xffff;
4c020a96 4689 wmb();
0e485150 4690 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4691 }
4692
bea3348e 4693 return work_done;
1da177e4 4694}
1da177e4 4695
523a6094
FR		 4696static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4697{
4698 struct rtl8169_private *tp = netdev_priv(dev);
4699
4700 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4701 return;
4702
4703 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4704 RTL_W32(RxMissed, 0);
4705}
4706
1da177e4
LT		 4707static void rtl8169_down(struct net_device *dev)
4708{
4709 struct rtl8169_private *tp = netdev_priv(dev);
4710 void __iomem *ioaddr = tp->mmio_addr;
1da177e4
LT		 4711
4712 rtl8169_delete_timer(dev);
4713
4714 netif_stop_queue(dev);
4715
93dd79e8 4716 napi_disable(&tp->napi);
93dd79e8 4717
1da177e4
LT		 4718 spin_lock_irq(&tp->lock);
4719
4720 rtl8169_asic_down(ioaddr);
323bb685
SG		 4721 /*
4722 * At this point device interrupts can not be enabled in any function,
4723 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4724 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4725 */
523a6094 4726 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4727
4728 spin_unlock_irq(&tp->lock);
4729
4730 synchronize_irq(dev->irq);
4731
1da177e4 4732 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 4733 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 4734
1da177e4
LT		 4735 rtl8169_tx_clear(tp);
4736
4737 rtl8169_rx_clear(tp);
065c27c1 4738
4739 rtl_pll_power_down(tp);
1da177e4
LT		 4740}
4741
4742static int rtl8169_close(struct net_device *dev)
4743{
4744 struct rtl8169_private *tp = netdev_priv(dev);
4745 struct pci_dev *pdev = tp->pci_dev;
4746
e1759441
RW		 4747 pm_runtime_get_sync(&pdev->dev);
4748
355423d0
IV		 4749 /* update counters before going down */
4750 rtl8169_update_counters(dev);
4751
1da177e4
LT		 4752 rtl8169_down(dev);
4753
4754 free_irq(dev->irq, dev);
4755
82553bb6
SG		 4756 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4757 tp->RxPhyAddr);
4758 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4759 tp->TxPhyAddr);
1da177e4
LT		 4760 tp->TxDescArray = NULL;
4761 tp->RxDescArray = NULL;
4762
e1759441
RW		 4763 pm_runtime_put_sync(&pdev->dev);
4764
1da177e4
LT		 4765 return 0;
4766}
4767
07ce4064 4768static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 4769{
4770 struct rtl8169_private *tp = netdev_priv(dev);
4771 void __iomem *ioaddr = tp->mmio_addr;
4772 unsigned long flags;
4773 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 4774 int rx_mode;
1da177e4
LT		 4775 u32 tmp = 0;
4776
4777 if (dev->flags & IFF_PROMISC) {
4778 /* Unconditionally log net taps. */
bf82c189 4779 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 4780 rx_mode =
4781 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4782 AcceptAllPhys;
4783 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 4784 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 4785 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 4786 /* Too many to filter perfectly -- accept all multicasts. */
4787 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4788 mc_filter[1] = mc_filter[0] = 0xffffffff;
4789 } else {
22bedad3 4790 struct netdev_hw_addr *ha;
07d3f51f 4791
1da177e4
LT		 4792 rx_mode = AcceptBroadcast | AcceptMyPhys;
4793 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 4794 netdev_for_each_mc_addr(ha, dev) {
4795 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 4796 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4797 rx_mode |= AcceptMulticast;
4798 }
4799 }
4800
4801 spin_lock_irqsave(&tp->lock, flags);
4802
4803 tmp = rtl8169_rx_config | rx_mode |
4804 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4805
f887cce8 4806 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 4807 u32 data = mc_filter[0];
4808
4809 mc_filter[0] = swab32(mc_filter[1]);
4810 mc_filter[1] = swab32(data);
bcf0bf90
FR		 4811 }
4812
1da177e4 4813 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 4814 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 4815
57a9f236
FR		 4816 RTL_W32(RxConfig, tmp);
4817
1da177e4
LT		 4818 spin_unlock_irqrestore(&tp->lock, flags);
4819}
4820
4821/**
4822 * rtl8169_get_stats - Get rtl8169 read/write statistics
4823 * @dev: The Ethernet Device to get statistics for
4824 *
4825 * Get TX/RX statistics for rtl8169
4826 */
4827static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4828{
4829 struct rtl8169_private *tp = netdev_priv(dev);
4830 void __iomem *ioaddr = tp->mmio_addr;
4831 unsigned long flags;
4832
4833 if (netif_running(dev)) {
4834 spin_lock_irqsave(&tp->lock, flags);
523a6094 4835 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4836 spin_unlock_irqrestore(&tp->lock, flags);
4837 }
5b0384f4 4838
cebf8cc7 4839 return &dev->stats;
1da177e4
LT		 4840}
4841
861ab440 4842static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 4843{
065c27c1 4844 struct rtl8169_private *tp = netdev_priv(dev);
4845
5d06a99f 4846 if (!netif_running(dev))
861ab440 4847 return;
5d06a99f 4848
065c27c1 4849 rtl_pll_power_down(tp);
4850
5d06a99f
FR		 4851 netif_device_detach(dev);
4852 netif_stop_queue(dev);
861ab440
RW		 4853}
4854
4855#ifdef CONFIG_PM
4856
4857static int rtl8169_suspend(struct device *device)
4858{
4859 struct pci_dev *pdev = to_pci_dev(device);
4860 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 4861
861ab440 4862 rtl8169_net_suspend(dev);
1371fa6d 4863
5d06a99f
FR		 4864 return 0;
4865}
4866
e1759441
RW		 4867static void __rtl8169_resume(struct net_device *dev)
4868{
065c27c1 4869 struct rtl8169_private *tp = netdev_priv(dev);
4870
e1759441 4871 netif_device_attach(dev);
065c27c1 4872
4873 rtl_pll_power_up(tp);
4874
e1759441
RW		 4875 rtl8169_schedule_work(dev, rtl8169_reset_task);
4876}
4877
861ab440 4878static int rtl8169_resume(struct device *device)
5d06a99f 4879{
861ab440 4880 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 4881 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 4882 struct rtl8169_private *tp = netdev_priv(dev);
4883
4884 rtl8169_init_phy(dev, tp);
5d06a99f 4885
e1759441
RW		 4886 if (netif_running(dev))
4887 __rtl8169_resume(dev);
5d06a99f 4888
e1759441
RW		 4889 return 0;
4890}
4891
4892static int rtl8169_runtime_suspend(struct device *device)
4893{
4894 struct pci_dev *pdev = to_pci_dev(device);
4895 struct net_device *dev = pci_get_drvdata(pdev);
4896 struct rtl8169_private *tp = netdev_priv(dev);
4897
4898 if (!tp->TxDescArray)
4899 return 0;
4900
4901 spin_lock_irq(&tp->lock);
4902 tp->saved_wolopts = __rtl8169_get_wol(tp);
4903 __rtl8169_set_wol(tp, WAKE_ANY);
4904 spin_unlock_irq(&tp->lock);
4905
4906 rtl8169_net_suspend(dev);
4907
4908 return 0;
4909}
4910
4911static int rtl8169_runtime_resume(struct device *device)
4912{
4913 struct pci_dev *pdev = to_pci_dev(device);
4914 struct net_device *dev = pci_get_drvdata(pdev);
4915 struct rtl8169_private *tp = netdev_priv(dev);
4916
4917 if (!tp->TxDescArray)
4918 return 0;
4919
4920 spin_lock_irq(&tp->lock);
4921 __rtl8169_set_wol(tp, tp->saved_wolopts);
4922 tp->saved_wolopts = 0;
4923 spin_unlock_irq(&tp->lock);
4924
fccec10b
SG		 4925 rtl8169_init_phy(dev, tp);
4926
e1759441 4927 __rtl8169_resume(dev);
5d06a99f 4928
5d06a99f
FR		 4929 return 0;
4930}
4931
e1759441
RW		 4932static int rtl8169_runtime_idle(struct device *device)
4933{
4934 struct pci_dev *pdev = to_pci_dev(device);
4935 struct net_device *dev = pci_get_drvdata(pdev);
4936 struct rtl8169_private *tp = netdev_priv(dev);
4937
e4fbce74 4938 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 4939}
4940
47145210 4941static const struct dev_pm_ops rtl8169_pm_ops = {
861ab440
RW		 4942 .suspend = rtl8169_suspend,
4943 .resume = rtl8169_resume,
4944 .freeze = rtl8169_suspend,
4945 .thaw = rtl8169_resume,
4946 .poweroff = rtl8169_suspend,
4947 .restore = rtl8169_resume,
e1759441
RW		 4948 .runtime_suspend = rtl8169_runtime_suspend,
4949 .runtime_resume = rtl8169_runtime_resume,
4950 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 4951};
4952
4953#define RTL8169_PM_OPS (&rtl8169_pm_ops)
4954
4955#else /* !CONFIG_PM */
4956
4957#define RTL8169_PM_OPS NULL
4958
4959#endif /* !CONFIG_PM */
4960
1765f95d
FR		 4961static void rtl_shutdown(struct pci_dev *pdev)
4962{
861ab440 4963 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 4964 struct rtl8169_private *tp = netdev_priv(dev);
4965 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 4966
4967 rtl8169_net_suspend(dev);
1765f95d 4968
cc098dc7
IV		 4969 /* restore original MAC address */
4970 rtl_rar_set(tp, dev->perm_addr);
4971
4bb3f522 4972 spin_lock_irq(&tp->lock);
4973
4974 rtl8169_asic_down(ioaddr);
4975
4976 spin_unlock_irq(&tp->lock);
4977
861ab440 4978 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 4979 /* WoL fails with some 8168 when the receiver is disabled. */
4980 if (tp->features & RTL_FEATURE_WOL) {
4981 pci_clear_master(pdev);
4982
4983 RTL_W8(ChipCmd, CmdRxEnb);
4984 /* PCI commit */
4985 RTL_R8(ChipCmd);
4986 }
4987
861ab440
RW		 4988 pci_wake_from_d3(pdev, true);
4989 pci_set_power_state(pdev, PCI_D3hot);
4990 }
4991}
5d06a99f 4992
1da177e4
LT		 4993static struct pci_driver rtl8169_pci_driver = {
4994 .name = MODULENAME,
4995 .id_table = rtl8169_pci_tbl,
4996 .probe = rtl8169_init_one,
4997 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 4998 .shutdown = rtl_shutdown,
861ab440 4999 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5000};
5001
07d3f51f 5002static int __init rtl8169_init_module(void)
1da177e4 5003{
29917620 5004 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5005}
5006
07d3f51f 5007static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5008{
5009 pci_unregister_driver(&rtl8169_pci_driver);
5010}
5011
5012module_init(rtl8169_init_module);
5013module_exit(rtl8169_cleanup_module);
Linux kernel - Deliverables
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