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[deliverable/linux.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
865c652d 31#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 32#define MODULENAME "r8169"
33#define PFX MODULENAME ": "
34
35#ifdef RTL8169_DEBUG
36#define assert(expr) \
5b0384f4
FR		 37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 39 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 40 }
06fa7358
JP		 41#define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 43#else
44#define assert(expr) do {} while (0)
45#define dprintk(fmt, args...) do {} while (0)
46#endif /* RTL8169_DEBUG */
47
b57b7e5a 48#define R8169_MSG_DEFAULT \
f0e837d9 49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 50
1da177e4
LT		 51#define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
1da177e4
LT		 54/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
55 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 56static const int multicast_filter_limit = 32;
1da177e4
LT		 57
58/* MAC address length */
59#define MAC_ADDR_LEN 6
60
9c14ceaf 61#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 62#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
63#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
64#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 65#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 66#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
67#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68
69#define R8169_REGS_SIZE 256
70#define R8169_NAPI_WEIGHT 64
71#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
73#define RX_BUF_SIZE 1536 /* Rx Buffer size */
74#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
75#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
76
77#define RTL8169_TX_TIMEOUT (6*HZ)
78#define RTL8169_PHY_TIMEOUT (10*HZ)
79
ea8dbdd1 80#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
81#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 82#define RTL_EEPROM_SIG_ADDR 0x0000
83
1da177e4
LT		 84/* write/read MMIO register */
85#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88#define RTL_R8(reg) readb (ioaddr + (reg))
89#define RTL_R16(reg) readw (ioaddr + (reg))
90#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
91
92enum mac_version {
f21b75e9 93 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 94 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
95 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
96 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
97 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
98 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 99 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 100 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
101 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
102 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
103 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 104 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 105 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
106 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
107 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
108 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
109 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
110 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
111 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
112 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 113 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 114 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 115 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 116 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 117 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 118 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
119 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
120 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
1da177e4
LT		 121};
122
1da177e4
LT		 123#define _R(NAME,MAC,MASK) \
124 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
125
3c6bee1d 126static const struct {
1da177e4
LT		 127 const char *name;
128 u8 mac_version;
129 u32 RxConfigMask; /* Clears the bits supported by this chip */
130} rtl_chip_info[] = {
ba6eb6ee
FR		 131 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
132 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
133 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
134 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
135 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 137 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
138 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
140 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
143 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
144 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 145 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
147 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
148 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9 154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
daf9df6d 155 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
157 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
1da177e4
LT		 158};
159#undef _R
160
bcf0bf90
FR		 161enum cfg_version {
162 RTL_CFG_0 = 0x00,
163 RTL_CFG_1,
164 RTL_CFG_2
165};
166
07ce4064
FR		 167static void rtl_hw_start_8169(struct net_device *);
168static void rtl_hw_start_8168(struct net_device *);
169static void rtl_hw_start_8101(struct net_device *);
170
a3aa1884 171static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
177 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 178 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 179 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
180 { PCI_VENDOR_ID_LINKSYS, 0x1032,
181 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 182 { 0x0001, 0x8168,
183 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 184 {0,},
185};
186
187MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
188
189static int rx_copybreak = 200;
4300e8c7 190static int use_dac;
b57b7e5a
SH		 191static struct {
192 u32 msg_enable;
193} debug = { -1 };
1da177e4 194
07d3f51f
FR		 195enum rtl_registers {
196 MAC0 = 0, /* Ethernet hardware address. */
773d2021 197 MAC4 = 4,
07d3f51f
FR		 198 MAR0 = 8, /* Multicast filter. */
199 CounterAddrLow = 0x10,
200 CounterAddrHigh = 0x14,
201 TxDescStartAddrLow = 0x20,
202 TxDescStartAddrHigh = 0x24,
203 TxHDescStartAddrLow = 0x28,
204 TxHDescStartAddrHigh = 0x2c,
205 FLASH = 0x30,
206 ERSR = 0x36,
207 ChipCmd = 0x37,
208 TxPoll = 0x38,
209 IntrMask = 0x3c,
210 IntrStatus = 0x3e,
211 TxConfig = 0x40,
212 RxConfig = 0x44,
213 RxMissed = 0x4c,
214 Cfg9346 = 0x50,
215 Config0 = 0x51,
216 Config1 = 0x52,
217 Config2 = 0x53,
218 Config3 = 0x54,
219 Config4 = 0x55,
220 Config5 = 0x56,
221 MultiIntr = 0x5c,
222 PHYAR = 0x60,
07d3f51f
FR		 223 PHYstatus = 0x6c,
224 RxMaxSize = 0xda,
225 CPlusCmd = 0xe0,
226 IntrMitigate = 0xe2,
227 RxDescAddrLow = 0xe4,
228 RxDescAddrHigh = 0xe8,
229 EarlyTxThres = 0xec,
230 FuncEvent = 0xf0,
231 FuncEventMask = 0xf4,
232 FuncPresetState = 0xf8,
233 FuncForceEvent = 0xfc,
1da177e4
LT		 234};
235
f162a5d1
FR		 236enum rtl8110_registers {
237 TBICSR = 0x64,
238 TBI_ANAR = 0x68,
239 TBI_LPAR = 0x6a,
240};
241
242enum rtl8168_8101_registers {
243 CSIDR = 0x64,
244 CSIAR = 0x68,
245#define CSIAR_FLAG 0x80000000
246#define CSIAR_WRITE_CMD 0x80000000
247#define CSIAR_BYTE_ENABLE 0x0f
248#define CSIAR_BYTE_ENABLE_SHIFT 12
249#define CSIAR_ADDR_MASK 0x0fff
250
251 EPHYAR = 0x80,
252#define EPHYAR_FLAG 0x80000000
253#define EPHYAR_WRITE_CMD 0x80000000
254#define EPHYAR_REG_MASK 0x1f
255#define EPHYAR_REG_SHIFT 16
256#define EPHYAR_DATA_MASK 0xffff
257 DBG_REG = 0xd1,
258#define FIX_NAK_1 (1 << 4)
259#define FIX_NAK_2 (1 << 3)
daf9df6d 260 EFUSEAR = 0xdc,
261#define EFUSEAR_FLAG 0x80000000
262#define EFUSEAR_WRITE_CMD 0x80000000
263#define EFUSEAR_READ_CMD 0x00000000
264#define EFUSEAR_REG_MASK 0x03ff
265#define EFUSEAR_REG_SHIFT 8
266#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 267};
268
07d3f51f 269enum rtl_register_content {
1da177e4 270 /* InterruptStatusBits */
07d3f51f
FR		 271 SYSErr = 0x8000,
272 PCSTimeout = 0x4000,
273 SWInt = 0x0100,
274 TxDescUnavail = 0x0080,
275 RxFIFOOver = 0x0040,
276 LinkChg = 0x0020,
277 RxOverflow = 0x0010,
278 TxErr = 0x0008,
279 TxOK = 0x0004,
280 RxErr = 0x0002,
281 RxOK = 0x0001,
1da177e4
LT		 282
283 /* RxStatusDesc */
9dccf611
FR		 284 RxFOVF = (1 << 23),
285 RxRWT = (1 << 22),
286 RxRES = (1 << 21),
287 RxRUNT = (1 << 20),
288 RxCRC = (1 << 19),
1da177e4
LT		 289
290 /* ChipCmdBits */
07d3f51f
FR		 291 CmdReset = 0x10,
292 CmdRxEnb = 0x08,
293 CmdTxEnb = 0x04,
294 RxBufEmpty = 0x01,
1da177e4 295
275391a4
FR		 296 /* TXPoll register p.5 */
297 HPQ = 0x80, /* Poll cmd on the high prio queue */
298 NPQ = 0x40, /* Poll cmd on the low prio queue */
299 FSWInt = 0x01, /* Forced software interrupt */
300
1da177e4 301 /* Cfg9346Bits */
07d3f51f
FR		 302 Cfg9346_Lock = 0x00,
303 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 304
305 /* rx_mode_bits */
07d3f51f
FR		 306 AcceptErr = 0x20,
307 AcceptRunt = 0x10,
308 AcceptBroadcast = 0x08,
309 AcceptMulticast = 0x04,
310 AcceptMyPhys = 0x02,
311 AcceptAllPhys = 0x01,
1da177e4
LT		 312
313 /* RxConfigBits */
07d3f51f
FR		 314 RxCfgFIFOShift = 13,
315 RxCfgDMAShift = 8,
1da177e4
LT		 316
317 /* TxConfigBits */
318 TxInterFrameGapShift = 24,
319 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
320
5d06a99f 321 /* Config1 register p.24 */
f162a5d1
FR		 322 LEDS1 = (1 << 7),
323 LEDS0 = (1 << 6),
fbac58fc 324 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 325 Speed_down = (1 << 4),
326 MEMMAP = (1 << 3),
327 IOMAP = (1 << 2),
328 VPD = (1 << 1),
5d06a99f
FR		 329 PMEnable = (1 << 0), /* Power Management Enable */
330
6dccd16b
FR		 331 /* Config2 register p. 25 */
332 PCI_Clock_66MHz = 0x01,
333 PCI_Clock_33MHz = 0x00,
334
61a4dcc2
FR		 335 /* Config3 register p.25 */
336 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
337 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 338 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 339
5d06a99f 340 /* Config5 register p.27 */
61a4dcc2
FR		 341 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
342 MWF = (1 << 5), /* Accept Multicast wakeup frame */
343 UWF = (1 << 4), /* Accept Unicast wakeup frame */
344 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 345 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
346
1da177e4
LT		 347 /* TBICSR p.28 */
348 TBIReset = 0x80000000,
349 TBILoopback = 0x40000000,
350 TBINwEnable = 0x20000000,
351 TBINwRestart = 0x10000000,
352 TBILinkOk = 0x02000000,
353 TBINwComplete = 0x01000000,
354
355 /* CPlusCmd p.31 */
f162a5d1
FR		 356 EnableBist = (1 << 15), // 8168 8101
357 Mac_dbgo_oe = (1 << 14), // 8168 8101
358 Normal_mode = (1 << 13), // unused
359 Force_half_dup = (1 << 12), // 8168 8101
360 Force_rxflow_en = (1 << 11), // 8168 8101
361 Force_txflow_en = (1 << 10), // 8168 8101
362 Cxpl_dbg_sel = (1 << 9), // 8168 8101
363 ASF = (1 << 8), // 8168 8101
364 PktCntrDisable = (1 << 7), // 8168 8101
365 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 366 RxVlan = (1 << 6),
367 RxChkSum = (1 << 5),
368 PCIDAC = (1 << 4),
369 PCIMulRW = (1 << 3),
0e485150
FR		 370 INTT_0 = 0x0000, // 8168
371 INTT_1 = 0x0001, // 8168
372 INTT_2 = 0x0002, // 8168
373 INTT_3 = 0x0003, // 8168
1da177e4
LT		 374
375 /* rtl8169_PHYstatus */
07d3f51f
FR		 376 TBI_Enable = 0x80,
377 TxFlowCtrl = 0x40,
378 RxFlowCtrl = 0x20,
379 _1000bpsF = 0x10,
380 _100bps = 0x08,
381 _10bps = 0x04,
382 LinkStatus = 0x02,
383 FullDup = 0x01,
1da177e4 384
1da177e4 385 /* _TBICSRBit */
07d3f51f 386 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 387
388 /* DumpCounterCommand */
07d3f51f 389 CounterDump = 0x8,
1da177e4
LT		 390};
391
07d3f51f 392enum desc_status_bit {
1da177e4
LT		 393 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
394 RingEnd = (1 << 30), /* End of descriptor ring */
395 FirstFrag = (1 << 29), /* First segment of a packet */
396 LastFrag = (1 << 28), /* Final segment of a packet */
397
398 /* Tx private */
399 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
400 MSSShift = 16, /* MSS value position */
401 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
402 IPCS = (1 << 18), /* Calculate IP checksum */
403 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
404 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
405 TxVlanTag = (1 << 17), /* Add VLAN tag */
406
407 /* Rx private */
408 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
409 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
410
411#define RxProtoUDP (PID1)
412#define RxProtoTCP (PID0)
413#define RxProtoIP (PID1 | PID0)
414#define RxProtoMask RxProtoIP
415
416 IPFail = (1 << 16), /* IP checksum failed */
417 UDPFail = (1 << 15), /* UDP/IP checksum failed */
418 TCPFail = (1 << 14), /* TCP/IP checksum failed */
419 RxVlanTag = (1 << 16), /* VLAN tag available */
420};
421
422#define RsvdMask 0x3fffc000
423
424struct TxDesc {
6cccd6e7
REB		 425 __le32 opts1;
426 __le32 opts2;
427 __le64 addr;
1da177e4
LT		 428};
429
430struct RxDesc {
6cccd6e7
REB		 431 __le32 opts1;
432 __le32 opts2;
433 __le64 addr;
1da177e4
LT		 434};
435
436struct ring_info {
437 struct sk_buff *skb;
438 u32 len;
439 u8 __pad[sizeof(void *) - sizeof(u32)];
440};
441
f23e7fda 442enum features {
ccdffb9a
FR		 443 RTL_FEATURE_WOL = (1 << 0),
444 RTL_FEATURE_MSI = (1 << 1),
445 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 446};
447
355423d0
IV		 448struct rtl8169_counters {
449 __le64 tx_packets;
450 __le64 rx_packets;
451 __le64 tx_errors;
452 __le32 rx_errors;
453 __le16 rx_missed;
454 __le16 align_errors;
455 __le32 tx_one_collision;
456 __le32 tx_multi_collision;
457 __le64 rx_unicast;
458 __le64 rx_broadcast;
459 __le32 rx_multicast;
460 __le16 tx_aborted;
461 __le16 tx_underun;
462};
463
1da177e4
LT		 464struct rtl8169_private {
465 void __iomem *mmio_addr; /* memory map physical address */
466 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 467 struct net_device *dev;
bea3348e 468 struct napi_struct napi;
1da177e4 469 spinlock_t lock; /* spin lock flag */
b57b7e5a 470 u32 msg_enable;
1da177e4
LT		 471 int chipset;
472 int mac_version;
1da177e4
LT		 473 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
474 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
475 u32 dirty_rx;
476 u32 dirty_tx;
477 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
478 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
479 dma_addr_t TxPhyAddr;
480 dma_addr_t RxPhyAddr;
481 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
482 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 483 unsigned align;
1da177e4
LT		 484 unsigned rx_buf_sz;
485 struct timer_list timer;
486 u16 cp_cmd;
0e485150
FR		 487 u16 intr_event;
488 u16 napi_event;
1da177e4 489 u16 intr_mask;
1da177e4
LT		 490 int phy_1000_ctrl_reg;
491#ifdef CONFIG_R8169_VLAN
492 struct vlan_group *vlgrp;
493#endif
494 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 495 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 496 void (*phy_reset_enable)(void __iomem *);
07ce4064 497 void (*hw_start)(struct net_device *);
1da177e4
LT		 498 unsigned int (*phy_reset_pending)(void __iomem *);
499 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 500 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 501 int pcie_cap;
c4028958 502 struct delayed_work task;
f23e7fda 503 unsigned features;
ccdffb9a
FR		 504
505 struct mii_if_info mii;
355423d0 506 struct rtl8169_counters counters;
1da177e4
LT		 507};
508
979b6c13 509MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 510MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 511module_param(rx_copybreak, int, 0);
1b7efd58 512MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4 513module_param(use_dac, int, 0);
4300e8c7 514MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 515module_param_named(debug, debug.msg_enable, int, 0);
516MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 517MODULE_LICENSE("GPL");
518MODULE_VERSION(RTL8169_VERSION);
519
520static int rtl8169_open(struct net_device *dev);
61357325
SH		 521static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
522 struct net_device *dev);
7d12e780 523static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 524static int rtl8169_init_ring(struct net_device *dev);
07ce4064 525static void rtl_hw_start(struct net_device *dev);
1da177e4 526static int rtl8169_close(struct net_device *dev);
07ce4064 527static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 528static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 529static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 530static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 531 void __iomem *, u32 budget);
4dcb7d33 532static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 533static void rtl8169_down(struct net_device *dev);
99f252b0 534static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 535static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 536
1da177e4 537static const unsigned int rtl8169_rx_config =
5b0384f4 538 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 539
07d3f51f 540static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 541{
542 int i;
543
a6baf3af 544 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 545
2371408c 546 for (i = 20; i > 0; i--) {
07d3f51f
FR		 547 /*
548 * Check if the RTL8169 has completed writing to the specified
549 * MII register.
550 */
5b0384f4 551 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 552 break;
2371408c 553 udelay(25);
1da177e4
LT		 554 }
555}
556
07d3f51f 557static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 558{
559 int i, value = -1;
560
a6baf3af 561 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 562
2371408c 563 for (i = 20; i > 0; i--) {
07d3f51f
FR		 564 /*
565 * Check if the RTL8169 has completed retrieving data from
566 * the specified MII register.
567 */
1da177e4 568 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 569 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 570 break;
571 }
2371408c 572 udelay(25);
1da177e4
LT		 573 }
574 return value;
575}
576
dacf8154
FR		 577static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
578{
579 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
580}
581
daf9df6d 582static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
583{
584 int val;
585
586 val = mdio_read(ioaddr, reg_addr);
587 mdio_write(ioaddr, reg_addr, (val | p) & ~m);
588}
589
ccdffb9a
FR		 590static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
591 int val)
592{
593 struct rtl8169_private *tp = netdev_priv(dev);
594 void __iomem *ioaddr = tp->mmio_addr;
595
596 mdio_write(ioaddr, location, val);
597}
598
599static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
600{
601 struct rtl8169_private *tp = netdev_priv(dev);
602 void __iomem *ioaddr = tp->mmio_addr;
603
604 return mdio_read(ioaddr, location);
605}
606
dacf8154
FR		 607static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
608{
609 unsigned int i;
610
611 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
612 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
613
614 for (i = 0; i < 100; i++) {
615 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
616 break;
617 udelay(10);
618 }
619}
620
621static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
622{
623 u16 value = 0xffff;
624 unsigned int i;
625
626 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
627
628 for (i = 0; i < 100; i++) {
629 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
630 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
631 break;
632 }
633 udelay(10);
634 }
635
636 return value;
637}
638
639static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
640{
641 unsigned int i;
642
643 RTL_W32(CSIDR, value);
644 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
645 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
646
647 for (i = 0; i < 100; i++) {
648 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
649 break;
650 udelay(10);
651 }
652}
653
654static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
655{
656 u32 value = ~0x00;
657 unsigned int i;
658
659 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
660 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
661
662 for (i = 0; i < 100; i++) {
663 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
664 value = RTL_R32(CSIDR);
665 break;
666 }
667 udelay(10);
668 }
669
670 return value;
671}
672
daf9df6d 673static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
674{
675 u8 value = 0xff;
676 unsigned int i;
677
678 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
679
680 for (i = 0; i < 300; i++) {
681 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
682 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
683 break;
684 }
685 udelay(100);
686 }
687
688 return value;
689}
690
1da177e4
LT		 691static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
692{
693 RTL_W16(IntrMask, 0x0000);
694
695 RTL_W16(IntrStatus, 0xffff);
696}
697
698static void rtl8169_asic_down(void __iomem *ioaddr)
699{
700 RTL_W8(ChipCmd, 0x00);
701 rtl8169_irq_mask_and_ack(ioaddr);
702 RTL_R16(CPlusCmd);
703}
704
705static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
706{
707 return RTL_R32(TBICSR) & TBIReset;
708}
709
710static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
711{
64e4bfb4 712 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 713}
714
715static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
716{
717 return RTL_R32(TBICSR) & TBILinkOk;
718}
719
720static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
721{
722 return RTL_R8(PHYstatus) & LinkStatus;
723}
724
725static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
726{
727 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
728}
729
730static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
731{
732 unsigned int val;
733
9e0db8ef
FR		 734 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
735 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 736}
737
738static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 739 struct rtl8169_private *tp,
740 void __iomem *ioaddr)
1da177e4
LT		 741{
742 unsigned long flags;
743
744 spin_lock_irqsave(&tp->lock, flags);
745 if (tp->link_ok(ioaddr)) {
746 netif_carrier_on(dev);
bf82c189 747 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 748 } else {
1da177e4 749 netif_carrier_off(dev);
bf82c189 750 netif_info(tp, ifdown, dev, "link down\n");
b57b7e5a 751 }
1da177e4
LT		 752 spin_unlock_irqrestore(&tp->lock, flags);
753}
754
61a4dcc2
FR		 755static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
756{
757 struct rtl8169_private *tp = netdev_priv(dev);
758 void __iomem *ioaddr = tp->mmio_addr;
759 u8 options;
760
761 wol->wolopts = 0;
762
763#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
764 wol->supported = WAKE_ANY;
765
766 spin_lock_irq(&tp->lock);
767
768 options = RTL_R8(Config1);
769 if (!(options & PMEnable))
770 goto out_unlock;
771
772 options = RTL_R8(Config3);
773 if (options & LinkUp)
774 wol->wolopts |= WAKE_PHY;
775 if (options & MagicPacket)
776 wol->wolopts |= WAKE_MAGIC;
777
778 options = RTL_R8(Config5);
779 if (options & UWF)
780 wol->wolopts |= WAKE_UCAST;
781 if (options & BWF)
5b0384f4 782 wol->wolopts |= WAKE_BCAST;
61a4dcc2 783 if (options & MWF)
5b0384f4 784 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 785
786out_unlock:
787 spin_unlock_irq(&tp->lock);
788}
789
790static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
791{
792 struct rtl8169_private *tp = netdev_priv(dev);
793 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 794 unsigned int i;
350f7596 795 static const struct {
61a4dcc2
FR		 796 u32 opt;
797 u16 reg;
798 u8 mask;
799 } cfg[] = {
800 { WAKE_ANY, Config1, PMEnable },
801 { WAKE_PHY, Config3, LinkUp },
802 { WAKE_MAGIC, Config3, MagicPacket },
803 { WAKE_UCAST, Config5, UWF },
804 { WAKE_BCAST, Config5, BWF },
805 { WAKE_MCAST, Config5, MWF },
806 { WAKE_ANY, Config5, LanWake }
807 };
808
809 spin_lock_irq(&tp->lock);
810
811 RTL_W8(Cfg9346, Cfg9346_Unlock);
812
813 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
814 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
815 if (wol->wolopts & cfg[i].opt)
816 options |= cfg[i].mask;
817 RTL_W8(cfg[i].reg, options);
818 }
819
820 RTL_W8(Cfg9346, Cfg9346_Lock);
821
f23e7fda
FR		 822 if (wol->wolopts)
823 tp->features |= RTL_FEATURE_WOL;
824 else
825 tp->features &= ~RTL_FEATURE_WOL;
8b76ab39 826 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
61a4dcc2
FR		 827
828 spin_unlock_irq(&tp->lock);
829
830 return 0;
831}
832
1da177e4
LT		 833static void rtl8169_get_drvinfo(struct net_device *dev,
834 struct ethtool_drvinfo *info)
835{
836 struct rtl8169_private *tp = netdev_priv(dev);
837
838 strcpy(info->driver, MODULENAME);
839 strcpy(info->version, RTL8169_VERSION);
840 strcpy(info->bus_info, pci_name(tp->pci_dev));
841}
842
843static int rtl8169_get_regs_len(struct net_device *dev)
844{
845 return R8169_REGS_SIZE;
846}
847
848static int rtl8169_set_speed_tbi(struct net_device *dev,
849 u8 autoneg, u16 speed, u8 duplex)
850{
851 struct rtl8169_private *tp = netdev_priv(dev);
852 void __iomem *ioaddr = tp->mmio_addr;
853 int ret = 0;
854 u32 reg;
855
856 reg = RTL_R32(TBICSR);
857 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
858 (duplex == DUPLEX_FULL)) {
859 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
860 } else if (autoneg == AUTONEG_ENABLE)
861 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
862 else {
bf82c189
JP		 863 netif_warn(tp, link, dev,
864 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 865 ret = -EOPNOTSUPP;
866 }
867
868 return ret;
869}
870
871static int rtl8169_set_speed_xmii(struct net_device *dev,
872 u8 autoneg, u16 speed, u8 duplex)
873{
874 struct rtl8169_private *tp = netdev_priv(dev);
875 void __iomem *ioaddr = tp->mmio_addr;
3577aa1b 876 int giga_ctrl, bmcr;
1da177e4
LT		 877
878 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 879 int auto_nego;
880
881 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
64e4bfb4
FR		 882 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
883 ADVERTISE_100HALF | ADVERTISE_100FULL);
3577aa1b 884 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 885
3577aa1b 886 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
887 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 888
3577aa1b 889 /* The 8100e/8101e/8102e do Fast Ethernet only. */
890 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
891 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
892 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
893 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
894 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
895 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
896 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
897 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
898 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
bf82c189
JP		 899 } else {
900 netif_info(tp, link, dev,
901 "PHY does not support 1000Mbps\n");
bcf0bf90 902 }
1da177e4 903
3577aa1b 904 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
905
906 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
907 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
908 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
909 /*
910 * Wake up the PHY.
911 * Vendor specific (0x1f) and reserved (0x0e) MII
912 * registers.
913 */
914 mdio_write(ioaddr, 0x1f, 0x0000);
915 mdio_write(ioaddr, 0x0e, 0x0000);
916 }
917
918 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
919 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
920 } else {
921 giga_ctrl = 0;
922
923 if (speed == SPEED_10)
924 bmcr = 0;
925 else if (speed == SPEED_100)
926 bmcr = BMCR_SPEED100;
927 else
928 return -EINVAL;
929
930 if (duplex == DUPLEX_FULL)
931 bmcr |= BMCR_FULLDPLX;
623a1593 932
2584fbc3 933 mdio_write(ioaddr, 0x1f, 0x0000);
2584fbc3
RS		 934 }
935
1da177e4
LT		 936 tp->phy_1000_ctrl_reg = giga_ctrl;
937
3577aa1b 938 mdio_write(ioaddr, MII_BMCR, bmcr);
939
940 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
941 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
942 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
943 mdio_write(ioaddr, 0x17, 0x2138);
944 mdio_write(ioaddr, 0x0e, 0x0260);
945 } else {
946 mdio_write(ioaddr, 0x17, 0x2108);
947 mdio_write(ioaddr, 0x0e, 0x0000);
948 }
949 }
950
1da177e4
LT		 951 return 0;
952}
953
954static int rtl8169_set_speed(struct net_device *dev,
955 u8 autoneg, u16 speed, u8 duplex)
956{
957 struct rtl8169_private *tp = netdev_priv(dev);
958 int ret;
959
960 ret = tp->set_speed(dev, autoneg, speed, duplex);
961
64e4bfb4 962 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 963 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
964
965 return ret;
966}
967
968static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
969{
970 struct rtl8169_private *tp = netdev_priv(dev);
971 unsigned long flags;
972 int ret;
973
974 spin_lock_irqsave(&tp->lock, flags);
975 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
976 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 977
1da177e4
LT		 978 return ret;
979}
980
981static u32 rtl8169_get_rx_csum(struct net_device *dev)
982{
983 struct rtl8169_private *tp = netdev_priv(dev);
984
985 return tp->cp_cmd & RxChkSum;
986}
987
988static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
989{
990 struct rtl8169_private *tp = netdev_priv(dev);
991 void __iomem *ioaddr = tp->mmio_addr;
992 unsigned long flags;
993
994 spin_lock_irqsave(&tp->lock, flags);
995
996 if (data)
997 tp->cp_cmd |= RxChkSum;
998 else
999 tp->cp_cmd &= ~RxChkSum;
1000
1001 RTL_W16(CPlusCmd, tp->cp_cmd);
1002 RTL_R16(CPlusCmd);
1003
1004 spin_unlock_irqrestore(&tp->lock, flags);
1005
1006 return 0;
1007}
1008
1009#ifdef CONFIG_R8169_VLAN
1010
1011static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1012 struct sk_buff *skb)
1013{
1014 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
1015 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1016}
1017
1018static void rtl8169_vlan_rx_register(struct net_device *dev,
1019 struct vlan_group *grp)
1020{
1021 struct rtl8169_private *tp = netdev_priv(dev);
1022 void __iomem *ioaddr = tp->mmio_addr;
1023 unsigned long flags;
1024
1025 spin_lock_irqsave(&tp->lock, flags);
1026 tp->vlgrp = grp;
05af2142
SW		 1027 /*
1028 * Do not disable RxVlan on 8110SCd.
1029 */
1030 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1da177e4
LT		 1031 tp->cp_cmd |= RxVlan;
1032 else
1033 tp->cp_cmd &= ~RxVlan;
1034 RTL_W16(CPlusCmd, tp->cp_cmd);
1035 RTL_R16(CPlusCmd);
1036 spin_unlock_irqrestore(&tp->lock, flags);
1037}
1038
1da177e4
LT		 1039static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1040 struct sk_buff *skb)
1041{
1042 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1043 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1044 int ret;
1045
865c652d
FR		 1046 if (vlgrp && (opts2 & RxVlanTag)) {
1047 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 1048 ret = 0;
1049 } else
1050 ret = -1;
1051 desc->opts2 = 0;
1052 return ret;
1053}
1054
1055#else /* !CONFIG_R8169_VLAN */
1056
1057static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1058 struct sk_buff *skb)
1059{
1060 return 0;
1061}
1062
1063static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1064 struct sk_buff *skb)
1065{
1066 return -1;
1067}
1068
1069#endif
1070
ccdffb9a 1071static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1072{
1073 struct rtl8169_private *tp = netdev_priv(dev);
1074 void __iomem *ioaddr = tp->mmio_addr;
1075 u32 status;
1076
1077 cmd->supported =
1078 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1079 cmd->port = PORT_FIBRE;
1080 cmd->transceiver = XCVR_INTERNAL;
1081
1082 status = RTL_R32(TBICSR);
1083 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1084 cmd->autoneg = !!(status & TBINwEnable);
1085
1086 cmd->speed = SPEED_1000;
1087 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1088
1089 return 0;
1da177e4
LT		 1090}
1091
ccdffb9a 1092static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1093{
1094 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1095
1096 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1097}
1098
1099static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1100{
1101 struct rtl8169_private *tp = netdev_priv(dev);
1102 unsigned long flags;
ccdffb9a 1103 int rc;
1da177e4
LT		 1104
1105 spin_lock_irqsave(&tp->lock, flags);
1106
ccdffb9a 1107 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1108
1109 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1110 return rc;
1da177e4
LT		 1111}
1112
1113static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1114 void *p)
1115{
5b0384f4
FR		 1116 struct rtl8169_private *tp = netdev_priv(dev);
1117 unsigned long flags;
1da177e4 1118
5b0384f4
FR		 1119 if (regs->len > R8169_REGS_SIZE)
1120 regs->len = R8169_REGS_SIZE;
1da177e4 1121
5b0384f4
FR		 1122 spin_lock_irqsave(&tp->lock, flags);
1123 memcpy_fromio(p, tp->mmio_addr, regs->len);
1124 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1125}
1126
b57b7e5a
SH		 1127static u32 rtl8169_get_msglevel(struct net_device *dev)
1128{
1129 struct rtl8169_private *tp = netdev_priv(dev);
1130
1131 return tp->msg_enable;
1132}
1133
1134static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1135{
1136 struct rtl8169_private *tp = netdev_priv(dev);
1137
1138 tp->msg_enable = value;
1139}
1140
d4a3a0fc
SH		 1141static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1142 "tx_packets",
1143 "rx_packets",
1144 "tx_errors",
1145 "rx_errors",
1146 "rx_missed",
1147 "align_errors",
1148 "tx_single_collisions",
1149 "tx_multi_collisions",
1150 "unicast",
1151 "broadcast",
1152 "multicast",
1153 "tx_aborted",
1154 "tx_underrun",
1155};
1156
b9f2c044 1157static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1158{
b9f2c044
JG		 1159 switch (sset) {
1160 case ETH_SS_STATS:
1161 return ARRAY_SIZE(rtl8169_gstrings);
1162 default:
1163 return -EOPNOTSUPP;
1164 }
d4a3a0fc
SH		 1165}
1166
355423d0 1167static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1168{
1169 struct rtl8169_private *tp = netdev_priv(dev);
1170 void __iomem *ioaddr = tp->mmio_addr;
1171 struct rtl8169_counters *counters;
1172 dma_addr_t paddr;
1173 u32 cmd;
355423d0 1174 int wait = 1000;
d4a3a0fc 1175
355423d0
IV		 1176 /*
1177 * Some chips are unable to dump tally counters when the receiver
1178 * is disabled.
1179 */
1180 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1181 return;
d4a3a0fc
SH		 1182
1183 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1184 if (!counters)
1185 return;
1186
1187 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1188 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1189 RTL_W32(CounterAddrLow, cmd);
1190 RTL_W32(CounterAddrLow, cmd | CounterDump);
1191
355423d0
IV		 1192 while (wait--) {
1193 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1194 /* copy updated counters */
1195 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1196 break;
355423d0
IV		 1197 }
1198 udelay(10);
d4a3a0fc
SH		 1199 }
1200
1201 RTL_W32(CounterAddrLow, 0);
1202 RTL_W32(CounterAddrHigh, 0);
1203
d4a3a0fc
SH		 1204 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1205}
1206
355423d0
IV		 1207static void rtl8169_get_ethtool_stats(struct net_device *dev,
1208 struct ethtool_stats *stats, u64 *data)
1209{
1210 struct rtl8169_private *tp = netdev_priv(dev);
1211
1212 ASSERT_RTNL();
1213
1214 rtl8169_update_counters(dev);
1215
1216 data[0] = le64_to_cpu(tp->counters.tx_packets);
1217 data[1] = le64_to_cpu(tp->counters.rx_packets);
1218 data[2] = le64_to_cpu(tp->counters.tx_errors);
1219 data[3] = le32_to_cpu(tp->counters.rx_errors);
1220 data[4] = le16_to_cpu(tp->counters.rx_missed);
1221 data[5] = le16_to_cpu(tp->counters.align_errors);
1222 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1223 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1224 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1225 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1226 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1227 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1228 data[12] = le16_to_cpu(tp->counters.tx_underun);
1229}
1230
d4a3a0fc
SH		 1231static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1232{
1233 switch(stringset) {
1234 case ETH_SS_STATS:
1235 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1236 break;
1237 }
1238}
1239
7282d491 1240static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1241 .get_drvinfo = rtl8169_get_drvinfo,
1242 .get_regs_len = rtl8169_get_regs_len,
1243 .get_link = ethtool_op_get_link,
1244 .get_settings = rtl8169_get_settings,
1245 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1246 .get_msglevel = rtl8169_get_msglevel,
1247 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1248 .get_rx_csum = rtl8169_get_rx_csum,
1249 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1250 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1251 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1252 .set_tso = ethtool_op_set_tso,
1253 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1254 .get_wol = rtl8169_get_wol,
1255 .set_wol = rtl8169_set_wol,
d4a3a0fc 1256 .get_strings = rtl8169_get_strings,
b9f2c044 1257 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1258 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1259};
1260
07d3f51f
FR		 1261static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1262 void __iomem *ioaddr)
1da177e4 1263{
0e485150
FR		 1264 /*
1265 * The driver currently handles the 8168Bf and the 8168Be identically
1266 * but they can be identified more specifically through the test below
1267 * if needed:
1268 *
1269 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1270 *
1271 * Same thing for the 8101Eb and the 8101Ec:
1272 *
1273 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1274 */
350f7596 1275 static const struct {
1da177e4 1276 u32 mask;
e3cf0cc0 1277 u32 val;
1da177e4
LT		 1278 int mac_version;
1279 } mac_info[] = {
5b538df9 1280 /* 8168D family. */
daf9df6d 1281 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1282 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1283 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1284 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1285
ef808d50 1286 /* 8168C family. */
7f3e3d3a 1287 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1288 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1289 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1290 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1291 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1292 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1293 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1294 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1295 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1296
1297 /* 8168B family. */
1298 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1299 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1300 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1301 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1302
1303 /* 8101 family. */
2857ffb7
FR		 1304 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1305 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1306 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1307 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1308 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1309 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1310 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1311 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1312 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1313 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1314 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1315 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1316 /* FIXME: where did these entries come from ? -- FR */
1317 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1318 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1319
1320 /* 8110 family. */
1321 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1322 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1323 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1324 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1325 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1326 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1327
f21b75e9
JD		 1328 /* Catch-all */
1329 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1330 }, *p = mac_info;
1331 u32 reg;
1332
e3cf0cc0
FR		 1333 reg = RTL_R32(TxConfig);
1334 while ((reg & p->mask) != p->val)
1da177e4
LT		 1335 p++;
1336 tp->mac_version = p->mac_version;
1337}
1338
1339static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1340{
bcf0bf90 1341 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1342}
1343
867763c1
FR		 1344struct phy_reg {
1345 u16 reg;
1346 u16 val;
1347};
1348
350f7596 1349static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
867763c1
FR		 1350{
1351 while (len-- > 0) {
1352 mdio_write(ioaddr, regs->reg, regs->val);
1353 regs++;
1354 }
1355}
1356
5615d9f1 1357static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1358{
350f7596 1359 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1360 { 0x1f, 0x0001 },
1361 { 0x06, 0x006e },
1362 { 0x08, 0x0708 },
1363 { 0x15, 0x4000 },
1364 { 0x18, 0x65c7 },
1da177e4 1365
0b9b571d 1366 { 0x1f, 0x0001 },
1367 { 0x03, 0x00a1 },
1368 { 0x02, 0x0008 },
1369 { 0x01, 0x0120 },
1370 { 0x00, 0x1000 },
1371 { 0x04, 0x0800 },
1372 { 0x04, 0x0000 },
1da177e4 1373
0b9b571d 1374 { 0x03, 0xff41 },
1375 { 0x02, 0xdf60 },
1376 { 0x01, 0x0140 },
1377 { 0x00, 0x0077 },
1378 { 0x04, 0x7800 },
1379 { 0x04, 0x7000 },
1380
1381 { 0x03, 0x802f },
1382 { 0x02, 0x4f02 },
1383 { 0x01, 0x0409 },
1384 { 0x00, 0xf0f9 },
1385 { 0x04, 0x9800 },
1386 { 0x04, 0x9000 },
1387
1388 { 0x03, 0xdf01 },
1389 { 0x02, 0xdf20 },
1390 { 0x01, 0xff95 },
1391 { 0x00, 0xba00 },
1392 { 0x04, 0xa800 },
1393 { 0x04, 0xa000 },
1394
1395 { 0x03, 0xff41 },
1396 { 0x02, 0xdf20 },
1397 { 0x01, 0x0140 },
1398 { 0x00, 0x00bb },
1399 { 0x04, 0xb800 },
1400 { 0x04, 0xb000 },
1401
1402 { 0x03, 0xdf41 },
1403 { 0x02, 0xdc60 },
1404 { 0x01, 0x6340 },
1405 { 0x00, 0x007d },
1406 { 0x04, 0xd800 },
1407 { 0x04, 0xd000 },
1408
1409 { 0x03, 0xdf01 },
1410 { 0x02, 0xdf20 },
1411 { 0x01, 0x100a },
1412 { 0x00, 0xa0ff },
1413 { 0x04, 0xf800 },
1414 { 0x04, 0xf000 },
1415
1416 { 0x1f, 0x0000 },
1417 { 0x0b, 0x0000 },
1418 { 0x00, 0x9200 }
1419 };
1da177e4 1420
0b9b571d 1421 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1422}
1423
5615d9f1
FR		 1424static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1425{
350f7596 1426 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1427 { 0x1f, 0x0002 },
1428 { 0x01, 0x90d0 },
1429 { 0x1f, 0x0000 }
1430 };
1431
1432 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1433}
1434
2e955856 1435static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1436 void __iomem *ioaddr)
1437{
1438 struct pci_dev *pdev = tp->pci_dev;
1439 u16 vendor_id, device_id;
1440
1441 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1442 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1443
1444 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1445 return;
1446
1447 mdio_write(ioaddr, 0x1f, 0x0001);
1448 mdio_write(ioaddr, 0x10, 0xf01b);
1449 mdio_write(ioaddr, 0x1f, 0x0000);
1450}
1451
1452static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1453 void __iomem *ioaddr)
1454{
350f7596 1455 static const struct phy_reg phy_reg_init[] = {
2e955856 1456 { 0x1f, 0x0001 },
1457 { 0x04, 0x0000 },
1458 { 0x03, 0x00a1 },
1459 { 0x02, 0x0008 },
1460 { 0x01, 0x0120 },
1461 { 0x00, 0x1000 },
1462 { 0x04, 0x0800 },
1463 { 0x04, 0x9000 },
1464 { 0x03, 0x802f },
1465 { 0x02, 0x4f02 },
1466 { 0x01, 0x0409 },
1467 { 0x00, 0xf099 },
1468 { 0x04, 0x9800 },
1469 { 0x04, 0xa000 },
1470 { 0x03, 0xdf01 },
1471 { 0x02, 0xdf20 },
1472 { 0x01, 0xff95 },
1473 { 0x00, 0xba00 },
1474 { 0x04, 0xa800 },
1475 { 0x04, 0xf000 },
1476 { 0x03, 0xdf01 },
1477 { 0x02, 0xdf20 },
1478 { 0x01, 0x101a },
1479 { 0x00, 0xa0ff },
1480 { 0x04, 0xf800 },
1481 { 0x04, 0x0000 },
1482 { 0x1f, 0x0000 },
1483
1484 { 0x1f, 0x0001 },
1485 { 0x10, 0xf41b },
1486 { 0x14, 0xfb54 },
1487 { 0x18, 0xf5c7 },
1488 { 0x1f, 0x0000 },
1489
1490 { 0x1f, 0x0001 },
1491 { 0x17, 0x0cc0 },
1492 { 0x1f, 0x0000 }
1493 };
1494
1495 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1496
1497 rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1498}
1499
8c7006aa 1500static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1501{
350f7596 1502 static const struct phy_reg phy_reg_init[] = {
8c7006aa 1503 { 0x1f, 0x0001 },
1504 { 0x04, 0x0000 },
1505 { 0x03, 0x00a1 },
1506 { 0x02, 0x0008 },
1507 { 0x01, 0x0120 },
1508 { 0x00, 0x1000 },
1509 { 0x04, 0x0800 },
1510 { 0x04, 0x9000 },
1511 { 0x03, 0x802f },
1512 { 0x02, 0x4f02 },
1513 { 0x01, 0x0409 },
1514 { 0x00, 0xf099 },
1515 { 0x04, 0x9800 },
1516 { 0x04, 0xa000 },
1517 { 0x03, 0xdf01 },
1518 { 0x02, 0xdf20 },
1519 { 0x01, 0xff95 },
1520 { 0x00, 0xba00 },
1521 { 0x04, 0xa800 },
1522 { 0x04, 0xf000 },
1523 { 0x03, 0xdf01 },
1524 { 0x02, 0xdf20 },
1525 { 0x01, 0x101a },
1526 { 0x00, 0xa0ff },
1527 { 0x04, 0xf800 },
1528 { 0x04, 0x0000 },
1529 { 0x1f, 0x0000 },
1530
1531 { 0x1f, 0x0001 },
1532 { 0x0b, 0x8480 },
1533 { 0x1f, 0x0000 },
1534
1535 { 0x1f, 0x0001 },
1536 { 0x18, 0x67c7 },
1537 { 0x04, 0x2000 },
1538 { 0x03, 0x002f },
1539 { 0x02, 0x4360 },
1540 { 0x01, 0x0109 },
1541 { 0x00, 0x3022 },
1542 { 0x04, 0x2800 },
1543 { 0x1f, 0x0000 },
1544
1545 { 0x1f, 0x0001 },
1546 { 0x17, 0x0cc0 },
1547 { 0x1f, 0x0000 }
1548 };
1549
1550 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1551}
1552
236b8082
FR		 1553static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1554{
350f7596 1555 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1556 { 0x10, 0xf41b },
1557 { 0x1f, 0x0000 }
1558 };
1559
1560 mdio_write(ioaddr, 0x1f, 0x0001);
1561 mdio_patch(ioaddr, 0x16, 1 << 0);
1562
1563 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1564}
1565
1566static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1567{
350f7596 1568 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1569 { 0x1f, 0x0001 },
1570 { 0x10, 0xf41b },
1571 { 0x1f, 0x0000 }
1572 };
1573
1574 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1575}
1576
ef3386f0 1577static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
867763c1 1578{
350f7596 1579 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 1580 { 0x1f, 0x0000 },
1581 { 0x1d, 0x0f00 },
1582 { 0x1f, 0x0002 },
1583 { 0x0c, 0x1ec8 },
1584 { 0x1f, 0x0000 }
1585 };
1586
1587 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1588}
1589
ef3386f0
FR		 1590static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1591{
350f7596 1592 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 1593 { 0x1f, 0x0001 },
1594 { 0x1d, 0x3d98 },
1595 { 0x1f, 0x0000 }
1596 };
1597
1598 mdio_write(ioaddr, 0x1f, 0x0000);
1599 mdio_patch(ioaddr, 0x14, 1 << 5);
1600 mdio_patch(ioaddr, 0x0d, 1 << 5);
1601
1602 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1603}
1604
219a1e9d 1605static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
867763c1 1606{
350f7596 1607 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1608 { 0x1f, 0x0001 },
1609 { 0x12, 0x2300 },
867763c1
FR		 1610 { 0x1f, 0x0002 },
1611 { 0x00, 0x88d4 },
1612 { 0x01, 0x82b1 },
1613 { 0x03, 0x7002 },
1614 { 0x08, 0x9e30 },
1615 { 0x09, 0x01f0 },
1616 { 0x0a, 0x5500 },
1617 { 0x0c, 0x00c8 },
1618 { 0x1f, 0x0003 },
1619 { 0x12, 0xc096 },
1620 { 0x16, 0x000a },
f50d4275
FR		 1621 { 0x1f, 0x0000 },
1622 { 0x1f, 0x0000 },
1623 { 0x09, 0x2000 },
1624 { 0x09, 0x0000 }
867763c1
FR		 1625 };
1626
1627 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1628
1629 mdio_patch(ioaddr, 0x14, 1 << 5);
1630 mdio_patch(ioaddr, 0x0d, 1 << 5);
1631 mdio_write(ioaddr, 0x1f, 0x0000);
867763c1
FR		 1632}
1633
219a1e9d 1634static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
7da97ec9 1635{
350f7596 1636 static const struct phy_reg phy_reg_init[] = {
f50d4275 1637 { 0x1f, 0x0001 },
7da97ec9 1638 { 0x12, 0x2300 },
f50d4275
FR		 1639 { 0x03, 0x802f },
1640 { 0x02, 0x4f02 },
1641 { 0x01, 0x0409 },
1642 { 0x00, 0xf099 },
1643 { 0x04, 0x9800 },
1644 { 0x04, 0x9000 },
1645 { 0x1d, 0x3d98 },
7da97ec9
FR		 1646 { 0x1f, 0x0002 },
1647 { 0x0c, 0x7eb8 },
f50d4275
FR		 1648 { 0x06, 0x0761 },
1649 { 0x1f, 0x0003 },
1650 { 0x16, 0x0f0a },
7da97ec9
FR		 1651 { 0x1f, 0x0000 }
1652 };
1653
1654 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1655
1656 mdio_patch(ioaddr, 0x16, 1 << 0);
1657 mdio_patch(ioaddr, 0x14, 1 << 5);
1658 mdio_patch(ioaddr, 0x0d, 1 << 5);
1659 mdio_write(ioaddr, 0x1f, 0x0000);
7da97ec9
FR		 1660}
1661
197ff761
FR		 1662static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1663{
350f7596 1664 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 1665 { 0x1f, 0x0001 },
1666 { 0x12, 0x2300 },
1667 { 0x1d, 0x3d98 },
1668 { 0x1f, 0x0002 },
1669 { 0x0c, 0x7eb8 },
1670 { 0x06, 0x5461 },
1671 { 0x1f, 0x0003 },
1672 { 0x16, 0x0f0a },
1673 { 0x1f, 0x0000 }
1674 };
1675
1676 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1677
1678 mdio_patch(ioaddr, 0x16, 1 << 0);
1679 mdio_patch(ioaddr, 0x14, 1 << 5);
1680 mdio_patch(ioaddr, 0x0d, 1 << 5);
1681 mdio_write(ioaddr, 0x1f, 0x0000);
1682}
1683
6fb07058
FR		 1684static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1685{
1686 rtl8168c_3_hw_phy_config(ioaddr);
1687}
1688
daf9df6d 1689static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
5b538df9 1690{
350f7596 1691 static const struct phy_reg phy_reg_init_0[] = {
5b538df9 1692 { 0x1f, 0x0001 },
daf9df6d 1693 { 0x06, 0x4064 },
1694 { 0x07, 0x2863 },
1695 { 0x08, 0x059c },
1696 { 0x09, 0x26b4 },
1697 { 0x0a, 0x6a19 },
1698 { 0x0b, 0xdcc8 },
1699 { 0x10, 0xf06d },
1700 { 0x14, 0x7f68 },
1701 { 0x18, 0x7fd9 },
1702 { 0x1c, 0xf0ff },
1703 { 0x1d, 0x3d9c },
5b538df9 1704 { 0x1f, 0x0003 },
daf9df6d 1705 { 0x12, 0xf49f },
1706 { 0x13, 0x070b },
1707 { 0x1a, 0x05ad },
1708 { 0x14, 0x94c0 }
1709 };
350f7596 1710 static const struct phy_reg phy_reg_init_1[] = {
5b538df9 1711 { 0x1f, 0x0002 },
daf9df6d 1712 { 0x06, 0x5561 },
1713 { 0x1f, 0x0005 },
1714 { 0x05, 0x8332 },
1715 { 0x06, 0x5561 }
1716 };
350f7596 1717 static const struct phy_reg phy_reg_init_2[] = {
daf9df6d 1718 { 0x1f, 0x0005 },
1719 { 0x05, 0xffc2 },
1720 { 0x1f, 0x0005 },
1721 { 0x05, 0x8000 },
1722 { 0x06, 0xf8f9 },
1723 { 0x06, 0xfaef },
1724 { 0x06, 0x59ee },
1725 { 0x06, 0xf8ea },
1726 { 0x06, 0x00ee },
1727 { 0x06, 0xf8eb },
1728 { 0x06, 0x00e0 },
1729 { 0x06, 0xf87c },
1730 { 0x06, 0xe1f8 },
1731 { 0x06, 0x7d59 },
1732 { 0x06, 0x0fef },
1733 { 0x06, 0x0139 },
1734 { 0x06, 0x029e },
1735 { 0x06, 0x06ef },
1736 { 0x06, 0x1039 },
1737 { 0x06, 0x089f },
1738 { 0x06, 0x2aee },
1739 { 0x06, 0xf8ea },
1740 { 0x06, 0x00ee },
1741 { 0x06, 0xf8eb },
1742 { 0x06, 0x01e0 },
1743 { 0x06, 0xf87c },
1744 { 0x06, 0xe1f8 },
1745 { 0x06, 0x7d58 },
1746 { 0x06, 0x409e },
1747 { 0x06, 0x0f39 },
1748 { 0x06, 0x46aa },
1749 { 0x06, 0x0bbf },
1750 { 0x06, 0x8290 },
1751 { 0x06, 0xd682 },
1752 { 0x06, 0x9802 },
1753 { 0x06, 0x014f },
1754 { 0x06, 0xae09 },
1755 { 0x06, 0xbf82 },
1756 { 0x06, 0x98d6 },
1757 { 0x06, 0x82a0 },
1758 { 0x06, 0x0201 },
1759 { 0x06, 0x4fef },
1760 { 0x06, 0x95fe },
1761 { 0x06, 0xfdfc },
1762 { 0x06, 0x05f8 },
1763 { 0x06, 0xf9fa },
1764 { 0x06, 0xeef8 },
1765 { 0x06, 0xea00 },
1766 { 0x06, 0xeef8 },
1767 { 0x06, 0xeb00 },
1768 { 0x06, 0xe2f8 },
1769 { 0x06, 0x7ce3 },
1770 { 0x06, 0xf87d },
1771 { 0x06, 0xa511 },
1772 { 0x06, 0x1112 },
1773 { 0x06, 0xd240 },
1774 { 0x06, 0xd644 },
1775 { 0x06, 0x4402 },
1776 { 0x06, 0x8217 },
1777 { 0x06, 0xd2a0 },
1778 { 0x06, 0xd6aa },
1779 { 0x06, 0xaa02 },
1780 { 0x06, 0x8217 },
1781 { 0x06, 0xae0f },
1782 { 0x06, 0xa544 },
1783 { 0x06, 0x4402 },
1784 { 0x06, 0xae4d },
1785 { 0x06, 0xa5aa },
1786 { 0x06, 0xaa02 },
1787 { 0x06, 0xae47 },
1788 { 0x06, 0xaf82 },
1789 { 0x06, 0x13ee },
1790 { 0x06, 0x834e },
1791 { 0x06, 0x00ee },
1792 { 0x06, 0x834d },
1793 { 0x06, 0x0fee },
1794 { 0x06, 0x834c },
1795 { 0x06, 0x0fee },
1796 { 0x06, 0x834f },
1797 { 0x06, 0x00ee },
1798 { 0x06, 0x8351 },
1799 { 0x06, 0x00ee },
1800 { 0x06, 0x834a },
1801 { 0x06, 0xffee },
1802 { 0x06, 0x834b },
1803 { 0x06, 0xffe0 },
1804 { 0x06, 0x8330 },
1805 { 0x06, 0xe183 },
1806 { 0x06, 0x3158 },
1807 { 0x06, 0xfee4 },
1808 { 0x06, 0xf88a },
1809 { 0x06, 0xe5f8 },
1810 { 0x06, 0x8be0 },
1811 { 0x06, 0x8332 },
1812 { 0x06, 0xe183 },
1813 { 0x06, 0x3359 },
1814 { 0x06, 0x0fe2 },
1815 { 0x06, 0x834d },
1816 { 0x06, 0x0c24 },
1817 { 0x06, 0x5af0 },
1818 { 0x06, 0x1e12 },
1819 { 0x06, 0xe4f8 },
1820 { 0x06, 0x8ce5 },
1821 { 0x06, 0xf88d },
1822 { 0x06, 0xaf82 },
1823 { 0x06, 0x13e0 },
1824 { 0x06, 0x834f },
1825 { 0x06, 0x10e4 },
1826 { 0x06, 0x834f },
1827 { 0x06, 0xe083 },
1828 { 0x06, 0x4e78 },
1829 { 0x06, 0x009f },
1830 { 0x06, 0x0ae0 },
1831 { 0x06, 0x834f },
1832 { 0x06, 0xa010 },
1833 { 0x06, 0xa5ee },
1834 { 0x06, 0x834e },
1835 { 0x06, 0x01e0 },
1836 { 0x06, 0x834e },
1837 { 0x06, 0x7805 },
1838 { 0x06, 0x9e9a },
1839 { 0x06, 0xe083 },
1840 { 0x06, 0x4e78 },
1841 { 0x06, 0x049e },
1842 { 0x06, 0x10e0 },
1843 { 0x06, 0x834e },
1844 { 0x06, 0x7803 },
1845 { 0x06, 0x9e0f },
1846 { 0x06, 0xe083 },
1847 { 0x06, 0x4e78 },
1848 { 0x06, 0x019e },
1849 { 0x06, 0x05ae },
1850 { 0x06, 0x0caf },
1851 { 0x06, 0x81f8 },
1852 { 0x06, 0xaf81 },
1853 { 0x06, 0xa3af },
1854 { 0x06, 0x81dc },
1855 { 0x06, 0xaf82 },
1856 { 0x06, 0x13ee },
1857 { 0x06, 0x8348 },
1858 { 0x06, 0x00ee },
1859 { 0x06, 0x8349 },
1860 { 0x06, 0x00e0 },
1861 { 0x06, 0x8351 },
1862 { 0x06, 0x10e4 },
1863 { 0x06, 0x8351 },
1864 { 0x06, 0x5801 },
1865 { 0x06, 0x9fea },
1866 { 0x06, 0xd000 },
1867 { 0x06, 0xd180 },
1868 { 0x06, 0x1f66 },
1869 { 0x06, 0xe2f8 },
1870 { 0x06, 0xeae3 },
1871 { 0x06, 0xf8eb },
1872 { 0x06, 0x5af8 },
1873 { 0x06, 0x1e20 },
1874 { 0x06, 0xe6f8 },
1875 { 0x06, 0xeae5 },
1876 { 0x06, 0xf8eb },
1877 { 0x06, 0xd302 },
1878 { 0x06, 0xb3fe },
1879 { 0x06, 0xe2f8 },
1880 { 0x06, 0x7cef },
1881 { 0x06, 0x325b },
1882 { 0x06, 0x80e3 },
1883 { 0x06, 0xf87d },
1884 { 0x06, 0x9e03 },
1885 { 0x06, 0x7dff },
1886 { 0x06, 0xff0d },
1887 { 0x06, 0x581c },
1888 { 0x06, 0x551a },
1889 { 0x06, 0x6511 },
1890 { 0x06, 0xa190 },
1891 { 0x06, 0xd3e2 },
1892 { 0x06, 0x8348 },
1893 { 0x06, 0xe383 },
1894 { 0x06, 0x491b },
1895 { 0x06, 0x56ab },
1896 { 0x06, 0x08ef },
1897 { 0x06, 0x56e6 },
1898 { 0x06, 0x8348 },
1899 { 0x06, 0xe783 },
1900 { 0x06, 0x4910 },
1901 { 0x06, 0xd180 },
1902 { 0x06, 0x1f66 },
1903 { 0x06, 0xa004 },
1904 { 0x06, 0xb9e2 },
1905 { 0x06, 0x8348 },
1906 { 0x06, 0xe383 },
1907 { 0x06, 0x49ef },
1908 { 0x06, 0x65e2 },
1909 { 0x06, 0x834a },
1910 { 0x06, 0xe383 },
1911 { 0x06, 0x4b1b },
1912 { 0x06, 0x56aa },
1913 { 0x06, 0x0eef },
1914 { 0x06, 0x56e6 },
1915 { 0x06, 0x834a },
1916 { 0x06, 0xe783 },
1917 { 0x06, 0x4be2 },
1918 { 0x06, 0x834d },
1919 { 0x06, 0xe683 },
1920 { 0x06, 0x4ce0 },
1921 { 0x06, 0x834d },
1922 { 0x06, 0xa000 },
1923 { 0x06, 0x0caf },
1924 { 0x06, 0x81dc },
1925 { 0x06, 0xe083 },
1926 { 0x06, 0x4d10 },
1927 { 0x06, 0xe483 },
1928 { 0x06, 0x4dae },
1929 { 0x06, 0x0480 },
1930 { 0x06, 0xe483 },
1931 { 0x06, 0x4de0 },
1932 { 0x06, 0x834e },
1933 { 0x06, 0x7803 },
1934 { 0x06, 0x9e0b },
1935 { 0x06, 0xe083 },
1936 { 0x06, 0x4e78 },
1937 { 0x06, 0x049e },
1938 { 0x06, 0x04ee },
1939 { 0x06, 0x834e },
1940 { 0x06, 0x02e0 },
1941 { 0x06, 0x8332 },
1942 { 0x06, 0xe183 },
1943 { 0x06, 0x3359 },
1944 { 0x06, 0x0fe2 },
1945 { 0x06, 0x834d },
1946 { 0x06, 0x0c24 },
1947 { 0x06, 0x5af0 },
1948 { 0x06, 0x1e12 },
1949 { 0x06, 0xe4f8 },
1950 { 0x06, 0x8ce5 },
1951 { 0x06, 0xf88d },
1952 { 0x06, 0xe083 },
1953 { 0x06, 0x30e1 },
1954 { 0x06, 0x8331 },
1955 { 0x06, 0x6801 },
1956 { 0x06, 0xe4f8 },
1957 { 0x06, 0x8ae5 },
1958 { 0x06, 0xf88b },
1959 { 0x06, 0xae37 },
1960 { 0x06, 0xee83 },
1961 { 0x06, 0x4e03 },
1962 { 0x06, 0xe083 },
1963 { 0x06, 0x4ce1 },
1964 { 0x06, 0x834d },
1965 { 0x06, 0x1b01 },
1966 { 0x06, 0x9e04 },
1967 { 0x06, 0xaaa1 },
1968 { 0x06, 0xaea8 },
1969 { 0x06, 0xee83 },
1970 { 0x06, 0x4e04 },
1971 { 0x06, 0xee83 },
1972 { 0x06, 0x4f00 },
1973 { 0x06, 0xaeab },
1974 { 0x06, 0xe083 },
1975 { 0x06, 0x4f78 },
1976 { 0x06, 0x039f },
1977 { 0x06, 0x14ee },
1978 { 0x06, 0x834e },
1979 { 0x06, 0x05d2 },
1980 { 0x06, 0x40d6 },
1981 { 0x06, 0x5554 },
1982 { 0x06, 0x0282 },
1983 { 0x06, 0x17d2 },
1984 { 0x06, 0xa0d6 },
1985 { 0x06, 0xba00 },
1986 { 0x06, 0x0282 },
1987 { 0x06, 0x17fe },
1988 { 0x06, 0xfdfc },
1989 { 0x06, 0x05f8 },
1990 { 0x06, 0xe0f8 },
1991 { 0x06, 0x60e1 },
1992 { 0x06, 0xf861 },
1993 { 0x06, 0x6802 },
1994 { 0x06, 0xe4f8 },
1995 { 0x06, 0x60e5 },
1996 { 0x06, 0xf861 },
1997 { 0x06, 0xe0f8 },
1998 { 0x06, 0x48e1 },
1999 { 0x06, 0xf849 },
2000 { 0x06, 0x580f },
2001 { 0x06, 0x1e02 },
2002 { 0x06, 0xe4f8 },
2003 { 0x06, 0x48e5 },
2004 { 0x06, 0xf849 },
2005 { 0x06, 0xd000 },
2006 { 0x06, 0x0282 },
2007 { 0x06, 0x5bbf },
2008 { 0x06, 0x8350 },
2009 { 0x06, 0xef46 },
2010 { 0x06, 0xdc19 },
2011 { 0x06, 0xddd0 },
2012 { 0x06, 0x0102 },
2013 { 0x06, 0x825b },
2014 { 0x06, 0x0282 },
2015 { 0x06, 0x77e0 },
2016 { 0x06, 0xf860 },
2017 { 0x06, 0xe1f8 },
2018 { 0x06, 0x6158 },
2019 { 0x06, 0xfde4 },
2020 { 0x06, 0xf860 },
2021 { 0x06, 0xe5f8 },
2022 { 0x06, 0x61fc },
2023 { 0x06, 0x04f9 },
2024 { 0x06, 0xfafb },
2025 { 0x06, 0xc6bf },
2026 { 0x06, 0xf840 },
2027 { 0x06, 0xbe83 },
2028 { 0x06, 0x50a0 },
2029 { 0x06, 0x0101 },
2030 { 0x06, 0x071b },
2031 { 0x06, 0x89cf },
2032 { 0x06, 0xd208 },
2033 { 0x06, 0xebdb },
2034 { 0x06, 0x19b2 },
2035 { 0x06, 0xfbff },
2036 { 0x06, 0xfefd },
2037 { 0x06, 0x04f8 },
2038 { 0x06, 0xe0f8 },
2039 { 0x06, 0x48e1 },
2040 { 0x06, 0xf849 },
2041 { 0x06, 0x6808 },
2042 { 0x06, 0xe4f8 },
2043 { 0x06, 0x48e5 },
2044 { 0x06, 0xf849 },
2045 { 0x06, 0x58f7 },
2046 { 0x06, 0xe4f8 },
2047 { 0x06, 0x48e5 },
2048 { 0x06, 0xf849 },
2049 { 0x06, 0xfc04 },
2050 { 0x06, 0x4d20 },
2051 { 0x06, 0x0002 },
2052 { 0x06, 0x4e22 },
2053 { 0x06, 0x0002 },
2054 { 0x06, 0x4ddf },
2055 { 0x06, 0xff01 },
2056 { 0x06, 0x4edd },
2057 { 0x06, 0xff01 },
2058 { 0x05, 0x83d4 },
2059 { 0x06, 0x8000 },
2060 { 0x05, 0x83d8 },
2061 { 0x06, 0x8051 },
2062 { 0x02, 0x6010 },
2063 { 0x03, 0xdc00 },
2064 { 0x05, 0xfff6 },
2065 { 0x06, 0x00fc },
5b538df9 2066 { 0x1f, 0x0000 },
daf9df6d 2067
5b538df9 2068 { 0x1f, 0x0000 },
daf9df6d 2069 { 0x0d, 0xf880 },
2070 { 0x1f, 0x0000 }
2071 };
2072
2073 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2074
2075 mdio_write(ioaddr, 0x1f, 0x0002);
2076 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2077 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2078
2079 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2080
2081 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2082 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2083 { 0x1f, 0x0002 },
2084 { 0x05, 0x669a },
2085 { 0x1f, 0x0005 },
2086 { 0x05, 0x8330 },
2087 { 0x06, 0x669a },
2088 { 0x1f, 0x0002 }
2089 };
2090 int val;
2091
2092 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2093
2094 val = mdio_read(ioaddr, 0x0d);
2095
2096 if ((val & 0x00ff) != 0x006c) {
350f7596 2097 static const u32 set[] = {
daf9df6d 2098 0x0065, 0x0066, 0x0067, 0x0068,
2099 0x0069, 0x006a, 0x006b, 0x006c
2100 };
2101 int i;
2102
2103 mdio_write(ioaddr, 0x1f, 0x0002);
2104
2105 val &= 0xff00;
2106 for (i = 0; i < ARRAY_SIZE(set); i++)
2107 mdio_write(ioaddr, 0x0d, val | set[i]);
2108 }
2109 } else {
350f7596 2110 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2111 { 0x1f, 0x0002 },
2112 { 0x05, 0x6662 },
2113 { 0x1f, 0x0005 },
2114 { 0x05, 0x8330 },
2115 { 0x06, 0x6662 }
2116 };
2117
2118 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2119 }
2120
2121 mdio_write(ioaddr, 0x1f, 0x0002);
2122 mdio_patch(ioaddr, 0x0d, 0x0300);
2123 mdio_patch(ioaddr, 0x0f, 0x0010);
2124
2125 mdio_write(ioaddr, 0x1f, 0x0002);
2126 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2127 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2128
2129 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
2130}
2131
2132static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2133{
350f7596 2134 static const struct phy_reg phy_reg_init_0[] = {
daf9df6d 2135 { 0x1f, 0x0001 },
2136 { 0x06, 0x4064 },
2137 { 0x07, 0x2863 },
2138 { 0x08, 0x059c },
2139 { 0x09, 0x26b4 },
2140 { 0x0a, 0x6a19 },
2141 { 0x0b, 0xdcc8 },
2142 { 0x10, 0xf06d },
2143 { 0x14, 0x7f68 },
2144 { 0x18, 0x7fd9 },
2145 { 0x1c, 0xf0ff },
2146 { 0x1d, 0x3d9c },
2147 { 0x1f, 0x0003 },
2148 { 0x12, 0xf49f },
2149 { 0x13, 0x070b },
2150 { 0x1a, 0x05ad },
2151 { 0x14, 0x94c0 },
2152
2153 { 0x1f, 0x0002 },
2154 { 0x06, 0x5561 },
2155 { 0x1f, 0x0005 },
2156 { 0x05, 0x8332 },
2157 { 0x06, 0x5561 }
2158 };
350f7596 2159 static const struct phy_reg phy_reg_init_1[] = {
daf9df6d 2160 { 0x1f, 0x0005 },
2161 { 0x05, 0xffc2 },
5b538df9 2162 { 0x1f, 0x0005 },
daf9df6d 2163 { 0x05, 0x8000 },
2164 { 0x06, 0xf8f9 },
2165 { 0x06, 0xfaee },
2166 { 0x06, 0xf8ea },
2167 { 0x06, 0x00ee },
2168 { 0x06, 0xf8eb },
2169 { 0x06, 0x00e2 },
2170 { 0x06, 0xf87c },
2171 { 0x06, 0xe3f8 },
2172 { 0x06, 0x7da5 },
2173 { 0x06, 0x1111 },
2174 { 0x06, 0x12d2 },
2175 { 0x06, 0x40d6 },
2176 { 0x06, 0x4444 },
2177 { 0x06, 0x0281 },
2178 { 0x06, 0xc6d2 },
2179 { 0x06, 0xa0d6 },
2180 { 0x06, 0xaaaa },
2181 { 0x06, 0x0281 },
2182 { 0x06, 0xc6ae },
2183 { 0x06, 0x0fa5 },
2184 { 0x06, 0x4444 },
2185 { 0x06, 0x02ae },
2186 { 0x06, 0x4da5 },
2187 { 0x06, 0xaaaa },
2188 { 0x06, 0x02ae },
2189 { 0x06, 0x47af },
2190 { 0x06, 0x81c2 },
2191 { 0x06, 0xee83 },
2192 { 0x06, 0x4e00 },
2193 { 0x06, 0xee83 },
2194 { 0x06, 0x4d0f },
2195 { 0x06, 0xee83 },
2196 { 0x06, 0x4c0f },
2197 { 0x06, 0xee83 },
2198 { 0x06, 0x4f00 },
2199 { 0x06, 0xee83 },
2200 { 0x06, 0x5100 },
2201 { 0x06, 0xee83 },
2202 { 0x06, 0x4aff },
2203 { 0x06, 0xee83 },
2204 { 0x06, 0x4bff },
2205 { 0x06, 0xe083 },
2206 { 0x06, 0x30e1 },
2207 { 0x06, 0x8331 },
2208 { 0x06, 0x58fe },
2209 { 0x06, 0xe4f8 },
2210 { 0x06, 0x8ae5 },
2211 { 0x06, 0xf88b },
2212 { 0x06, 0xe083 },
2213 { 0x06, 0x32e1 },
2214 { 0x06, 0x8333 },
2215 { 0x06, 0x590f },
2216 { 0x06, 0xe283 },
2217 { 0x06, 0x4d0c },
2218 { 0x06, 0x245a },
2219 { 0x06, 0xf01e },
2220 { 0x06, 0x12e4 },
2221 { 0x06, 0xf88c },
2222 { 0x06, 0xe5f8 },
2223 { 0x06, 0x8daf },
2224 { 0x06, 0x81c2 },
2225 { 0x06, 0xe083 },
2226 { 0x06, 0x4f10 },
2227 { 0x06, 0xe483 },
2228 { 0x06, 0x4fe0 },
2229 { 0x06, 0x834e },
2230 { 0x06, 0x7800 },
2231 { 0x06, 0x9f0a },
2232 { 0x06, 0xe083 },
2233 { 0x06, 0x4fa0 },
2234 { 0x06, 0x10a5 },
2235 { 0x06, 0xee83 },
2236 { 0x06, 0x4e01 },
2237 { 0x06, 0xe083 },
2238 { 0x06, 0x4e78 },
2239 { 0x06, 0x059e },
2240 { 0x06, 0x9ae0 },
2241 { 0x06, 0x834e },
2242 { 0x06, 0x7804 },
2243 { 0x06, 0x9e10 },
2244 { 0x06, 0xe083 },
2245 { 0x06, 0x4e78 },
2246 { 0x06, 0x039e },
2247 { 0x06, 0x0fe0 },
2248 { 0x06, 0x834e },
2249 { 0x06, 0x7801 },
2250 { 0x06, 0x9e05 },
2251 { 0x06, 0xae0c },
2252 { 0x06, 0xaf81 },
2253 { 0x06, 0xa7af },
2254 { 0x06, 0x8152 },
2255 { 0x06, 0xaf81 },
2256 { 0x06, 0x8baf },
2257 { 0x06, 0x81c2 },
2258 { 0x06, 0xee83 },
2259 { 0x06, 0x4800 },
2260 { 0x06, 0xee83 },
2261 { 0x06, 0x4900 },
2262 { 0x06, 0xe083 },
2263 { 0x06, 0x5110 },
2264 { 0x06, 0xe483 },
2265 { 0x06, 0x5158 },
2266 { 0x06, 0x019f },
2267 { 0x06, 0xead0 },
2268 { 0x06, 0x00d1 },
2269 { 0x06, 0x801f },
2270 { 0x06, 0x66e2 },
2271 { 0x06, 0xf8ea },
2272 { 0x06, 0xe3f8 },
2273 { 0x06, 0xeb5a },
2274 { 0x06, 0xf81e },
2275 { 0x06, 0x20e6 },
2276 { 0x06, 0xf8ea },
2277 { 0x06, 0xe5f8 },
2278 { 0x06, 0xebd3 },
2279 { 0x06, 0x02b3 },
2280 { 0x06, 0xfee2 },
2281 { 0x06, 0xf87c },
2282 { 0x06, 0xef32 },
2283 { 0x06, 0x5b80 },
2284 { 0x06, 0xe3f8 },
2285 { 0x06, 0x7d9e },
2286 { 0x06, 0x037d },
2287 { 0x06, 0xffff },
2288 { 0x06, 0x0d58 },
2289 { 0x06, 0x1c55 },
2290 { 0x06, 0x1a65 },
2291 { 0x06, 0x11a1 },
2292 { 0x06, 0x90d3 },
2293 { 0x06, 0xe283 },
2294 { 0x06, 0x48e3 },
2295 { 0x06, 0x8349 },
2296 { 0x06, 0x1b56 },
2297 { 0x06, 0xab08 },
2298 { 0x06, 0xef56 },
2299 { 0x06, 0xe683 },
2300 { 0x06, 0x48e7 },
2301 { 0x06, 0x8349 },
2302 { 0x06, 0x10d1 },
2303 { 0x06, 0x801f },
2304 { 0x06, 0x66a0 },
2305 { 0x06, 0x04b9 },
2306 { 0x06, 0xe283 },
2307 { 0x06, 0x48e3 },
2308 { 0x06, 0x8349 },
2309 { 0x06, 0xef65 },
2310 { 0x06, 0xe283 },
2311 { 0x06, 0x4ae3 },
2312 { 0x06, 0x834b },
2313 { 0x06, 0x1b56 },
2314 { 0x06, 0xaa0e },
2315 { 0x06, 0xef56 },
2316 { 0x06, 0xe683 },
2317 { 0x06, 0x4ae7 },
2318 { 0x06, 0x834b },
2319 { 0x06, 0xe283 },
2320 { 0x06, 0x4de6 },
2321 { 0x06, 0x834c },
2322 { 0x06, 0xe083 },
2323 { 0x06, 0x4da0 },
2324 { 0x06, 0x000c },
2325 { 0x06, 0xaf81 },
2326 { 0x06, 0x8be0 },
2327 { 0x06, 0x834d },
2328 { 0x06, 0x10e4 },
2329 { 0x06, 0x834d },
2330 { 0x06, 0xae04 },
2331 { 0x06, 0x80e4 },
2332 { 0x06, 0x834d },
2333 { 0x06, 0xe083 },
2334 { 0x06, 0x4e78 },
2335 { 0x06, 0x039e },
2336 { 0x06, 0x0be0 },
2337 { 0x06, 0x834e },
2338 { 0x06, 0x7804 },
2339 { 0x06, 0x9e04 },
2340 { 0x06, 0xee83 },
2341 { 0x06, 0x4e02 },
2342 { 0x06, 0xe083 },
2343 { 0x06, 0x32e1 },
2344 { 0x06, 0x8333 },
2345 { 0x06, 0x590f },
2346 { 0x06, 0xe283 },
2347 { 0x06, 0x4d0c },
2348 { 0x06, 0x245a },
2349 { 0x06, 0xf01e },
2350 { 0x06, 0x12e4 },
2351 { 0x06, 0xf88c },
2352 { 0x06, 0xe5f8 },
2353 { 0x06, 0x8de0 },
2354 { 0x06, 0x8330 },
2355 { 0x06, 0xe183 },
2356 { 0x06, 0x3168 },
2357 { 0x06, 0x01e4 },
2358 { 0x06, 0xf88a },
2359 { 0x06, 0xe5f8 },
2360 { 0x06, 0x8bae },
2361 { 0x06, 0x37ee },
2362 { 0x06, 0x834e },
2363 { 0x06, 0x03e0 },
2364 { 0x06, 0x834c },
2365 { 0x06, 0xe183 },
2366 { 0x06, 0x4d1b },
2367 { 0x06, 0x019e },
2368 { 0x06, 0x04aa },
2369 { 0x06, 0xa1ae },
2370 { 0x06, 0xa8ee },
2371 { 0x06, 0x834e },
2372 { 0x06, 0x04ee },
2373 { 0x06, 0x834f },
2374 { 0x06, 0x00ae },
2375 { 0x06, 0xabe0 },
2376 { 0x06, 0x834f },
2377 { 0x06, 0x7803 },
2378 { 0x06, 0x9f14 },
2379 { 0x06, 0xee83 },
2380 { 0x06, 0x4e05 },
2381 { 0x06, 0xd240 },
2382 { 0x06, 0xd655 },
2383 { 0x06, 0x5402 },
2384 { 0x06, 0x81c6 },
2385 { 0x06, 0xd2a0 },
2386 { 0x06, 0xd6ba },
2387 { 0x06, 0x0002 },
2388 { 0x06, 0x81c6 },
2389 { 0x06, 0xfefd },
2390 { 0x06, 0xfc05 },
2391 { 0x06, 0xf8e0 },
2392 { 0x06, 0xf860 },
2393 { 0x06, 0xe1f8 },
2394 { 0x06, 0x6168 },
2395 { 0x06, 0x02e4 },
2396 { 0x06, 0xf860 },
2397 { 0x06, 0xe5f8 },
2398 { 0x06, 0x61e0 },
2399 { 0x06, 0xf848 },
2400 { 0x06, 0xe1f8 },
2401 { 0x06, 0x4958 },
2402 { 0x06, 0x0f1e },
2403 { 0x06, 0x02e4 },
2404 { 0x06, 0xf848 },
2405 { 0x06, 0xe5f8 },
2406 { 0x06, 0x49d0 },
2407 { 0x06, 0x0002 },
2408 { 0x06, 0x820a },
2409 { 0x06, 0xbf83 },
2410 { 0x06, 0x50ef },
2411 { 0x06, 0x46dc },
2412 { 0x06, 0x19dd },
2413 { 0x06, 0xd001 },
2414 { 0x06, 0x0282 },
2415 { 0x06, 0x0a02 },
2416 { 0x06, 0x8226 },
2417 { 0x06, 0xe0f8 },
2418 { 0x06, 0x60e1 },
2419 { 0x06, 0xf861 },
2420 { 0x06, 0x58fd },
2421 { 0x06, 0xe4f8 },
2422 { 0x06, 0x60e5 },
2423 { 0x06, 0xf861 },
2424 { 0x06, 0xfc04 },
2425 { 0x06, 0xf9fa },
2426 { 0x06, 0xfbc6 },
2427 { 0x06, 0xbff8 },
2428 { 0x06, 0x40be },
2429 { 0x06, 0x8350 },
2430 { 0x06, 0xa001 },
2431 { 0x06, 0x0107 },
2432 { 0x06, 0x1b89 },
2433 { 0x06, 0xcfd2 },
2434 { 0x06, 0x08eb },
2435 { 0x06, 0xdb19 },
2436 { 0x06, 0xb2fb },
2437 { 0x06, 0xfffe },
2438 { 0x06, 0xfd04 },
2439 { 0x06, 0xf8e0 },
2440 { 0x06, 0xf848 },
2441 { 0x06, 0xe1f8 },
2442 { 0x06, 0x4968 },
2443 { 0x06, 0x08e4 },
2444 { 0x06, 0xf848 },
2445 { 0x06, 0xe5f8 },
2446 { 0x06, 0x4958 },
2447 { 0x06, 0xf7e4 },
2448 { 0x06, 0xf848 },
2449 { 0x06, 0xe5f8 },
2450 { 0x06, 0x49fc },
2451 { 0x06, 0x044d },
2452 { 0x06, 0x2000 },
2453 { 0x06, 0x024e },
2454 { 0x06, 0x2200 },
2455 { 0x06, 0x024d },
2456 { 0x06, 0xdfff },
2457 { 0x06, 0x014e },
2458 { 0x06, 0xddff },
2459 { 0x06, 0x0100 },
2460 { 0x05, 0x83d8 },
2461 { 0x06, 0x8000 },
2462 { 0x03, 0xdc00 },
2463 { 0x05, 0xfff6 },
2464 { 0x06, 0x00fc },
2465 { 0x1f, 0x0000 },
2466
2467 { 0x1f, 0x0000 },
2468 { 0x0d, 0xf880 },
2469 { 0x1f, 0x0000 }
5b538df9
FR		 2470 };
2471
2472 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2473
daf9df6d 2474 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2475 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2476 { 0x1f, 0x0002 },
2477 { 0x05, 0x669a },
5b538df9 2478 { 0x1f, 0x0005 },
daf9df6d 2479 { 0x05, 0x8330 },
2480 { 0x06, 0x669a },
2481
2482 { 0x1f, 0x0002 }
2483 };
2484 int val;
2485
2486 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2487
2488 val = mdio_read(ioaddr, 0x0d);
2489 if ((val & 0x00ff) != 0x006c) {
2490 u32 set[] = {
2491 0x0065, 0x0066, 0x0067, 0x0068,
2492 0x0069, 0x006a, 0x006b, 0x006c
2493 };
2494 int i;
2495
2496 mdio_write(ioaddr, 0x1f, 0x0002);
2497
2498 val &= 0xff00;
2499 for (i = 0; i < ARRAY_SIZE(set); i++)
2500 mdio_write(ioaddr, 0x0d, val | set[i]);
2501 }
2502 } else {
350f7596 2503 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2504 { 0x1f, 0x0002 },
2505 { 0x05, 0x2642 },
5b538df9 2506 { 0x1f, 0x0005 },
daf9df6d 2507 { 0x05, 0x8330 },
2508 { 0x06, 0x2642 }
5b538df9
FR		 2509 };
2510
daf9df6d 2511 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2512 }
2513
daf9df6d 2514 mdio_write(ioaddr, 0x1f, 0x0002);
2515 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2516 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2517
2518 mdio_write(ioaddr, 0x1f, 0x0001);
2519 mdio_write(ioaddr, 0x17, 0x0cc0);
2520
2521 mdio_write(ioaddr, 0x1f, 0x0002);
2522 mdio_patch(ioaddr, 0x0f, 0x0017);
2523
2524 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2525}
2526
2527static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2528{
350f7596 2529 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2530 { 0x1f, 0x0002 },
2531 { 0x10, 0x0008 },
2532 { 0x0d, 0x006c },
2533
2534 { 0x1f, 0x0000 },
2535 { 0x0d, 0xf880 },
2536
2537 { 0x1f, 0x0001 },
2538 { 0x17, 0x0cc0 },
2539
2540 { 0x1f, 0x0001 },
2541 { 0x0b, 0xa4d8 },
2542 { 0x09, 0x281c },
2543 { 0x07, 0x2883 },
2544 { 0x0a, 0x6b35 },
2545 { 0x1d, 0x3da4 },
2546 { 0x1c, 0xeffd },
2547 { 0x14, 0x7f52 },
2548 { 0x18, 0x7fc6 },
2549 { 0x08, 0x0601 },
2550 { 0x06, 0x4063 },
2551 { 0x10, 0xf074 },
2552 { 0x1f, 0x0003 },
2553 { 0x13, 0x0789 },
2554 { 0x12, 0xf4bd },
2555 { 0x1a, 0x04fd },
2556 { 0x14, 0x84b0 },
2557 { 0x1f, 0x0000 },
2558 { 0x00, 0x9200 },
2559
2560 { 0x1f, 0x0005 },
2561 { 0x01, 0x0340 },
2562 { 0x1f, 0x0001 },
2563 { 0x04, 0x4000 },
2564 { 0x03, 0x1d21 },
2565 { 0x02, 0x0c32 },
2566 { 0x01, 0x0200 },
2567 { 0x00, 0x5554 },
2568 { 0x04, 0x4800 },
2569 { 0x04, 0x4000 },
2570 { 0x04, 0xf000 },
2571 { 0x03, 0xdf01 },
2572 { 0x02, 0xdf20 },
2573 { 0x01, 0x101a },
2574 { 0x00, 0xa0ff },
2575 { 0x04, 0xf800 },
2576 { 0x04, 0xf000 },
2577 { 0x1f, 0x0000 },
2578
2579 { 0x1f, 0x0007 },
2580 { 0x1e, 0x0023 },
2581 { 0x16, 0x0000 },
2582 { 0x1f, 0x0000 }
2583 };
2584
2585 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2586}
2587
2857ffb7
FR		 2588static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2589{
350f7596 2590 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2591 { 0x1f, 0x0003 },
2592 { 0x08, 0x441d },
2593 { 0x01, 0x9100 },
2594 { 0x1f, 0x0000 }
2595 };
2596
2597 mdio_write(ioaddr, 0x1f, 0x0000);
2598 mdio_patch(ioaddr, 0x11, 1 << 12);
2599 mdio_patch(ioaddr, 0x19, 1 << 13);
85910a8e 2600 mdio_patch(ioaddr, 0x10, 1 << 15);
2857ffb7
FR		 2601
2602 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2603}
2604
5615d9f1
FR		 2605static void rtl_hw_phy_config(struct net_device *dev)
2606{
2607 struct rtl8169_private *tp = netdev_priv(dev);
2608 void __iomem *ioaddr = tp->mmio_addr;
2609
2610 rtl8169_print_mac_version(tp);
2611
2612 switch (tp->mac_version) {
2613 case RTL_GIGA_MAC_VER_01:
2614 break;
2615 case RTL_GIGA_MAC_VER_02:
2616 case RTL_GIGA_MAC_VER_03:
2617 rtl8169s_hw_phy_config(ioaddr);
2618 break;
2619 case RTL_GIGA_MAC_VER_04:
2620 rtl8169sb_hw_phy_config(ioaddr);
2621 break;
2e955856 2622 case RTL_GIGA_MAC_VER_05:
2623 rtl8169scd_hw_phy_config(tp, ioaddr);
2624 break;
8c7006aa 2625 case RTL_GIGA_MAC_VER_06:
2626 rtl8169sce_hw_phy_config(ioaddr);
2627 break;
2857ffb7
FR		 2628 case RTL_GIGA_MAC_VER_07:
2629 case RTL_GIGA_MAC_VER_08:
2630 case RTL_GIGA_MAC_VER_09:
2631 rtl8102e_hw_phy_config(ioaddr);
2632 break;
236b8082
FR		 2633 case RTL_GIGA_MAC_VER_11:
2634 rtl8168bb_hw_phy_config(ioaddr);
2635 break;
2636 case RTL_GIGA_MAC_VER_12:
2637 rtl8168bef_hw_phy_config(ioaddr);
2638 break;
2639 case RTL_GIGA_MAC_VER_17:
2640 rtl8168bef_hw_phy_config(ioaddr);
2641 break;
867763c1 2642 case RTL_GIGA_MAC_VER_18:
ef3386f0 2643 rtl8168cp_1_hw_phy_config(ioaddr);
867763c1
FR		 2644 break;
2645 case RTL_GIGA_MAC_VER_19:
219a1e9d 2646 rtl8168c_1_hw_phy_config(ioaddr);
867763c1 2647 break;
7da97ec9 2648 case RTL_GIGA_MAC_VER_20:
219a1e9d 2649 rtl8168c_2_hw_phy_config(ioaddr);
7da97ec9 2650 break;
197ff761
FR		 2651 case RTL_GIGA_MAC_VER_21:
2652 rtl8168c_3_hw_phy_config(ioaddr);
2653 break;
6fb07058
FR		 2654 case RTL_GIGA_MAC_VER_22:
2655 rtl8168c_4_hw_phy_config(ioaddr);
2656 break;
ef3386f0 2657 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2658 case RTL_GIGA_MAC_VER_24:
ef3386f0
FR		 2659 rtl8168cp_2_hw_phy_config(ioaddr);
2660 break;
5b538df9 2661 case RTL_GIGA_MAC_VER_25:
daf9df6d 2662 rtl8168d_1_hw_phy_config(ioaddr);
2663 break;
2664 case RTL_GIGA_MAC_VER_26:
2665 rtl8168d_2_hw_phy_config(ioaddr);
2666 break;
2667 case RTL_GIGA_MAC_VER_27:
2668 rtl8168d_3_hw_phy_config(ioaddr);
5b538df9 2669 break;
ef3386f0 2670
5615d9f1
FR		 2671 default:
2672 break;
2673 }
2674}
2675
1da177e4
LT		 2676static void rtl8169_phy_timer(unsigned long __opaque)
2677{
2678 struct net_device *dev = (struct net_device *)__opaque;
2679 struct rtl8169_private *tp = netdev_priv(dev);
2680 struct timer_list *timer = &tp->timer;
2681 void __iomem *ioaddr = tp->mmio_addr;
2682 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2683
bcf0bf90 2684 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2685
64e4bfb4 2686 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 2687 return;
2688
2689 spin_lock_irq(&tp->lock);
2690
2691 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 2692 /*
1da177e4
LT		 2693 * A busy loop could burn quite a few cycles on nowadays CPU.
2694 * Let's delay the execution of the timer for a few ticks.
2695 */
2696 timeout = HZ/10;
2697 goto out_mod_timer;
2698 }
2699
2700 if (tp->link_ok(ioaddr))
2701 goto out_unlock;
2702
bf82c189 2703 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4
LT		 2704
2705 tp->phy_reset_enable(ioaddr);
2706
2707out_mod_timer:
2708 mod_timer(timer, jiffies + timeout);
2709out_unlock:
2710 spin_unlock_irq(&tp->lock);
2711}
2712
2713static inline void rtl8169_delete_timer(struct net_device *dev)
2714{
2715 struct rtl8169_private *tp = netdev_priv(dev);
2716 struct timer_list *timer = &tp->timer;
2717
e179bb7b 2718 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2719 return;
2720
2721 del_timer_sync(timer);
2722}
2723
2724static inline void rtl8169_request_timer(struct net_device *dev)
2725{
2726 struct rtl8169_private *tp = netdev_priv(dev);
2727 struct timer_list *timer = &tp->timer;
2728
e179bb7b 2729 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2730 return;
2731
2efa53f3 2732 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 2733}
2734
2735#ifdef CONFIG_NET_POLL_CONTROLLER
2736/*
2737 * Polling 'interrupt' - used by things like netconsole to send skbs
2738 * without having to re-enable interrupts. It's not called while
2739 * the interrupt routine is executing.
2740 */
2741static void rtl8169_netpoll(struct net_device *dev)
2742{
2743 struct rtl8169_private *tp = netdev_priv(dev);
2744 struct pci_dev *pdev = tp->pci_dev;
2745
2746 disable_irq(pdev->irq);
7d12e780 2747 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2748 enable_irq(pdev->irq);
2749}
2750#endif
2751
2752static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2753 void __iomem *ioaddr)
2754{
2755 iounmap(ioaddr);
2756 pci_release_regions(pdev);
2757 pci_disable_device(pdev);
2758 free_netdev(dev);
2759}
2760
bf793295
FR		 2761static void rtl8169_phy_reset(struct net_device *dev,
2762 struct rtl8169_private *tp)
2763{
2764 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2765 unsigned int i;
bf793295
FR		 2766
2767 tp->phy_reset_enable(ioaddr);
2768 for (i = 0; i < 100; i++) {
2769 if (!tp->phy_reset_pending(ioaddr))
2770 return;
2771 msleep(1);
2772 }
bf82c189 2773 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2774}
2775
4ff96fa6
FR		 2776static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2777{
2778 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2779
5615d9f1 2780 rtl_hw_phy_config(dev);
4ff96fa6 2781
77332894
MS		 2782 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2783 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2784 RTL_W8(0x82, 0x01);
2785 }
4ff96fa6 2786
6dccd16b
FR		 2787 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2788
2789 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2790 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2791
bcf0bf90 2792 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2793 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2794 RTL_W8(0x82, 0x01);
2795 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2796 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2797 }
2798
bf793295
FR		 2799 rtl8169_phy_reset(dev, tp);
2800
901dda2b
FR		 2801 /*
2802 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2803 * only 8101. Don't panic.
2804 */
2805 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6 2806
bf82c189
JP		 2807 if (RTL_R8(PHYstatus) & TBI_Enable)
2808 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2809}
2810
773d2021
FR		 2811static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2812{
2813 void __iomem *ioaddr = tp->mmio_addr;
2814 u32 high;
2815 u32 low;
2816
2817 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2818 high = addr[4] | (addr[5] << 8);
2819
2820 spin_lock_irq(&tp->lock);
2821
2822 RTL_W8(Cfg9346, Cfg9346_Unlock);
2823 RTL_W32(MAC0, low);
2824 RTL_W32(MAC4, high);
2825 RTL_W8(Cfg9346, Cfg9346_Lock);
2826
2827 spin_unlock_irq(&tp->lock);
2828}
2829
2830static int rtl_set_mac_address(struct net_device *dev, void *p)
2831{
2832 struct rtl8169_private *tp = netdev_priv(dev);
2833 struct sockaddr *addr = p;
2834
2835 if (!is_valid_ether_addr(addr->sa_data))
2836 return -EADDRNOTAVAIL;
2837
2838 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2839
2840 rtl_rar_set(tp, dev->dev_addr);
2841
2842 return 0;
2843}
2844
5f787a1a
FR		 2845static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2846{
2847 struct rtl8169_private *tp = netdev_priv(dev);
2848 struct mii_ioctl_data *data = if_mii(ifr);
2849
8b4ab28d
FR		 2850 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2851}
5f787a1a 2852
8b4ab28d
FR		 2853static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2854{
5f787a1a
FR		 2855 switch (cmd) {
2856 case SIOCGMIIPHY:
2857 data->phy_id = 32; /* Internal PHY */
2858 return 0;
2859
2860 case SIOCGMIIREG:
2861 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2862 return 0;
2863
2864 case SIOCSMIIREG:
5f787a1a
FR		 2865 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2866 return 0;
2867 }
2868 return -EOPNOTSUPP;
2869}
2870
8b4ab28d
FR		 2871static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2872{
2873 return -EOPNOTSUPP;
2874}
2875
0e485150
FR		 2876static const struct rtl_cfg_info {
2877 void (*hw_start)(struct net_device *);
2878 unsigned int region;
2879 unsigned int align;
2880 u16 intr_event;
2881 u16 napi_event;
ccdffb9a 2882 unsigned features;
f21b75e9 2883 u8 default_ver;
0e485150
FR		 2884} rtl_cfg_infos [] = {
2885 [RTL_CFG_0] = {
2886 .hw_start = rtl_hw_start_8169,
2887 .region = 1,
e9f63f30 2888 .align = 0,
0e485150
FR		 2889 .intr_event = SYSErr | LinkChg | RxOverflow |
2890 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2891 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2892 .features = RTL_FEATURE_GMII,
2893 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2894 },
2895 [RTL_CFG_1] = {
2896 .hw_start = rtl_hw_start_8168,
2897 .region = 2,
2898 .align = 8,
2899 .intr_event = SYSErr | LinkChg | RxOverflow |
2900 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2901 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2902 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2903 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2904 },
2905 [RTL_CFG_2] = {
2906 .hw_start = rtl_hw_start_8101,
2907 .region = 2,
2908 .align = 8,
2909 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2910 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2911 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2912 .features = RTL_FEATURE_MSI,
2913 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2914 }
2915};
2916
fbac58fc
FR		 2917/* Cfg9346_Unlock assumed. */
2918static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2919 const struct rtl_cfg_info *cfg)
2920{
2921 unsigned msi = 0;
2922 u8 cfg2;
2923
2924 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2925 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2926 if (pci_enable_msi(pdev)) {
2927 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2928 } else {
2929 cfg2 |= MSIEnable;
2930 msi = RTL_FEATURE_MSI;
2931 }
2932 }
2933 RTL_W8(Config2, cfg2);
2934 return msi;
2935}
2936
2937static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2938{
2939 if (tp->features & RTL_FEATURE_MSI) {
2940 pci_disable_msi(pdev);
2941 tp->features &= ~RTL_FEATURE_MSI;
2942 }
2943}
2944
8b4ab28d
FR		 2945static const struct net_device_ops rtl8169_netdev_ops = {
2946 .ndo_open = rtl8169_open,
2947 .ndo_stop = rtl8169_close,
2948 .ndo_get_stats = rtl8169_get_stats,
00829823 2949 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2950 .ndo_tx_timeout = rtl8169_tx_timeout,
2951 .ndo_validate_addr = eth_validate_addr,
2952 .ndo_change_mtu = rtl8169_change_mtu,
2953 .ndo_set_mac_address = rtl_set_mac_address,
2954 .ndo_do_ioctl = rtl8169_ioctl,
2955 .ndo_set_multicast_list = rtl_set_rx_mode,
2956#ifdef CONFIG_R8169_VLAN
2957 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2958#endif
2959#ifdef CONFIG_NET_POLL_CONTROLLER
2960 .ndo_poll_controller = rtl8169_netpoll,
2961#endif
2962
2963};
2964
1da177e4 2965static int __devinit
4ff96fa6 2966rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 2967{
0e485150
FR		 2968 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2969 const unsigned int region = cfg->region;
1da177e4 2970 struct rtl8169_private *tp;
ccdffb9a 2971 struct mii_if_info *mii;
4ff96fa6
FR		 2972 struct net_device *dev;
2973 void __iomem *ioaddr;
07d3f51f
FR		 2974 unsigned int i;
2975 int rc;
1da177e4 2976
4ff96fa6
FR		 2977 if (netif_msg_drv(&debug)) {
2978 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2979 MODULENAME, RTL8169_VERSION);
2980 }
1da177e4 2981
1da177e4 2982 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 2983 if (!dev) {
b57b7e5a 2984 if (netif_msg_drv(&debug))
9b91cf9d 2985 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 2986 rc = -ENOMEM;
2987 goto out;
1da177e4
LT		 2988 }
2989
1da177e4 2990 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 2991 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 2992 tp = netdev_priv(dev);
c4028958 2993 tp->dev = dev;
21e197f2 2994 tp->pci_dev = pdev;
b57b7e5a 2995 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 2996
ccdffb9a
FR		 2997 mii = &tp->mii;
2998 mii->dev = dev;
2999 mii->mdio_read = rtl_mdio_read;
3000 mii->mdio_write = rtl_mdio_write;
3001 mii->phy_id_mask = 0x1f;
3002 mii->reg_num_mask = 0x1f;
3003 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3004
1da177e4
LT		 3005 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3006 rc = pci_enable_device(pdev);
b57b7e5a 3007 if (rc < 0) {
bf82c189 3008 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3009 goto err_out_free_dev_1;
1da177e4
LT		 3010 }
3011
3012 rc = pci_set_mwi(pdev);
3013 if (rc < 0)
4ff96fa6 3014 goto err_out_disable_2;
1da177e4 3015
1da177e4 3016 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3017 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3018 netif_err(tp, probe, dev,
3019 "region #%d not an MMIO resource, aborting\n",
3020 region);
1da177e4 3021 rc = -ENODEV;
4ff96fa6 3022 goto err_out_mwi_3;
1da177e4 3023 }
4ff96fa6 3024
1da177e4 3025 /* check for weird/broken PCI region reporting */
bcf0bf90 3026 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3027 netif_err(tp, probe, dev,
3028 "Invalid PCI region size(s), aborting\n");
1da177e4 3029 rc = -ENODEV;
4ff96fa6 3030 goto err_out_mwi_3;
1da177e4
LT		 3031 }
3032
3033 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3034 if (rc < 0) {
bf82c189 3035 netif_err(tp, probe, dev, "could not request regions\n");
4ff96fa6 3036 goto err_out_mwi_3;
1da177e4
LT		 3037 }
3038
3039 tp->cp_cmd = PCIMulRW | RxChkSum;
3040
3041 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3042 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3043 tp->cp_cmd |= PCIDAC;
3044 dev->features |= NETIF_F_HIGHDMA;
3045 } else {
284901a9 3046 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3047 if (rc < 0) {
bf82c189 3048 netif_err(tp, probe, dev, "DMA configuration failed\n");
4ff96fa6 3049 goto err_out_free_res_4;
1da177e4
LT		 3050 }
3051 }
3052
1da177e4 3053 /* ioremap MMIO region */
bcf0bf90 3054 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3055 if (!ioaddr) {
bf82c189 3056 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3057 rc = -EIO;
4ff96fa6 3058 goto err_out_free_res_4;
1da177e4
LT		 3059 }
3060
4300e8c7
DM		 3061 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3062 if (!tp->pcie_cap)
3063 netif_info(tp, probe, dev, "no PCI Express capability\n");
3064
d78ad8cb 3065 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 3066
3067 /* Soft reset the chip. */
3068 RTL_W8(ChipCmd, CmdReset);
3069
3070 /* Check that the chip has finished the reset. */
07d3f51f 3071 for (i = 0; i < 100; i++) {
1da177e4
LT		 3072 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3073 break;
b518fa8e 3074 msleep_interruptible(1);
1da177e4
LT		 3075 }
3076
d78ad8cb
KW		 3077 RTL_W16(IntrStatus, 0xffff);
3078
ca52efd5 3079 pci_set_master(pdev);
3080
1da177e4
LT		 3081 /* Identify chip attached to board */
3082 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 3083
f21b75e9
JD		 3084 /* Use appropriate default if unknown */
3085 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
bf82c189
JP		 3086 netif_notice(tp, probe, dev,
3087 "unknown MAC, using family default\n");
f21b75e9
JD		 3088 tp->mac_version = cfg->default_ver;
3089 }
3090
1da177e4 3091 rtl8169_print_mac_version(tp);
1da177e4 3092
cee60c37 3093 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 3094 if (tp->mac_version == rtl_chip_info[i].mac_version)
3095 break;
3096 }
cee60c37 3097 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 3098 dev_err(&pdev->dev,
3099 "driver bug, MAC version not found in rtl_chip_info\n");
3100 goto err_out_msi_5;
1da177e4
LT		 3101 }
3102 tp->chipset = i;
3103
5d06a99f
FR		 3104 RTL_W8(Cfg9346, Cfg9346_Unlock);
3105 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3106 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3107 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3108 tp->features |= RTL_FEATURE_WOL;
3109 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3110 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3111 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3112 RTL_W8(Cfg9346, Cfg9346_Lock);
3113
66ec5d4f
FR		 3114 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3115 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3116 tp->set_speed = rtl8169_set_speed_tbi;
3117 tp->get_settings = rtl8169_gset_tbi;
3118 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3119 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3120 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3121 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 3122
64e4bfb4 3123 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 3124 } else {
3125 tp->set_speed = rtl8169_set_speed_xmii;
3126 tp->get_settings = rtl8169_gset_xmii;
3127 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3128 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3129 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3130 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3131 }
3132
df58ef51
FR		 3133 spin_lock_init(&tp->lock);
3134
738e1e69
PV		 3135 tp->mmio_addr = ioaddr;
3136
7bf6bf48 3137 /* Get MAC address */
1da177e4
LT		 3138 for (i = 0; i < MAC_ADDR_LEN; i++)
3139 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3140 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3141
1da177e4 3142 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3143 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3144 dev->irq = pdev->irq;
3145 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3146
bea3348e 3147 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 3148
3149#ifdef CONFIG_R8169_VLAN
3150 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 3151#endif
3152
3153 tp->intr_mask = 0xffff;
0e485150
FR		 3154 tp->align = cfg->align;
3155 tp->hw_start = cfg->hw_start;
3156 tp->intr_event = cfg->intr_event;
3157 tp->napi_event = cfg->napi_event;
1da177e4 3158
2efa53f3
FR		 3159 init_timer(&tp->timer);
3160 tp->timer.data = (unsigned long) dev;
3161 tp->timer.function = rtl8169_phy_timer;
3162
1da177e4 3163 rc = register_netdev(dev);
4ff96fa6 3164 if (rc < 0)
fbac58fc 3165 goto err_out_msi_5;
1da177e4
LT		 3166
3167 pci_set_drvdata(pdev, dev);
3168
bf82c189
JP		 3169 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3170 rtl_chip_info[tp->chipset].name,
3171 dev->base_addr, dev->dev_addr,
3172 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3173
4ff96fa6 3174 rtl8169_init_phy(dev, tp);
05af2142
SW		 3175
3176 /*
3177 * Pretend we are using VLANs; This bypasses a nasty bug where
3178 * Interrupts stop flowing on high load on 8110SCd controllers.
3179 */
3180 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3181 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3182
8b76ab39 3183 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3184
4ff96fa6
FR		 3185out:
3186 return rc;
1da177e4 3187
fbac58fc
FR		 3188err_out_msi_5:
3189 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 3190 iounmap(ioaddr);
3191err_out_free_res_4:
3192 pci_release_regions(pdev);
3193err_out_mwi_3:
3194 pci_clear_mwi(pdev);
3195err_out_disable_2:
3196 pci_disable_device(pdev);
3197err_out_free_dev_1:
3198 free_netdev(dev);
3199 goto out;
1da177e4
LT		 3200}
3201
07d3f51f 3202static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3203{
3204 struct net_device *dev = pci_get_drvdata(pdev);
3205 struct rtl8169_private *tp = netdev_priv(dev);
3206
eb2a021c
FR		 3207 flush_scheduled_work();
3208
1da177e4 3209 unregister_netdev(dev);
cc098dc7
IV		 3210
3211 /* restore original MAC address */
3212 rtl_rar_set(tp, dev->perm_addr);
3213
fbac58fc 3214 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3215 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3216 pci_set_drvdata(pdev, NULL);
3217}
3218
1da177e4
LT		 3219static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
3220 struct net_device *dev)
3221{
8812304c 3222 unsigned int max_frame = dev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
1da177e4 3223
8812304c 3224 tp->rx_buf_sz = (max_frame > RX_BUF_SIZE) ? max_frame : RX_BUF_SIZE;
1da177e4
LT		 3225}
3226
3227static int rtl8169_open(struct net_device *dev)
3228{
3229 struct rtl8169_private *tp = netdev_priv(dev);
3230 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3231 int retval = -ENOMEM;
1da177e4 3232
1da177e4 3233
99f252b0 3234 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 3235
3236 /*
3237 * Rx and Tx desscriptors needs 256 bytes alignment.
3238 * pci_alloc_consistent provides more.
3239 */
3240 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
3241 &tp->TxPhyAddr);
3242 if (!tp->TxDescArray)
99f252b0 3243 goto out;
1da177e4
LT		 3244
3245 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
3246 &tp->RxPhyAddr);
3247 if (!tp->RxDescArray)
99f252b0 3248 goto err_free_tx_0;
1da177e4
LT		 3249
3250 retval = rtl8169_init_ring(dev);
3251 if (retval < 0)
99f252b0 3252 goto err_free_rx_1;
1da177e4 3253
c4028958 3254 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3255
99f252b0
FR		 3256 smp_mb();
3257
fbac58fc
FR		 3258 retval = request_irq(dev->irq, rtl8169_interrupt,
3259 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3260 dev->name, dev);
3261 if (retval < 0)
3262 goto err_release_ring_2;
3263
bea3348e 3264 napi_enable(&tp->napi);
bea3348e 3265
07ce4064 3266 rtl_hw_start(dev);
1da177e4
LT		 3267
3268 rtl8169_request_timer(dev);
3269
3270 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3271out:
3272 return retval;
3273
99f252b0
FR		 3274err_release_ring_2:
3275 rtl8169_rx_clear(tp);
3276err_free_rx_1:
1da177e4
LT		 3277 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3278 tp->RxPhyAddr);
99f252b0 3279err_free_tx_0:
1da177e4
LT		 3280 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3281 tp->TxPhyAddr);
1da177e4
LT		 3282 goto out;
3283}
3284
3285static void rtl8169_hw_reset(void __iomem *ioaddr)
3286{
3287 /* Disable interrupts */
3288 rtl8169_irq_mask_and_ack(ioaddr);
3289
3290 /* Reset the chipset */
3291 RTL_W8(ChipCmd, CmdReset);
3292
3293 /* PCI commit */
3294 RTL_R8(ChipCmd);
3295}
3296
7f796d83 3297static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3298{
3299 void __iomem *ioaddr = tp->mmio_addr;
3300 u32 cfg = rtl8169_rx_config;
3301
3302 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3303 RTL_W32(RxConfig, cfg);
3304
3305 /* Set DMA burst size and Interframe Gap Time */
3306 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3307 (InterFrameGap << TxInterFrameGapShift));
3308}
3309
07ce4064 3310static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3311{
3312 struct rtl8169_private *tp = netdev_priv(dev);
3313 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 3314 unsigned int i;
1da177e4
LT		 3315
3316 /* Soft reset the chip. */
3317 RTL_W8(ChipCmd, CmdReset);
3318
3319 /* Check that the chip has finished the reset. */
07d3f51f 3320 for (i = 0; i < 100; i++) {
1da177e4
LT		 3321 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3322 break;
b518fa8e 3323 msleep_interruptible(1);
1da177e4
LT		 3324 }
3325
07ce4064
FR		 3326 tp->hw_start(dev);
3327
07ce4064
FR		 3328 netif_start_queue(dev);
3329}
3330
3331
7f796d83
FR		 3332static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3333 void __iomem *ioaddr)
3334{
3335 /*
3336 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3337 * register to be written before TxDescAddrLow to work.
3338 * Switching from MMIO to I/O access fixes the issue as well.
3339 */
3340 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3341 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3342 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3343 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3344}
3345
3346static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3347{
3348 u16 cmd;
3349
3350 cmd = RTL_R16(CPlusCmd);
3351 RTL_W16(CPlusCmd, cmd);
3352 return cmd;
3353}
3354
fdd7b4c3 3355static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3356{
3357 /* Low hurts. Let's disable the filtering. */
207d6e87 3358 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3359}
3360
6dccd16b
FR		 3361static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3362{
350f7596 3363 static const struct {
6dccd16b
FR		 3364 u32 mac_version;
3365 u32 clk;
3366 u32 val;
3367 } cfg2_info [] = {
3368 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3369 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3370 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3371 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3372 }, *p = cfg2_info;
3373 unsigned int i;
3374 u32 clk;
3375
3376 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3377 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3378 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3379 RTL_W32(0x7c, p->val);
3380 break;
3381 }
3382 }
3383}
3384
07ce4064
FR		 3385static void rtl_hw_start_8169(struct net_device *dev)
3386{
3387 struct rtl8169_private *tp = netdev_priv(dev);
3388 void __iomem *ioaddr = tp->mmio_addr;
3389 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3390
9cb427b6
FR		 3391 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3392 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3393 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3394 }
3395
1da177e4 3396 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 3397 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3398 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3399 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3400 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3401 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3402
1da177e4
LT		 3403 RTL_W8(EarlyTxThres, EarlyTxThld);
3404
fdd7b4c3 3405 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
1da177e4 3406
c946b304
FR		 3407 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3408 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3409 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3410 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3411 rtl_set_rx_tx_config_registers(tp);
1da177e4 3412
7f796d83 3413 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3414
bcf0bf90
FR		 3415 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3416 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 3417 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3418 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3419 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3420 }
3421
bcf0bf90
FR		 3422 RTL_W16(CPlusCmd, tp->cp_cmd);
3423
6dccd16b
FR		 3424 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3425
1da177e4
LT		 3426 /*
3427 * Undocumented corner. Supposedly:
3428 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3429 */
3430 RTL_W16(IntrMitigate, 0x0000);
3431
7f796d83 3432 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3433
c946b304
FR		 3434 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3435 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3436 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3437 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3438 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3439 rtl_set_rx_tx_config_registers(tp);
3440 }
3441
1da177e4 3442 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3443
3444 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3445 RTL_R8(IntrMask);
1da177e4
LT		 3446
3447 RTL_W32(RxMissed, 0);
3448
07ce4064 3449 rtl_set_rx_mode(dev);
1da177e4
LT		 3450
3451 /* no early-rx interrupts */
3452 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3453
3454 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3455 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3456}
1da177e4 3457
9c14ceaf 3458static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3459{
9c14ceaf
FR		 3460 struct net_device *dev = pci_get_drvdata(pdev);
3461 struct rtl8169_private *tp = netdev_priv(dev);
3462 int cap = tp->pcie_cap;
3463
3464 if (cap) {
3465 u16 ctl;
458a9f61 3466
9c14ceaf
FR		 3467 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3468 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3469 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3470 }
458a9f61
FR		 3471}
3472
dacf8154
FR		 3473static void rtl_csi_access_enable(void __iomem *ioaddr)
3474{
3475 u32 csi;
3476
3477 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3478 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3479}
3480
3481struct ephy_info {
3482 unsigned int offset;
3483 u16 mask;
3484 u16 bits;
3485};
3486
350f7596 3487static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3488{
3489 u16 w;
3490
3491 while (len-- > 0) {
3492 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3493 rtl_ephy_write(ioaddr, e->offset, w);
3494 e++;
3495 }
3496}
3497
b726e493
FR		 3498static void rtl_disable_clock_request(struct pci_dev *pdev)
3499{
3500 struct net_device *dev = pci_get_drvdata(pdev);
3501 struct rtl8169_private *tp = netdev_priv(dev);
3502 int cap = tp->pcie_cap;
3503
3504 if (cap) {
3505 u16 ctl;
3506
3507 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3508 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3509 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3510 }
3511}
3512
3513#define R8168_CPCMD_QUIRK_MASK (\
3514 EnableBist | \
3515 Mac_dbgo_oe | \
3516 Force_half_dup | \
3517 Force_rxflow_en | \
3518 Force_txflow_en | \
3519 Cxpl_dbg_sel | \
3520 ASF | \
3521 PktCntrDisable | \
3522 Mac_dbgo_sel)
3523
219a1e9d
FR		 3524static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3525{
b726e493
FR		 3526 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3527
3528 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3529
2e68ae44
FR		 3530 rtl_tx_performance_tweak(pdev,
3531 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3532}
3533
3534static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3535{
3536 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493
FR		 3537
3538 RTL_W8(EarlyTxThres, EarlyTxThld);
3539
3540 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3541}
3542
3543static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3544{
b726e493
FR		 3545 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3546
3547 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3548
219a1e9d 3549 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3550
3551 rtl_disable_clock_request(pdev);
3552
3553 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3554}
3555
ef3386f0 3556static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3557{
350f7596 3558 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3559 { 0x01, 0, 0x0001 },
3560 { 0x02, 0x0800, 0x1000 },
3561 { 0x03, 0, 0x0042 },
3562 { 0x06, 0x0080, 0x0000 },
3563 { 0x07, 0, 0x2000 }
3564 };
3565
3566 rtl_csi_access_enable(ioaddr);
3567
3568 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3569
219a1e9d
FR		 3570 __rtl_hw_start_8168cp(ioaddr, pdev);
3571}
3572
ef3386f0
FR		 3573static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3574{
3575 rtl_csi_access_enable(ioaddr);
3576
3577 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3578
3579 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3580
3581 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3582}
3583
7f3e3d3a
FR		 3584static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3585{
3586 rtl_csi_access_enable(ioaddr);
3587
3588 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3589
3590 /* Magic. */
3591 RTL_W8(DBG_REG, 0x20);
3592
3593 RTL_W8(EarlyTxThres, EarlyTxThld);
3594
3595 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3596
3597 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3598}
3599
219a1e9d
FR		 3600static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3601{
350f7596 3602 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3603 { 0x02, 0x0800, 0x1000 },
3604 { 0x03, 0, 0x0002 },
3605 { 0x06, 0x0080, 0x0000 }
3606 };
3607
3608 rtl_csi_access_enable(ioaddr);
3609
3610 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3611
3612 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3613
219a1e9d
FR		 3614 __rtl_hw_start_8168cp(ioaddr, pdev);
3615}
3616
3617static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3618{
350f7596 3619 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3620 { 0x01, 0, 0x0001 },
3621 { 0x03, 0x0400, 0x0220 }
3622 };
3623
3624 rtl_csi_access_enable(ioaddr);
3625
3626 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3627
219a1e9d
FR		 3628 __rtl_hw_start_8168cp(ioaddr, pdev);
3629}
3630
197ff761
FR		 3631static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3632{
3633 rtl_hw_start_8168c_2(ioaddr, pdev);
3634}
3635
6fb07058
FR		 3636static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3637{
3638 rtl_csi_access_enable(ioaddr);
3639
3640 __rtl_hw_start_8168cp(ioaddr, pdev);
3641}
3642
5b538df9
FR		 3643static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3644{
3645 rtl_csi_access_enable(ioaddr);
3646
3647 rtl_disable_clock_request(pdev);
3648
3649 RTL_W8(EarlyTxThres, EarlyTxThld);
3650
3651 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3652
3653 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3654}
3655
07ce4064
FR		 3656static void rtl_hw_start_8168(struct net_device *dev)
3657{
2dd99530
FR		 3658 struct rtl8169_private *tp = netdev_priv(dev);
3659 void __iomem *ioaddr = tp->mmio_addr;
0e485150 3660 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 3661
3662 RTL_W8(Cfg9346, Cfg9346_Unlock);
3663
3664 RTL_W8(EarlyTxThres, EarlyTxThld);
3665
fdd7b4c3 3666 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2dd99530 3667
0e485150 3668 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 3669
3670 RTL_W16(CPlusCmd, tp->cp_cmd);
3671
0e485150 3672 RTL_W16(IntrMitigate, 0x5151);
2dd99530 3673
0e485150
FR		 3674 /* Work around for RxFIFO overflow. */
3675 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3676 tp->intr_event |= RxFIFOOver | PCSTimeout;
3677 tp->intr_event &= ~RxOverflow;
3678 }
3679
3680 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 3681
b8363901
FR		 3682 rtl_set_rx_mode(dev);
3683
3684 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3685 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 3686
3687 RTL_R8(IntrMask);
3688
219a1e9d
FR		 3689 switch (tp->mac_version) {
3690 case RTL_GIGA_MAC_VER_11:
3691 rtl_hw_start_8168bb(ioaddr, pdev);
3692 break;
3693
3694 case RTL_GIGA_MAC_VER_12:
3695 case RTL_GIGA_MAC_VER_17:
3696 rtl_hw_start_8168bef(ioaddr, pdev);
3697 break;
3698
3699 case RTL_GIGA_MAC_VER_18:
ef3386f0 3700 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 3701 break;
3702
3703 case RTL_GIGA_MAC_VER_19:
3704 rtl_hw_start_8168c_1(ioaddr, pdev);
3705 break;
3706
3707 case RTL_GIGA_MAC_VER_20:
3708 rtl_hw_start_8168c_2(ioaddr, pdev);
3709 break;
3710
197ff761
FR		 3711 case RTL_GIGA_MAC_VER_21:
3712 rtl_hw_start_8168c_3(ioaddr, pdev);
3713 break;
3714
6fb07058
FR		 3715 case RTL_GIGA_MAC_VER_22:
3716 rtl_hw_start_8168c_4(ioaddr, pdev);
3717 break;
3718
ef3386f0
FR		 3719 case RTL_GIGA_MAC_VER_23:
3720 rtl_hw_start_8168cp_2(ioaddr, pdev);
3721 break;
3722
7f3e3d3a
FR		 3723 case RTL_GIGA_MAC_VER_24:
3724 rtl_hw_start_8168cp_3(ioaddr, pdev);
3725 break;
3726
5b538df9 3727 case RTL_GIGA_MAC_VER_25:
daf9df6d 3728 case RTL_GIGA_MAC_VER_26:
3729 case RTL_GIGA_MAC_VER_27:
5b538df9
FR		 3730 rtl_hw_start_8168d(ioaddr, pdev);
3731 break;
3732
219a1e9d
FR		 3733 default:
3734 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3735 dev->name, tp->mac_version);
3736 break;
3737 }
2dd99530 3738
0e485150
FR		 3739 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3740
b8363901
FR		 3741 RTL_W8(Cfg9346, Cfg9346_Lock);
3742
2dd99530 3743 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 3744
0e485150 3745 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3746}
1da177e4 3747
2857ffb7
FR		 3748#define R810X_CPCMD_QUIRK_MASK (\
3749 EnableBist | \
3750 Mac_dbgo_oe | \
3751 Force_half_dup | \
5edcc537 3752 Force_rxflow_en | \
2857ffb7
FR		 3753 Force_txflow_en | \
3754 Cxpl_dbg_sel | \
3755 ASF | \
3756 PktCntrDisable | \
3757 PCIDAC | \
3758 PCIMulRW)
3759
3760static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3761{
350f7596 3762 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 3763 { 0x01, 0, 0x6e65 },
3764 { 0x02, 0, 0x091f },
3765 { 0x03, 0, 0xc2f9 },
3766 { 0x06, 0, 0xafb5 },
3767 { 0x07, 0, 0x0e00 },
3768 { 0x19, 0, 0xec80 },
3769 { 0x01, 0, 0x2e65 },
3770 { 0x01, 0, 0x6e65 }
3771 };
3772 u8 cfg1;
3773
3774 rtl_csi_access_enable(ioaddr);
3775
3776 RTL_W8(DBG_REG, FIX_NAK_1);
3777
3778 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3779
3780 RTL_W8(Config1,
3781 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3782 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3783
3784 cfg1 = RTL_R8(Config1);
3785 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3786 RTL_W8(Config1, cfg1 & ~LEDS0);
3787
3788 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3789
3790 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3791}
3792
3793static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3794{
3795 rtl_csi_access_enable(ioaddr);
3796
3797 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3798
3799 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3800 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3801
3802 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3803}
3804
3805static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3806{
3807 rtl_hw_start_8102e_2(ioaddr, pdev);
3808
3809 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3810}
3811
07ce4064
FR		 3812static void rtl_hw_start_8101(struct net_device *dev)
3813{
cdf1a608
FR		 3814 struct rtl8169_private *tp = netdev_priv(dev);
3815 void __iomem *ioaddr = tp->mmio_addr;
3816 struct pci_dev *pdev = tp->pci_dev;
3817
e3cf0cc0
FR		 3818 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3819 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 3820 int cap = tp->pcie_cap;
3821
3822 if (cap) {
3823 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3824 PCI_EXP_DEVCTL_NOSNOOP_EN);
3825 }
cdf1a608
FR		 3826 }
3827
2857ffb7
FR		 3828 switch (tp->mac_version) {
3829 case RTL_GIGA_MAC_VER_07:
3830 rtl_hw_start_8102e_1(ioaddr, pdev);
3831 break;
3832
3833 case RTL_GIGA_MAC_VER_08:
3834 rtl_hw_start_8102e_3(ioaddr, pdev);
3835 break;
3836
3837 case RTL_GIGA_MAC_VER_09:
3838 rtl_hw_start_8102e_2(ioaddr, pdev);
3839 break;
cdf1a608
FR		 3840 }
3841
3842 RTL_W8(Cfg9346, Cfg9346_Unlock);
3843
3844 RTL_W8(EarlyTxThres, EarlyTxThld);
3845
fdd7b4c3 3846 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
cdf1a608
FR		 3847
3848 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3849
3850 RTL_W16(CPlusCmd, tp->cp_cmd);
3851
3852 RTL_W16(IntrMitigate, 0x0000);
3853
3854 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3855
3856 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3857 rtl_set_rx_tx_config_registers(tp);
3858
3859 RTL_W8(Cfg9346, Cfg9346_Lock);
3860
3861 RTL_R8(IntrMask);
3862
cdf1a608
FR		 3863 rtl_set_rx_mode(dev);
3864
0e485150
FR		 3865 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3866
cdf1a608 3867 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 3868
0e485150 3869 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3870}
3871
3872static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3873{
3874 struct rtl8169_private *tp = netdev_priv(dev);
3875 int ret = 0;
3876
3877 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3878 return -EINVAL;
3879
3880 dev->mtu = new_mtu;
3881
3882 if (!netif_running(dev))
3883 goto out;
3884
3885 rtl8169_down(dev);
3886
3887 rtl8169_set_rxbufsize(tp, dev);
3888
3889 ret = rtl8169_init_ring(dev);
3890 if (ret < 0)
3891 goto out;
3892
bea3348e 3893 napi_enable(&tp->napi);
1da177e4 3894
07ce4064 3895 rtl_hw_start(dev);
1da177e4
LT		 3896
3897 rtl8169_request_timer(dev);
3898
3899out:
3900 return ret;
3901}
3902
3903static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3904{
95e0918d 3905 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 3906 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3907}
3908
3909static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3910 struct sk_buff **sk_buff, struct RxDesc *desc)
3911{
3912 struct pci_dev *pdev = tp->pci_dev;
3913
3914 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
3915 PCI_DMA_FROMDEVICE);
3916 dev_kfree_skb(*sk_buff);
3917 *sk_buff = NULL;
3918 rtl8169_make_unusable_by_asic(desc);
3919}
3920
3921static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3922{
3923 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3924
3925 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3926}
3927
3928static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3929 u32 rx_buf_sz)
3930{
3931 desc->addr = cpu_to_le64(mapping);
3932 wmb();
3933 rtl8169_mark_to_asic(desc, rx_buf_sz);
3934}
3935
15d31758
SH		 3936static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
3937 struct net_device *dev,
3938 struct RxDesc *desc, int rx_buf_sz,
3939 unsigned int align)
1da177e4
LT		 3940{
3941 struct sk_buff *skb;
3942 dma_addr_t mapping;
e9f63f30 3943 unsigned int pad;
1da177e4 3944
e9f63f30
FR		 3945 pad = align ? align : NET_IP_ALIGN;
3946
3947 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 3948 if (!skb)
3949 goto err_out;
3950
e9f63f30 3951 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 3952
689be439 3953 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 3954 PCI_DMA_FROMDEVICE);
3955
3956 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 3957out:
15d31758 3958 return skb;
1da177e4
LT		 3959
3960err_out:
1da177e4
LT		 3961 rtl8169_make_unusable_by_asic(desc);
3962 goto out;
3963}
3964
3965static void rtl8169_rx_clear(struct rtl8169_private *tp)
3966{
07d3f51f 3967 unsigned int i;
1da177e4
LT		 3968
3969 for (i = 0; i < NUM_RX_DESC; i++) {
3970 if (tp->Rx_skbuff[i]) {
3971 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
3972 tp->RxDescArray + i);
3973 }
3974 }
3975}
3976
3977static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
3978 u32 start, u32 end)
3979{
3980 u32 cur;
5b0384f4 3981
4ae47c2d 3982 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 3983 struct sk_buff *skb;
3984 unsigned int i = cur % NUM_RX_DESC;
1da177e4 3985
4ae47c2d
FR		 3986 WARN_ON((s32)(end - cur) < 0);
3987
1da177e4
LT		 3988 if (tp->Rx_skbuff[i])
3989 continue;
bcf0bf90 3990
15d31758
SH		 3991 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
3992 tp->RxDescArray + i,
3993 tp->rx_buf_sz, tp->align);
3994 if (!skb)
1da177e4 3995 break;
15d31758
SH		 3996
3997 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 3998 }
3999 return cur - start;
4000}
4001
4002static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4003{
4004 desc->opts1 |= cpu_to_le32(RingEnd);
4005}
4006
4007static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4008{
4009 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4010}
4011
4012static int rtl8169_init_ring(struct net_device *dev)
4013{
4014 struct rtl8169_private *tp = netdev_priv(dev);
4015
4016 rtl8169_init_ring_indexes(tp);
4017
4018 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4019 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
4020
4021 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
4022 goto err_out;
4023
4024 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4025
4026 return 0;
4027
4028err_out:
4029 rtl8169_rx_clear(tp);
4030 return -ENOMEM;
4031}
4032
4033static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
4034 struct TxDesc *desc)
4035{
4036 unsigned int len = tx_skb->len;
4037
4038 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
4039 desc->opts1 = 0x00;
4040 desc->opts2 = 0x00;
4041 desc->addr = 0x00;
4042 tx_skb->len = 0;
4043}
4044
4045static void rtl8169_tx_clear(struct rtl8169_private *tp)
4046{
4047 unsigned int i;
4048
4049 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
4050 unsigned int entry = i % NUM_TX_DESC;
4051 struct ring_info *tx_skb = tp->tx_skb + entry;
4052 unsigned int len = tx_skb->len;
4053
4054 if (len) {
4055 struct sk_buff *skb = tx_skb->skb;
4056
4057 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
4058 tp->TxDescArray + entry);
4059 if (skb) {
4060 dev_kfree_skb(skb);
4061 tx_skb->skb = NULL;
4062 }
cebf8cc7 4063 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4064 }
4065 }
4066 tp->cur_tx = tp->dirty_tx = 0;
4067}
4068
c4028958 4069static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4070{
4071 struct rtl8169_private *tp = netdev_priv(dev);
4072
c4028958 4073 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4074 schedule_delayed_work(&tp->task, 4);
4075}
4076
4077static void rtl8169_wait_for_quiescence(struct net_device *dev)
4078{
4079 struct rtl8169_private *tp = netdev_priv(dev);
4080 void __iomem *ioaddr = tp->mmio_addr;
4081
4082 synchronize_irq(dev->irq);
4083
4084 /* Wait for any pending NAPI task to complete */
bea3348e 4085 napi_disable(&tp->napi);
1da177e4
LT		 4086
4087 rtl8169_irq_mask_and_ack(ioaddr);
4088
d1d08d12
DM		 4089 tp->intr_mask = 0xffff;
4090 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4091 napi_enable(&tp->napi);
1da177e4
LT		 4092}
4093
c4028958 4094static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4095{
c4028958
DH		 4096 struct rtl8169_private *tp =
4097 container_of(work, struct rtl8169_private, task.work);
4098 struct net_device *dev = tp->dev;
1da177e4
LT		 4099 int ret;
4100
eb2a021c
FR		 4101 rtnl_lock();
4102
4103 if (!netif_running(dev))
4104 goto out_unlock;
4105
4106 rtl8169_wait_for_quiescence(dev);
4107 rtl8169_close(dev);
1da177e4
LT		 4108
4109 ret = rtl8169_open(dev);
4110 if (unlikely(ret < 0)) {
bf82c189
JP		 4111 if (net_ratelimit())
4112 netif_err(tp, drv, dev,
4113 "reinit failure (status = %d). Rescheduling\n",
4114 ret);
1da177e4
LT		 4115 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4116 }
eb2a021c
FR		 4117
4118out_unlock:
4119 rtnl_unlock();
1da177e4
LT		 4120}
4121
c4028958 4122static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4123{
c4028958
DH		 4124 struct rtl8169_private *tp =
4125 container_of(work, struct rtl8169_private, task.work);
4126 struct net_device *dev = tp->dev;
1da177e4 4127
eb2a021c
FR		 4128 rtnl_lock();
4129
1da177e4 4130 if (!netif_running(dev))
eb2a021c 4131 goto out_unlock;
1da177e4
LT		 4132
4133 rtl8169_wait_for_quiescence(dev);
4134
bea3348e 4135 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 4136 rtl8169_tx_clear(tp);
4137
4138 if (tp->dirty_rx == tp->cur_rx) {
4139 rtl8169_init_ring_indexes(tp);
07ce4064 4140 rtl_hw_start(dev);
1da177e4 4141 netif_wake_queue(dev);
cebf8cc7 4142 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 4143 } else {
bf82c189
JP		 4144 if (net_ratelimit())
4145 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
1da177e4
LT		 4146 rtl8169_schedule_work(dev, rtl8169_reset_task);
4147 }
eb2a021c
FR		 4148
4149out_unlock:
4150 rtnl_unlock();
1da177e4
LT		 4151}
4152
4153static void rtl8169_tx_timeout(struct net_device *dev)
4154{
4155 struct rtl8169_private *tp = netdev_priv(dev);
4156
4157 rtl8169_hw_reset(tp->mmio_addr);
4158
4159 /* Let's wait a bit while any (async) irq lands on */
4160 rtl8169_schedule_work(dev, rtl8169_reset_task);
4161}
4162
4163static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4164 u32 opts1)
4165{
4166 struct skb_shared_info *info = skb_shinfo(skb);
4167 unsigned int cur_frag, entry;
a6343afb 4168 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 4169
4170 entry = tp->cur_tx;
4171 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4172 skb_frag_t *frag = info->frags + cur_frag;
4173 dma_addr_t mapping;
4174 u32 status, len;
4175 void *addr;
4176
4177 entry = (entry + 1) % NUM_TX_DESC;
4178
4179 txd = tp->TxDescArray + entry;
4180 len = frag->size;
4181 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4182 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
4183
4184 /* anti gcc 2.95.3 bugware (sic) */
4185 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4186
4187 txd->opts1 = cpu_to_le32(status);
4188 txd->addr = cpu_to_le64(mapping);
4189
4190 tp->tx_skb[entry].len = len;
4191 }
4192
4193 if (cur_frag) {
4194 tp->tx_skb[entry].skb = skb;
4195 txd->opts1 |= cpu_to_le32(LastFrag);
4196 }
4197
4198 return cur_frag;
4199}
4200
4201static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4202{
4203 if (dev->features & NETIF_F_TSO) {
7967168c 4204 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 4205
4206 if (mss)
4207 return LargeSend | ((mss & MSSMask) << MSSShift);
4208 }
84fa7933 4209 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4210 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4211
4212 if (ip->protocol == IPPROTO_TCP)
4213 return IPCS | TCPCS;
4214 else if (ip->protocol == IPPROTO_UDP)
4215 return IPCS | UDPCS;
4216 WARN_ON(1); /* we need a WARN() */
4217 }
4218 return 0;
4219}
4220
61357325
SH		 4221static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4222 struct net_device *dev)
1da177e4
LT		 4223{
4224 struct rtl8169_private *tp = netdev_priv(dev);
4225 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
4226 struct TxDesc *txd = tp->TxDescArray + entry;
4227 void __iomem *ioaddr = tp->mmio_addr;
4228 dma_addr_t mapping;
4229 u32 status, len;
4230 u32 opts1;
5b0384f4 4231
1da177e4 4232 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4233 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
1da177e4
LT		 4234 goto err_stop;
4235 }
4236
4237 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4238 goto err_stop;
4239
4240 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4241
4242 frags = rtl8169_xmit_frags(tp, skb, opts1);
4243 if (frags) {
4244 len = skb_headlen(skb);
4245 opts1 |= FirstFrag;
4246 } else {
4247 len = skb->len;
1da177e4
LT		 4248 opts1 |= FirstFrag | LastFrag;
4249 tp->tx_skb[entry].skb = skb;
4250 }
4251
4252 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
4253
4254 tp->tx_skb[entry].len = len;
4255 txd->addr = cpu_to_le64(mapping);
4256 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4257
4258 wmb();
4259
4260 /* anti gcc 2.95.3 bugware (sic) */
4261 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4262 txd->opts1 = cpu_to_le32(status);
4263
1da177e4
LT		 4264 tp->cur_tx += frags + 1;
4265
4c020a96 4266 wmb();
1da177e4 4267
275391a4 4268 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 4269
4270 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4271 netif_stop_queue(dev);
4272 smp_rmb();
4273 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4274 netif_wake_queue(dev);
4275 }
4276
61357325 4277 return NETDEV_TX_OK;
1da177e4
LT		 4278
4279err_stop:
4280 netif_stop_queue(dev);
cebf8cc7 4281 dev->stats.tx_dropped++;
61357325 4282 return NETDEV_TX_BUSY;
1da177e4
LT		 4283}
4284
4285static void rtl8169_pcierr_interrupt(struct net_device *dev)
4286{
4287 struct rtl8169_private *tp = netdev_priv(dev);
4288 struct pci_dev *pdev = tp->pci_dev;
4289 void __iomem *ioaddr = tp->mmio_addr;
4290 u16 pci_status, pci_cmd;
4291
4292 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4293 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4294
bf82c189
JP		 4295 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4296 pci_cmd, pci_status);
1da177e4
LT		 4297
4298 /*
4299 * The recovery sequence below admits a very elaborated explanation:
4300 * - it seems to work;
d03902b8
FR		 4301 * - I did not see what else could be done;
4302 * - it makes iop3xx happy.
1da177e4
LT		 4303 *
4304 * Feel free to adjust to your needs.
4305 */
a27993f3 4306 if (pdev->broken_parity_status)
d03902b8
FR		 4307 pci_cmd &= ~PCI_COMMAND_PARITY;
4308 else
4309 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4310
4311 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4312
4313 pci_write_config_word(pdev, PCI_STATUS,
4314 pci_status & (PCI_STATUS_DETECTED_PARITY |
4315 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4316 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4317
4318 /* The infamous DAC f*ckup only happens at boot time */
4319 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
bf82c189 4320 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4321 tp->cp_cmd &= ~PCIDAC;
4322 RTL_W16(CPlusCmd, tp->cp_cmd);
4323 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4324 }
4325
4326 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 4327
4328 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4329}
4330
07d3f51f
FR		 4331static void rtl8169_tx_interrupt(struct net_device *dev,
4332 struct rtl8169_private *tp,
4333 void __iomem *ioaddr)
1da177e4
LT		 4334{
4335 unsigned int dirty_tx, tx_left;
4336
1da177e4
LT		 4337 dirty_tx = tp->dirty_tx;
4338 smp_rmb();
4339 tx_left = tp->cur_tx - dirty_tx;
4340
4341 while (tx_left > 0) {
4342 unsigned int entry = dirty_tx % NUM_TX_DESC;
4343 struct ring_info *tx_skb = tp->tx_skb + entry;
4344 u32 len = tx_skb->len;
4345 u32 status;
4346
4347 rmb();
4348 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4349 if (status & DescOwn)
4350 break;
4351
cebf8cc7
FR		 4352 dev->stats.tx_bytes += len;
4353 dev->stats.tx_packets++;
1da177e4
LT		 4354
4355 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
4356
4357 if (status & LastFrag) {
87433bfc 4358 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4359 tx_skb->skb = NULL;
4360 }
4361 dirty_tx++;
4362 tx_left--;
4363 }
4364
4365 if (tp->dirty_tx != dirty_tx) {
4366 tp->dirty_tx = dirty_tx;
4367 smp_wmb();
4368 if (netif_queue_stopped(dev) &&
4369 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4370 netif_wake_queue(dev);
4371 }
d78ae2dc
FR		 4372 /*
4373 * 8168 hack: TxPoll requests are lost when the Tx packets are
4374 * too close. Let's kick an extra TxPoll request when a burst
4375 * of start_xmit activity is detected (if it is not detected,
4376 * it is slow enough). -- FR
4377 */
4378 smp_rmb();
4379 if (tp->cur_tx != dirty_tx)
4380 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4381 }
4382}
4383
126fa4b9
FR		 4384static inline int rtl8169_fragmented_frame(u32 status)
4385{
4386 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4387}
4388
1da177e4
LT		 4389static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
4390{
4391 u32 opts1 = le32_to_cpu(desc->opts1);
4392 u32 status = opts1 & RxProtoMask;
4393
4394 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4395 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
4396 ((status == RxProtoIP) && !(opts1 & IPFail)))
4397 skb->ip_summed = CHECKSUM_UNNECESSARY;
4398 else
4399 skb->ip_summed = CHECKSUM_NONE;
4400}
4401
07d3f51f
FR		 4402static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
4403 struct rtl8169_private *tp, int pkt_size,
4404 dma_addr_t addr)
1da177e4 4405{
b449655f
SH		 4406 struct sk_buff *skb;
4407 bool done = false;
1da177e4 4408
b449655f
SH		 4409 if (pkt_size >= rx_copybreak)
4410 goto out;
1da177e4 4411
89d71a66 4412 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
b449655f
SH		 4413 if (!skb)
4414 goto out;
4415
07d3f51f
FR		 4416 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
4417 PCI_DMA_FROMDEVICE);
b449655f
SH		 4418 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
4419 *sk_buff = skb;
4420 done = true;
4421out:
4422 return done;
1da177e4
LT		 4423}
4424
07d3f51f
FR		 4425static int rtl8169_rx_interrupt(struct net_device *dev,
4426 struct rtl8169_private *tp,
bea3348e 4427 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4428{
4429 unsigned int cur_rx, rx_left;
4430 unsigned int delta, count;
4431
1da177e4
LT		 4432 cur_rx = tp->cur_rx;
4433 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4434 rx_left = min(rx_left, budget);
1da177e4 4435
4dcb7d33 4436 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4437 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4438 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4439 u32 status;
4440
4441 rmb();
126fa4b9 4442 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4443
4444 if (status & DescOwn)
4445 break;
4dcb7d33 4446 if (unlikely(status & RxRES)) {
bf82c189
JP		 4447 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4448 status);
cebf8cc7 4449 dev->stats.rx_errors++;
1da177e4 4450 if (status & (RxRWT | RxRUNT))
cebf8cc7 4451 dev->stats.rx_length_errors++;
1da177e4 4452 if (status & RxCRC)
cebf8cc7 4453 dev->stats.rx_crc_errors++;
9dccf611
FR		 4454 if (status & RxFOVF) {
4455 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4456 dev->stats.rx_fifo_errors++;
9dccf611 4457 }
126fa4b9 4458 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 4459 } else {
1da177e4 4460 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 4461 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4462 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 4463 struct pci_dev *pdev = tp->pci_dev;
1da177e4 4464
126fa4b9
FR		 4465 /*
4466 * The driver does not support incoming fragmented
4467 * frames. They are seen as a symptom of over-mtu
4468 * sized frames.
4469 */
4470 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4471 dev->stats.rx_dropped++;
4472 dev->stats.rx_length_errors++;
126fa4b9 4473 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 4474 continue;
126fa4b9
FR		 4475 }
4476
1da177e4 4477 rtl8169_rx_csum(skb, desc);
bcf0bf90 4478
07d3f51f 4479 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 4480 pci_dma_sync_single_for_device(pdev, addr,
4481 pkt_size, PCI_DMA_FROMDEVICE);
4482 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4483 } else {
a866bbf6 4484 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
b449655f 4485 PCI_DMA_FROMDEVICE);
1da177e4
LT		 4486 tp->Rx_skbuff[entry] = NULL;
4487 }
4488
1da177e4
LT		 4489 skb_put(skb, pkt_size);
4490 skb->protocol = eth_type_trans(skb, dev);
4491
4492 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
865c652d 4493 netif_receive_skb(skb);
1da177e4 4494
cebf8cc7
FR		 4495 dev->stats.rx_bytes += pkt_size;
4496 dev->stats.rx_packets++;
1da177e4 4497 }
6dccd16b
FR		 4498
4499 /* Work around for AMD plateform. */
95e0918d 4500 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4501 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4502 desc->opts2 = 0;
4503 cur_rx++;
4504 }
1da177e4
LT		 4505 }
4506
4507 count = cur_rx - tp->cur_rx;
4508 tp->cur_rx = cur_rx;
4509
4510 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
bf82c189
JP		 4511 if (!delta && count)
4512 netif_info(tp, intr, dev, "no Rx buffer allocated\n");
1da177e4
LT		 4513 tp->dirty_rx += delta;
4514
4515 /*
4516 * FIXME: until there is periodic timer to try and refill the ring,
4517 * a temporary shortage may definitely kill the Rx process.
4518 * - disable the asic to try and avoid an overflow and kick it again
4519 * after refill ?
4520 * - how do others driver handle this condition (Uh oh...).
4521 */
bf82c189
JP		 4522 if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx)
4523 netif_emerg(tp, intr, dev, "Rx buffers exhausted\n");
1da177e4
LT		 4524
4525 return count;
4526}
4527
07d3f51f 4528static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4529{
07d3f51f 4530 struct net_device *dev = dev_instance;
1da177e4 4531 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4532 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4533 int handled = 0;
865c652d 4534 int status;
1da177e4 4535
f11a377b
DD		 4536 /* loop handling interrupts until we have no new ones or
4537 * we hit a invalid/hotplug case.
4538 */
865c652d 4539 status = RTL_R16(IntrStatus);
f11a377b
DD		 4540 while (status && status != 0xffff) {
4541 handled = 1;
1da177e4 4542
f11a377b
DD		 4543 /* Handle all of the error cases first. These will reset
4544 * the chip, so just exit the loop.
4545 */
4546 if (unlikely(!netif_running(dev))) {
4547 rtl8169_asic_down(ioaddr);
4548 break;
4549 }
1da177e4 4550
f11a377b
DD		 4551 /* Work around for rx fifo overflow */
4552 if (unlikely(status & RxFIFOOver) &&
4553 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4554 netif_stop_queue(dev);
4555 rtl8169_tx_timeout(dev);
4556 break;
4557 }
1da177e4 4558
f11a377b
DD		 4559 if (unlikely(status & SYSErr)) {
4560 rtl8169_pcierr_interrupt(dev);
4561 break;
4562 }
1da177e4 4563
f11a377b
DD		 4564 if (status & LinkChg)
4565 rtl8169_check_link_status(dev, tp, ioaddr);
0e485150 4566
f11a377b
DD		 4567 /* We need to see the lastest version of tp->intr_mask to
4568 * avoid ignoring an MSI interrupt and having to wait for
4569 * another event which may never come.
4570 */
4571 smp_rmb();
4572 if (status & tp->intr_mask & tp->napi_event) {
4573 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4574 tp->intr_mask = ~tp->napi_event;
4575
4576 if (likely(napi_schedule_prep(&tp->napi)))
4577 __napi_schedule(&tp->napi);
bf82c189
JP		 4578 else
4579 netif_info(tp, intr, dev,
4580 "interrupt %04x in poll\n", status);
f11a377b 4581 }
1da177e4 4582
f11a377b
DD		 4583 /* We only get a new MSI interrupt when all active irq
4584 * sources on the chip have been acknowledged. So, ack
4585 * everything we've seen and check if new sources have become
4586 * active to avoid blocking all interrupts from the chip.
4587 */
4588 RTL_W16(IntrStatus,
4589 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4590 status = RTL_R16(IntrStatus);
865c652d 4591 }
1da177e4 4592
1da177e4
LT		 4593 return IRQ_RETVAL(handled);
4594}
4595
bea3348e 4596static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 4597{
bea3348e
SH		 4598 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4599 struct net_device *dev = tp->dev;
1da177e4 4600 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 4601 int work_done;
1da177e4 4602
bea3348e 4603 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 4604 rtl8169_tx_interrupt(dev, tp, ioaddr);
4605
bea3348e 4606 if (work_done < budget) {
288379f0 4607 napi_complete(napi);
f11a377b
DD		 4608
4609 /* We need for force the visibility of tp->intr_mask
4610 * for other CPUs, as we can loose an MSI interrupt
4611 * and potentially wait for a retransmit timeout if we don't.
4612 * The posted write to IntrMask is safe, as it will
4613 * eventually make it to the chip and we won't loose anything
4614 * until it does.
1da177e4 4615 */
f11a377b 4616 tp->intr_mask = 0xffff;
4c020a96 4617 wmb();
0e485150 4618 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4619 }
4620
bea3348e 4621 return work_done;
1da177e4 4622}
1da177e4 4623
523a6094
FR		 4624static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4625{
4626 struct rtl8169_private *tp = netdev_priv(dev);
4627
4628 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4629 return;
4630
4631 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4632 RTL_W32(RxMissed, 0);
4633}
4634
1da177e4
LT		 4635static void rtl8169_down(struct net_device *dev)
4636{
4637 struct rtl8169_private *tp = netdev_priv(dev);
4638 void __iomem *ioaddr = tp->mmio_addr;
733b736c 4639 unsigned int intrmask;
1da177e4
LT		 4640
4641 rtl8169_delete_timer(dev);
4642
4643 netif_stop_queue(dev);
4644
93dd79e8 4645 napi_disable(&tp->napi);
93dd79e8 4646
1da177e4
LT		 4647core_down:
4648 spin_lock_irq(&tp->lock);
4649
4650 rtl8169_asic_down(ioaddr);
4651
523a6094 4652 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4653
4654 spin_unlock_irq(&tp->lock);
4655
4656 synchronize_irq(dev->irq);
4657
1da177e4 4658 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 4659 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 4660
4661 /*
4662 * And now for the 50k$ question: are IRQ disabled or not ?
4663 *
4664 * Two paths lead here:
4665 * 1) dev->close
4666 * -> netif_running() is available to sync the current code and the
4667 * IRQ handler. See rtl8169_interrupt for details.
4668 * 2) dev->change_mtu
4669 * -> rtl8169_poll can not be issued again and re-enable the
4670 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 4671 *
4672 * No loop if hotpluged or major error (0xffff).
1da177e4 4673 */
733b736c
AP		 4674 intrmask = RTL_R16(IntrMask);
4675 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 4676 goto core_down;
4677
4678 rtl8169_tx_clear(tp);
4679
4680 rtl8169_rx_clear(tp);
4681}
4682
4683static int rtl8169_close(struct net_device *dev)
4684{
4685 struct rtl8169_private *tp = netdev_priv(dev);
4686 struct pci_dev *pdev = tp->pci_dev;
4687
355423d0
IV		 4688 /* update counters before going down */
4689 rtl8169_update_counters(dev);
4690
1da177e4
LT		 4691 rtl8169_down(dev);
4692
4693 free_irq(dev->irq, dev);
4694
1da177e4
LT		 4695 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
4696 tp->RxPhyAddr);
4697 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
4698 tp->TxPhyAddr);
4699 tp->TxDescArray = NULL;
4700 tp->RxDescArray = NULL;
4701
4702 return 0;
4703}
4704
07ce4064 4705static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 4706{
4707 struct rtl8169_private *tp = netdev_priv(dev);
4708 void __iomem *ioaddr = tp->mmio_addr;
4709 unsigned long flags;
4710 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 4711 int rx_mode;
1da177e4
LT		 4712 u32 tmp = 0;
4713
4714 if (dev->flags & IFF_PROMISC) {
4715 /* Unconditionally log net taps. */
bf82c189 4716 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 4717 rx_mode =
4718 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4719 AcceptAllPhys;
4720 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 4721 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 4722 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 4723 /* Too many to filter perfectly -- accept all multicasts. */
4724 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4725 mc_filter[1] = mc_filter[0] = 0xffffffff;
4726 } else {
4727 struct dev_mc_list *mclist;
07d3f51f 4728
1da177e4
LT		 4729 rx_mode = AcceptBroadcast | AcceptMyPhys;
4730 mc_filter[1] = mc_filter[0] = 0;
f9dcbcc9 4731 netdev_for_each_mc_addr(mclist, dev) {
1da177e4
LT		 4732 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
4733 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4734 rx_mode |= AcceptMulticast;
4735 }
4736 }
4737
4738 spin_lock_irqsave(&tp->lock, flags);
4739
4740 tmp = rtl8169_rx_config | rx_mode |
4741 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4742
f887cce8 4743 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 4744 u32 data = mc_filter[0];
4745
4746 mc_filter[0] = swab32(mc_filter[1]);
4747 mc_filter[1] = swab32(data);
bcf0bf90
FR		 4748 }
4749
1da177e4
LT		 4750 RTL_W32(MAR0 + 0, mc_filter[0]);
4751 RTL_W32(MAR0 + 4, mc_filter[1]);
4752
57a9f236
FR		 4753 RTL_W32(RxConfig, tmp);
4754
1da177e4
LT		 4755 spin_unlock_irqrestore(&tp->lock, flags);
4756}
4757
4758/**
4759 * rtl8169_get_stats - Get rtl8169 read/write statistics
4760 * @dev: The Ethernet Device to get statistics for
4761 *
4762 * Get TX/RX statistics for rtl8169
4763 */
4764static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4765{
4766 struct rtl8169_private *tp = netdev_priv(dev);
4767 void __iomem *ioaddr = tp->mmio_addr;
4768 unsigned long flags;
4769
4770 if (netif_running(dev)) {
4771 spin_lock_irqsave(&tp->lock, flags);
523a6094 4772 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4773 spin_unlock_irqrestore(&tp->lock, flags);
4774 }
5b0384f4 4775
cebf8cc7 4776 return &dev->stats;
1da177e4
LT		 4777}
4778
861ab440 4779static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 4780{
5d06a99f 4781 if (!netif_running(dev))
861ab440 4782 return;
5d06a99f
FR		 4783
4784 netif_device_detach(dev);
4785 netif_stop_queue(dev);
861ab440
RW		 4786}
4787
4788#ifdef CONFIG_PM
4789
4790static int rtl8169_suspend(struct device *device)
4791{
4792 struct pci_dev *pdev = to_pci_dev(device);
4793 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 4794
861ab440 4795 rtl8169_net_suspend(dev);
1371fa6d 4796
5d06a99f
FR		 4797 return 0;
4798}
4799
861ab440 4800static int rtl8169_resume(struct device *device)
5d06a99f 4801{
861ab440 4802 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f
FR		 4803 struct net_device *dev = pci_get_drvdata(pdev);
4804
4805 if (!netif_running(dev))
4806 goto out;
4807
4808 netif_device_attach(dev);
4809
5d06a99f
FR		 4810 rtl8169_schedule_work(dev, rtl8169_reset_task);
4811out:
4812 return 0;
4813}
4814
47145210 4815static const struct dev_pm_ops rtl8169_pm_ops = {
861ab440
RW		 4816 .suspend = rtl8169_suspend,
4817 .resume = rtl8169_resume,
4818 .freeze = rtl8169_suspend,
4819 .thaw = rtl8169_resume,
4820 .poweroff = rtl8169_suspend,
4821 .restore = rtl8169_resume,
4822};
4823
4824#define RTL8169_PM_OPS (&rtl8169_pm_ops)
4825
4826#else /* !CONFIG_PM */
4827
4828#define RTL8169_PM_OPS NULL
4829
4830#endif /* !CONFIG_PM */
4831
1765f95d
FR		 4832static void rtl_shutdown(struct pci_dev *pdev)
4833{
861ab440 4834 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 4835 struct rtl8169_private *tp = netdev_priv(dev);
4836 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 4837
4838 rtl8169_net_suspend(dev);
1765f95d 4839
cc098dc7
IV		 4840 /* restore original MAC address */
4841 rtl_rar_set(tp, dev->perm_addr);
4842
4bb3f522 4843 spin_lock_irq(&tp->lock);
4844
4845 rtl8169_asic_down(ioaddr);
4846
4847 spin_unlock_irq(&tp->lock);
4848
861ab440 4849 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 4850 /* WoL fails with some 8168 when the receiver is disabled. */
4851 if (tp->features & RTL_FEATURE_WOL) {
4852 pci_clear_master(pdev);
4853
4854 RTL_W8(ChipCmd, CmdRxEnb);
4855 /* PCI commit */
4856 RTL_R8(ChipCmd);
4857 }
4858
861ab440
RW		 4859 pci_wake_from_d3(pdev, true);
4860 pci_set_power_state(pdev, PCI_D3hot);
4861 }
4862}
5d06a99f 4863
1da177e4
LT		 4864static struct pci_driver rtl8169_pci_driver = {
4865 .name = MODULENAME,
4866 .id_table = rtl8169_pci_tbl,
4867 .probe = rtl8169_init_one,
4868 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 4869 .shutdown = rtl_shutdown,
861ab440 4870 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 4871};
4872
07d3f51f 4873static int __init rtl8169_init_module(void)
1da177e4 4874{
29917620 4875 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 4876}
4877
07d3f51f 4878static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 4879{
4880 pci_unregister_driver(&rtl8169_pci_driver);
4881}
4882
4883module_init(rtl8169_init_module);
4884module_exit(rtl8169_cleanup_module);
Linux kernel - Deliverables
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